1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */
5 #define __DISABLE_TRACE_MMIO__
8 #include <linux/console.h>
10 #include <linux/iopoll.h>
11 #include <linux/irq.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/pm_opp.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/pm_wakeirq.h>
19 #include <linux/qcom-geni-se.h>
20 #include <linux/serial.h>
21 #include <linux/serial_core.h>
22 #include <linux/slab.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <dt-bindings/interconnect/qcom,icc.h>
27 /* UART specific GENI registers */
28 #define SE_UART_LOOPBACK_CFG 0x22c
29 #define SE_UART_IO_MACRO_CTRL 0x240
30 #define SE_UART_TX_TRANS_CFG 0x25c
31 #define SE_UART_TX_WORD_LEN 0x268
32 #define SE_UART_TX_STOP_BIT_LEN 0x26c
33 #define SE_UART_TX_TRANS_LEN 0x270
34 #define SE_UART_RX_TRANS_CFG 0x280
35 #define SE_UART_RX_WORD_LEN 0x28c
36 #define SE_UART_RX_STALE_CNT 0x294
37 #define SE_UART_TX_PARITY_CFG 0x2a4
38 #define SE_UART_RX_PARITY_CFG 0x2a8
39 #define SE_UART_MANUAL_RFR 0x2ac
41 /* SE_UART_TRANS_CFG */
42 #define UART_TX_PAR_EN BIT(0)
43 #define UART_CTS_MASK BIT(1)
45 /* SE_UART_TX_WORD_LEN */
46 #define TX_WORD_LEN_MSK GENMASK(9, 0)
48 /* SE_UART_TX_STOP_BIT_LEN */
49 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
50 #define TX_STOP_BIT_LEN_1 0
51 #define TX_STOP_BIT_LEN_1_5 1
52 #define TX_STOP_BIT_LEN_2 2
54 /* SE_UART_TX_TRANS_LEN */
55 #define TX_TRANS_LEN_MSK GENMASK(23, 0)
57 /* SE_UART_RX_TRANS_CFG */
58 #define UART_RX_INS_STATUS_BIT BIT(2)
59 #define UART_RX_PAR_EN BIT(3)
61 /* SE_UART_RX_WORD_LEN */
62 #define RX_WORD_LEN_MASK GENMASK(9, 0)
64 /* SE_UART_RX_STALE_CNT */
65 #define RX_STALE_CNT GENMASK(23, 0)
67 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
68 #define PAR_CALC_EN BIT(0)
69 #define PAR_MODE_MSK GENMASK(2, 1)
70 #define PAR_MODE_SHFT 1
73 #define PAR_SPACE 0x10
76 /* SE_UART_MANUAL_RFR register fields */
77 #define UART_MANUAL_RFR_EN BIT(31)
78 #define UART_RFR_NOT_READY BIT(1)
79 #define UART_RFR_READY BIT(0)
81 /* UART M_CMD OP codes */
82 #define UART_START_TX 0x1
83 #define UART_START_BREAK 0x4
84 #define UART_STOP_BREAK 0x5
85 /* UART S_CMD OP codes */
86 #define UART_START_READ 0x1
87 #define UART_PARAM 0x1
89 #define UART_OVERSAMPLING 32
90 #define STALE_TIMEOUT 16
91 #define DEFAULT_BITS_PER_CHAR 10
92 #define GENI_UART_CONS_PORTS 1
93 #define GENI_UART_PORTS 3
94 #define DEF_FIFO_DEPTH_WORDS 16
96 #define DEF_FIFO_WIDTH_BITS 32
99 /* SE_UART_LOOPBACK_CFG */
100 #define RX_TX_SORTED BIT(0)
101 #define CTS_RTS_SORTED BIT(1)
102 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED)
104 /* UART pin swap value */
105 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)
106 #define IO_MACRO_IO0_SEL 0x3
107 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)
108 #define IO_MACRO_IO2_IO3_SWAP 0x4640
110 /* We always configure 4 bytes per FIFO word */
111 #define BYTES_PER_FIFO_WORD 4
113 struct qcom_geni_private_data {
114 /* NOTE: earlycon port will have NULL here */
115 struct uart_driver *drv;
117 u32 poll_cached_bytes;
118 unsigned int poll_cached_bytes_cnt;
120 u32 write_cached_bytes;
121 unsigned int write_cached_bytes_cnt;
124 struct qcom_geni_serial_port {
125 struct uart_port uport;
132 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
138 unsigned int tx_remaining;
143 struct qcom_geni_private_data private_data;
146 static const struct uart_ops qcom_geni_console_pops;
147 static const struct uart_ops qcom_geni_uart_pops;
148 static struct uart_driver qcom_geni_console_driver;
149 static struct uart_driver qcom_geni_uart_driver;
150 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
151 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
152 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
153 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
154 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
156 #define to_dev_port(ptr, member) \
157 container_of(ptr, struct qcom_geni_serial_port, member)
159 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
163 .ops = &qcom_geni_uart_pops,
164 .flags = UPF_BOOT_AUTOCONF,
171 .ops = &qcom_geni_uart_pops,
172 .flags = UPF_BOOT_AUTOCONF,
179 .ops = &qcom_geni_uart_pops,
180 .flags = UPF_BOOT_AUTOCONF,
186 static struct qcom_geni_serial_port qcom_geni_console_port = {
189 .ops = &qcom_geni_console_pops,
190 .flags = UPF_BOOT_AUTOCONF,
195 static int qcom_geni_serial_request_port(struct uart_port *uport)
197 struct platform_device *pdev = to_platform_device(uport->dev);
198 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
200 uport->membase = devm_platform_ioremap_resource(pdev, 0);
201 if (IS_ERR(uport->membase))
202 return PTR_ERR(uport->membase);
203 port->se.base = uport->membase;
207 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
209 if (cfg_flags & UART_CONFIG_TYPE) {
210 uport->type = PORT_MSM;
211 qcom_geni_serial_request_port(uport);
215 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
217 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
220 if (uart_console(uport)) {
223 geni_ios = readl(uport->membase + SE_GENI_IOS);
224 if (!(geni_ios & IO2_DATA_IN))
231 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
234 u32 uart_manual_rfr = 0;
235 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
237 if (uart_console(uport))
240 if (mctrl & TIOCM_LOOP)
241 port->loopback = RX_TX_CTS_RTS_SORTED;
243 if (!(mctrl & TIOCM_RTS) && !uport->suspended)
244 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
245 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
248 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
253 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
255 struct qcom_geni_serial_port *port;
256 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
258 if (line < 0 || line >= nr_ports)
259 return ERR_PTR(-ENXIO);
261 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
265 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
266 int offset, int field, bool set)
269 struct qcom_geni_serial_port *port;
271 unsigned int fifo_bits;
272 unsigned long timeout_us = 20000;
273 struct qcom_geni_private_data *private_data = uport->private_data;
275 if (private_data->drv) {
276 port = to_dev_port(uport, uport);
280 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
282 * Total polling iterations based on FIFO worth of bytes to be
283 * sent at current baud. Add a little fluff to the wait.
285 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
289 * Use custom implementation instead of readl_poll_atomic since ktimer
290 * is not ready at the time of early console.
292 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
294 reg = readl(uport->membase + offset);
295 if ((bool)(reg & field) == set)
303 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
307 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
308 m_cmd = UART_START_TX << M_OPCODE_SHFT;
309 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
312 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
315 u32 irq_clear = M_CMD_DONE_EN;
317 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
318 M_CMD_DONE_EN, true);
320 writel(M_GENI_CMD_ABORT, uport->membase +
321 SE_GENI_M_CMD_CTRL_REG);
322 irq_clear |= M_CMD_ABORT_EN;
323 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
324 M_CMD_ABORT_EN, true);
326 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
329 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
331 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
333 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
334 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
335 S_GENI_CMD_ABORT, false);
336 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
337 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
340 #ifdef CONFIG_CONSOLE_POLL
342 static int qcom_geni_serial_get_char(struct uart_port *uport)
344 struct qcom_geni_private_data *private_data = uport->private_data;
349 if (!private_data->poll_cached_bytes_cnt) {
350 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
351 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
353 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
354 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
356 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
357 word_cnt = status & RX_FIFO_WC_MSK;
361 if (word_cnt == 1 && (status & RX_LAST))
363 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
364 * treated as if it was BYTES_PER_FIFO_WORD.
366 private_data->poll_cached_bytes_cnt =
367 (status & RX_LAST_BYTE_VALID_MSK) >>
368 RX_LAST_BYTE_VALID_SHFT;
370 if (private_data->poll_cached_bytes_cnt == 0)
371 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
373 private_data->poll_cached_bytes =
374 readl(uport->membase + SE_GENI_RX_FIFOn);
377 private_data->poll_cached_bytes_cnt--;
378 ret = private_data->poll_cached_bytes & 0xff;
379 private_data->poll_cached_bytes >>= 8;
384 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
387 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
388 qcom_geni_serial_setup_tx(uport, 1);
389 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
390 M_TX_FIFO_WATERMARK_EN, true));
391 writel(c, uport->membase + SE_GENI_TX_FIFOn);
392 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
393 qcom_geni_serial_poll_tx_done(uport);
397 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
398 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch)
400 struct qcom_geni_private_data *private_data = uport->private_data;
402 private_data->write_cached_bytes =
403 (private_data->write_cached_bytes >> 8) | (ch << 24);
404 private_data->write_cached_bytes_cnt++;
406 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
407 writel(private_data->write_cached_bytes,
408 uport->membase + SE_GENI_TX_FIFOn);
409 private_data->write_cached_bytes_cnt = 0;
414 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
417 struct qcom_geni_private_data *private_data = uport->private_data;
420 u32 bytes_to_send = count;
422 for (i = 0; i < count; i++) {
424 * uart_console_write() adds a carriage return for each newline.
425 * Account for additional bytes to be written.
431 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
432 qcom_geni_serial_setup_tx(uport, bytes_to_send);
433 for (i = 0; i < count; ) {
434 size_t chars_to_write = 0;
435 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
438 * If the WM bit never set, then the Tx state machine is not
439 * in a valid state, so break, cancel/abort any existing
440 * command. Unfortunately the current data being written is
443 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
444 M_TX_FIFO_WATERMARK_EN, true))
446 chars_to_write = min_t(size_t, count - i, avail / 2);
447 uart_console_write(uport, s + i, chars_to_write,
448 qcom_geni_serial_wr_char);
449 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
450 SE_GENI_M_IRQ_CLEAR);
454 if (private_data->write_cached_bytes_cnt) {
455 private_data->write_cached_bytes >>= BITS_PER_BYTE *
456 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
457 writel(private_data->write_cached_bytes,
458 uport->membase + SE_GENI_TX_FIFOn);
459 private_data->write_cached_bytes_cnt = 0;
462 qcom_geni_serial_poll_tx_done(uport);
465 static void qcom_geni_serial_console_write(struct console *co, const char *s,
468 struct uart_port *uport;
469 struct qcom_geni_serial_port *port;
475 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
477 port = get_port_from_line(co->index, true);
481 uport = &port->uport;
482 if (oops_in_progress)
483 locked = spin_trylock_irqsave(&uport->lock, flags);
485 spin_lock_irqsave(&uport->lock, flags);
487 geni_status = readl(uport->membase + SE_GENI_STATUS);
489 /* Cancel the current write to log the fault */
491 geni_se_cancel_m_cmd(&port->se);
492 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
493 M_CMD_CANCEL_EN, true)) {
494 geni_se_abort_m_cmd(&port->se);
495 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
496 M_CMD_ABORT_EN, true);
497 writel(M_CMD_ABORT_EN, uport->membase +
498 SE_GENI_M_IRQ_CLEAR);
500 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
501 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
503 * It seems we can't interrupt existing transfers if all data
504 * has been sent, in which case we need to look for done first.
506 qcom_geni_serial_poll_tx_done(uport);
508 if (!uart_circ_empty(&uport->state->xmit)) {
509 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
510 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
511 uport->membase + SE_GENI_M_IRQ_EN);
515 __qcom_geni_serial_console_write(uport, s, count);
517 if (port->tx_remaining)
518 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
521 spin_unlock_irqrestore(&uport->lock, flags);
524 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
527 unsigned char buf[sizeof(u32)];
528 struct tty_port *tport;
529 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
531 tport = &uport->state->port;
532 for (i = 0; i < bytes; ) {
534 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
536 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
541 for (c = 0; c < chunk; c++) {
545 if (port->brk && buf[c] == 0) {
547 if (uart_handle_break(uport))
551 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
554 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
558 tty_flip_buffer_push(tport);
562 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
567 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
569 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
571 struct tty_port *tport;
572 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
573 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
574 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
577 tport = &uport->state->port;
578 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
582 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
584 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
585 __func__, ret, bytes);
588 uport->icount.rx += ret;
589 tty_flip_buffer_push(tport);
593 static void qcom_geni_serial_start_tx(struct uart_port *uport)
598 status = readl(uport->membase + SE_GENI_STATUS);
599 if (status & M_GENI_CMD_ACTIVE)
602 if (!qcom_geni_serial_tx_empty(uport))
605 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
606 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
608 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
609 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
612 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
616 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
618 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
619 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
620 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
621 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
622 status = readl(uport->membase + SE_GENI_STATUS);
623 /* Possible stop tx is called multiple times. */
624 if (!(status & M_GENI_CMD_ACTIVE))
627 geni_se_cancel_m_cmd(&port->se);
628 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
629 M_CMD_CANCEL_EN, true)) {
630 geni_se_abort_m_cmd(&port->se);
631 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
632 M_CMD_ABORT_EN, true);
633 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
635 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
638 static void qcom_geni_serial_start_rx(struct uart_port *uport)
642 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
644 status = readl(uport->membase + SE_GENI_STATUS);
645 if (status & S_GENI_CMD_ACTIVE)
646 qcom_geni_serial_stop_rx(uport);
648 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
650 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
651 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
652 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
654 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
655 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
656 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
659 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
663 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
666 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
667 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
668 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
670 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
671 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
672 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
674 status = readl(uport->membase + SE_GENI_STATUS);
675 /* Possible stop rx is called multiple times. */
676 if (!(status & S_GENI_CMD_ACTIVE))
679 geni_se_cancel_s_cmd(&port->se);
680 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
681 S_CMD_CANCEL_EN, true);
683 * If timeout occurs secondary engine remains active
684 * and Abort sequence is executed.
686 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
687 /* Flush the Rx buffer */
688 if (s_irq_status & S_RX_FIFO_LAST_EN)
689 qcom_geni_serial_handle_rx(uport, true);
690 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
692 status = readl(uport->membase + SE_GENI_STATUS);
693 if (status & S_GENI_CMD_ACTIVE)
694 qcom_geni_serial_abort_rx(uport);
697 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
701 u32 last_word_byte_cnt;
702 u32 last_word_partial;
704 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
706 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
707 word_cnt = status & RX_FIFO_WC_MSK;
708 last_word_partial = status & RX_LAST;
709 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
710 RX_LAST_BYTE_VALID_SHFT;
714 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
715 if (last_word_partial && last_word_byte_cnt)
716 total_bytes += last_word_byte_cnt;
718 total_bytes += BYTES_PER_FIFO_WORD;
719 port->handle_rx(uport, total_bytes, drop);
722 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
725 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
726 struct circ_buf *xmit = &uport->state->xmit;
736 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
738 /* Complete the current tx command before taking newly added data */
740 pending = port->tx_remaining;
742 pending = uart_circ_chars_pending(xmit);
744 /* All data has been transmitted and acknowledged as received */
745 if (!pending && !status && done) {
746 qcom_geni_serial_stop_tx(uport);
747 goto out_write_wakeup;
750 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
751 avail *= BYTES_PER_FIFO_WORD;
754 chunk = min(avail, pending);
756 goto out_write_wakeup;
758 if (!port->tx_remaining) {
759 qcom_geni_serial_setup_tx(uport, pending);
760 port->tx_remaining = pending;
762 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
763 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
764 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
765 uport->membase + SE_GENI_M_IRQ_EN);
769 for (i = 0; i < chunk; ) {
770 unsigned int tx_bytes;
774 memset(buf, 0, sizeof(buf));
775 tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD);
777 for (c = 0; c < tx_bytes ; c++) {
778 buf[c] = xmit->buf[tail++];
779 tail &= UART_XMIT_SIZE - 1;
782 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
785 uport->icount.tx += tx_bytes;
786 remaining -= tx_bytes;
787 port->tx_remaining -= tx_bytes;
793 * The tx fifo watermark is level triggered and latched. Though we had
794 * cleared it in qcom_geni_serial_isr it will have already reasserted
795 * so we must clear it again here after our writes.
797 writel(M_TX_FIFO_WATERMARK_EN,
798 uport->membase + SE_GENI_M_IRQ_CLEAR);
801 if (!port->tx_remaining) {
802 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
803 if (irq_en & M_TX_FIFO_WATERMARK_EN)
804 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
805 uport->membase + SE_GENI_M_IRQ_EN);
808 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
809 uart_write_wakeup(uport);
812 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
818 struct uart_port *uport = dev;
819 bool drop_rx = false;
820 struct tty_port *tport = &uport->state->port;
821 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
823 if (uport->suspended)
826 spin_lock(&uport->lock);
828 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
829 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
830 geni_status = readl(uport->membase + SE_GENI_STATUS);
831 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
832 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
833 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
835 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
838 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
839 uport->icount.overrun++;
840 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
843 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
844 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
845 geni_status & M_GENI_CMD_ACTIVE);
847 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
848 if (s_irq_status & S_GP_IRQ_0_EN)
849 uport->icount.parity++;
851 } else if (s_irq_status & S_GP_IRQ_2_EN ||
852 s_irq_status & S_GP_IRQ_3_EN) {
857 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
858 s_irq_status & S_RX_FIFO_LAST_EN)
859 qcom_geni_serial_handle_rx(uport, drop_rx);
862 uart_unlock_and_check_sysrq(uport);
867 static int setup_fifos(struct qcom_geni_serial_port *port)
869 struct uart_port *uport;
870 u32 old_rx_fifo_depth = port->rx_fifo_depth;
872 uport = &port->uport;
873 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
874 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
875 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
877 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
879 if (port->rx_fifo && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) {
880 port->rx_fifo = devm_krealloc(uport->dev, port->rx_fifo,
881 port->rx_fifo_depth * sizeof(u32),
891 static void qcom_geni_serial_shutdown(struct uart_port *uport)
893 disable_irq(uport->irq);
896 static int qcom_geni_serial_port_setup(struct uart_port *uport)
898 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
899 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
904 proto = geni_se_read_proto(&port->se);
905 if (proto != GENI_SE_UART) {
906 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
910 qcom_geni_serial_stop_rx(uport);
912 ret = setup_fifos(port);
916 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
918 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
919 if (port->rx_tx_swap) {
920 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
921 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
923 if (port->cts_rts_swap) {
924 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
925 pin_swap |= IO_MACRO_IO0_SEL;
927 /* Configure this register if RX-TX, CTS-RTS pins are swapped */
928 if (port->rx_tx_swap || port->cts_rts_swap)
929 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
932 * Make an unconditional cancel on the main sequencer to reset
933 * it else we could end up in data loss scenarios.
935 if (uart_console(uport))
936 qcom_geni_serial_poll_tx_done(uport);
937 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
939 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
940 geni_se_select_mode(&port->se, GENI_SE_FIFO);
946 static int qcom_geni_serial_startup(struct uart_port *uport)
949 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
952 ret = qcom_geni_serial_port_setup(uport);
956 enable_irq(uport->irq);
961 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk,
962 unsigned int *clk_div, unsigned int percent_tol)
965 unsigned long div, maxdiv;
967 unsigned long offset, abs_tol, achieved;
969 abs_tol = div_u64((u64)desired_clk * percent_tol, 100);
970 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
972 while (div <= maxdiv) {
973 mult = (u64)div * desired_clk;
974 if (mult != (unsigned long)mult)
977 offset = div * abs_tol;
978 freq = clk_round_rate(clk, mult - offset);
980 /* Can only get lower if we're done */
981 if (freq < mult - offset)
985 * Re-calculate div in case rounding skipped rates but we
986 * ended up at a good one, then check for a match.
988 div = DIV_ROUND_CLOSEST(freq, desired_clk);
989 achieved = DIV_ROUND_CLOSEST(freq, div);
990 if (achieved <= desired_clk + abs_tol &&
991 achieved >= desired_clk - abs_tol) {
996 div = DIV_ROUND_UP(freq, desired_clk);
1002 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
1003 unsigned int sampling_rate, unsigned int *clk_div)
1005 unsigned long ser_clk;
1006 unsigned long desired_clk;
1008 desired_clk = baud * sampling_rate;
1013 * try to find a clock rate within 2% tolerance, then within 5%
1015 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2);
1017 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5);
1022 static void qcom_geni_serial_set_termios(struct uart_port *uport,
1023 struct ktermios *termios,
1024 const struct ktermios *old)
1033 unsigned int clk_div;
1035 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1036 unsigned long clk_rate;
1037 u32 ver, sampling_rate;
1038 unsigned int avg_bw_core;
1040 qcom_geni_serial_stop_rx(uport);
1042 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1045 sampling_rate = UART_OVERSAMPLING;
1046 /* Sampling rate is halved for IP versions >= 2.5 */
1047 ver = geni_se_get_qup_hw_version(&port->se);
1048 if (ver >= QUP_SE_VERSION_2_5)
1051 clk_rate = get_clk_div_rate(port->se.clk, baud,
1052 sampling_rate, &clk_div);
1054 dev_err(port->se.dev,
1055 "Couldn't find suitable clock rate for %u\n",
1056 baud * sampling_rate);
1057 goto out_restart_rx;
1060 dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n",
1061 baud * sampling_rate, clk_rate, clk_div);
1063 uport->uartclk = clk_rate;
1064 dev_pm_opp_set_rate(uport->dev, clk_rate);
1065 ser_clk_cfg = SER_CLK_EN;
1066 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1069 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1072 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1074 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1075 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1076 geni_icc_set_bw(&port->se);
1079 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1080 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1081 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1082 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1083 if (termios->c_cflag & PARENB) {
1084 tx_trans_cfg |= UART_TX_PAR_EN;
1085 rx_trans_cfg |= UART_RX_PAR_EN;
1086 tx_parity_cfg |= PAR_CALC_EN;
1087 rx_parity_cfg |= PAR_CALC_EN;
1088 if (termios->c_cflag & PARODD) {
1089 tx_parity_cfg |= PAR_ODD;
1090 rx_parity_cfg |= PAR_ODD;
1091 } else if (termios->c_cflag & CMSPAR) {
1092 tx_parity_cfg |= PAR_SPACE;
1093 rx_parity_cfg |= PAR_SPACE;
1095 tx_parity_cfg |= PAR_EVEN;
1096 rx_parity_cfg |= PAR_EVEN;
1099 tx_trans_cfg &= ~UART_TX_PAR_EN;
1100 rx_trans_cfg &= ~UART_RX_PAR_EN;
1101 tx_parity_cfg &= ~PAR_CALC_EN;
1102 rx_parity_cfg &= ~PAR_CALC_EN;
1106 bits_per_char = tty_get_char_size(termios->c_cflag);
1109 if (termios->c_cflag & CSTOPB)
1110 stop_bit_len = TX_STOP_BIT_LEN_2;
1112 stop_bit_len = TX_STOP_BIT_LEN_1;
1114 /* flow control, clear the CTS_MASK bit if using flow control. */
1115 if (termios->c_cflag & CRTSCTS)
1116 tx_trans_cfg &= ~UART_CTS_MASK;
1118 tx_trans_cfg |= UART_CTS_MASK;
1121 uart_update_timeout(uport, termios->c_cflag, baud);
1123 if (!uart_console(uport))
1124 writel(port->loopback,
1125 uport->membase + SE_UART_LOOPBACK_CFG);
1126 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1127 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1128 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1129 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1130 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1131 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1132 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1133 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1134 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1136 qcom_geni_serial_start_rx(uport);
1139 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1141 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1144 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1145 static int qcom_geni_console_setup(struct console *co, char *options)
1147 struct uart_port *uport;
1148 struct qcom_geni_serial_port *port;
1155 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1158 port = get_port_from_line(co->index, true);
1160 pr_err("Invalid line %d\n", co->index);
1161 return PTR_ERR(port);
1164 uport = &port->uport;
1166 if (unlikely(!uport->membase))
1170 ret = qcom_geni_serial_port_setup(uport);
1176 uart_parse_options(options, &baud, &parity, &bits, &flow);
1178 return uart_set_options(uport, co, baud, parity, bits, flow);
1181 static void qcom_geni_serial_earlycon_write(struct console *con,
1182 const char *s, unsigned int n)
1184 struct earlycon_device *dev = con->data;
1186 __qcom_geni_serial_console_write(&dev->port, s, n);
1189 #ifdef CONFIG_CONSOLE_POLL
1190 static int qcom_geni_serial_earlycon_read(struct console *con,
1191 char *s, unsigned int n)
1193 struct earlycon_device *dev = con->data;
1194 struct uart_port *uport = &dev->port;
1198 while (num_read < n) {
1199 ch = qcom_geni_serial_get_char(uport);
1200 if (ch == NO_POLL_CHAR)
1208 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1209 struct console *con)
1211 geni_se_setup_s_cmd(se, UART_START_READ, 0);
1212 con->read = qcom_geni_serial_earlycon_read;
1215 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1216 struct console *con) { }
1219 static struct qcom_geni_private_data earlycon_private_data;
1221 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1224 struct uart_port *uport = &dev->port;
1226 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1227 u32 rx_trans_cfg = 0;
1228 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1229 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1233 if (!uport->membase)
1236 uport->private_data = &earlycon_private_data;
1238 memset(&se, 0, sizeof(se));
1239 se.base = uport->membase;
1240 if (geni_se_read_proto(&se) != GENI_SE_UART)
1243 * Ignore Flow control.
1246 tx_trans_cfg = UART_CTS_MASK;
1247 bits_per_char = BITS_PER_BYTE;
1250 * Make an unconditional cancel on the main sequencer to reset
1251 * it else we could end up in data loss scenarios.
1253 qcom_geni_serial_poll_tx_done(uport);
1254 qcom_geni_serial_abort_rx(uport);
1255 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1257 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1258 geni_se_select_mode(&se, GENI_SE_FIFO);
1260 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1261 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1262 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1263 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1264 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1265 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1266 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1268 dev->con->write = qcom_geni_serial_earlycon_write;
1269 dev->con->setup = NULL;
1270 qcom_geni_serial_enable_early_read(&se, dev->con);
1274 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1275 qcom_geni_serial_earlycon_setup);
1277 static int __init console_register(struct uart_driver *drv)
1279 return uart_register_driver(drv);
1282 static void console_unregister(struct uart_driver *drv)
1284 uart_unregister_driver(drv);
1287 static struct console cons_ops = {
1289 .write = qcom_geni_serial_console_write,
1290 .device = uart_console_device,
1291 .setup = qcom_geni_console_setup,
1292 .flags = CON_PRINTBUFFER,
1294 .data = &qcom_geni_console_driver,
1297 static struct uart_driver qcom_geni_console_driver = {
1298 .owner = THIS_MODULE,
1299 .driver_name = "qcom_geni_console",
1300 .dev_name = "ttyMSM",
1301 .nr = GENI_UART_CONS_PORTS,
1305 static int console_register(struct uart_driver *drv)
1310 static void console_unregister(struct uart_driver *drv)
1313 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1315 static struct uart_driver qcom_geni_uart_driver = {
1316 .owner = THIS_MODULE,
1317 .driver_name = "qcom_geni_uart",
1318 .dev_name = "ttyHS",
1319 .nr = GENI_UART_PORTS,
1322 static void qcom_geni_serial_pm(struct uart_port *uport,
1323 unsigned int new_state, unsigned int old_state)
1325 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1327 /* If we've never been called, treat it as off */
1328 if (old_state == UART_PM_STATE_UNDEFINED)
1329 old_state = UART_PM_STATE_OFF;
1331 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1332 geni_icc_enable(&port->se);
1333 geni_se_resources_on(&port->se);
1334 } else if (new_state == UART_PM_STATE_OFF &&
1335 old_state == UART_PM_STATE_ON) {
1336 geni_se_resources_off(&port->se);
1337 geni_icc_disable(&port->se);
1341 static const struct uart_ops qcom_geni_console_pops = {
1342 .tx_empty = qcom_geni_serial_tx_empty,
1343 .stop_tx = qcom_geni_serial_stop_tx,
1344 .start_tx = qcom_geni_serial_start_tx,
1345 .stop_rx = qcom_geni_serial_stop_rx,
1346 .start_rx = qcom_geni_serial_start_rx,
1347 .set_termios = qcom_geni_serial_set_termios,
1348 .startup = qcom_geni_serial_startup,
1349 .request_port = qcom_geni_serial_request_port,
1350 .config_port = qcom_geni_serial_config_port,
1351 .shutdown = qcom_geni_serial_shutdown,
1352 .type = qcom_geni_serial_get_type,
1353 .set_mctrl = qcom_geni_serial_set_mctrl,
1354 .get_mctrl = qcom_geni_serial_get_mctrl,
1355 #ifdef CONFIG_CONSOLE_POLL
1356 .poll_get_char = qcom_geni_serial_get_char,
1357 .poll_put_char = qcom_geni_serial_poll_put_char,
1359 .pm = qcom_geni_serial_pm,
1362 static const struct uart_ops qcom_geni_uart_pops = {
1363 .tx_empty = qcom_geni_serial_tx_empty,
1364 .stop_tx = qcom_geni_serial_stop_tx,
1365 .start_tx = qcom_geni_serial_start_tx,
1366 .stop_rx = qcom_geni_serial_stop_rx,
1367 .set_termios = qcom_geni_serial_set_termios,
1368 .startup = qcom_geni_serial_startup,
1369 .request_port = qcom_geni_serial_request_port,
1370 .config_port = qcom_geni_serial_config_port,
1371 .shutdown = qcom_geni_serial_shutdown,
1372 .type = qcom_geni_serial_get_type,
1373 .set_mctrl = qcom_geni_serial_set_mctrl,
1374 .get_mctrl = qcom_geni_serial_get_mctrl,
1375 .pm = qcom_geni_serial_pm,
1378 static int qcom_geni_serial_probe(struct platform_device *pdev)
1382 struct qcom_geni_serial_port *port;
1383 struct uart_port *uport;
1384 struct resource *res;
1386 bool console = false;
1387 struct uart_driver *drv;
1389 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1393 drv = &qcom_geni_console_driver;
1394 line = of_alias_get_id(pdev->dev.of_node, "serial");
1396 drv = &qcom_geni_uart_driver;
1397 line = of_alias_get_id(pdev->dev.of_node, "serial");
1398 if (line == -ENODEV) /* compat with non-standard aliases */
1399 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1402 port = get_port_from_line(line, console);
1404 dev_err(&pdev->dev, "Invalid line %d\n", line);
1405 return PTR_ERR(port);
1408 uport = &port->uport;
1409 /* Don't allow 2 drivers to access the same port */
1410 if (uport->private_data)
1413 uport->dev = &pdev->dev;
1414 port->se.dev = &pdev->dev;
1415 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1416 port->se.clk = devm_clk_get(&pdev->dev, "se");
1417 if (IS_ERR(port->se.clk)) {
1418 ret = PTR_ERR(port->se.clk);
1419 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1423 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1426 uport->mapbase = res->start;
1428 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1429 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1430 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1433 port->rx_fifo = devm_kcalloc(uport->dev,
1434 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1439 ret = geni_icc_get(&port->se, NULL);
1442 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1443 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1445 /* Set BW for register access */
1446 ret = geni_icc_set_bw(&port->se);
1450 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1451 "qcom_geni_serial_%s%d",
1452 uart_console(uport) ? "console" : "uart", uport->line);
1456 irq = platform_get_irq(pdev, 0);
1460 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1463 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1465 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1466 port->rx_tx_swap = true;
1468 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1469 port->cts_rts_swap = true;
1471 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1474 /* OPP table is optional */
1475 ret = devm_pm_opp_of_add_table(&pdev->dev);
1476 if (ret && ret != -ENODEV) {
1477 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1481 port->private_data.drv = drv;
1482 uport->private_data = &port->private_data;
1483 platform_set_drvdata(pdev, port);
1484 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1486 ret = uart_add_one_port(drv, uport);
1490 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1491 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1492 IRQF_TRIGGER_HIGH, port->name, uport);
1494 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1495 uart_remove_one_port(drv, uport);
1500 * Set pm_runtime status as ACTIVE so that wakeup_irq gets
1501 * enabled/disabled from dev_pm_arm_wake_irq during system
1502 * suspend/resume respectively.
1504 pm_runtime_set_active(&pdev->dev);
1506 if (port->wakeup_irq > 0) {
1507 device_init_wakeup(&pdev->dev, true);
1508 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1511 device_init_wakeup(&pdev->dev, false);
1512 uart_remove_one_port(drv, uport);
1520 static int qcom_geni_serial_remove(struct platform_device *pdev)
1522 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1523 struct uart_driver *drv = port->private_data.drv;
1525 dev_pm_clear_wake_irq(&pdev->dev);
1526 device_init_wakeup(&pdev->dev, false);
1527 uart_remove_one_port(drv, &port->uport);
1532 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1534 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1535 struct uart_port *uport = &port->uport;
1536 struct qcom_geni_private_data *private_data = uport->private_data;
1539 * This is done so we can hit the lowest possible state in suspend
1540 * even with no_console_suspend
1542 if (uart_console(uport)) {
1543 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY);
1544 geni_icc_set_bw(&port->se);
1546 return uart_suspend_port(private_data->drv, uport);
1549 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1552 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1553 struct uart_port *uport = &port->uport;
1554 struct qcom_geni_private_data *private_data = uport->private_data;
1556 ret = uart_resume_port(private_data->drv, uport);
1557 if (uart_console(uport)) {
1558 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);
1559 geni_icc_set_bw(&port->se);
1564 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1565 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1566 qcom_geni_serial_sys_resume)
1569 static const struct of_device_id qcom_geni_serial_match_table[] = {
1570 { .compatible = "qcom,geni-debug-uart", },
1571 { .compatible = "qcom,geni-uart", },
1574 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1576 static struct platform_driver qcom_geni_serial_platform_driver = {
1577 .remove = qcom_geni_serial_remove,
1578 .probe = qcom_geni_serial_probe,
1580 .name = "qcom_geni_serial",
1581 .of_match_table = qcom_geni_serial_match_table,
1582 .pm = &qcom_geni_serial_pm_ops,
1586 static int __init qcom_geni_serial_init(void)
1590 ret = console_register(&qcom_geni_console_driver);
1594 ret = uart_register_driver(&qcom_geni_uart_driver);
1596 console_unregister(&qcom_geni_console_driver);
1600 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1602 console_unregister(&qcom_geni_console_driver);
1603 uart_unregister_driver(&qcom_geni_uart_driver);
1607 module_init(qcom_geni_serial_init);
1609 static void __exit qcom_geni_serial_exit(void)
1611 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1612 console_unregister(&qcom_geni_console_driver);
1613 uart_unregister_driver(&qcom_geni_uart_driver);
1615 module_exit(qcom_geni_serial_exit);
1617 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1618 MODULE_LICENSE("GPL v2");