1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */
5 #define __DISABLE_TRACE_MMIO__
8 #include <linux/console.h>
10 #include <linux/iopoll.h>
11 #include <linux/irq.h>
12 #include <linux/module.h>
14 #include <linux/of_device.h>
15 #include <linux/pm_opp.h>
16 #include <linux/platform_device.h>
17 #include <linux/pm_runtime.h>
18 #include <linux/pm_wakeirq.h>
19 #include <linux/qcom-geni-se.h>
20 #include <linux/serial.h>
21 #include <linux/serial_core.h>
22 #include <linux/slab.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
26 /* UART specific GENI registers */
27 #define SE_UART_LOOPBACK_CFG 0x22c
28 #define SE_UART_IO_MACRO_CTRL 0x240
29 #define SE_UART_TX_TRANS_CFG 0x25c
30 #define SE_UART_TX_WORD_LEN 0x268
31 #define SE_UART_TX_STOP_BIT_LEN 0x26c
32 #define SE_UART_TX_TRANS_LEN 0x270
33 #define SE_UART_RX_TRANS_CFG 0x280
34 #define SE_UART_RX_WORD_LEN 0x28c
35 #define SE_UART_RX_STALE_CNT 0x294
36 #define SE_UART_TX_PARITY_CFG 0x2a4
37 #define SE_UART_RX_PARITY_CFG 0x2a8
38 #define SE_UART_MANUAL_RFR 0x2ac
40 /* SE_UART_TRANS_CFG */
41 #define UART_TX_PAR_EN BIT(0)
42 #define UART_CTS_MASK BIT(1)
44 /* SE_UART_TX_WORD_LEN */
45 #define TX_WORD_LEN_MSK GENMASK(9, 0)
47 /* SE_UART_TX_STOP_BIT_LEN */
48 #define TX_STOP_BIT_LEN_MSK GENMASK(23, 0)
49 #define TX_STOP_BIT_LEN_1 0
50 #define TX_STOP_BIT_LEN_1_5 1
51 #define TX_STOP_BIT_LEN_2 2
53 /* SE_UART_TX_TRANS_LEN */
54 #define TX_TRANS_LEN_MSK GENMASK(23, 0)
56 /* SE_UART_RX_TRANS_CFG */
57 #define UART_RX_INS_STATUS_BIT BIT(2)
58 #define UART_RX_PAR_EN BIT(3)
60 /* SE_UART_RX_WORD_LEN */
61 #define RX_WORD_LEN_MASK GENMASK(9, 0)
63 /* SE_UART_RX_STALE_CNT */
64 #define RX_STALE_CNT GENMASK(23, 0)
66 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
67 #define PAR_CALC_EN BIT(0)
68 #define PAR_MODE_MSK GENMASK(2, 1)
69 #define PAR_MODE_SHFT 1
72 #define PAR_SPACE 0x10
75 /* SE_UART_MANUAL_RFR register fields */
76 #define UART_MANUAL_RFR_EN BIT(31)
77 #define UART_RFR_NOT_READY BIT(1)
78 #define UART_RFR_READY BIT(0)
80 /* UART M_CMD OP codes */
81 #define UART_START_TX 0x1
82 #define UART_START_BREAK 0x4
83 #define UART_STOP_BREAK 0x5
84 /* UART S_CMD OP codes */
85 #define UART_START_READ 0x1
86 #define UART_PARAM 0x1
88 #define UART_OVERSAMPLING 32
89 #define STALE_TIMEOUT 16
90 #define DEFAULT_BITS_PER_CHAR 10
91 #define GENI_UART_CONS_PORTS 1
92 #define GENI_UART_PORTS 3
93 #define DEF_FIFO_DEPTH_WORDS 16
95 #define DEF_FIFO_WIDTH_BITS 32
98 /* SE_UART_LOOPBACK_CFG */
99 #define RX_TX_SORTED BIT(0)
100 #define CTS_RTS_SORTED BIT(1)
101 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED)
103 /* UART pin swap value */
104 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)
105 #define IO_MACRO_IO0_SEL 0x3
106 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)
107 #define IO_MACRO_IO2_IO3_SWAP 0x4640
109 /* We always configure 4 bytes per FIFO word */
110 #define BYTES_PER_FIFO_WORD 4
112 struct qcom_geni_private_data {
113 /* NOTE: earlycon port will have NULL here */
114 struct uart_driver *drv;
116 u32 poll_cached_bytes;
117 unsigned int poll_cached_bytes_cnt;
119 u32 write_cached_bytes;
120 unsigned int write_cached_bytes_cnt;
123 struct qcom_geni_serial_port {
124 struct uart_port uport;
131 int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
137 unsigned int tx_remaining;
142 struct qcom_geni_private_data private_data;
145 static const struct uart_ops qcom_geni_console_pops;
146 static const struct uart_ops qcom_geni_uart_pops;
147 static struct uart_driver qcom_geni_console_driver;
148 static struct uart_driver qcom_geni_uart_driver;
149 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
150 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
151 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
152 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
153 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
155 #define to_dev_port(ptr, member) \
156 container_of(ptr, struct qcom_geni_serial_port, member)
158 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
162 .ops = &qcom_geni_uart_pops,
163 .flags = UPF_BOOT_AUTOCONF,
170 .ops = &qcom_geni_uart_pops,
171 .flags = UPF_BOOT_AUTOCONF,
178 .ops = &qcom_geni_uart_pops,
179 .flags = UPF_BOOT_AUTOCONF,
185 static struct qcom_geni_serial_port qcom_geni_console_port = {
188 .ops = &qcom_geni_console_pops,
189 .flags = UPF_BOOT_AUTOCONF,
194 static int qcom_geni_serial_request_port(struct uart_port *uport)
196 struct platform_device *pdev = to_platform_device(uport->dev);
197 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
199 uport->membase = devm_platform_ioremap_resource(pdev, 0);
200 if (IS_ERR(uport->membase))
201 return PTR_ERR(uport->membase);
202 port->se.base = uport->membase;
206 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
208 if (cfg_flags & UART_CONFIG_TYPE) {
209 uport->type = PORT_MSM;
210 qcom_geni_serial_request_port(uport);
214 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
216 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
219 if (uart_console(uport)) {
222 geni_ios = readl(uport->membase + SE_GENI_IOS);
223 if (!(geni_ios & IO2_DATA_IN))
230 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
233 u32 uart_manual_rfr = 0;
234 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
236 if (uart_console(uport))
239 if (mctrl & TIOCM_LOOP)
240 port->loopback = RX_TX_CTS_RTS_SORTED;
242 if (!(mctrl & TIOCM_RTS) && !uport->suspended)
243 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
244 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
247 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
252 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
254 struct qcom_geni_serial_port *port;
255 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
257 if (line < 0 || line >= nr_ports)
258 return ERR_PTR(-ENXIO);
260 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
264 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
265 int offset, int field, bool set)
268 struct qcom_geni_serial_port *port;
270 unsigned int fifo_bits;
271 unsigned long timeout_us = 20000;
272 struct qcom_geni_private_data *private_data = uport->private_data;
274 if (private_data->drv) {
275 port = to_dev_port(uport, uport);
279 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
281 * Total polling iterations based on FIFO worth of bytes to be
282 * sent at current baud. Add a little fluff to the wait.
284 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
288 * Use custom implementation instead of readl_poll_atomic since ktimer
289 * is not ready at the time of early console.
291 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
293 reg = readl(uport->membase + offset);
294 if ((bool)(reg & field) == set)
302 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
306 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
307 m_cmd = UART_START_TX << M_OPCODE_SHFT;
308 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
311 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
314 u32 irq_clear = M_CMD_DONE_EN;
316 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
317 M_CMD_DONE_EN, true);
319 writel(M_GENI_CMD_ABORT, uport->membase +
320 SE_GENI_M_CMD_CTRL_REG);
321 irq_clear |= M_CMD_ABORT_EN;
322 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
323 M_CMD_ABORT_EN, true);
325 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
328 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
330 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
332 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
333 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
334 S_GENI_CMD_ABORT, false);
335 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
336 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
339 #ifdef CONFIG_CONSOLE_POLL
341 static int qcom_geni_serial_get_char(struct uart_port *uport)
343 struct qcom_geni_private_data *private_data = uport->private_data;
348 if (!private_data->poll_cached_bytes_cnt) {
349 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
350 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
352 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
353 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
355 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
356 word_cnt = status & RX_FIFO_WC_MSK;
360 if (word_cnt == 1 && (status & RX_LAST))
362 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
363 * treated as if it was BYTES_PER_FIFO_WORD.
365 private_data->poll_cached_bytes_cnt =
366 (status & RX_LAST_BYTE_VALID_MSK) >>
367 RX_LAST_BYTE_VALID_SHFT;
369 if (private_data->poll_cached_bytes_cnt == 0)
370 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
372 private_data->poll_cached_bytes =
373 readl(uport->membase + SE_GENI_RX_FIFOn);
376 private_data->poll_cached_bytes_cnt--;
377 ret = private_data->poll_cached_bytes & 0xff;
378 private_data->poll_cached_bytes >>= 8;
383 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
386 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
387 qcom_geni_serial_setup_tx(uport, 1);
388 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
389 M_TX_FIFO_WATERMARK_EN, true));
390 writel(c, uport->membase + SE_GENI_TX_FIFOn);
391 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
392 qcom_geni_serial_poll_tx_done(uport);
396 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
397 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch)
399 struct qcom_geni_private_data *private_data = uport->private_data;
401 private_data->write_cached_bytes =
402 (private_data->write_cached_bytes >> 8) | (ch << 24);
403 private_data->write_cached_bytes_cnt++;
405 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
406 writel(private_data->write_cached_bytes,
407 uport->membase + SE_GENI_TX_FIFOn);
408 private_data->write_cached_bytes_cnt = 0;
413 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
416 struct qcom_geni_private_data *private_data = uport->private_data;
419 u32 bytes_to_send = count;
421 for (i = 0; i < count; i++) {
423 * uart_console_write() adds a carriage return for each newline.
424 * Account for additional bytes to be written.
430 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
431 qcom_geni_serial_setup_tx(uport, bytes_to_send);
432 for (i = 0; i < count; ) {
433 size_t chars_to_write = 0;
434 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
437 * If the WM bit never set, then the Tx state machine is not
438 * in a valid state, so break, cancel/abort any existing
439 * command. Unfortunately the current data being written is
442 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
443 M_TX_FIFO_WATERMARK_EN, true))
445 chars_to_write = min_t(size_t, count - i, avail / 2);
446 uart_console_write(uport, s + i, chars_to_write,
447 qcom_geni_serial_wr_char);
448 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
449 SE_GENI_M_IRQ_CLEAR);
453 if (private_data->write_cached_bytes_cnt) {
454 private_data->write_cached_bytes >>= BITS_PER_BYTE *
455 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
456 writel(private_data->write_cached_bytes,
457 uport->membase + SE_GENI_TX_FIFOn);
458 private_data->write_cached_bytes_cnt = 0;
461 qcom_geni_serial_poll_tx_done(uport);
464 static void qcom_geni_serial_console_write(struct console *co, const char *s,
467 struct uart_port *uport;
468 struct qcom_geni_serial_port *port;
474 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
476 port = get_port_from_line(co->index, true);
480 uport = &port->uport;
481 if (oops_in_progress)
482 locked = spin_trylock_irqsave(&uport->lock, flags);
484 spin_lock_irqsave(&uport->lock, flags);
486 geni_status = readl(uport->membase + SE_GENI_STATUS);
488 /* Cancel the current write to log the fault */
490 geni_se_cancel_m_cmd(&port->se);
491 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
492 M_CMD_CANCEL_EN, true)) {
493 geni_se_abort_m_cmd(&port->se);
494 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
495 M_CMD_ABORT_EN, true);
496 writel(M_CMD_ABORT_EN, uport->membase +
497 SE_GENI_M_IRQ_CLEAR);
499 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
500 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
502 * It seems we can't interrupt existing transfers if all data
503 * has been sent, in which case we need to look for done first.
505 qcom_geni_serial_poll_tx_done(uport);
507 if (!uart_circ_empty(&uport->state->xmit)) {
508 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
509 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
510 uport->membase + SE_GENI_M_IRQ_EN);
514 __qcom_geni_serial_console_write(uport, s, count);
516 if (port->tx_remaining)
517 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
520 spin_unlock_irqrestore(&uport->lock, flags);
523 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
526 unsigned char buf[sizeof(u32)];
527 struct tty_port *tport;
528 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
530 tport = &uport->state->port;
531 for (i = 0; i < bytes; ) {
533 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
535 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
540 for (c = 0; c < chunk; c++) {
544 if (port->brk && buf[c] == 0) {
546 if (uart_handle_break(uport))
550 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
553 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
557 tty_flip_buffer_push(tport);
561 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
566 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
568 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
570 struct tty_port *tport;
571 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
572 u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
573 u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
576 tport = &uport->state->port;
577 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
581 ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
583 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
584 __func__, ret, bytes);
587 uport->icount.rx += ret;
588 tty_flip_buffer_push(tport);
592 static void qcom_geni_serial_start_tx(struct uart_port *uport)
597 status = readl(uport->membase + SE_GENI_STATUS);
598 if (status & M_GENI_CMD_ACTIVE)
601 if (!qcom_geni_serial_tx_empty(uport))
604 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
605 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
607 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
608 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
611 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
615 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
617 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
618 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
619 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
620 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
621 status = readl(uport->membase + SE_GENI_STATUS);
622 /* Possible stop tx is called multiple times. */
623 if (!(status & M_GENI_CMD_ACTIVE))
626 geni_se_cancel_m_cmd(&port->se);
627 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
628 M_CMD_CANCEL_EN, true)) {
629 geni_se_abort_m_cmd(&port->se);
630 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
631 M_CMD_ABORT_EN, true);
632 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
634 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
637 static void qcom_geni_serial_start_rx(struct uart_port *uport)
641 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
643 status = readl(uport->membase + SE_GENI_STATUS);
644 if (status & S_GENI_CMD_ACTIVE)
645 qcom_geni_serial_stop_rx(uport);
647 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
649 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
650 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
651 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
653 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
654 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
655 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
658 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
662 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
665 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
666 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
667 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
669 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
670 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
671 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
673 status = readl(uport->membase + SE_GENI_STATUS);
674 /* Possible stop rx is called multiple times. */
675 if (!(status & S_GENI_CMD_ACTIVE))
678 geni_se_cancel_s_cmd(&port->se);
679 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
680 S_CMD_CANCEL_EN, true);
682 * If timeout occurs secondary engine remains active
683 * and Abort sequence is executed.
685 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
686 /* Flush the Rx buffer */
687 if (s_irq_status & S_RX_FIFO_LAST_EN)
688 qcom_geni_serial_handle_rx(uport, true);
689 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
691 status = readl(uport->membase + SE_GENI_STATUS);
692 if (status & S_GENI_CMD_ACTIVE)
693 qcom_geni_serial_abort_rx(uport);
696 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
700 u32 last_word_byte_cnt;
701 u32 last_word_partial;
703 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
705 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
706 word_cnt = status & RX_FIFO_WC_MSK;
707 last_word_partial = status & RX_LAST;
708 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
709 RX_LAST_BYTE_VALID_SHFT;
713 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
714 if (last_word_partial && last_word_byte_cnt)
715 total_bytes += last_word_byte_cnt;
717 total_bytes += BYTES_PER_FIFO_WORD;
718 port->handle_rx(uport, total_bytes, drop);
721 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
724 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
725 struct circ_buf *xmit = &uport->state->xmit;
735 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
737 /* Complete the current tx command before taking newly added data */
739 pending = port->tx_remaining;
741 pending = uart_circ_chars_pending(xmit);
743 /* All data has been transmitted and acknowledged as received */
744 if (!pending && !status && done) {
745 qcom_geni_serial_stop_tx(uport);
746 goto out_write_wakeup;
749 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
750 avail *= BYTES_PER_FIFO_WORD;
753 chunk = min(avail, pending);
755 goto out_write_wakeup;
757 if (!port->tx_remaining) {
758 qcom_geni_serial_setup_tx(uport, pending);
759 port->tx_remaining = pending;
761 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
762 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
763 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
764 uport->membase + SE_GENI_M_IRQ_EN);
768 for (i = 0; i < chunk; ) {
769 unsigned int tx_bytes;
773 memset(buf, 0, sizeof(buf));
774 tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD);
776 for (c = 0; c < tx_bytes ; c++) {
777 buf[c] = xmit->buf[tail++];
778 tail &= UART_XMIT_SIZE - 1;
781 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
784 uport->icount.tx += tx_bytes;
785 remaining -= tx_bytes;
786 port->tx_remaining -= tx_bytes;
792 * The tx fifo watermark is level triggered and latched. Though we had
793 * cleared it in qcom_geni_serial_isr it will have already reasserted
794 * so we must clear it again here after our writes.
796 writel(M_TX_FIFO_WATERMARK_EN,
797 uport->membase + SE_GENI_M_IRQ_CLEAR);
800 if (!port->tx_remaining) {
801 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
802 if (irq_en & M_TX_FIFO_WATERMARK_EN)
803 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
804 uport->membase + SE_GENI_M_IRQ_EN);
807 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
808 uart_write_wakeup(uport);
811 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
817 struct uart_port *uport = dev;
818 bool drop_rx = false;
819 struct tty_port *tport = &uport->state->port;
820 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
822 if (uport->suspended)
825 spin_lock(&uport->lock);
827 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
828 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
829 geni_status = readl(uport->membase + SE_GENI_STATUS);
830 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
831 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
832 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
834 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
837 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
838 uport->icount.overrun++;
839 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
842 if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
843 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
844 geni_status & M_GENI_CMD_ACTIVE);
846 if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
847 if (s_irq_status & S_GP_IRQ_0_EN)
848 uport->icount.parity++;
850 } else if (s_irq_status & S_GP_IRQ_2_EN ||
851 s_irq_status & S_GP_IRQ_3_EN) {
856 if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
857 s_irq_status & S_RX_FIFO_LAST_EN)
858 qcom_geni_serial_handle_rx(uport, drop_rx);
861 uart_unlock_and_check_sysrq(uport);
866 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
868 struct uart_port *uport;
870 uport = &port->uport;
871 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
872 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
873 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
875 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
879 static void qcom_geni_serial_shutdown(struct uart_port *uport)
881 disable_irq(uport->irq);
884 static int qcom_geni_serial_port_setup(struct uart_port *uport)
886 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
887 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
891 proto = geni_se_read_proto(&port->se);
892 if (proto != GENI_SE_UART) {
893 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
897 qcom_geni_serial_stop_rx(uport);
899 get_tx_fifo_size(port);
901 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
903 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
904 if (port->rx_tx_swap) {
905 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
906 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
908 if (port->cts_rts_swap) {
909 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
910 pin_swap |= IO_MACRO_IO0_SEL;
912 /* Configure this register if RX-TX, CTS-RTS pins are swapped */
913 if (port->rx_tx_swap || port->cts_rts_swap)
914 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
917 * Make an unconditional cancel on the main sequencer to reset
918 * it else we could end up in data loss scenarios.
920 if (uart_console(uport))
921 qcom_geni_serial_poll_tx_done(uport);
922 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
924 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
925 geni_se_select_mode(&port->se, GENI_SE_FIFO);
931 static int qcom_geni_serial_startup(struct uart_port *uport)
934 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
937 ret = qcom_geni_serial_port_setup(uport);
941 enable_irq(uport->irq);
946 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk,
947 unsigned int *clk_div, unsigned int percent_tol)
950 unsigned long div, maxdiv;
952 unsigned long offset, abs_tol, achieved;
954 abs_tol = div_u64((u64)desired_clk * percent_tol, 100);
955 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
957 while (div <= maxdiv) {
958 mult = (u64)div * desired_clk;
959 if (mult != (unsigned long)mult)
962 offset = div * abs_tol;
963 freq = clk_round_rate(clk, mult - offset);
965 /* Can only get lower if we're done */
966 if (freq < mult - offset)
970 * Re-calculate div in case rounding skipped rates but we
971 * ended up at a good one, then check for a match.
973 div = DIV_ROUND_CLOSEST(freq, desired_clk);
974 achieved = DIV_ROUND_CLOSEST(freq, div);
975 if (achieved <= desired_clk + abs_tol &&
976 achieved >= desired_clk - abs_tol) {
981 div = DIV_ROUND_UP(freq, desired_clk);
987 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
988 unsigned int sampling_rate, unsigned int *clk_div)
990 unsigned long ser_clk;
991 unsigned long desired_clk;
993 desired_clk = baud * sampling_rate;
998 * try to find a clock rate within 2% tolerance, then within 5%
1000 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2);
1002 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5);
1007 static void qcom_geni_serial_set_termios(struct uart_port *uport,
1008 struct ktermios *termios, struct ktermios *old)
1017 unsigned int clk_div;
1019 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1020 unsigned long clk_rate;
1021 u32 ver, sampling_rate;
1022 unsigned int avg_bw_core;
1024 qcom_geni_serial_stop_rx(uport);
1026 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1029 sampling_rate = UART_OVERSAMPLING;
1030 /* Sampling rate is halved for IP versions >= 2.5 */
1031 ver = geni_se_get_qup_hw_version(&port->se);
1032 if (ver >= QUP_SE_VERSION_2_5)
1035 clk_rate = get_clk_div_rate(port->se.clk, baud,
1036 sampling_rate, &clk_div);
1038 dev_err(port->se.dev,
1039 "Couldn't find suitable clock rate for %u\n",
1040 baud * sampling_rate);
1041 goto out_restart_rx;
1044 dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n",
1045 baud * sampling_rate, clk_rate, clk_div);
1047 uport->uartclk = clk_rate;
1048 dev_pm_opp_set_rate(uport->dev, clk_rate);
1049 ser_clk_cfg = SER_CLK_EN;
1050 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1053 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1056 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1058 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1059 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1060 geni_icc_set_bw(&port->se);
1063 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1064 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1065 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1066 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1067 if (termios->c_cflag & PARENB) {
1068 tx_trans_cfg |= UART_TX_PAR_EN;
1069 rx_trans_cfg |= UART_RX_PAR_EN;
1070 tx_parity_cfg |= PAR_CALC_EN;
1071 rx_parity_cfg |= PAR_CALC_EN;
1072 if (termios->c_cflag & PARODD) {
1073 tx_parity_cfg |= PAR_ODD;
1074 rx_parity_cfg |= PAR_ODD;
1075 } else if (termios->c_cflag & CMSPAR) {
1076 tx_parity_cfg |= PAR_SPACE;
1077 rx_parity_cfg |= PAR_SPACE;
1079 tx_parity_cfg |= PAR_EVEN;
1080 rx_parity_cfg |= PAR_EVEN;
1083 tx_trans_cfg &= ~UART_TX_PAR_EN;
1084 rx_trans_cfg &= ~UART_RX_PAR_EN;
1085 tx_parity_cfg &= ~PAR_CALC_EN;
1086 rx_parity_cfg &= ~PAR_CALC_EN;
1090 bits_per_char = tty_get_char_size(termios->c_cflag);
1093 if (termios->c_cflag & CSTOPB)
1094 stop_bit_len = TX_STOP_BIT_LEN_2;
1096 stop_bit_len = TX_STOP_BIT_LEN_1;
1098 /* flow control, clear the CTS_MASK bit if using flow control. */
1099 if (termios->c_cflag & CRTSCTS)
1100 tx_trans_cfg &= ~UART_CTS_MASK;
1102 tx_trans_cfg |= UART_CTS_MASK;
1105 uart_update_timeout(uport, termios->c_cflag, baud);
1107 if (!uart_console(uport))
1108 writel(port->loopback,
1109 uport->membase + SE_UART_LOOPBACK_CFG);
1110 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1111 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1112 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1113 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1114 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1115 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1116 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1117 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1118 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1120 qcom_geni_serial_start_rx(uport);
1123 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1125 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1128 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1129 static int qcom_geni_console_setup(struct console *co, char *options)
1131 struct uart_port *uport;
1132 struct qcom_geni_serial_port *port;
1139 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1142 port = get_port_from_line(co->index, true);
1144 pr_err("Invalid line %d\n", co->index);
1145 return PTR_ERR(port);
1148 uport = &port->uport;
1150 if (unlikely(!uport->membase))
1154 ret = qcom_geni_serial_port_setup(uport);
1160 uart_parse_options(options, &baud, &parity, &bits, &flow);
1162 return uart_set_options(uport, co, baud, parity, bits, flow);
1165 static void qcom_geni_serial_earlycon_write(struct console *con,
1166 const char *s, unsigned int n)
1168 struct earlycon_device *dev = con->data;
1170 __qcom_geni_serial_console_write(&dev->port, s, n);
1173 #ifdef CONFIG_CONSOLE_POLL
1174 static int qcom_geni_serial_earlycon_read(struct console *con,
1175 char *s, unsigned int n)
1177 struct earlycon_device *dev = con->data;
1178 struct uart_port *uport = &dev->port;
1182 while (num_read < n) {
1183 ch = qcom_geni_serial_get_char(uport);
1184 if (ch == NO_POLL_CHAR)
1192 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1193 struct console *con)
1195 geni_se_setup_s_cmd(se, UART_START_READ, 0);
1196 con->read = qcom_geni_serial_earlycon_read;
1199 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1200 struct console *con) { }
1203 static struct qcom_geni_private_data earlycon_private_data;
1205 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1208 struct uart_port *uport = &dev->port;
1210 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1211 u32 rx_trans_cfg = 0;
1212 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1213 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1217 if (!uport->membase)
1220 uport->private_data = &earlycon_private_data;
1222 memset(&se, 0, sizeof(se));
1223 se.base = uport->membase;
1224 if (geni_se_read_proto(&se) != GENI_SE_UART)
1227 * Ignore Flow control.
1230 tx_trans_cfg = UART_CTS_MASK;
1231 bits_per_char = BITS_PER_BYTE;
1234 * Make an unconditional cancel on the main sequencer to reset
1235 * it else we could end up in data loss scenarios.
1237 qcom_geni_serial_poll_tx_done(uport);
1238 qcom_geni_serial_abort_rx(uport);
1239 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1241 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1242 geni_se_select_mode(&se, GENI_SE_FIFO);
1244 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1245 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1246 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1247 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1248 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1249 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1250 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1252 dev->con->write = qcom_geni_serial_earlycon_write;
1253 dev->con->setup = NULL;
1254 qcom_geni_serial_enable_early_read(&se, dev->con);
1258 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1259 qcom_geni_serial_earlycon_setup);
1261 static int __init console_register(struct uart_driver *drv)
1263 return uart_register_driver(drv);
1266 static void console_unregister(struct uart_driver *drv)
1268 uart_unregister_driver(drv);
1271 static struct console cons_ops = {
1273 .write = qcom_geni_serial_console_write,
1274 .device = uart_console_device,
1275 .setup = qcom_geni_console_setup,
1276 .flags = CON_PRINTBUFFER,
1278 .data = &qcom_geni_console_driver,
1281 static struct uart_driver qcom_geni_console_driver = {
1282 .owner = THIS_MODULE,
1283 .driver_name = "qcom_geni_console",
1284 .dev_name = "ttyMSM",
1285 .nr = GENI_UART_CONS_PORTS,
1289 static int console_register(struct uart_driver *drv)
1294 static void console_unregister(struct uart_driver *drv)
1297 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1299 static struct uart_driver qcom_geni_uart_driver = {
1300 .owner = THIS_MODULE,
1301 .driver_name = "qcom_geni_uart",
1302 .dev_name = "ttyHS",
1303 .nr = GENI_UART_PORTS,
1306 static void qcom_geni_serial_pm(struct uart_port *uport,
1307 unsigned int new_state, unsigned int old_state)
1309 struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1311 /* If we've never been called, treat it as off */
1312 if (old_state == UART_PM_STATE_UNDEFINED)
1313 old_state = UART_PM_STATE_OFF;
1315 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1316 geni_icc_enable(&port->se);
1317 geni_se_resources_on(&port->se);
1318 } else if (new_state == UART_PM_STATE_OFF &&
1319 old_state == UART_PM_STATE_ON) {
1320 geni_se_resources_off(&port->se);
1321 geni_icc_disable(&port->se);
1325 static const struct uart_ops qcom_geni_console_pops = {
1326 .tx_empty = qcom_geni_serial_tx_empty,
1327 .stop_tx = qcom_geni_serial_stop_tx,
1328 .start_tx = qcom_geni_serial_start_tx,
1329 .stop_rx = qcom_geni_serial_stop_rx,
1330 .start_rx = qcom_geni_serial_start_rx,
1331 .set_termios = qcom_geni_serial_set_termios,
1332 .startup = qcom_geni_serial_startup,
1333 .request_port = qcom_geni_serial_request_port,
1334 .config_port = qcom_geni_serial_config_port,
1335 .shutdown = qcom_geni_serial_shutdown,
1336 .type = qcom_geni_serial_get_type,
1337 .set_mctrl = qcom_geni_serial_set_mctrl,
1338 .get_mctrl = qcom_geni_serial_get_mctrl,
1339 #ifdef CONFIG_CONSOLE_POLL
1340 .poll_get_char = qcom_geni_serial_get_char,
1341 .poll_put_char = qcom_geni_serial_poll_put_char,
1343 .pm = qcom_geni_serial_pm,
1346 static const struct uart_ops qcom_geni_uart_pops = {
1347 .tx_empty = qcom_geni_serial_tx_empty,
1348 .stop_tx = qcom_geni_serial_stop_tx,
1349 .start_tx = qcom_geni_serial_start_tx,
1350 .stop_rx = qcom_geni_serial_stop_rx,
1351 .set_termios = qcom_geni_serial_set_termios,
1352 .startup = qcom_geni_serial_startup,
1353 .request_port = qcom_geni_serial_request_port,
1354 .config_port = qcom_geni_serial_config_port,
1355 .shutdown = qcom_geni_serial_shutdown,
1356 .type = qcom_geni_serial_get_type,
1357 .set_mctrl = qcom_geni_serial_set_mctrl,
1358 .get_mctrl = qcom_geni_serial_get_mctrl,
1359 .pm = qcom_geni_serial_pm,
1362 static int qcom_geni_serial_probe(struct platform_device *pdev)
1366 struct qcom_geni_serial_port *port;
1367 struct uart_port *uport;
1368 struct resource *res;
1370 bool console = false;
1371 struct uart_driver *drv;
1373 if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1377 drv = &qcom_geni_console_driver;
1378 line = of_alias_get_id(pdev->dev.of_node, "serial");
1380 drv = &qcom_geni_uart_driver;
1381 line = of_alias_get_id(pdev->dev.of_node, "serial");
1382 if (line == -ENODEV) /* compat with non-standard aliases */
1383 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1386 port = get_port_from_line(line, console);
1388 dev_err(&pdev->dev, "Invalid line %d\n", line);
1389 return PTR_ERR(port);
1392 uport = &port->uport;
1393 /* Don't allow 2 drivers to access the same port */
1394 if (uport->private_data)
1397 uport->dev = &pdev->dev;
1398 port->se.dev = &pdev->dev;
1399 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1400 port->se.clk = devm_clk_get(&pdev->dev, "se");
1401 if (IS_ERR(port->se.clk)) {
1402 ret = PTR_ERR(port->se.clk);
1403 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1407 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1410 uport->mapbase = res->start;
1412 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1413 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1414 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1417 port->rx_fifo = devm_kcalloc(uport->dev,
1418 port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1423 ret = geni_icc_get(&port->se, NULL);
1426 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1427 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1429 /* Set BW for register access */
1430 ret = geni_icc_set_bw(&port->se);
1434 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1435 "qcom_geni_serial_%s%d",
1436 uart_console(uport) ? "console" : "uart", uport->line);
1440 irq = platform_get_irq(pdev, 0);
1444 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1447 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1449 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1450 port->rx_tx_swap = true;
1452 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1453 port->cts_rts_swap = true;
1455 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1458 /* OPP table is optional */
1459 ret = devm_pm_opp_of_add_table(&pdev->dev);
1460 if (ret && ret != -ENODEV) {
1461 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1465 port->private_data.drv = drv;
1466 uport->private_data = &port->private_data;
1467 platform_set_drvdata(pdev, port);
1468 port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1470 ret = uart_add_one_port(drv, uport);
1474 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1475 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1476 IRQF_TRIGGER_HIGH, port->name, uport);
1478 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1479 uart_remove_one_port(drv, uport);
1484 * Set pm_runtime status as ACTIVE so that wakeup_irq gets
1485 * enabled/disabled from dev_pm_arm_wake_irq during system
1486 * suspend/resume respectively.
1488 pm_runtime_set_active(&pdev->dev);
1490 if (port->wakeup_irq > 0) {
1491 device_init_wakeup(&pdev->dev, true);
1492 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1495 device_init_wakeup(&pdev->dev, false);
1496 uart_remove_one_port(drv, uport);
1504 static int qcom_geni_serial_remove(struct platform_device *pdev)
1506 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1507 struct uart_driver *drv = port->private_data.drv;
1509 dev_pm_clear_wake_irq(&pdev->dev);
1510 device_init_wakeup(&pdev->dev, false);
1511 uart_remove_one_port(drv, &port->uport);
1516 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1518 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1519 struct uart_port *uport = &port->uport;
1520 struct qcom_geni_private_data *private_data = uport->private_data;
1523 * This is done so we can hit the lowest possible state in suspend
1524 * even with no_console_suspend
1526 if (uart_console(uport)) {
1527 geni_icc_set_tag(&port->se, 0x3);
1528 geni_icc_set_bw(&port->se);
1530 return uart_suspend_port(private_data->drv, uport);
1533 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1536 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1537 struct uart_port *uport = &port->uport;
1538 struct qcom_geni_private_data *private_data = uport->private_data;
1540 ret = uart_resume_port(private_data->drv, uport);
1541 if (uart_console(uport)) {
1542 geni_icc_set_tag(&port->se, 0x7);
1543 geni_icc_set_bw(&port->se);
1548 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1549 SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1550 qcom_geni_serial_sys_resume)
1553 static const struct of_device_id qcom_geni_serial_match_table[] = {
1554 { .compatible = "qcom,geni-debug-uart", },
1555 { .compatible = "qcom,geni-uart", },
1558 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1560 static struct platform_driver qcom_geni_serial_platform_driver = {
1561 .remove = qcom_geni_serial_remove,
1562 .probe = qcom_geni_serial_probe,
1564 .name = "qcom_geni_serial",
1565 .of_match_table = qcom_geni_serial_match_table,
1566 .pm = &qcom_geni_serial_pm_ops,
1570 static int __init qcom_geni_serial_init(void)
1574 ret = console_register(&qcom_geni_console_driver);
1578 ret = uart_register_driver(&qcom_geni_uart_driver);
1580 console_unregister(&qcom_geni_console_driver);
1584 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1586 console_unregister(&qcom_geni_console_driver);
1587 uart_unregister_driver(&qcom_geni_uart_driver);
1591 module_init(qcom_geni_serial_init);
1593 static void __exit qcom_geni_serial_exit(void)
1595 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1596 console_unregister(&qcom_geni_console_driver);
1597 uart_unregister_driver(&qcom_geni_uart_driver);
1599 module_exit(qcom_geni_serial_exit);
1601 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1602 MODULE_LICENSE("GPL v2");