drivers/tty/serial/qcom_geni_serial.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
   3
   4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */
   5 #define __DISABLE_TRACE_MMIO__
   6
   7 #include <linux/clk.h>
   8 #include <linux/console.h>
   9 #include <linux/io.h>
  10 #include <linux/iopoll.h>
  11 #include <linux/irq.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/of_device.h>
  15 #include <linux/pm_opp.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/pm_runtime.h>
  18 #include <linux/pm_wakeirq.h>
  19 #include <linux/qcom-geni-se.h>
  20 #include <linux/serial.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/slab.h>
  23 #include <linux/tty.h>
  24 #include <linux/tty_flip.h>
  25 #include <dt-bindings/interconnect/qcom,icc.h>
  26
  27 /* UART specific GENI registers */
  28 #define SE_UART_LOOPBACK_CFG            0x22c
  29 #define SE_UART_IO_MACRO_CTRL           0x240
  30 #define SE_UART_TX_TRANS_CFG            0x25c
  31 #define SE_UART_TX_WORD_LEN             0x268
  32 #define SE_UART_TX_STOP_BIT_LEN         0x26c
  33 #define SE_UART_TX_TRANS_LEN            0x270
  34 #define SE_UART_RX_TRANS_CFG            0x280
  35 #define SE_UART_RX_WORD_LEN             0x28c
  36 #define SE_UART_RX_STALE_CNT            0x294
  37 #define SE_UART_TX_PARITY_CFG           0x2a4
  38 #define SE_UART_RX_PARITY_CFG           0x2a8
  39 #define SE_UART_MANUAL_RFR              0x2ac
  40
  41 /* SE_UART_TRANS_CFG */
  42 #define UART_TX_PAR_EN          BIT(0)
  43 #define UART_CTS_MASK           BIT(1)
  44
  45 /* SE_UART_TX_WORD_LEN */
  46 #define TX_WORD_LEN_MSK         GENMASK(9, 0)
  47
  48 /* SE_UART_TX_STOP_BIT_LEN */
  49 #define TX_STOP_BIT_LEN_MSK     GENMASK(23, 0)
  50 #define TX_STOP_BIT_LEN_1       0
  51 #define TX_STOP_BIT_LEN_1_5     1
  52 #define TX_STOP_BIT_LEN_2       2
  53
  54 /* SE_UART_TX_TRANS_LEN */
  55 #define TX_TRANS_LEN_MSK        GENMASK(23, 0)
  56
  57 /* SE_UART_RX_TRANS_CFG */
  58 #define UART_RX_INS_STATUS_BIT  BIT(2)
  59 #define UART_RX_PAR_EN          BIT(3)
  60
  61 /* SE_UART_RX_WORD_LEN */
  62 #define RX_WORD_LEN_MASK        GENMASK(9, 0)
  63
  64 /* SE_UART_RX_STALE_CNT */
  65 #define RX_STALE_CNT            GENMASK(23, 0)
  66
  67 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
  68 #define PAR_CALC_EN             BIT(0)
  69 #define PAR_MODE_MSK            GENMASK(2, 1)
  70 #define PAR_MODE_SHFT           1
  71 #define PAR_EVEN                0x00
  72 #define PAR_ODD                 0x01
  73 #define PAR_SPACE               0x10
  74 #define PAR_MARK                0x11
  75
  76 /* SE_UART_MANUAL_RFR register fields */
  77 #define UART_MANUAL_RFR_EN      BIT(31)
  78 #define UART_RFR_NOT_READY      BIT(1)
  79 #define UART_RFR_READY          BIT(0)
  80
  81 /* UART M_CMD OP codes */
  82 #define UART_START_TX           0x1
  83 #define UART_START_BREAK        0x4
  84 #define UART_STOP_BREAK         0x5
  85 /* UART S_CMD OP codes */
  86 #define UART_START_READ         0x1
  87 #define UART_PARAM              0x1
  88
  89 #define UART_OVERSAMPLING       32
  90 #define STALE_TIMEOUT           16
  91 #define DEFAULT_BITS_PER_CHAR   10
  92 #define GENI_UART_CONS_PORTS    1
  93 #define GENI_UART_PORTS         3
  94 #define DEF_FIFO_DEPTH_WORDS    16
  95 #define DEF_TX_WM               2
  96 #define DEF_FIFO_WIDTH_BITS     32
  97 #define UART_RX_WM              2
  98
  99 /* SE_UART_LOOPBACK_CFG */
 100 #define RX_TX_SORTED    BIT(0)
 101 #define CTS_RTS_SORTED  BIT(1)
 102 #define RX_TX_CTS_RTS_SORTED    (RX_TX_SORTED | CTS_RTS_SORTED)
 103
 104 /* UART pin swap value */
 105 #define DEFAULT_IO_MACRO_IO0_IO1_MASK           GENMASK(3, 0)
 106 #define IO_MACRO_IO0_SEL                0x3
 107 #define DEFAULT_IO_MACRO_IO2_IO3_MASK           GENMASK(15, 4)
 108 #define IO_MACRO_IO2_IO3_SWAP           0x4640
 109
 110 /* We always configure 4 bytes per FIFO word */
 111 #define BYTES_PER_FIFO_WORD             4
 112
 113 struct qcom_geni_private_data {
 114         /* NOTE: earlycon port will have NULL here */
 115         struct uart_driver *drv;
 116
 117         u32 poll_cached_bytes;
 118         unsigned int poll_cached_bytes_cnt;
 119
 120         u32 write_cached_bytes;
 121         unsigned int write_cached_bytes_cnt;
 122 };
 123
 124 struct qcom_geni_serial_port {
 125         struct uart_port uport;
 126         struct geni_se se;
 127         const char *name;
 128         u32 tx_fifo_depth;
 129         u32 tx_fifo_width;
 130         u32 rx_fifo_depth;
 131         bool setup;
 132         int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
 133         unsigned int baud;
 134         void *rx_fifo;
 135         u32 loopback;
 136         bool brk;
 137
 138         unsigned int tx_remaining;
 139         int wakeup_irq;
 140         bool rx_tx_swap;
 141         bool cts_rts_swap;
 142
 143         struct qcom_geni_private_data private_data;
 144 };
 145
 146 static const struct uart_ops qcom_geni_console_pops;
 147 static const struct uart_ops qcom_geni_uart_pops;
 148 static struct uart_driver qcom_geni_console_driver;
 149 static struct uart_driver qcom_geni_uart_driver;
 150 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
 151 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
 152 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
 153 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
 154 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
 155
 156 #define to_dev_port(ptr, member) \
 157                 container_of(ptr, struct qcom_geni_serial_port, member)
 158
 159 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
 160         [0] = {
 161                 .uport = {
 162                                 .iotype = UPIO_MEM,
 163                                 .ops = &qcom_geni_uart_pops,
 164                                 .flags = UPF_BOOT_AUTOCONF,
 165                                 .line = 0,
 166                 },
 167         },
 168         [1] = {
 169                 .uport = {
 170                                 .iotype = UPIO_MEM,
 171                                 .ops = &qcom_geni_uart_pops,
 172                                 .flags = UPF_BOOT_AUTOCONF,
 173                                 .line = 1,
 174                 },
 175         },
 176         [2] = {
 177                 .uport = {
 178                                 .iotype = UPIO_MEM,
 179                                 .ops = &qcom_geni_uart_pops,
 180                                 .flags = UPF_BOOT_AUTOCONF,
 181                                 .line = 2,
 182                 },
 183         },
 184 };
 185
 186 static struct qcom_geni_serial_port qcom_geni_console_port = {
 187         .uport = {
 188                 .iotype = UPIO_MEM,
 189                 .ops = &qcom_geni_console_pops,
 190                 .flags = UPF_BOOT_AUTOCONF,
 191                 .line = 0,
 192         },
 193 };
 194
 195 static int qcom_geni_serial_request_port(struct uart_port *uport)
 196 {
 197         struct platform_device *pdev = to_platform_device(uport->dev);
 198         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 199
 200         uport->membase = devm_platform_ioremap_resource(pdev, 0);
 201         if (IS_ERR(uport->membase))
 202                 return PTR_ERR(uport->membase);
 203         port->se.base = uport->membase;
 204         return 0;
 205 }
 206
 207 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
 208 {
 209         if (cfg_flags & UART_CONFIG_TYPE) {
 210                 uport->type = PORT_MSM;
 211                 qcom_geni_serial_request_port(uport);
 212         }
 213 }
 214
 215 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
 216 {
 217         unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
 218         u32 geni_ios;
 219
 220         if (uart_console(uport)) {
 221                 mctrl |= TIOCM_CTS;
 222         } else {
 223                 geni_ios = readl(uport->membase + SE_GENI_IOS);
 224                 if (!(geni_ios & IO2_DATA_IN))
 225                         mctrl |= TIOCM_CTS;
 226         }
 227
 228         return mctrl;
 229 }
 230
 231 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
 232                                                         unsigned int mctrl)
 233 {
 234         u32 uart_manual_rfr = 0;
 235         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 236
 237         if (uart_console(uport))
 238                 return;
 239
 240         if (mctrl & TIOCM_LOOP)
 241                 port->loopback = RX_TX_CTS_RTS_SORTED;
 242
 243         if (!(mctrl & TIOCM_RTS) && !uport->suspended)
 244                 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
 245         writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
 246 }
 247
 248 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
 249 {
 250         return "MSM";
 251 }
 252
 253 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
 254 {
 255         struct qcom_geni_serial_port *port;
 256         int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
 257
 258         if (line < 0 || line >= nr_ports)
 259                 return ERR_PTR(-ENXIO);
 260
 261         port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
 262         return port;
 263 }
 264
 265 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
 266                                 int offset, int field, bool set)
 267 {
 268         u32 reg;
 269         struct qcom_geni_serial_port *port;
 270         unsigned int baud;
 271         unsigned int fifo_bits;
 272         unsigned long timeout_us = 20000;
 273         struct qcom_geni_private_data *private_data = uport->private_data;
 274
 275         if (private_data->drv) {
 276                 port = to_dev_port(uport, uport);
 277                 baud = port->baud;
 278                 if (!baud)
 279                         baud = 115200;
 280                 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
 281                 /*
 282                  * Total polling iterations based on FIFO worth of bytes to be
 283                  * sent at current baud. Add a little fluff to the wait.
 284                  */
 285                 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
 286         }
 287
 288         /*
 289          * Use custom implementation instead of readl_poll_atomic since ktimer
 290          * is not ready at the time of early console.
 291          */
 292         timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
 293         while (timeout_us) {
 294                 reg = readl(uport->membase + offset);
 295                 if ((bool)(reg & field) == set)
 296                         return true;
 297                 udelay(10);
 298                 timeout_us -= 10;
 299         }
 300         return false;
 301 }
 302
 303 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
 304 {
 305         u32 m_cmd;
 306
 307         writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
 308         m_cmd = UART_START_TX << M_OPCODE_SHFT;
 309         writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
 310 }
 311
 312 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
 313 {
 314         int done;
 315         u32 irq_clear = M_CMD_DONE_EN;
 316
 317         done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 318                                                 M_CMD_DONE_EN, true);
 319         if (!done) {
 320                 writel(M_GENI_CMD_ABORT, uport->membase +
 321                                                 SE_GENI_M_CMD_CTRL_REG);
 322                 irq_clear |= M_CMD_ABORT_EN;
 323                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 324                                                         M_CMD_ABORT_EN, true);
 325         }
 326         writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
 327 }
 328
 329 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
 330 {
 331         u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
 332
 333         writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
 334         qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
 335                                         S_GENI_CMD_ABORT, false);
 336         writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
 337         writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
 338 }
 339
 340 #ifdef CONFIG_CONSOLE_POLL
 341
 342 static int qcom_geni_serial_get_char(struct uart_port *uport)
 343 {
 344         struct qcom_geni_private_data *private_data = uport->private_data;
 345         u32 status;
 346         u32 word_cnt;
 347         int ret;
 348
 349         if (!private_data->poll_cached_bytes_cnt) {
 350                 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 351                 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 352
 353                 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 354                 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 355
 356                 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 357                 word_cnt = status & RX_FIFO_WC_MSK;
 358                 if (!word_cnt)
 359                         return NO_POLL_CHAR;
 360
 361                 if (word_cnt == 1 && (status & RX_LAST))
 362                         /*
 363                          * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
 364                          * treated as if it was BYTES_PER_FIFO_WORD.
 365                          */
 366                         private_data->poll_cached_bytes_cnt =
 367                                 (status & RX_LAST_BYTE_VALID_MSK) >>
 368                                 RX_LAST_BYTE_VALID_SHFT;
 369
 370                 if (private_data->poll_cached_bytes_cnt == 0)
 371                         private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
 372
 373                 private_data->poll_cached_bytes =
 374                         readl(uport->membase + SE_GENI_RX_FIFOn);
 375         }
 376
 377         private_data->poll_cached_bytes_cnt--;
 378         ret = private_data->poll_cached_bytes & 0xff;
 379         private_data->poll_cached_bytes >>= 8;
 380
 381         return ret;
 382 }
 383
 384 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
 385                                                         unsigned char c)
 386 {
 387         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 388         qcom_geni_serial_setup_tx(uport, 1);
 389         WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 390                                                 M_TX_FIFO_WATERMARK_EN, true));
 391         writel(c, uport->membase + SE_GENI_TX_FIFOn);
 392         writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 393         qcom_geni_serial_poll_tx_done(uport);
 394 }
 395 #endif
 396
 397 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
 398 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch)
 399 {
 400         struct qcom_geni_private_data *private_data = uport->private_data;
 401
 402         private_data->write_cached_bytes =
 403                 (private_data->write_cached_bytes >> 8) | (ch << 24);
 404         private_data->write_cached_bytes_cnt++;
 405
 406         if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
 407                 writel(private_data->write_cached_bytes,
 408                        uport->membase + SE_GENI_TX_FIFOn);
 409                 private_data->write_cached_bytes_cnt = 0;
 410         }
 411 }
 412
 413 static void
 414 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
 415                                  unsigned int count)
 416 {
 417         struct qcom_geni_private_data *private_data = uport->private_data;
 418
 419         int i;
 420         u32 bytes_to_send = count;
 421
 422         for (i = 0; i < count; i++) {
 423                 /*
 424                  * uart_console_write() adds a carriage return for each newline.
 425                  * Account for additional bytes to be written.
 426                  */
 427                 if (s[i] == '\n')
 428                         bytes_to_send++;
 429         }
 430
 431         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 432         qcom_geni_serial_setup_tx(uport, bytes_to_send);
 433         for (i = 0; i < count; ) {
 434                 size_t chars_to_write = 0;
 435                 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
 436
 437                 /*
 438                  * If the WM bit never set, then the Tx state machine is not
 439                  * in a valid state, so break, cancel/abort any existing
 440                  * command. Unfortunately the current data being written is
 441                  * lost.
 442                  */
 443                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 444                                                 M_TX_FIFO_WATERMARK_EN, true))
 445                         break;
 446                 chars_to_write = min_t(size_t, count - i, avail / 2);
 447                 uart_console_write(uport, s + i, chars_to_write,
 448                                                 qcom_geni_serial_wr_char);
 449                 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
 450                                                         SE_GENI_M_IRQ_CLEAR);
 451                 i += chars_to_write;
 452         }
 453
 454         if (private_data->write_cached_bytes_cnt) {
 455                 private_data->write_cached_bytes >>= BITS_PER_BYTE *
 456                         (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
 457                 writel(private_data->write_cached_bytes,
 458                        uport->membase + SE_GENI_TX_FIFOn);
 459                 private_data->write_cached_bytes_cnt = 0;
 460         }
 461
 462         qcom_geni_serial_poll_tx_done(uport);
 463 }
 464
 465 static void qcom_geni_serial_console_write(struct console *co, const char *s,
 466                               unsigned int count)
 467 {
 468         struct uart_port *uport;
 469         struct qcom_geni_serial_port *port;
 470         bool locked = true;
 471         unsigned long flags;
 472         u32 geni_status;
 473         u32 irq_en;
 474
 475         WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
 476
 477         port = get_port_from_line(co->index, true);
 478         if (IS_ERR(port))
 479                 return;
 480
 481         uport = &port->uport;
 482         if (oops_in_progress)
 483                 locked = spin_trylock_irqsave(&uport->lock, flags);
 484         else
 485                 spin_lock_irqsave(&uport->lock, flags);
 486
 487         geni_status = readl(uport->membase + SE_GENI_STATUS);
 488
 489         /* Cancel the current write to log the fault */
 490         if (!locked) {
 491                 geni_se_cancel_m_cmd(&port->se);
 492                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 493                                                 M_CMD_CANCEL_EN, true)) {
 494                         geni_se_abort_m_cmd(&port->se);
 495                         qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 496                                                         M_CMD_ABORT_EN, true);
 497                         writel(M_CMD_ABORT_EN, uport->membase +
 498                                                         SE_GENI_M_IRQ_CLEAR);
 499                 }
 500                 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 501         } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
 502                 /*
 503                  * It seems we can't interrupt existing transfers if all data
 504                  * has been sent, in which case we need to look for done first.
 505                  */
 506                 qcom_geni_serial_poll_tx_done(uport);
 507
 508                 if (!uart_circ_empty(&uport->state->xmit)) {
 509                         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 510                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 511                                         uport->membase + SE_GENI_M_IRQ_EN);
 512                 }
 513         }
 514
 515         __qcom_geni_serial_console_write(uport, s, count);
 516
 517         if (port->tx_remaining)
 518                 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
 519
 520         if (locked)
 521                 spin_unlock_irqrestore(&uport->lock, flags);
 522 }
 523
 524 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 525 {
 526         u32 i;
 527         unsigned char buf[sizeof(u32)];
 528         struct tty_port *tport;
 529         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 530
 531         tport = &uport->state->port;
 532         for (i = 0; i < bytes; ) {
 533                 int c;
 534                 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
 535
 536                 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
 537                 i += chunk;
 538                 if (drop)
 539                         continue;
 540
 541                 for (c = 0; c < chunk; c++) {
 542                         int sysrq;
 543
 544                         uport->icount.rx++;
 545                         if (port->brk && buf[c] == 0) {
 546                                 port->brk = false;
 547                                 if (uart_handle_break(uport))
 548                                         continue;
 549                         }
 550
 551                         sysrq = uart_prepare_sysrq_char(uport, buf[c]);
 552
 553                         if (!sysrq)
 554                                 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
 555                 }
 556         }
 557         if (!drop)
 558                 tty_flip_buffer_push(tport);
 559         return 0;
 560 }
 561 #else
 562 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 563 {
 564         return -EPERM;
 565 }
 566
 567 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
 568
 569 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
 570 {
 571         struct tty_port *tport;
 572         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 573         u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
 574         u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
 575         int ret;
 576
 577         tport = &uport->state->port;
 578         ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
 579         if (drop)
 580                 return 0;
 581
 582         ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
 583         if (ret != bytes) {
 584                 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
 585                                 __func__, ret, bytes);
 586                 WARN_ON_ONCE(1);
 587         }
 588         uport->icount.rx += ret;
 589         tty_flip_buffer_push(tport);
 590         return ret;
 591 }
 592
 593 static void qcom_geni_serial_start_tx(struct uart_port *uport)
 594 {
 595         u32 irq_en;
 596         u32 status;
 597
 598         status = readl(uport->membase + SE_GENI_STATUS);
 599         if (status & M_GENI_CMD_ACTIVE)
 600                 return;
 601
 602         if (!qcom_geni_serial_tx_empty(uport))
 603                 return;
 604
 605         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 606         irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
 607
 608         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 609         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 610 }
 611
 612 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
 613 {
 614         u32 irq_en;
 615         u32 status;
 616         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 617
 618         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 619         irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
 620         writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
 621         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 622         status = readl(uport->membase + SE_GENI_STATUS);
 623         /* Possible stop tx is called multiple times. */
 624         if (!(status & M_GENI_CMD_ACTIVE))
 625                 return;
 626
 627         geni_se_cancel_m_cmd(&port->se);
 628         if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 629                                                 M_CMD_CANCEL_EN, true)) {
 630                 geni_se_abort_m_cmd(&port->se);
 631                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 632                                                 M_CMD_ABORT_EN, true);
 633                 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 634         }
 635         writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 636 }
 637
 638 static void qcom_geni_serial_start_rx(struct uart_port *uport)
 639 {
 640         u32 irq_en;
 641         u32 status;
 642         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 643
 644         status = readl(uport->membase + SE_GENI_STATUS);
 645         if (status & S_GENI_CMD_ACTIVE)
 646                 qcom_geni_serial_stop_rx(uport);
 647
 648         geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
 649
 650         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 651         irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
 652         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 653
 654         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 655         irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
 656         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 657 }
 658
 659 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
 660 {
 661         u32 irq_en;
 662         u32 status;
 663         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 664         u32 s_irq_status;
 665
 666         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 667         irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
 668         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 669
 670         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 671         irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
 672         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 673
 674         status = readl(uport->membase + SE_GENI_STATUS);
 675         /* Possible stop rx is called multiple times. */
 676         if (!(status & S_GENI_CMD_ACTIVE))
 677                 return;
 678
 679         geni_se_cancel_s_cmd(&port->se);
 680         qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
 681                                         S_CMD_CANCEL_EN, true);
 682         /*
 683          * If timeout occurs secondary engine remains active
 684          * and Abort sequence is executed.
 685          */
 686         s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 687         /* Flush the Rx buffer */
 688         if (s_irq_status & S_RX_FIFO_LAST_EN)
 689                 qcom_geni_serial_handle_rx(uport, true);
 690         writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 691
 692         status = readl(uport->membase + SE_GENI_STATUS);
 693         if (status & S_GENI_CMD_ACTIVE)
 694                 qcom_geni_serial_abort_rx(uport);
 695 }
 696
 697 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
 698 {
 699         u32 status;
 700         u32 word_cnt;
 701         u32 last_word_byte_cnt;
 702         u32 last_word_partial;
 703         u32 total_bytes;
 704         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 705
 706         status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 707         word_cnt = status & RX_FIFO_WC_MSK;
 708         last_word_partial = status & RX_LAST;
 709         last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
 710                                                 RX_LAST_BYTE_VALID_SHFT;
 711
 712         if (!word_cnt)
 713                 return;
 714         total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
 715         if (last_word_partial && last_word_byte_cnt)
 716                 total_bytes += last_word_byte_cnt;
 717         else
 718                 total_bytes += BYTES_PER_FIFO_WORD;
 719         port->handle_rx(uport, total_bytes, drop);
 720 }
 721
 722 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
 723                 bool active)
 724 {
 725         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 726         struct circ_buf *xmit = &uport->state->xmit;
 727         size_t avail;
 728         size_t remaining;
 729         size_t pending;
 730         int i;
 731         u32 status;
 732         u32 irq_en;
 733         unsigned int chunk;
 734         int tail;
 735
 736         status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
 737
 738         /* Complete the current tx command before taking newly added data */
 739         if (active)
 740                 pending = port->tx_remaining;
 741         else
 742                 pending = uart_circ_chars_pending(xmit);
 743
 744         /* All data has been transmitted and acknowledged as received */
 745         if (!pending && !status && done) {
 746                 qcom_geni_serial_stop_tx(uport);
 747                 goto out_write_wakeup;
 748         }
 749
 750         avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
 751         avail *= BYTES_PER_FIFO_WORD;
 752
 753         tail = xmit->tail;
 754         chunk = min(avail, pending);
 755         if (!chunk)
 756                 goto out_write_wakeup;
 757
 758         if (!port->tx_remaining) {
 759                 qcom_geni_serial_setup_tx(uport, pending);
 760                 port->tx_remaining = pending;
 761
 762                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 763                 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
 764                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 765                                         uport->membase + SE_GENI_M_IRQ_EN);
 766         }
 767
 768         remaining = chunk;
 769         for (i = 0; i < chunk; ) {
 770                 unsigned int tx_bytes;
 771                 u8 buf[sizeof(u32)];
 772                 int c;
 773
 774                 memset(buf, 0, sizeof(buf));
 775                 tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD);
 776
 777                 for (c = 0; c < tx_bytes ; c++) {
 778                         buf[c] = xmit->buf[tail++];
 779                         tail &= UART_XMIT_SIZE - 1;
 780                 }
 781
 782                 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
 783
 784                 i += tx_bytes;
 785                 uport->icount.tx += tx_bytes;
 786                 remaining -= tx_bytes;
 787                 port->tx_remaining -= tx_bytes;
 788         }
 789
 790         xmit->tail = tail;
 791
 792         /*
 793          * The tx fifo watermark is level triggered and latched. Though we had
 794          * cleared it in qcom_geni_serial_isr it will have already reasserted
 795          * so we must clear it again here after our writes.
 796          */
 797         writel(M_TX_FIFO_WATERMARK_EN,
 798                         uport->membase + SE_GENI_M_IRQ_CLEAR);
 799
 800 out_write_wakeup:
 801         if (!port->tx_remaining) {
 802                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 803                 if (irq_en & M_TX_FIFO_WATERMARK_EN)
 804                         writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
 805                                         uport->membase + SE_GENI_M_IRQ_EN);
 806         }
 807
 808         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 809                 uart_write_wakeup(uport);
 810 }
 811
 812 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
 813 {
 814         u32 m_irq_en;
 815         u32 m_irq_status;
 816         u32 s_irq_status;
 817         u32 geni_status;
 818         struct uart_port *uport = dev;
 819         bool drop_rx = false;
 820         struct tty_port *tport = &uport->state->port;
 821         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 822
 823         if (uport->suspended)
 824                 return IRQ_NONE;
 825
 826         spin_lock(&uport->lock);
 827
 828         m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 829         s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 830         geni_status = readl(uport->membase + SE_GENI_STATUS);
 831         m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 832         writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 833         writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 834
 835         if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
 836                 goto out_unlock;
 837
 838         if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
 839                 uport->icount.overrun++;
 840                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 841         }
 842
 843         if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
 844                 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
 845                                         geni_status & M_GENI_CMD_ACTIVE);
 846
 847         if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
 848                 if (s_irq_status & S_GP_IRQ_0_EN)
 849                         uport->icount.parity++;
 850                 drop_rx = true;
 851         } else if (s_irq_status & S_GP_IRQ_2_EN ||
 852                                         s_irq_status & S_GP_IRQ_3_EN) {
 853                 uport->icount.brk++;
 854                 port->brk = true;
 855         }
 856
 857         if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
 858                                         s_irq_status & S_RX_FIFO_LAST_EN)
 859                 qcom_geni_serial_handle_rx(uport, drop_rx);
 860
 861 out_unlock:
 862         uart_unlock_and_check_sysrq(uport);
 863
 864         return IRQ_HANDLED;
 865 }
 866
 867 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
 868 {
 869         struct uart_port *uport;
 870
 871         uport = &port->uport;
 872         port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
 873         port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
 874         port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
 875         uport->fifosize =
 876                 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
 877 }
 878
 879
 880 static void qcom_geni_serial_shutdown(struct uart_port *uport)
 881 {
 882         disable_irq(uport->irq);
 883 }
 884
 885 static int qcom_geni_serial_port_setup(struct uart_port *uport)
 886 {
 887         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 888         u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
 889         u32 proto;
 890         u32 pin_swap;
 891
 892         proto = geni_se_read_proto(&port->se);
 893         if (proto != GENI_SE_UART) {
 894                 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
 895                 return -ENXIO;
 896         }
 897
 898         qcom_geni_serial_stop_rx(uport);
 899
 900         get_tx_fifo_size(port);
 901
 902         writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
 903
 904         pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
 905         if (port->rx_tx_swap) {
 906                 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
 907                 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
 908         }
 909         if (port->cts_rts_swap) {
 910                 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
 911                 pin_swap |= IO_MACRO_IO0_SEL;
 912         }
 913         /* Configure this register if RX-TX, CTS-RTS pins are swapped */
 914         if (port->rx_tx_swap || port->cts_rts_swap)
 915                 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
 916
 917         /*
 918          * Make an unconditional cancel on the main sequencer to reset
 919          * it else we could end up in data loss scenarios.
 920          */
 921         if (uart_console(uport))
 922                 qcom_geni_serial_poll_tx_done(uport);
 923         geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
 924                                false, true, true);
 925         geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
 926         geni_se_select_mode(&port->se, GENI_SE_FIFO);
 927         port->setup = true;
 928
 929         return 0;
 930 }
 931
 932 static int qcom_geni_serial_startup(struct uart_port *uport)
 933 {
 934         int ret;
 935         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 936
 937         if (!port->setup) {
 938                 ret = qcom_geni_serial_port_setup(uport);
 939                 if (ret)
 940                         return ret;
 941         }
 942         enable_irq(uport->irq);
 943
 944         return 0;
 945 }
 946
 947 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk,
 948                         unsigned int *clk_div, unsigned int percent_tol)
 949 {
 950         unsigned long freq;
 951         unsigned long div, maxdiv;
 952         u64 mult;
 953         unsigned long offset, abs_tol, achieved;
 954
 955         abs_tol = div_u64((u64)desired_clk * percent_tol, 100);
 956         maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
 957         div = 1;
 958         while (div <= maxdiv) {
 959                 mult = (u64)div * desired_clk;
 960                 if (mult != (unsigned long)mult)
 961                         break;
 962
 963                 offset = div * abs_tol;
 964                 freq = clk_round_rate(clk, mult - offset);
 965
 966                 /* Can only get lower if we're done */
 967                 if (freq < mult - offset)
 968                         break;
 969
 970                 /*
 971                  * Re-calculate div in case rounding skipped rates but we
 972                  * ended up at a good one, then check for a match.
 973                  */
 974                 div = DIV_ROUND_CLOSEST(freq, desired_clk);
 975                 achieved = DIV_ROUND_CLOSEST(freq, div);
 976                 if (achieved <= desired_clk + abs_tol &&
 977                     achieved >= desired_clk - abs_tol) {
 978                         *clk_div = div;
 979                         return freq;
 980                 }
 981
 982                 div = DIV_ROUND_UP(freq, desired_clk);
 983         }
 984
 985         return 0;
 986 }
 987
 988 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
 989                         unsigned int sampling_rate, unsigned int *clk_div)
 990 {
 991         unsigned long ser_clk;
 992         unsigned long desired_clk;
 993
 994         desired_clk = baud * sampling_rate;
 995         if (!desired_clk)
 996                 return 0;
 997
 998         /*
 999          * try to find a clock rate within 2% tolerance, then within 5%
1000          */
1001         ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2);
1002         if (!ser_clk)
1003                 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5);
1004
1005         return ser_clk;
1006 }
1007
1008 static void qcom_geni_serial_set_termios(struct uart_port *uport,
1009                                          struct ktermios *termios,
1010                                          const struct ktermios *old)
1011 {
1012         unsigned int baud;
1013         u32 bits_per_char;
1014         u32 tx_trans_cfg;
1015         u32 tx_parity_cfg;
1016         u32 rx_trans_cfg;
1017         u32 rx_parity_cfg;
1018         u32 stop_bit_len;
1019         unsigned int clk_div;
1020         u32 ser_clk_cfg;
1021         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1022         unsigned long clk_rate;
1023         u32 ver, sampling_rate;
1024         unsigned int avg_bw_core;
1025
1026         qcom_geni_serial_stop_rx(uport);
1027         /* baud rate */
1028         baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1029         port->baud = baud;
1030
1031         sampling_rate = UART_OVERSAMPLING;
1032         /* Sampling rate is halved for IP versions >= 2.5 */
1033         ver = geni_se_get_qup_hw_version(&port->se);
1034         if (ver >= QUP_SE_VERSION_2_5)
1035                 sampling_rate /= 2;
1036
1037         clk_rate = get_clk_div_rate(port->se.clk, baud,
1038                 sampling_rate, &clk_div);
1039         if (!clk_rate) {
1040                 dev_err(port->se.dev,
1041                         "Couldn't find suitable clock rate for %u\n",
1042                         baud * sampling_rate);
1043                 goto out_restart_rx;
1044         }
1045
1046         dev_dbg(port->se.dev, "desired_rate-%u, clk_rate-%lu, clk_div-%u\n",
1047                         baud * sampling_rate, clk_rate, clk_div);
1048
1049         uport->uartclk = clk_rate;
1050         dev_pm_opp_set_rate(uport->dev, clk_rate);
1051         ser_clk_cfg = SER_CLK_EN;
1052         ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1053
1054         /*
1055          * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1056          * only.
1057          */
1058         avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1059                                                 : GENI_DEFAULT_BW;
1060         port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1061         port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1062         geni_icc_set_bw(&port->se);
1063
1064         /* parity */
1065         tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1066         tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1067         rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1068         rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1069         if (termios->c_cflag & PARENB) {
1070                 tx_trans_cfg |= UART_TX_PAR_EN;
1071                 rx_trans_cfg |= UART_RX_PAR_EN;
1072                 tx_parity_cfg |= PAR_CALC_EN;
1073                 rx_parity_cfg |= PAR_CALC_EN;
1074                 if (termios->c_cflag & PARODD) {
1075                         tx_parity_cfg |= PAR_ODD;
1076                         rx_parity_cfg |= PAR_ODD;
1077                 } else if (termios->c_cflag & CMSPAR) {
1078                         tx_parity_cfg |= PAR_SPACE;
1079                         rx_parity_cfg |= PAR_SPACE;
1080                 } else {
1081                         tx_parity_cfg |= PAR_EVEN;
1082                         rx_parity_cfg |= PAR_EVEN;
1083                 }
1084         } else {
1085                 tx_trans_cfg &= ~UART_TX_PAR_EN;
1086                 rx_trans_cfg &= ~UART_RX_PAR_EN;
1087                 tx_parity_cfg &= ~PAR_CALC_EN;
1088                 rx_parity_cfg &= ~PAR_CALC_EN;
1089         }
1090
1091         /* bits per char */
1092         bits_per_char = tty_get_char_size(termios->c_cflag);
1093
1094         /* stop bits */
1095         if (termios->c_cflag & CSTOPB)
1096                 stop_bit_len = TX_STOP_BIT_LEN_2;
1097         else
1098                 stop_bit_len = TX_STOP_BIT_LEN_1;
1099
1100         /* flow control, clear the CTS_MASK bit if using flow control. */
1101         if (termios->c_cflag & CRTSCTS)
1102                 tx_trans_cfg &= ~UART_CTS_MASK;
1103         else
1104                 tx_trans_cfg |= UART_CTS_MASK;
1105
1106         if (baud)
1107                 uart_update_timeout(uport, termios->c_cflag, baud);
1108
1109         if (!uart_console(uport))
1110                 writel(port->loopback,
1111                                 uport->membase + SE_UART_LOOPBACK_CFG);
1112         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1113         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1114         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1115         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1116         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1117         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1118         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1119         writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1120         writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1121 out_restart_rx:
1122         qcom_geni_serial_start_rx(uport);
1123 }
1124
1125 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1126 {
1127         return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1128 }
1129
1130 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1131 static int qcom_geni_console_setup(struct console *co, char *options)
1132 {
1133         struct uart_port *uport;
1134         struct qcom_geni_serial_port *port;
1135         int baud = 115200;
1136         int bits = 8;
1137         int parity = 'n';
1138         int flow = 'n';
1139         int ret;
1140
1141         if (co->index >= GENI_UART_CONS_PORTS  || co->index < 0)
1142                 return -ENXIO;
1143
1144         port = get_port_from_line(co->index, true);
1145         if (IS_ERR(port)) {
1146                 pr_err("Invalid line %d\n", co->index);
1147                 return PTR_ERR(port);
1148         }
1149
1150         uport = &port->uport;
1151
1152         if (unlikely(!uport->membase))
1153                 return -ENXIO;
1154
1155         if (!port->setup) {
1156                 ret = qcom_geni_serial_port_setup(uport);
1157                 if (ret)
1158                         return ret;
1159         }
1160
1161         if (options)
1162                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1163
1164         return uart_set_options(uport, co, baud, parity, bits, flow);
1165 }
1166
1167 static void qcom_geni_serial_earlycon_write(struct console *con,
1168                                         const char *s, unsigned int n)
1169 {
1170         struct earlycon_device *dev = con->data;
1171
1172         __qcom_geni_serial_console_write(&dev->port, s, n);
1173 }
1174
1175 #ifdef CONFIG_CONSOLE_POLL
1176 static int qcom_geni_serial_earlycon_read(struct console *con,
1177                                           char *s, unsigned int n)
1178 {
1179         struct earlycon_device *dev = con->data;
1180         struct uart_port *uport = &dev->port;
1181         int num_read = 0;
1182         int ch;
1183
1184         while (num_read < n) {
1185                 ch = qcom_geni_serial_get_char(uport);
1186                 if (ch == NO_POLL_CHAR)
1187                         break;
1188                 s[num_read++] = ch;
1189         }
1190
1191         return num_read;
1192 }
1193
1194 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1195                                                       struct console *con)
1196 {
1197         geni_se_setup_s_cmd(se, UART_START_READ, 0);
1198         con->read = qcom_geni_serial_earlycon_read;
1199 }
1200 #else
1201 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1202                                                       struct console *con) { }
1203 #endif
1204
1205 static struct qcom_geni_private_data earlycon_private_data;
1206
1207 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1208                                                                 const char *opt)
1209 {
1210         struct uart_port *uport = &dev->port;
1211         u32 tx_trans_cfg;
1212         u32 tx_parity_cfg = 0;  /* Disable Tx Parity */
1213         u32 rx_trans_cfg = 0;
1214         u32 rx_parity_cfg = 0;  /* Disable Rx Parity */
1215         u32 stop_bit_len = 0;   /* Default stop bit length - 1 bit */
1216         u32 bits_per_char;
1217         struct geni_se se;
1218
1219         if (!uport->membase)
1220                 return -EINVAL;
1221
1222         uport->private_data = &earlycon_private_data;
1223
1224         memset(&se, 0, sizeof(se));
1225         se.base = uport->membase;
1226         if (geni_se_read_proto(&se) != GENI_SE_UART)
1227                 return -ENXIO;
1228         /*
1229          * Ignore Flow control.
1230          * n = 8.
1231          */
1232         tx_trans_cfg = UART_CTS_MASK;
1233         bits_per_char = BITS_PER_BYTE;
1234
1235         /*
1236          * Make an unconditional cancel on the main sequencer to reset
1237          * it else we could end up in data loss scenarios.
1238          */
1239         qcom_geni_serial_poll_tx_done(uport);
1240         qcom_geni_serial_abort_rx(uport);
1241         geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1242                                false, true, true);
1243         geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1244         geni_se_select_mode(&se, GENI_SE_FIFO);
1245
1246         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1247         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1248         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1249         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1250         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1251         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1252         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1253
1254         dev->con->write = qcom_geni_serial_earlycon_write;
1255         dev->con->setup = NULL;
1256         qcom_geni_serial_enable_early_read(&se, dev->con);
1257
1258         return 0;
1259 }
1260 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1261                                 qcom_geni_serial_earlycon_setup);
1262
1263 static int __init console_register(struct uart_driver *drv)
1264 {
1265         return uart_register_driver(drv);
1266 }
1267
1268 static void console_unregister(struct uart_driver *drv)
1269 {
1270         uart_unregister_driver(drv);
1271 }
1272
1273 static struct console cons_ops = {
1274         .name = "ttyMSM",
1275         .write = qcom_geni_serial_console_write,
1276         .device = uart_console_device,
1277         .setup = qcom_geni_console_setup,
1278         .flags = CON_PRINTBUFFER,
1279         .index = -1,
1280         .data = &qcom_geni_console_driver,
1281 };
1282
1283 static struct uart_driver qcom_geni_console_driver = {
1284         .owner = THIS_MODULE,
1285         .driver_name = "qcom_geni_console",
1286         .dev_name = "ttyMSM",
1287         .nr =  GENI_UART_CONS_PORTS,
1288         .cons = &cons_ops,
1289 };
1290 #else
1291 static int console_register(struct uart_driver *drv)
1292 {
1293         return 0;
1294 }
1295
1296 static void console_unregister(struct uart_driver *drv)
1297 {
1298 }
1299 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1300
1301 static struct uart_driver qcom_geni_uart_driver = {
1302         .owner = THIS_MODULE,
1303         .driver_name = "qcom_geni_uart",
1304         .dev_name = "ttyHS",
1305         .nr =  GENI_UART_PORTS,
1306 };
1307
1308 static void qcom_geni_serial_pm(struct uart_port *uport,
1309                 unsigned int new_state, unsigned int old_state)
1310 {
1311         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1312
1313         /* If we've never been called, treat it as off */
1314         if (old_state == UART_PM_STATE_UNDEFINED)
1315                 old_state = UART_PM_STATE_OFF;
1316
1317         if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1318                 geni_icc_enable(&port->se);
1319                 geni_se_resources_on(&port->se);
1320         } else if (new_state == UART_PM_STATE_OFF &&
1321                         old_state == UART_PM_STATE_ON) {
1322                 geni_se_resources_off(&port->se);
1323                 geni_icc_disable(&port->se);
1324         }
1325 }
1326
1327 static const struct uart_ops qcom_geni_console_pops = {
1328         .tx_empty = qcom_geni_serial_tx_empty,
1329         .stop_tx = qcom_geni_serial_stop_tx,
1330         .start_tx = qcom_geni_serial_start_tx,
1331         .stop_rx = qcom_geni_serial_stop_rx,
1332         .start_rx = qcom_geni_serial_start_rx,
1333         .set_termios = qcom_geni_serial_set_termios,
1334         .startup = qcom_geni_serial_startup,
1335         .request_port = qcom_geni_serial_request_port,
1336         .config_port = qcom_geni_serial_config_port,
1337         .shutdown = qcom_geni_serial_shutdown,
1338         .type = qcom_geni_serial_get_type,
1339         .set_mctrl = qcom_geni_serial_set_mctrl,
1340         .get_mctrl = qcom_geni_serial_get_mctrl,
1341 #ifdef CONFIG_CONSOLE_POLL
1342         .poll_get_char  = qcom_geni_serial_get_char,
1343         .poll_put_char  = qcom_geni_serial_poll_put_char,
1344 #endif
1345         .pm = qcom_geni_serial_pm,
1346 };
1347
1348 static const struct uart_ops qcom_geni_uart_pops = {
1349         .tx_empty = qcom_geni_serial_tx_empty,
1350         .stop_tx = qcom_geni_serial_stop_tx,
1351         .start_tx = qcom_geni_serial_start_tx,
1352         .stop_rx = qcom_geni_serial_stop_rx,
1353         .set_termios = qcom_geni_serial_set_termios,
1354         .startup = qcom_geni_serial_startup,
1355         .request_port = qcom_geni_serial_request_port,
1356         .config_port = qcom_geni_serial_config_port,
1357         .shutdown = qcom_geni_serial_shutdown,
1358         .type = qcom_geni_serial_get_type,
1359         .set_mctrl = qcom_geni_serial_set_mctrl,
1360         .get_mctrl = qcom_geni_serial_get_mctrl,
1361         .pm = qcom_geni_serial_pm,
1362 };
1363
1364 static int qcom_geni_serial_probe(struct platform_device *pdev)
1365 {
1366         int ret = 0;
1367         int line;
1368         struct qcom_geni_serial_port *port;
1369         struct uart_port *uport;
1370         struct resource *res;
1371         int irq;
1372         bool console = false;
1373         struct uart_driver *drv;
1374
1375         if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1376                 console = true;
1377
1378         if (console) {
1379                 drv = &qcom_geni_console_driver;
1380                 line = of_alias_get_id(pdev->dev.of_node, "serial");
1381         } else {
1382                 drv = &qcom_geni_uart_driver;
1383                 line = of_alias_get_id(pdev->dev.of_node, "serial");
1384                 if (line == -ENODEV) /* compat with non-standard aliases */
1385                         line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1386         }
1387
1388         port = get_port_from_line(line, console);
1389         if (IS_ERR(port)) {
1390                 dev_err(&pdev->dev, "Invalid line %d\n", line);
1391                 return PTR_ERR(port);
1392         }
1393
1394         uport = &port->uport;
1395         /* Don't allow 2 drivers to access the same port */
1396         if (uport->private_data)
1397                 return -ENODEV;
1398
1399         uport->dev = &pdev->dev;
1400         port->se.dev = &pdev->dev;
1401         port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1402         port->se.clk = devm_clk_get(&pdev->dev, "se");
1403         if (IS_ERR(port->se.clk)) {
1404                 ret = PTR_ERR(port->se.clk);
1405                 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1406                 return ret;
1407         }
1408
1409         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1410         if (!res)
1411                 return -EINVAL;
1412         uport->mapbase = res->start;
1413
1414         port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1415         port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1416         port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1417
1418         if (!console) {
1419                 port->rx_fifo = devm_kcalloc(uport->dev,
1420                         port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1421                 if (!port->rx_fifo)
1422                         return -ENOMEM;
1423         }
1424
1425         ret = geni_icc_get(&port->se, NULL);
1426         if (ret)
1427                 return ret;
1428         port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1429         port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1430
1431         /* Set BW for register access */
1432         ret = geni_icc_set_bw(&port->se);
1433         if (ret)
1434                 return ret;
1435
1436         port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1437                         "qcom_geni_serial_%s%d",
1438                         uart_console(uport) ? "console" : "uart", uport->line);
1439         if (!port->name)
1440                 return -ENOMEM;
1441
1442         irq = platform_get_irq(pdev, 0);
1443         if (irq < 0)
1444                 return irq;
1445         uport->irq = irq;
1446         uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1447
1448         if (!console)
1449                 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1450
1451         if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1452                 port->rx_tx_swap = true;
1453
1454         if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1455                 port->cts_rts_swap = true;
1456
1457         ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1458         if (ret)
1459                 return ret;
1460         /* OPP table is optional */
1461         ret = devm_pm_opp_of_add_table(&pdev->dev);
1462         if (ret && ret != -ENODEV) {
1463                 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1464                 return ret;
1465         }
1466
1467         port->private_data.drv = drv;
1468         uport->private_data = &port->private_data;
1469         platform_set_drvdata(pdev, port);
1470         port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1471
1472         ret = uart_add_one_port(drv, uport);
1473         if (ret)
1474                 return ret;
1475
1476         irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1477         ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1478                         IRQF_TRIGGER_HIGH, port->name, uport);
1479         if (ret) {
1480                 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1481                 uart_remove_one_port(drv, uport);
1482                 return ret;
1483         }
1484
1485         /*
1486          * Set pm_runtime status as ACTIVE so that wakeup_irq gets
1487          * enabled/disabled from dev_pm_arm_wake_irq during system
1488          * suspend/resume respectively.
1489          */
1490         pm_runtime_set_active(&pdev->dev);
1491
1492         if (port->wakeup_irq > 0) {
1493                 device_init_wakeup(&pdev->dev, true);
1494                 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1495                                                 port->wakeup_irq);
1496                 if (ret) {
1497                         device_init_wakeup(&pdev->dev, false);
1498                         uart_remove_one_port(drv, uport);
1499                         return ret;
1500                 }
1501         }
1502
1503         return 0;
1504 }
1505
1506 static int qcom_geni_serial_remove(struct platform_device *pdev)
1507 {
1508         struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1509         struct uart_driver *drv = port->private_data.drv;
1510
1511         dev_pm_clear_wake_irq(&pdev->dev);
1512         device_init_wakeup(&pdev->dev, false);
1513         uart_remove_one_port(drv, &port->uport);
1514
1515         return 0;
1516 }
1517
1518 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1519 {
1520         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1521         struct uart_port *uport = &port->uport;
1522         struct qcom_geni_private_data *private_data = uport->private_data;
1523
1524         /*
1525          * This is done so we can hit the lowest possible state in suspend
1526          * even with no_console_suspend
1527          */
1528         if (uart_console(uport)) {
1529                 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY);
1530                 geni_icc_set_bw(&port->se);
1531         }
1532         return uart_suspend_port(private_data->drv, uport);
1533 }
1534
1535 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1536 {
1537         int ret;
1538         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1539         struct uart_port *uport = &port->uport;
1540         struct qcom_geni_private_data *private_data = uport->private_data;
1541
1542         ret = uart_resume_port(private_data->drv, uport);
1543         if (uart_console(uport)) {
1544                 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);
1545                 geni_icc_set_bw(&port->se);
1546         }
1547         return ret;
1548 }
1549
1550 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1551         SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1552                                         qcom_geni_serial_sys_resume)
1553 };
1554
1555 static const struct of_device_id qcom_geni_serial_match_table[] = {
1556         { .compatible = "qcom,geni-debug-uart", },
1557         { .compatible = "qcom,geni-uart", },
1558         {}
1559 };
1560 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1561
1562 static struct platform_driver qcom_geni_serial_platform_driver = {
1563         .remove = qcom_geni_serial_remove,
1564         .probe = qcom_geni_serial_probe,
1565         .driver = {
1566                 .name = "qcom_geni_serial",
1567                 .of_match_table = qcom_geni_serial_match_table,
1568                 .pm = &qcom_geni_serial_pm_ops,
1569         },
1570 };
1571
1572 static int __init qcom_geni_serial_init(void)
1573 {
1574         int ret;
1575
1576         ret = console_register(&qcom_geni_console_driver);
1577         if (ret)
1578                 return ret;
1579
1580         ret = uart_register_driver(&qcom_geni_uart_driver);
1581         if (ret) {
1582                 console_unregister(&qcom_geni_console_driver);
1583                 return ret;
1584         }
1585
1586         ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1587         if (ret) {
1588                 console_unregister(&qcom_geni_console_driver);
1589                 uart_unregister_driver(&qcom_geni_uart_driver);
1590         }
1591         return ret;
1592 }
1593 module_init(qcom_geni_serial_init);
1594
1595 static void __exit qcom_geni_serial_exit(void)
1596 {
1597         platform_driver_unregister(&qcom_geni_serial_platform_driver);
1598         console_unregister(&qcom_geni_console_driver);
1599         uart_unregister_driver(&qcom_geni_uart_driver);
1600 }
1601 module_exit(qcom_geni_serial_exit);
1602
1603 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1604 MODULE_LICENSE("GPL v2");