drivers/tty/serial/qcom_geni_serial.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
   3
   4 #include <linux/clk.h>
   5 #include <linux/console.h>
   6 #include <linux/io.h>
   7 #include <linux/iopoll.h>
   8 #include <linux/irq.h>
   9 #include <linux/module.h>
  10 #include <linux/of.h>
  11 #include <linux/of_device.h>
  12 #include <linux/pm_opp.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/pm_wakeirq.h>
  16 #include <linux/qcom-geni-se.h>
  17 #include <linux/serial.h>
  18 #include <linux/serial_core.h>
  19 #include <linux/slab.h>
  20 #include <linux/tty.h>
  21 #include <linux/tty_flip.h>
  22
  23 /* UART specific GENI registers */
  24 #define SE_UART_LOOPBACK_CFG            0x22c
  25 #define SE_UART_IO_MACRO_CTRL           0x240
  26 #define SE_UART_TX_TRANS_CFG            0x25c
  27 #define SE_UART_TX_WORD_LEN             0x268
  28 #define SE_UART_TX_STOP_BIT_LEN         0x26c
  29 #define SE_UART_TX_TRANS_LEN            0x270
  30 #define SE_UART_RX_TRANS_CFG            0x280
  31 #define SE_UART_RX_WORD_LEN             0x28c
  32 #define SE_UART_RX_STALE_CNT            0x294
  33 #define SE_UART_TX_PARITY_CFG           0x2a4
  34 #define SE_UART_RX_PARITY_CFG           0x2a8
  35 #define SE_UART_MANUAL_RFR              0x2ac
  36
  37 /* SE_UART_TRANS_CFG */
  38 #define UART_TX_PAR_EN          BIT(0)
  39 #define UART_CTS_MASK           BIT(1)
  40
  41 /* SE_UART_TX_WORD_LEN */
  42 #define TX_WORD_LEN_MSK         GENMASK(9, 0)
  43
  44 /* SE_UART_TX_STOP_BIT_LEN */
  45 #define TX_STOP_BIT_LEN_MSK     GENMASK(23, 0)
  46 #define TX_STOP_BIT_LEN_1       0
  47 #define TX_STOP_BIT_LEN_1_5     1
  48 #define TX_STOP_BIT_LEN_2       2
  49
  50 /* SE_UART_TX_TRANS_LEN */
  51 #define TX_TRANS_LEN_MSK        GENMASK(23, 0)
  52
  53 /* SE_UART_RX_TRANS_CFG */
  54 #define UART_RX_INS_STATUS_BIT  BIT(2)
  55 #define UART_RX_PAR_EN          BIT(3)
  56
  57 /* SE_UART_RX_WORD_LEN */
  58 #define RX_WORD_LEN_MASK        GENMASK(9, 0)
  59
  60 /* SE_UART_RX_STALE_CNT */
  61 #define RX_STALE_CNT            GENMASK(23, 0)
  62
  63 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
  64 #define PAR_CALC_EN             BIT(0)
  65 #define PAR_MODE_MSK            GENMASK(2, 1)
  66 #define PAR_MODE_SHFT           1
  67 #define PAR_EVEN                0x00
  68 #define PAR_ODD                 0x01
  69 #define PAR_SPACE               0x10
  70 #define PAR_MARK                0x11
  71
  72 /* SE_UART_MANUAL_RFR register fields */
  73 #define UART_MANUAL_RFR_EN      BIT(31)
  74 #define UART_RFR_NOT_READY      BIT(1)
  75 #define UART_RFR_READY          BIT(0)
  76
  77 /* UART M_CMD OP codes */
  78 #define UART_START_TX           0x1
  79 #define UART_START_BREAK        0x4
  80 #define UART_STOP_BREAK         0x5
  81 /* UART S_CMD OP codes */
  82 #define UART_START_READ         0x1
  83 #define UART_PARAM              0x1
  84
  85 #define UART_OVERSAMPLING       32
  86 #define STALE_TIMEOUT           16
  87 #define DEFAULT_BITS_PER_CHAR   10
  88 #define GENI_UART_CONS_PORTS    1
  89 #define GENI_UART_PORTS         3
  90 #define DEF_FIFO_DEPTH_WORDS    16
  91 #define DEF_TX_WM               2
  92 #define DEF_FIFO_WIDTH_BITS     32
  93 #define UART_RX_WM              2
  94
  95 /* SE_UART_LOOPBACK_CFG */
  96 #define RX_TX_SORTED    BIT(0)
  97 #define CTS_RTS_SORTED  BIT(1)
  98 #define RX_TX_CTS_RTS_SORTED    (RX_TX_SORTED | CTS_RTS_SORTED)
  99
 100 /* UART pin swap value */
 101 #define DEFAULT_IO_MACRO_IO0_IO1_MASK           GENMASK(3, 0)
 102 #define IO_MACRO_IO0_SEL                0x3
 103 #define DEFAULT_IO_MACRO_IO2_IO3_MASK           GENMASK(15, 4)
 104 #define IO_MACRO_IO2_IO3_SWAP           0x4640
 105
 106 /* We always configure 4 bytes per FIFO word */
 107 #define BYTES_PER_FIFO_WORD             4
 108
 109 struct qcom_geni_private_data {
 110         /* NOTE: earlycon port will have NULL here */
 111         struct uart_driver *drv;
 112
 113         u32 poll_cached_bytes;
 114         unsigned int poll_cached_bytes_cnt;
 115
 116         u32 write_cached_bytes;
 117         unsigned int write_cached_bytes_cnt;
 118 };
 119
 120 struct qcom_geni_serial_port {
 121         struct uart_port uport;
 122         struct geni_se se;
 123         const char *name;
 124         u32 tx_fifo_depth;
 125         u32 tx_fifo_width;
 126         u32 rx_fifo_depth;
 127         bool setup;
 128         int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
 129         unsigned int baud;
 130         void *rx_fifo;
 131         u32 loopback;
 132         bool brk;
 133
 134         unsigned int tx_remaining;
 135         int wakeup_irq;
 136         bool rx_tx_swap;
 137         bool cts_rts_swap;
 138
 139         struct qcom_geni_private_data private_data;
 140 };
 141
 142 static const struct uart_ops qcom_geni_console_pops;
 143 static const struct uart_ops qcom_geni_uart_pops;
 144 static struct uart_driver qcom_geni_console_driver;
 145 static struct uart_driver qcom_geni_uart_driver;
 146 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
 147 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
 148 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
 149 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
 150 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
 151
 152 #define to_dev_port(ptr, member) \
 153                 container_of(ptr, struct qcom_geni_serial_port, member)
 154
 155 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
 156         [0] = {
 157                 .uport = {
 158                                 .iotype = UPIO_MEM,
 159                                 .ops = &qcom_geni_uart_pops,
 160                                 .flags = UPF_BOOT_AUTOCONF,
 161                                 .line = 0,
 162                 },
 163         },
 164         [1] = {
 165                 .uport = {
 166                                 .iotype = UPIO_MEM,
 167                                 .ops = &qcom_geni_uart_pops,
 168                                 .flags = UPF_BOOT_AUTOCONF,
 169                                 .line = 1,
 170                 },
 171         },
 172         [2] = {
 173                 .uport = {
 174                                 .iotype = UPIO_MEM,
 175                                 .ops = &qcom_geni_uart_pops,
 176                                 .flags = UPF_BOOT_AUTOCONF,
 177                                 .line = 2,
 178                 },
 179         },
 180 };
 181
 182 static struct qcom_geni_serial_port qcom_geni_console_port = {
 183         .uport = {
 184                 .iotype = UPIO_MEM,
 185                 .ops = &qcom_geni_console_pops,
 186                 .flags = UPF_BOOT_AUTOCONF,
 187                 .line = 0,
 188         },
 189 };
 190
 191 static int qcom_geni_serial_request_port(struct uart_port *uport)
 192 {
 193         struct platform_device *pdev = to_platform_device(uport->dev);
 194         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 195
 196         uport->membase = devm_platform_ioremap_resource(pdev, 0);
 197         if (IS_ERR(uport->membase))
 198                 return PTR_ERR(uport->membase);
 199         port->se.base = uport->membase;
 200         return 0;
 201 }
 202
 203 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
 204 {
 205         if (cfg_flags & UART_CONFIG_TYPE) {
 206                 uport->type = PORT_MSM;
 207                 qcom_geni_serial_request_port(uport);
 208         }
 209 }
 210
 211 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
 212 {
 213         unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
 214         u32 geni_ios;
 215
 216         if (uart_console(uport)) {
 217                 mctrl |= TIOCM_CTS;
 218         } else {
 219                 geni_ios = readl(uport->membase + SE_GENI_IOS);
 220                 if (!(geni_ios & IO2_DATA_IN))
 221                         mctrl |= TIOCM_CTS;
 222         }
 223
 224         return mctrl;
 225 }
 226
 227 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
 228                                                         unsigned int mctrl)
 229 {
 230         u32 uart_manual_rfr = 0;
 231         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 232
 233         if (uart_console(uport))
 234                 return;
 235
 236         if (mctrl & TIOCM_LOOP)
 237                 port->loopback = RX_TX_CTS_RTS_SORTED;
 238
 239         if (!(mctrl & TIOCM_RTS) && !uport->suspended)
 240                 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
 241         writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
 242 }
 243
 244 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
 245 {
 246         return "MSM";
 247 }
 248
 249 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
 250 {
 251         struct qcom_geni_serial_port *port;
 252         int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
 253
 254         if (line < 0 || line >= nr_ports)
 255                 return ERR_PTR(-ENXIO);
 256
 257         port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
 258         return port;
 259 }
 260
 261 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
 262                                 int offset, int field, bool set)
 263 {
 264         u32 reg;
 265         struct qcom_geni_serial_port *port;
 266         unsigned int baud;
 267         unsigned int fifo_bits;
 268         unsigned long timeout_us = 20000;
 269         struct qcom_geni_private_data *private_data = uport->private_data;
 270
 271         if (private_data->drv) {
 272                 port = to_dev_port(uport, uport);
 273                 baud = port->baud;
 274                 if (!baud)
 275                         baud = 115200;
 276                 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
 277                 /*
 278                  * Total polling iterations based on FIFO worth of bytes to be
 279                  * sent at current baud. Add a little fluff to the wait.
 280                  */
 281                 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
 282         }
 283
 284         /*
 285          * Use custom implementation instead of readl_poll_atomic since ktimer
 286          * is not ready at the time of early console.
 287          */
 288         timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
 289         while (timeout_us) {
 290                 reg = readl(uport->membase + offset);
 291                 if ((bool)(reg & field) == set)
 292                         return true;
 293                 udelay(10);
 294                 timeout_us -= 10;
 295         }
 296         return false;
 297 }
 298
 299 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
 300 {
 301         u32 m_cmd;
 302
 303         writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
 304         m_cmd = UART_START_TX << M_OPCODE_SHFT;
 305         writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
 306 }
 307
 308 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
 309 {
 310         int done;
 311         u32 irq_clear = M_CMD_DONE_EN;
 312
 313         done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 314                                                 M_CMD_DONE_EN, true);
 315         if (!done) {
 316                 writel(M_GENI_CMD_ABORT, uport->membase +
 317                                                 SE_GENI_M_CMD_CTRL_REG);
 318                 irq_clear |= M_CMD_ABORT_EN;
 319                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 320                                                         M_CMD_ABORT_EN, true);
 321         }
 322         writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
 323 }
 324
 325 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
 326 {
 327         u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
 328
 329         writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
 330         qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
 331                                         S_GENI_CMD_ABORT, false);
 332         writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
 333         writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
 334 }
 335
 336 #ifdef CONFIG_CONSOLE_POLL
 337
 338 static int qcom_geni_serial_get_char(struct uart_port *uport)
 339 {
 340         struct qcom_geni_private_data *private_data = uport->private_data;
 341         u32 status;
 342         u32 word_cnt;
 343         int ret;
 344
 345         if (!private_data->poll_cached_bytes_cnt) {
 346                 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 347                 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 348
 349                 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 350                 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 351
 352                 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 353                 word_cnt = status & RX_FIFO_WC_MSK;
 354                 if (!word_cnt)
 355                         return NO_POLL_CHAR;
 356
 357                 if (word_cnt == 1 && (status & RX_LAST))
 358                         /*
 359                          * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
 360                          * treated as if it was BYTES_PER_FIFO_WORD.
 361                          */
 362                         private_data->poll_cached_bytes_cnt =
 363                                 (status & RX_LAST_BYTE_VALID_MSK) >>
 364                                 RX_LAST_BYTE_VALID_SHFT;
 365
 366                 if (private_data->poll_cached_bytes_cnt == 0)
 367                         private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
 368
 369                 private_data->poll_cached_bytes =
 370                         readl(uport->membase + SE_GENI_RX_FIFOn);
 371         }
 372
 373         private_data->poll_cached_bytes_cnt--;
 374         ret = private_data->poll_cached_bytes & 0xff;
 375         private_data->poll_cached_bytes >>= 8;
 376
 377         return ret;
 378 }
 379
 380 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
 381                                                         unsigned char c)
 382 {
 383         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 384         qcom_geni_serial_setup_tx(uport, 1);
 385         WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 386                                                 M_TX_FIFO_WATERMARK_EN, true));
 387         writel(c, uport->membase + SE_GENI_TX_FIFOn);
 388         writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 389         qcom_geni_serial_poll_tx_done(uport);
 390 }
 391 #endif
 392
 393 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
 394 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch)
 395 {
 396         struct qcom_geni_private_data *private_data = uport->private_data;
 397
 398         private_data->write_cached_bytes =
 399                 (private_data->write_cached_bytes >> 8) | (ch << 24);
 400         private_data->write_cached_bytes_cnt++;
 401
 402         if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
 403                 writel(private_data->write_cached_bytes,
 404                        uport->membase + SE_GENI_TX_FIFOn);
 405                 private_data->write_cached_bytes_cnt = 0;
 406         }
 407 }
 408
 409 static void
 410 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
 411                                  unsigned int count)
 412 {
 413         struct qcom_geni_private_data *private_data = uport->private_data;
 414
 415         int i;
 416         u32 bytes_to_send = count;
 417
 418         for (i = 0; i < count; i++) {
 419                 /*
 420                  * uart_console_write() adds a carriage return for each newline.
 421                  * Account for additional bytes to be written.
 422                  */
 423                 if (s[i] == '\n')
 424                         bytes_to_send++;
 425         }
 426
 427         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 428         qcom_geni_serial_setup_tx(uport, bytes_to_send);
 429         for (i = 0; i < count; ) {
 430                 size_t chars_to_write = 0;
 431                 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
 432
 433                 /*
 434                  * If the WM bit never set, then the Tx state machine is not
 435                  * in a valid state, so break, cancel/abort any existing
 436                  * command. Unfortunately the current data being written is
 437                  * lost.
 438                  */
 439                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 440                                                 M_TX_FIFO_WATERMARK_EN, true))
 441                         break;
 442                 chars_to_write = min_t(size_t, count - i, avail / 2);
 443                 uart_console_write(uport, s + i, chars_to_write,
 444                                                 qcom_geni_serial_wr_char);
 445                 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
 446                                                         SE_GENI_M_IRQ_CLEAR);
 447                 i += chars_to_write;
 448         }
 449
 450         if (private_data->write_cached_bytes_cnt) {
 451                 private_data->write_cached_bytes >>= BITS_PER_BYTE *
 452                         (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
 453                 writel(private_data->write_cached_bytes,
 454                        uport->membase + SE_GENI_TX_FIFOn);
 455                 private_data->write_cached_bytes_cnt = 0;
 456         }
 457
 458         qcom_geni_serial_poll_tx_done(uport);
 459 }
 460
 461 static void qcom_geni_serial_console_write(struct console *co, const char *s,
 462                               unsigned int count)
 463 {
 464         struct uart_port *uport;
 465         struct qcom_geni_serial_port *port;
 466         bool locked = true;
 467         unsigned long flags;
 468         u32 geni_status;
 469         u32 irq_en;
 470
 471         WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
 472
 473         port = get_port_from_line(co->index, true);
 474         if (IS_ERR(port))
 475                 return;
 476
 477         uport = &port->uport;
 478         if (oops_in_progress)
 479                 locked = spin_trylock_irqsave(&uport->lock, flags);
 480         else
 481                 spin_lock_irqsave(&uport->lock, flags);
 482
 483         geni_status = readl(uport->membase + SE_GENI_STATUS);
 484
 485         /* Cancel the current write to log the fault */
 486         if (!locked) {
 487                 geni_se_cancel_m_cmd(&port->se);
 488                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 489                                                 M_CMD_CANCEL_EN, true)) {
 490                         geni_se_abort_m_cmd(&port->se);
 491                         qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 492                                                         M_CMD_ABORT_EN, true);
 493                         writel(M_CMD_ABORT_EN, uport->membase +
 494                                                         SE_GENI_M_IRQ_CLEAR);
 495                 }
 496                 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 497         } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
 498                 /*
 499                  * It seems we can't interrupt existing transfers if all data
 500                  * has been sent, in which case we need to look for done first.
 501                  */
 502                 qcom_geni_serial_poll_tx_done(uport);
 503
 504                 if (!uart_circ_empty(&uport->state->xmit)) {
 505                         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 506                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 507                                         uport->membase + SE_GENI_M_IRQ_EN);
 508                 }
 509         }
 510
 511         __qcom_geni_serial_console_write(uport, s, count);
 512
 513         if (port->tx_remaining)
 514                 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
 515
 516         if (locked)
 517                 spin_unlock_irqrestore(&uport->lock, flags);
 518 }
 519
 520 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 521 {
 522         u32 i;
 523         unsigned char buf[sizeof(u32)];
 524         struct tty_port *tport;
 525         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 526
 527         tport = &uport->state->port;
 528         for (i = 0; i < bytes; ) {
 529                 int c;
 530                 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
 531
 532                 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
 533                 i += chunk;
 534                 if (drop)
 535                         continue;
 536
 537                 for (c = 0; c < chunk; c++) {
 538                         int sysrq;
 539
 540                         uport->icount.rx++;
 541                         if (port->brk && buf[c] == 0) {
 542                                 port->brk = false;
 543                                 if (uart_handle_break(uport))
 544                                         continue;
 545                         }
 546
 547                         sysrq = uart_prepare_sysrq_char(uport, buf[c]);
 548
 549                         if (!sysrq)
 550                                 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
 551                 }
 552         }
 553         if (!drop)
 554                 tty_flip_buffer_push(tport);
 555         return 0;
 556 }
 557 #else
 558 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 559 {
 560         return -EPERM;
 561 }
 562
 563 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
 564
 565 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
 566 {
 567         struct tty_port *tport;
 568         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 569         u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
 570         u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
 571         int ret;
 572
 573         tport = &uport->state->port;
 574         ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
 575         if (drop)
 576                 return 0;
 577
 578         ret = tty_insert_flip_string(tport, port->rx_fifo, bytes);
 579         if (ret != bytes) {
 580                 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
 581                                 __func__, ret, bytes);
 582                 WARN_ON_ONCE(1);
 583         }
 584         uport->icount.rx += ret;
 585         tty_flip_buffer_push(tport);
 586         return ret;
 587 }
 588
 589 static void qcom_geni_serial_start_tx(struct uart_port *uport)
 590 {
 591         u32 irq_en;
 592         u32 status;
 593
 594         status = readl(uport->membase + SE_GENI_STATUS);
 595         if (status & M_GENI_CMD_ACTIVE)
 596                 return;
 597
 598         if (!qcom_geni_serial_tx_empty(uport))
 599                 return;
 600
 601         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 602         irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
 603
 604         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 605         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 606 }
 607
 608 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
 609 {
 610         u32 irq_en;
 611         u32 status;
 612         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 613
 614         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 615         irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
 616         writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
 617         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 618         status = readl(uport->membase + SE_GENI_STATUS);
 619         /* Possible stop tx is called multiple times. */
 620         if (!(status & M_GENI_CMD_ACTIVE))
 621                 return;
 622
 623         geni_se_cancel_m_cmd(&port->se);
 624         if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 625                                                 M_CMD_CANCEL_EN, true)) {
 626                 geni_se_abort_m_cmd(&port->se);
 627                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 628                                                 M_CMD_ABORT_EN, true);
 629                 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 630         }
 631         writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 632 }
 633
 634 static void qcom_geni_serial_start_rx(struct uart_port *uport)
 635 {
 636         u32 irq_en;
 637         u32 status;
 638         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 639
 640         status = readl(uport->membase + SE_GENI_STATUS);
 641         if (status & S_GENI_CMD_ACTIVE)
 642                 qcom_geni_serial_stop_rx(uport);
 643
 644         geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
 645
 646         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 647         irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
 648         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 649
 650         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 651         irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
 652         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 653 }
 654
 655 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
 656 {
 657         u32 irq_en;
 658         u32 status;
 659         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 660         u32 s_irq_status;
 661
 662         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 663         irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
 664         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 665
 666         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 667         irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
 668         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 669
 670         status = readl(uport->membase + SE_GENI_STATUS);
 671         /* Possible stop rx is called multiple times. */
 672         if (!(status & S_GENI_CMD_ACTIVE))
 673                 return;
 674
 675         geni_se_cancel_s_cmd(&port->se);
 676         qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
 677                                         S_CMD_CANCEL_EN, true);
 678         /*
 679          * If timeout occurs secondary engine remains active
 680          * and Abort sequence is executed.
 681          */
 682         s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 683         /* Flush the Rx buffer */
 684         if (s_irq_status & S_RX_FIFO_LAST_EN)
 685                 qcom_geni_serial_handle_rx(uport, true);
 686         writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 687
 688         status = readl(uport->membase + SE_GENI_STATUS);
 689         if (status & S_GENI_CMD_ACTIVE)
 690                 qcom_geni_serial_abort_rx(uport);
 691 }
 692
 693 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
 694 {
 695         u32 status;
 696         u32 word_cnt;
 697         u32 last_word_byte_cnt;
 698         u32 last_word_partial;
 699         u32 total_bytes;
 700         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 701
 702         status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 703         word_cnt = status & RX_FIFO_WC_MSK;
 704         last_word_partial = status & RX_LAST;
 705         last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
 706                                                 RX_LAST_BYTE_VALID_SHFT;
 707
 708         if (!word_cnt)
 709                 return;
 710         total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
 711         if (last_word_partial && last_word_byte_cnt)
 712                 total_bytes += last_word_byte_cnt;
 713         else
 714                 total_bytes += BYTES_PER_FIFO_WORD;
 715         port->handle_rx(uport, total_bytes, drop);
 716 }
 717
 718 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
 719                 bool active)
 720 {
 721         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 722         struct circ_buf *xmit = &uport->state->xmit;
 723         size_t avail;
 724         size_t remaining;
 725         size_t pending;
 726         int i;
 727         u32 status;
 728         u32 irq_en;
 729         unsigned int chunk;
 730         int tail;
 731
 732         status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
 733
 734         /* Complete the current tx command before taking newly added data */
 735         if (active)
 736                 pending = port->tx_remaining;
 737         else
 738                 pending = uart_circ_chars_pending(xmit);
 739
 740         /* All data has been transmitted and acknowledged as received */
 741         if (!pending && !status && done) {
 742                 qcom_geni_serial_stop_tx(uport);
 743                 goto out_write_wakeup;
 744         }
 745
 746         avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
 747         avail *= BYTES_PER_FIFO_WORD;
 748
 749         tail = xmit->tail;
 750         chunk = min(avail, pending);
 751         if (!chunk)
 752                 goto out_write_wakeup;
 753
 754         if (!port->tx_remaining) {
 755                 qcom_geni_serial_setup_tx(uport, pending);
 756                 port->tx_remaining = pending;
 757
 758                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 759                 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
 760                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 761                                         uport->membase + SE_GENI_M_IRQ_EN);
 762         }
 763
 764         remaining = chunk;
 765         for (i = 0; i < chunk; ) {
 766                 unsigned int tx_bytes;
 767                 u8 buf[sizeof(u32)];
 768                 int c;
 769
 770                 memset(buf, 0, sizeof(buf));
 771                 tx_bytes = min_t(size_t, remaining, BYTES_PER_FIFO_WORD);
 772
 773                 for (c = 0; c < tx_bytes ; c++) {
 774                         buf[c] = xmit->buf[tail++];
 775                         tail &= UART_XMIT_SIZE - 1;
 776                 }
 777
 778                 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
 779
 780                 i += tx_bytes;
 781                 uport->icount.tx += tx_bytes;
 782                 remaining -= tx_bytes;
 783                 port->tx_remaining -= tx_bytes;
 784         }
 785
 786         xmit->tail = tail;
 787
 788         /*
 789          * The tx fifo watermark is level triggered and latched. Though we had
 790          * cleared it in qcom_geni_serial_isr it will have already reasserted
 791          * so we must clear it again here after our writes.
 792          */
 793         writel(M_TX_FIFO_WATERMARK_EN,
 794                         uport->membase + SE_GENI_M_IRQ_CLEAR);
 795
 796 out_write_wakeup:
 797         if (!port->tx_remaining) {
 798                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 799                 if (irq_en & M_TX_FIFO_WATERMARK_EN)
 800                         writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
 801                                         uport->membase + SE_GENI_M_IRQ_EN);
 802         }
 803
 804         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 805                 uart_write_wakeup(uport);
 806 }
 807
 808 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
 809 {
 810         u32 m_irq_en;
 811         u32 m_irq_status;
 812         u32 s_irq_status;
 813         u32 geni_status;
 814         struct uart_port *uport = dev;
 815         bool drop_rx = false;
 816         struct tty_port *tport = &uport->state->port;
 817         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 818
 819         if (uport->suspended)
 820                 return IRQ_NONE;
 821
 822         spin_lock(&uport->lock);
 823
 824         m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 825         s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 826         geni_status = readl(uport->membase + SE_GENI_STATUS);
 827         m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 828         writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 829         writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 830
 831         if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
 832                 goto out_unlock;
 833
 834         if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
 835                 uport->icount.overrun++;
 836                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 837         }
 838
 839         if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
 840                 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
 841                                         geni_status & M_GENI_CMD_ACTIVE);
 842
 843         if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
 844                 if (s_irq_status & S_GP_IRQ_0_EN)
 845                         uport->icount.parity++;
 846                 drop_rx = true;
 847         } else if (s_irq_status & S_GP_IRQ_2_EN ||
 848                                         s_irq_status & S_GP_IRQ_3_EN) {
 849                 uport->icount.brk++;
 850                 port->brk = true;
 851         }
 852
 853         if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
 854                                         s_irq_status & S_RX_FIFO_LAST_EN)
 855                 qcom_geni_serial_handle_rx(uport, drop_rx);
 856
 857 out_unlock:
 858         uart_unlock_and_check_sysrq(uport);
 859
 860         return IRQ_HANDLED;
 861 }
 862
 863 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
 864 {
 865         struct uart_port *uport;
 866
 867         uport = &port->uport;
 868         port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
 869         port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
 870         port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
 871         uport->fifosize =
 872                 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
 873 }
 874
 875
 876 static void qcom_geni_serial_shutdown(struct uart_port *uport)
 877 {
 878         disable_irq(uport->irq);
 879 }
 880
 881 static int qcom_geni_serial_port_setup(struct uart_port *uport)
 882 {
 883         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 884         u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
 885         u32 proto;
 886         u32 pin_swap;
 887
 888         proto = geni_se_read_proto(&port->se);
 889         if (proto != GENI_SE_UART) {
 890                 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
 891                 return -ENXIO;
 892         }
 893
 894         qcom_geni_serial_stop_rx(uport);
 895
 896         get_tx_fifo_size(port);
 897
 898         writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
 899
 900         pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
 901         if (port->rx_tx_swap) {
 902                 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
 903                 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
 904         }
 905         if (port->cts_rts_swap) {
 906                 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
 907                 pin_swap |= IO_MACRO_IO0_SEL;
 908         }
 909         /* Configure this register if RX-TX, CTS-RTS pins are swapped */
 910         if (port->rx_tx_swap || port->cts_rts_swap)
 911                 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
 912
 913         /*
 914          * Make an unconditional cancel on the main sequencer to reset
 915          * it else we could end up in data loss scenarios.
 916          */
 917         if (uart_console(uport))
 918                 qcom_geni_serial_poll_tx_done(uport);
 919         geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
 920                                false, true, true);
 921         geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
 922         geni_se_select_mode(&port->se, GENI_SE_FIFO);
 923         port->setup = true;
 924
 925         return 0;
 926 }
 927
 928 static int qcom_geni_serial_startup(struct uart_port *uport)
 929 {
 930         int ret;
 931         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 932
 933         if (!port->setup) {
 934                 ret = qcom_geni_serial_port_setup(uport);
 935                 if (ret)
 936                         return ret;
 937         }
 938         enable_irq(uport->irq);
 939
 940         return 0;
 941 }
 942
 943 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
 944                         unsigned int sampling_rate, unsigned int *clk_div)
 945 {
 946         unsigned long ser_clk;
 947         unsigned long desired_clk;
 948         unsigned long freq, prev;
 949         unsigned long div, maxdiv;
 950         int64_t mult;
 951
 952         desired_clk = baud * sampling_rate;
 953         if (!desired_clk) {
 954                 pr_err("%s: Invalid frequency\n", __func__);
 955                 return 0;
 956         }
 957
 958         maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
 959         prev = 0;
 960
 961         for (div = 1; div <= maxdiv; div++) {
 962                 mult = div * desired_clk;
 963                 if (mult > ULONG_MAX)
 964                         break;
 965
 966                 freq = clk_round_rate(clk, (unsigned long)mult);
 967                 if (!(freq % desired_clk)) {
 968                         ser_clk = freq;
 969                         break;
 970                 }
 971
 972                 if (!prev)
 973                         ser_clk = freq;
 974                 else if (prev == freq)
 975                         break;
 976
 977                 prev = freq;
 978         }
 979
 980         if (!ser_clk) {
 981                 pr_err("%s: Can't find matching DFS entry for baud %d\n",
 982                                                                 __func__, baud);
 983                 return ser_clk;
 984         }
 985
 986         *clk_div = ser_clk / desired_clk;
 987         if (!(*clk_div))
 988                 *clk_div = 1;
 989
 990         return ser_clk;
 991 }
 992
 993 static void qcom_geni_serial_set_termios(struct uart_port *uport,
 994                                 struct ktermios *termios, struct ktermios *old)
 995 {
 996         unsigned int baud;
 997         u32 bits_per_char;
 998         u32 tx_trans_cfg;
 999         u32 tx_parity_cfg;
1000         u32 rx_trans_cfg;
1001         u32 rx_parity_cfg;
1002         u32 stop_bit_len;
1003         unsigned int clk_div;
1004         u32 ser_clk_cfg;
1005         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1006         unsigned long clk_rate;
1007         u32 ver, sampling_rate;
1008         unsigned int avg_bw_core;
1009
1010         qcom_geni_serial_stop_rx(uport);
1011         /* baud rate */
1012         baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1013         port->baud = baud;
1014
1015         sampling_rate = UART_OVERSAMPLING;
1016         /* Sampling rate is halved for IP versions >= 2.5 */
1017         ver = geni_se_get_qup_hw_version(&port->se);
1018         if (ver >= QUP_SE_VERSION_2_5)
1019                 sampling_rate /= 2;
1020
1021         clk_rate = get_clk_div_rate(port->se.clk, baud,
1022                 sampling_rate, &clk_div);
1023         if (!clk_rate)
1024                 goto out_restart_rx;
1025
1026         uport->uartclk = clk_rate;
1027         dev_pm_opp_set_rate(uport->dev, clk_rate);
1028         ser_clk_cfg = SER_CLK_EN;
1029         ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1030
1031         /*
1032          * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1033          * only.
1034          */
1035         avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1036                                                 : GENI_DEFAULT_BW;
1037         port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1038         port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1039         geni_icc_set_bw(&port->se);
1040
1041         /* parity */
1042         tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1043         tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1044         rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1045         rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1046         if (termios->c_cflag & PARENB) {
1047                 tx_trans_cfg |= UART_TX_PAR_EN;
1048                 rx_trans_cfg |= UART_RX_PAR_EN;
1049                 tx_parity_cfg |= PAR_CALC_EN;
1050                 rx_parity_cfg |= PAR_CALC_EN;
1051                 if (termios->c_cflag & PARODD) {
1052                         tx_parity_cfg |= PAR_ODD;
1053                         rx_parity_cfg |= PAR_ODD;
1054                 } else if (termios->c_cflag & CMSPAR) {
1055                         tx_parity_cfg |= PAR_SPACE;
1056                         rx_parity_cfg |= PAR_SPACE;
1057                 } else {
1058                         tx_parity_cfg |= PAR_EVEN;
1059                         rx_parity_cfg |= PAR_EVEN;
1060                 }
1061         } else {
1062                 tx_trans_cfg &= ~UART_TX_PAR_EN;
1063                 rx_trans_cfg &= ~UART_RX_PAR_EN;
1064                 tx_parity_cfg &= ~PAR_CALC_EN;
1065                 rx_parity_cfg &= ~PAR_CALC_EN;
1066         }
1067
1068         /* bits per char */
1069         bits_per_char = tty_get_char_size(termios->c_cflag);
1070
1071         /* stop bits */
1072         if (termios->c_cflag & CSTOPB)
1073                 stop_bit_len = TX_STOP_BIT_LEN_2;
1074         else
1075                 stop_bit_len = TX_STOP_BIT_LEN_1;
1076
1077         /* flow control, clear the CTS_MASK bit if using flow control. */
1078         if (termios->c_cflag & CRTSCTS)
1079                 tx_trans_cfg &= ~UART_CTS_MASK;
1080         else
1081                 tx_trans_cfg |= UART_CTS_MASK;
1082
1083         if (baud)
1084                 uart_update_timeout(uport, termios->c_cflag, baud);
1085
1086         if (!uart_console(uport))
1087                 writel(port->loopback,
1088                                 uport->membase + SE_UART_LOOPBACK_CFG);
1089         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1090         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1091         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1092         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1093         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1094         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1095         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1096         writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1097         writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1098 out_restart_rx:
1099         qcom_geni_serial_start_rx(uport);
1100 }
1101
1102 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1103 {
1104         return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1105 }
1106
1107 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1108 static int qcom_geni_console_setup(struct console *co, char *options)
1109 {
1110         struct uart_port *uport;
1111         struct qcom_geni_serial_port *port;
1112         int baud = 115200;
1113         int bits = 8;
1114         int parity = 'n';
1115         int flow = 'n';
1116         int ret;
1117
1118         if (co->index >= GENI_UART_CONS_PORTS  || co->index < 0)
1119                 return -ENXIO;
1120
1121         port = get_port_from_line(co->index, true);
1122         if (IS_ERR(port)) {
1123                 pr_err("Invalid line %d\n", co->index);
1124                 return PTR_ERR(port);
1125         }
1126
1127         uport = &port->uport;
1128
1129         if (unlikely(!uport->membase))
1130                 return -ENXIO;
1131
1132         if (!port->setup) {
1133                 ret = qcom_geni_serial_port_setup(uport);
1134                 if (ret)
1135                         return ret;
1136         }
1137
1138         if (options)
1139                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1140
1141         return uart_set_options(uport, co, baud, parity, bits, flow);
1142 }
1143
1144 static void qcom_geni_serial_earlycon_write(struct console *con,
1145                                         const char *s, unsigned int n)
1146 {
1147         struct earlycon_device *dev = con->data;
1148
1149         __qcom_geni_serial_console_write(&dev->port, s, n);
1150 }
1151
1152 #ifdef CONFIG_CONSOLE_POLL
1153 static int qcom_geni_serial_earlycon_read(struct console *con,
1154                                           char *s, unsigned int n)
1155 {
1156         struct earlycon_device *dev = con->data;
1157         struct uart_port *uport = &dev->port;
1158         int num_read = 0;
1159         int ch;
1160
1161         while (num_read < n) {
1162                 ch = qcom_geni_serial_get_char(uport);
1163                 if (ch == NO_POLL_CHAR)
1164                         break;
1165                 s[num_read++] = ch;
1166         }
1167
1168         return num_read;
1169 }
1170
1171 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1172                                                       struct console *con)
1173 {
1174         geni_se_setup_s_cmd(se, UART_START_READ, 0);
1175         con->read = qcom_geni_serial_earlycon_read;
1176 }
1177 #else
1178 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1179                                                       struct console *con) { }
1180 #endif
1181
1182 static struct qcom_geni_private_data earlycon_private_data;
1183
1184 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1185                                                                 const char *opt)
1186 {
1187         struct uart_port *uport = &dev->port;
1188         u32 tx_trans_cfg;
1189         u32 tx_parity_cfg = 0;  /* Disable Tx Parity */
1190         u32 rx_trans_cfg = 0;
1191         u32 rx_parity_cfg = 0;  /* Disable Rx Parity */
1192         u32 stop_bit_len = 0;   /* Default stop bit length - 1 bit */
1193         u32 bits_per_char;
1194         struct geni_se se;
1195
1196         if (!uport->membase)
1197                 return -EINVAL;
1198
1199         uport->private_data = &earlycon_private_data;
1200
1201         memset(&se, 0, sizeof(se));
1202         se.base = uport->membase;
1203         if (geni_se_read_proto(&se) != GENI_SE_UART)
1204                 return -ENXIO;
1205         /*
1206          * Ignore Flow control.
1207          * n = 8.
1208          */
1209         tx_trans_cfg = UART_CTS_MASK;
1210         bits_per_char = BITS_PER_BYTE;
1211
1212         /*
1213          * Make an unconditional cancel on the main sequencer to reset
1214          * it else we could end up in data loss scenarios.
1215          */
1216         qcom_geni_serial_poll_tx_done(uport);
1217         qcom_geni_serial_abort_rx(uport);
1218         geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1219                                false, true, true);
1220         geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1221         geni_se_select_mode(&se, GENI_SE_FIFO);
1222
1223         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1224         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1225         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1226         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1227         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1228         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1229         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1230
1231         dev->con->write = qcom_geni_serial_earlycon_write;
1232         dev->con->setup = NULL;
1233         qcom_geni_serial_enable_early_read(&se, dev->con);
1234
1235         return 0;
1236 }
1237 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1238                                 qcom_geni_serial_earlycon_setup);
1239
1240 static int __init console_register(struct uart_driver *drv)
1241 {
1242         return uart_register_driver(drv);
1243 }
1244
1245 static void console_unregister(struct uart_driver *drv)
1246 {
1247         uart_unregister_driver(drv);
1248 }
1249
1250 static struct console cons_ops = {
1251         .name = "ttyMSM",
1252         .write = qcom_geni_serial_console_write,
1253         .device = uart_console_device,
1254         .setup = qcom_geni_console_setup,
1255         .flags = CON_PRINTBUFFER,
1256         .index = -1,
1257         .data = &qcom_geni_console_driver,
1258 };
1259
1260 static struct uart_driver qcom_geni_console_driver = {
1261         .owner = THIS_MODULE,
1262         .driver_name = "qcom_geni_console",
1263         .dev_name = "ttyMSM",
1264         .nr =  GENI_UART_CONS_PORTS,
1265         .cons = &cons_ops,
1266 };
1267 #else
1268 static int console_register(struct uart_driver *drv)
1269 {
1270         return 0;
1271 }
1272
1273 static void console_unregister(struct uart_driver *drv)
1274 {
1275 }
1276 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1277
1278 static struct uart_driver qcom_geni_uart_driver = {
1279         .owner = THIS_MODULE,
1280         .driver_name = "qcom_geni_uart",
1281         .dev_name = "ttyHS",
1282         .nr =  GENI_UART_PORTS,
1283 };
1284
1285 static void qcom_geni_serial_pm(struct uart_port *uport,
1286                 unsigned int new_state, unsigned int old_state)
1287 {
1288         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1289
1290         /* If we've never been called, treat it as off */
1291         if (old_state == UART_PM_STATE_UNDEFINED)
1292                 old_state = UART_PM_STATE_OFF;
1293
1294         if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1295                 geni_icc_enable(&port->se);
1296                 geni_se_resources_on(&port->se);
1297         } else if (new_state == UART_PM_STATE_OFF &&
1298                         old_state == UART_PM_STATE_ON) {
1299                 geni_se_resources_off(&port->se);
1300                 geni_icc_disable(&port->se);
1301         }
1302 }
1303
1304 static const struct uart_ops qcom_geni_console_pops = {
1305         .tx_empty = qcom_geni_serial_tx_empty,
1306         .stop_tx = qcom_geni_serial_stop_tx,
1307         .start_tx = qcom_geni_serial_start_tx,
1308         .stop_rx = qcom_geni_serial_stop_rx,
1309         .set_termios = qcom_geni_serial_set_termios,
1310         .startup = qcom_geni_serial_startup,
1311         .request_port = qcom_geni_serial_request_port,
1312         .config_port = qcom_geni_serial_config_port,
1313         .shutdown = qcom_geni_serial_shutdown,
1314         .type = qcom_geni_serial_get_type,
1315         .set_mctrl = qcom_geni_serial_set_mctrl,
1316         .get_mctrl = qcom_geni_serial_get_mctrl,
1317 #ifdef CONFIG_CONSOLE_POLL
1318         .poll_get_char  = qcom_geni_serial_get_char,
1319         .poll_put_char  = qcom_geni_serial_poll_put_char,
1320 #endif
1321         .pm = qcom_geni_serial_pm,
1322 };
1323
1324 static const struct uart_ops qcom_geni_uart_pops = {
1325         .tx_empty = qcom_geni_serial_tx_empty,
1326         .stop_tx = qcom_geni_serial_stop_tx,
1327         .start_tx = qcom_geni_serial_start_tx,
1328         .stop_rx = qcom_geni_serial_stop_rx,
1329         .set_termios = qcom_geni_serial_set_termios,
1330         .startup = qcom_geni_serial_startup,
1331         .request_port = qcom_geni_serial_request_port,
1332         .config_port = qcom_geni_serial_config_port,
1333         .shutdown = qcom_geni_serial_shutdown,
1334         .type = qcom_geni_serial_get_type,
1335         .set_mctrl = qcom_geni_serial_set_mctrl,
1336         .get_mctrl = qcom_geni_serial_get_mctrl,
1337         .pm = qcom_geni_serial_pm,
1338 };
1339
1340 static int qcom_geni_serial_probe(struct platform_device *pdev)
1341 {
1342         int ret = 0;
1343         int line;
1344         struct qcom_geni_serial_port *port;
1345         struct uart_port *uport;
1346         struct resource *res;
1347         int irq;
1348         bool console = false;
1349         struct uart_driver *drv;
1350
1351         if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1352                 console = true;
1353
1354         if (console) {
1355                 drv = &qcom_geni_console_driver;
1356                 line = of_alias_get_id(pdev->dev.of_node, "serial");
1357         } else {
1358                 drv = &qcom_geni_uart_driver;
1359                 line = of_alias_get_id(pdev->dev.of_node, "serial");
1360                 if (line == -ENODEV) /* compat with non-standard aliases */
1361                         line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1362         }
1363
1364         port = get_port_from_line(line, console);
1365         if (IS_ERR(port)) {
1366                 dev_err(&pdev->dev, "Invalid line %d\n", line);
1367                 return PTR_ERR(port);
1368         }
1369
1370         uport = &port->uport;
1371         /* Don't allow 2 drivers to access the same port */
1372         if (uport->private_data)
1373                 return -ENODEV;
1374
1375         uport->dev = &pdev->dev;
1376         port->se.dev = &pdev->dev;
1377         port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1378         port->se.clk = devm_clk_get(&pdev->dev, "se");
1379         if (IS_ERR(port->se.clk)) {
1380                 ret = PTR_ERR(port->se.clk);
1381                 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1382                 return ret;
1383         }
1384
1385         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1386         if (!res)
1387                 return -EINVAL;
1388         uport->mapbase = res->start;
1389
1390         port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1391         port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1392         port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1393
1394         if (!console) {
1395                 port->rx_fifo = devm_kcalloc(uport->dev,
1396                         port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
1397                 if (!port->rx_fifo)
1398                         return -ENOMEM;
1399         }
1400
1401         ret = geni_icc_get(&port->se, NULL);
1402         if (ret)
1403                 return ret;
1404         port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1405         port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1406
1407         /* Set BW for register access */
1408         ret = geni_icc_set_bw(&port->se);
1409         if (ret)
1410                 return ret;
1411
1412         port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1413                         "qcom_geni_serial_%s%d",
1414                         uart_console(uport) ? "console" : "uart", uport->line);
1415         if (!port->name)
1416                 return -ENOMEM;
1417
1418         irq = platform_get_irq(pdev, 0);
1419         if (irq < 0)
1420                 return irq;
1421         uport->irq = irq;
1422         uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1423
1424         if (!console)
1425                 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1426
1427         if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1428                 port->rx_tx_swap = true;
1429
1430         if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1431                 port->cts_rts_swap = true;
1432
1433         ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1434         if (ret)
1435                 return ret;
1436         /* OPP table is optional */
1437         ret = devm_pm_opp_of_add_table(&pdev->dev);
1438         if (ret && ret != -ENODEV) {
1439                 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1440                 return ret;
1441         }
1442
1443         port->private_data.drv = drv;
1444         uport->private_data = &port->private_data;
1445         platform_set_drvdata(pdev, port);
1446         port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1447
1448         ret = uart_add_one_port(drv, uport);
1449         if (ret)
1450                 return ret;
1451
1452         irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1453         ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1454                         IRQF_TRIGGER_HIGH, port->name, uport);
1455         if (ret) {
1456                 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1457                 uart_remove_one_port(drv, uport);
1458                 return ret;
1459         }
1460
1461         /*
1462          * Set pm_runtime status as ACTIVE so that wakeup_irq gets
1463          * enabled/disabled from dev_pm_arm_wake_irq during system
1464          * suspend/resume respectively.
1465          */
1466         pm_runtime_set_active(&pdev->dev);
1467
1468         if (port->wakeup_irq > 0) {
1469                 device_init_wakeup(&pdev->dev, true);
1470                 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1471                                                 port->wakeup_irq);
1472                 if (ret) {
1473                         device_init_wakeup(&pdev->dev, false);
1474                         uart_remove_one_port(drv, uport);
1475                         return ret;
1476                 }
1477         }
1478
1479         return 0;
1480 }
1481
1482 static int qcom_geni_serial_remove(struct platform_device *pdev)
1483 {
1484         struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1485         struct uart_driver *drv = port->private_data.drv;
1486
1487         dev_pm_clear_wake_irq(&pdev->dev);
1488         device_init_wakeup(&pdev->dev, false);
1489         uart_remove_one_port(drv, &port->uport);
1490
1491         return 0;
1492 }
1493
1494 static int __maybe_unused qcom_geni_serial_sys_suspend(struct device *dev)
1495 {
1496         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1497         struct uart_port *uport = &port->uport;
1498         struct qcom_geni_private_data *private_data = uport->private_data;
1499
1500         /*
1501          * This is done so we can hit the lowest possible state in suspend
1502          * even with no_console_suspend
1503          */
1504         if (uart_console(uport)) {
1505                 geni_icc_set_tag(&port->se, 0x3);
1506                 geni_icc_set_bw(&port->se);
1507         }
1508         return uart_suspend_port(private_data->drv, uport);
1509 }
1510
1511 static int __maybe_unused qcom_geni_serial_sys_resume(struct device *dev)
1512 {
1513         int ret;
1514         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1515         struct uart_port *uport = &port->uport;
1516         struct qcom_geni_private_data *private_data = uport->private_data;
1517
1518         ret = uart_resume_port(private_data->drv, uport);
1519         if (uart_console(uport)) {
1520                 geni_icc_set_tag(&port->se, 0x7);
1521                 geni_icc_set_bw(&port->se);
1522         }
1523         return ret;
1524 }
1525
1526 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1527         SET_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend,
1528                                         qcom_geni_serial_sys_resume)
1529 };
1530
1531 static const struct of_device_id qcom_geni_serial_match_table[] = {
1532         { .compatible = "qcom,geni-debug-uart", },
1533         { .compatible = "qcom,geni-uart", },
1534         {}
1535 };
1536 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1537
1538 static struct platform_driver qcom_geni_serial_platform_driver = {
1539         .remove = qcom_geni_serial_remove,
1540         .probe = qcom_geni_serial_probe,
1541         .driver = {
1542                 .name = "qcom_geni_serial",
1543                 .of_match_table = qcom_geni_serial_match_table,
1544                 .pm = &qcom_geni_serial_pm_ops,
1545         },
1546 };
1547
1548 static int __init qcom_geni_serial_init(void)
1549 {
1550         int ret;
1551
1552         ret = console_register(&qcom_geni_console_driver);
1553         if (ret)
1554                 return ret;
1555
1556         ret = uart_register_driver(&qcom_geni_uart_driver);
1557         if (ret) {
1558                 console_unregister(&qcom_geni_console_driver);
1559                 return ret;
1560         }
1561
1562         ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1563         if (ret) {
1564                 console_unregister(&qcom_geni_console_driver);
1565                 uart_unregister_driver(&qcom_geni_uart_driver);
1566         }
1567         return ret;
1568 }
1569 module_init(qcom_geni_serial_init);
1570
1571 static void __exit qcom_geni_serial_exit(void)
1572 {
1573         platform_driver_unregister(&qcom_geni_serial_platform_driver);
1574         console_unregister(&qcom_geni_console_driver);
1575         uart_unregister_driver(&qcom_geni_uart_driver);
1576 }
1577 module_exit(qcom_geni_serial_exit);
1578
1579 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1580 MODULE_LICENSE("GPL v2");