2 *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 *This program is free software; you can redistribute it and/or modify
5 *it under the terms of the GNU General Public License as published by
6 *the Free Software Foundation; version 2 of the License.
8 *This program is distributed in the hope that it will be useful,
9 *but WITHOUT ANY WARRANTY; without even the implied warranty of
10 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 *GNU General Public License for more details.
13 *You should have received a copy of the GNU General Public License
14 *along with this program; if not, write to the Free Software
15 *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
17 #include <linux/kernel.h>
18 #include <linux/serial_reg.h>
19 #include <linux/slab.h>
20 #include <linux/module.h>
21 #include <linux/pci.h>
22 #include <linux/serial_core.h>
23 #include <linux/tty.h>
24 #include <linux/tty_flip.h>
25 #include <linux/interrupt.h>
27 #include <linux/dmi.h>
28 #include <linux/console.h>
29 #include <linux/nmi.h>
30 #include <linux/delay.h>
32 #include <linux/debugfs.h>
33 #include <linux/dmaengine.h>
34 #include <linux/pch_dma.h>
37 PCH_UART_HANDLED_RX_INT_SHIFT,
38 PCH_UART_HANDLED_TX_INT_SHIFT,
39 PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
40 PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
41 PCH_UART_HANDLED_MS_INT_SHIFT,
49 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
51 /* Set the max number of UART port
52 * Intel EG20T PCH: 4 port
53 * LAPIS Semiconductor ML7213 IOH: 3 port
54 * LAPIS Semiconductor ML7223 IOH: 2 port
58 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
59 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
60 #define PCH_UART_HANDLED_RX_ERR_INT (1<<((\
61 PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
62 #define PCH_UART_HANDLED_RX_TRG_INT (1<<((\
63 PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
64 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
66 #define PCH_UART_RBR 0x00
67 #define PCH_UART_THR 0x00
69 #define PCH_UART_IER_MASK (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
70 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
71 #define PCH_UART_IER_ERBFI 0x00000001
72 #define PCH_UART_IER_ETBEI 0x00000002
73 #define PCH_UART_IER_ELSI 0x00000004
74 #define PCH_UART_IER_EDSSI 0x00000008
76 #define PCH_UART_IIR_IP 0x00000001
77 #define PCH_UART_IIR_IID 0x00000006
78 #define PCH_UART_IIR_MSI 0x00000000
79 #define PCH_UART_IIR_TRI 0x00000002
80 #define PCH_UART_IIR_RRI 0x00000004
81 #define PCH_UART_IIR_REI 0x00000006
82 #define PCH_UART_IIR_TOI 0x00000008
83 #define PCH_UART_IIR_FIFO256 0x00000020
84 #define PCH_UART_IIR_FIFO64 PCH_UART_IIR_FIFO256
85 #define PCH_UART_IIR_FE 0x000000C0
87 #define PCH_UART_FCR_FIFOE 0x00000001
88 #define PCH_UART_FCR_RFR 0x00000002
89 #define PCH_UART_FCR_TFR 0x00000004
90 #define PCH_UART_FCR_DMS 0x00000008
91 #define PCH_UART_FCR_FIFO256 0x00000020
92 #define PCH_UART_FCR_RFTL 0x000000C0
94 #define PCH_UART_FCR_RFTL1 0x00000000
95 #define PCH_UART_FCR_RFTL64 0x00000040
96 #define PCH_UART_FCR_RFTL128 0x00000080
97 #define PCH_UART_FCR_RFTL224 0x000000C0
98 #define PCH_UART_FCR_RFTL16 PCH_UART_FCR_RFTL64
99 #define PCH_UART_FCR_RFTL32 PCH_UART_FCR_RFTL128
100 #define PCH_UART_FCR_RFTL56 PCH_UART_FCR_RFTL224
101 #define PCH_UART_FCR_RFTL4 PCH_UART_FCR_RFTL64
102 #define PCH_UART_FCR_RFTL8 PCH_UART_FCR_RFTL128
103 #define PCH_UART_FCR_RFTL14 PCH_UART_FCR_RFTL224
104 #define PCH_UART_FCR_RFTL_SHIFT 6
106 #define PCH_UART_LCR_WLS 0x00000003
107 #define PCH_UART_LCR_STB 0x00000004
108 #define PCH_UART_LCR_PEN 0x00000008
109 #define PCH_UART_LCR_EPS 0x00000010
110 #define PCH_UART_LCR_SP 0x00000020
111 #define PCH_UART_LCR_SB 0x00000040
112 #define PCH_UART_LCR_DLAB 0x00000080
113 #define PCH_UART_LCR_NP 0x00000000
114 #define PCH_UART_LCR_OP PCH_UART_LCR_PEN
115 #define PCH_UART_LCR_EP (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
116 #define PCH_UART_LCR_1P (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
117 #define PCH_UART_LCR_0P (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
120 #define PCH_UART_LCR_5BIT 0x00000000
121 #define PCH_UART_LCR_6BIT 0x00000001
122 #define PCH_UART_LCR_7BIT 0x00000002
123 #define PCH_UART_LCR_8BIT 0x00000003
125 #define PCH_UART_MCR_DTR 0x00000001
126 #define PCH_UART_MCR_RTS 0x00000002
127 #define PCH_UART_MCR_OUT 0x0000000C
128 #define PCH_UART_MCR_LOOP 0x00000010
129 #define PCH_UART_MCR_AFE 0x00000020
131 #define PCH_UART_LSR_DR 0x00000001
132 #define PCH_UART_LSR_ERR (1<<7)
134 #define PCH_UART_MSR_DCTS 0x00000001
135 #define PCH_UART_MSR_DDSR 0x00000002
136 #define PCH_UART_MSR_TERI 0x00000004
137 #define PCH_UART_MSR_DDCD 0x00000008
138 #define PCH_UART_MSR_CTS 0x00000010
139 #define PCH_UART_MSR_DSR 0x00000020
140 #define PCH_UART_MSR_RI 0x00000040
141 #define PCH_UART_MSR_DCD 0x00000080
142 #define PCH_UART_MSR_DELTA (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
143 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
145 #define PCH_UART_DLL 0x00
146 #define PCH_UART_DLM 0x01
148 #define PCH_UART_BRCSR 0x0E
150 #define PCH_UART_IID_RLS (PCH_UART_IIR_REI)
151 #define PCH_UART_IID_RDR (PCH_UART_IIR_RRI)
152 #define PCH_UART_IID_RDR_TO (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
153 #define PCH_UART_IID_THRE (PCH_UART_IIR_TRI)
154 #define PCH_UART_IID_MS (PCH_UART_IIR_MSI)
156 #define PCH_UART_HAL_PARITY_NONE (PCH_UART_LCR_NP)
157 #define PCH_UART_HAL_PARITY_ODD (PCH_UART_LCR_OP)
158 #define PCH_UART_HAL_PARITY_EVEN (PCH_UART_LCR_EP)
159 #define PCH_UART_HAL_PARITY_FIX1 (PCH_UART_LCR_1P)
160 #define PCH_UART_HAL_PARITY_FIX0 (PCH_UART_LCR_0P)
161 #define PCH_UART_HAL_5BIT (PCH_UART_LCR_5BIT)
162 #define PCH_UART_HAL_6BIT (PCH_UART_LCR_6BIT)
163 #define PCH_UART_HAL_7BIT (PCH_UART_LCR_7BIT)
164 #define PCH_UART_HAL_8BIT (PCH_UART_LCR_8BIT)
165 #define PCH_UART_HAL_STB1 0
166 #define PCH_UART_HAL_STB2 (PCH_UART_LCR_STB)
168 #define PCH_UART_HAL_CLR_TX_FIFO (PCH_UART_FCR_TFR)
169 #define PCH_UART_HAL_CLR_RX_FIFO (PCH_UART_FCR_RFR)
170 #define PCH_UART_HAL_CLR_ALL_FIFO (PCH_UART_HAL_CLR_TX_FIFO | \
171 PCH_UART_HAL_CLR_RX_FIFO)
173 #define PCH_UART_HAL_DMA_MODE0 0
174 #define PCH_UART_HAL_FIFO_DIS 0
175 #define PCH_UART_HAL_FIFO16 (PCH_UART_FCR_FIFOE)
176 #define PCH_UART_HAL_FIFO256 (PCH_UART_FCR_FIFOE | \
177 PCH_UART_FCR_FIFO256)
178 #define PCH_UART_HAL_FIFO64 (PCH_UART_HAL_FIFO256)
179 #define PCH_UART_HAL_TRIGGER1 (PCH_UART_FCR_RFTL1)
180 #define PCH_UART_HAL_TRIGGER64 (PCH_UART_FCR_RFTL64)
181 #define PCH_UART_HAL_TRIGGER128 (PCH_UART_FCR_RFTL128)
182 #define PCH_UART_HAL_TRIGGER224 (PCH_UART_FCR_RFTL224)
183 #define PCH_UART_HAL_TRIGGER16 (PCH_UART_FCR_RFTL16)
184 #define PCH_UART_HAL_TRIGGER32 (PCH_UART_FCR_RFTL32)
185 #define PCH_UART_HAL_TRIGGER56 (PCH_UART_FCR_RFTL56)
186 #define PCH_UART_HAL_TRIGGER4 (PCH_UART_FCR_RFTL4)
187 #define PCH_UART_HAL_TRIGGER8 (PCH_UART_FCR_RFTL8)
188 #define PCH_UART_HAL_TRIGGER14 (PCH_UART_FCR_RFTL14)
189 #define PCH_UART_HAL_TRIGGER_L (PCH_UART_FCR_RFTL64)
190 #define PCH_UART_HAL_TRIGGER_M (PCH_UART_FCR_RFTL128)
191 #define PCH_UART_HAL_TRIGGER_H (PCH_UART_FCR_RFTL224)
193 #define PCH_UART_HAL_RX_INT (PCH_UART_IER_ERBFI)
194 #define PCH_UART_HAL_TX_INT (PCH_UART_IER_ETBEI)
195 #define PCH_UART_HAL_RX_ERR_INT (PCH_UART_IER_ELSI)
196 #define PCH_UART_HAL_MS_INT (PCH_UART_IER_EDSSI)
197 #define PCH_UART_HAL_ALL_INT (PCH_UART_IER_MASK)
199 #define PCH_UART_HAL_DTR (PCH_UART_MCR_DTR)
200 #define PCH_UART_HAL_RTS (PCH_UART_MCR_RTS)
201 #define PCH_UART_HAL_OUT (PCH_UART_MCR_OUT)
202 #define PCH_UART_HAL_LOOP (PCH_UART_MCR_LOOP)
203 #define PCH_UART_HAL_AFE (PCH_UART_MCR_AFE)
205 #define PCI_VENDOR_ID_ROHM 0x10DB
207 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
209 #define DEFAULT_UARTCLK 1843200 /* 1.8432 MHz */
210 #define CMITC_UARTCLK 192000000 /* 192.0000 MHz */
211 #define FRI2_64_UARTCLK 64000000 /* 64.0000 MHz */
212 #define FRI2_48_UARTCLK 48000000 /* 48.0000 MHz */
213 #define NTC1_UARTCLK 64000000 /* 64.0000 MHz */
215 struct pch_uart_buffer {
221 struct uart_port port;
223 void __iomem *membase;
224 resource_size_t mapbase;
226 struct pci_dev *pdev;
235 struct pch_uart_buffer rxbuf;
239 unsigned int use_dma;
240 unsigned int use_dma_flag;
241 struct dma_async_tx_descriptor *desc_tx;
242 struct dma_async_tx_descriptor *desc_rx;
243 struct pch_dma_slave param_tx;
244 struct pch_dma_slave param_rx;
245 struct dma_chan *chan_tx;
246 struct dma_chan *chan_rx;
247 struct scatterlist *sg_tx_p;
249 struct scatterlist sg_rx;
252 dma_addr_t rx_buf_dma;
254 struct dentry *debugfs;
258 * struct pch_uart_driver_data - private data structure for UART-DMA
259 * @port_type: The number of DMA channel
260 * @line_no: UART port line number (0, 1, 2...)
262 struct pch_uart_driver_data {
267 enum pch_uart_num_t {
281 static struct pch_uart_driver_data drv_dat[] = {
282 [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
283 [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
284 [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
285 [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
286 [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
287 [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
288 [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
289 [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
290 [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
291 [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
292 [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
295 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
296 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
298 static unsigned int default_baud = 9600;
299 static unsigned int user_uartclk = 0;
300 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
301 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
302 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
303 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
305 #ifdef CONFIG_DEBUG_FS
307 #define PCH_REGS_BUFSIZE 1024
310 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
311 size_t count, loff_t *ppos)
313 struct eg20t_port *priv = file->private_data;
319 buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
323 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
324 "PCH EG20T port[%d] regs:\n", priv->port.line);
326 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
327 "=================================\n");
328 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
329 "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
330 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
331 "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
332 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
333 "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
334 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
335 "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
336 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
337 "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
338 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
339 "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
340 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
342 ioread8(priv->membase + PCH_UART_BRCSR));
344 lcr = ioread8(priv->membase + UART_LCR);
345 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
346 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
347 "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
348 len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
349 "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
350 iowrite8(lcr, priv->membase + UART_LCR);
352 if (len > PCH_REGS_BUFSIZE)
353 len = PCH_REGS_BUFSIZE;
355 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
360 static const struct file_operations port_regs_ops = {
361 .owner = THIS_MODULE,
363 .read = port_show_regs,
364 .llseek = default_llseek,
366 #endif /* CONFIG_DEBUG_FS */
368 /* Return UART clock, checking for board specific clocks. */
369 static int pch_uart_get_uartclk(void)
376 cmp = dmi_get_system_info(DMI_BOARD_NAME);
377 if (cmp && strstr(cmp, "CM-iTC"))
378 return CMITC_UARTCLK;
380 cmp = dmi_get_system_info(DMI_BIOS_VERSION);
381 if (cmp && strnstr(cmp, "FRI2", 4))
382 return FRI2_64_UARTCLK;
384 cmp = dmi_get_system_info(DMI_PRODUCT_NAME);
385 if (cmp && strstr(cmp, "Fish River Island II"))
386 return FRI2_48_UARTCLK;
388 /* Kontron COMe-mTT10 (nanoETXexpress-TT) */
389 cmp = dmi_get_system_info(DMI_BOARD_NAME);
390 if (cmp && (strstr(cmp, "COMe-mTT") ||
391 strstr(cmp, "nanoETXexpress-TT")))
394 return DEFAULT_UARTCLK;
397 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
400 u8 ier = ioread8(priv->membase + UART_IER);
401 ier |= flag & PCH_UART_IER_MASK;
402 iowrite8(ier, priv->membase + UART_IER);
405 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
408 u8 ier = ioread8(priv->membase + UART_IER);
409 ier &= ~(flag & PCH_UART_IER_MASK);
410 iowrite8(ier, priv->membase + UART_IER);
413 static int pch_uart_hal_set_line(struct eg20t_port *priv, int baud,
414 unsigned int parity, unsigned int bits,
417 unsigned int dll, dlm, lcr;
420 div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
421 if (div < 0 || USHRT_MAX <= div) {
422 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
426 dll = (unsigned int)div & 0x00FFU;
427 dlm = ((unsigned int)div >> 8) & 0x00FFU;
429 if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
430 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
434 if (bits & ~PCH_UART_LCR_WLS) {
435 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
439 if (stb & ~PCH_UART_LCR_STB) {
440 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
448 dev_dbg(priv->port.dev, "%s:baud = %d, div = %04x, lcr = %02x (%lu)\n",
449 __func__, baud, div, lcr, jiffies);
450 iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
451 iowrite8(dll, priv->membase + PCH_UART_DLL);
452 iowrite8(dlm, priv->membase + PCH_UART_DLM);
453 iowrite8(lcr, priv->membase + UART_LCR);
458 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
461 if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
462 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
467 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
468 iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
469 priv->membase + UART_FCR);
470 iowrite8(priv->fcr, priv->membase + UART_FCR);
475 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
476 unsigned int dmamode,
477 unsigned int fifo_size, unsigned int trigger)
481 if (dmamode & ~PCH_UART_FCR_DMS) {
482 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
487 if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
488 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
489 __func__, fifo_size);
493 if (trigger & ~PCH_UART_FCR_RFTL) {
494 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
499 switch (priv->fifo_size) {
501 priv->trigger_level =
502 trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
505 priv->trigger_level =
506 trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
509 priv->trigger_level =
510 trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
513 priv->trigger_level =
514 trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
518 dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
519 iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
520 iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
521 priv->membase + UART_FCR);
522 iowrite8(fcr, priv->membase + UART_FCR);
528 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
530 unsigned int msr = ioread8(priv->membase + UART_MSR);
531 priv->dmsr = msr & PCH_UART_MSR_DELTA;
535 static void pch_uart_hal_write(struct eg20t_port *priv,
536 const unsigned char *buf, int tx_size)
541 for (i = 0; i < tx_size;) {
543 iowrite8(thr, priv->membase + PCH_UART_THR);
547 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
553 lsr = ioread8(priv->membase + UART_LSR);
554 for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
555 i < rx_size && lsr & UART_LSR_DR;
556 lsr = ioread8(priv->membase + UART_LSR)) {
557 rbr = ioread8(priv->membase + PCH_UART_RBR);
563 static unsigned int pch_uart_hal_get_iid(struct eg20t_port *priv)
568 iir = ioread8(priv->membase + UART_IIR);
569 ret = (iir & (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP));
573 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
575 return ioread8(priv->membase + UART_LSR);
578 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
582 lcr = ioread8(priv->membase + UART_LCR);
584 lcr |= PCH_UART_LCR_SB;
586 lcr &= ~PCH_UART_LCR_SB;
588 iowrite8(lcr, priv->membase + UART_LCR);
591 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
594 struct uart_port *port;
595 struct tty_struct *tty;
598 tty = tty_port_tty_get(&port->state->port);
600 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
604 tty_insert_flip_string(tty, buf, size);
605 tty_flip_buffer_push(tty);
611 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
614 struct uart_port *port = &priv->port;
617 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
618 __func__, port->x_char, jiffies);
619 buf[0] = port->x_char;
627 static int dma_push_rx(struct eg20t_port *priv, int size)
629 struct tty_struct *tty;
631 struct uart_port *port = &priv->port;
634 tty = tty_port_tty_get(&port->state->port);
636 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
640 room = tty_buffer_request_room(tty, size);
643 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
648 tty_insert_flip_string(tty, sg_virt(&priv->sg_rx), size);
650 port->icount.rx += room;
656 static void pch_free_dma(struct uart_port *port)
658 struct eg20t_port *priv;
659 priv = container_of(port, struct eg20t_port, port);
662 dma_release_channel(priv->chan_tx);
663 priv->chan_tx = NULL;
666 dma_release_channel(priv->chan_rx);
667 priv->chan_rx = NULL;
669 if (sg_dma_address(&priv->sg_rx))
670 dma_free_coherent(port->dev, port->fifosize,
671 sg_virt(&priv->sg_rx),
672 sg_dma_address(&priv->sg_rx));
677 static bool filter(struct dma_chan *chan, void *slave)
679 struct pch_dma_slave *param = slave;
681 if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
682 chan->device->dev)) {
683 chan->private = param;
690 static void pch_request_dma(struct uart_port *port)
693 struct dma_chan *chan;
694 struct pci_dev *dma_dev;
695 struct pch_dma_slave *param;
696 struct eg20t_port *priv =
697 container_of(port, struct eg20t_port, port);
699 dma_cap_set(DMA_SLAVE, mask);
701 dma_dev = pci_get_bus_and_slot(priv->pdev->bus->number,
702 PCI_DEVFN(0xa, 0)); /* Get DMA's dev
705 param = &priv->param_tx;
706 param->dma_dev = &dma_dev->dev;
707 param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
709 param->tx_reg = port->mapbase + UART_TX;
710 chan = dma_request_channel(mask, filter, param);
712 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
716 priv->chan_tx = chan;
719 param = &priv->param_rx;
720 param->dma_dev = &dma_dev->dev;
721 param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
723 param->rx_reg = port->mapbase + UART_RX;
724 chan = dma_request_channel(mask, filter, param);
726 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
728 dma_release_channel(priv->chan_tx);
729 priv->chan_tx = NULL;
733 /* Get Consistent memory for DMA */
734 priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
735 &priv->rx_buf_dma, GFP_KERNEL);
736 priv->chan_rx = chan;
739 static void pch_dma_rx_complete(void *arg)
741 struct eg20t_port *priv = arg;
742 struct uart_port *port = &priv->port;
743 struct tty_struct *tty = tty_port_tty_get(&port->state->port);
747 dev_dbg(priv->port.dev, "%s:tty is busy now", __func__);
751 dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
752 count = dma_push_rx(priv, priv->trigger_level);
754 tty_flip_buffer_push(tty);
756 async_tx_ack(priv->desc_rx);
757 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
760 static void pch_dma_tx_complete(void *arg)
762 struct eg20t_port *priv = arg;
763 struct uart_port *port = &priv->port;
764 struct circ_buf *xmit = &port->state->xmit;
765 struct scatterlist *sg = priv->sg_tx_p;
768 for (i = 0; i < priv->nent; i++, sg++) {
769 xmit->tail += sg_dma_len(sg);
770 port->icount.tx += sg_dma_len(sg);
772 xmit->tail &= UART_XMIT_SIZE - 1;
773 async_tx_ack(priv->desc_tx);
774 dma_unmap_sg(port->dev, sg, priv->nent, DMA_TO_DEVICE);
775 priv->tx_dma_use = 0;
777 kfree(priv->sg_tx_p);
778 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
781 static int pop_tx(struct eg20t_port *priv, int size)
784 struct uart_port *port = &priv->port;
785 struct circ_buf *xmit = &port->state->xmit;
787 if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
792 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
793 int sz = min(size - count, cnt_to_end);
794 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
795 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
797 } while (!uart_circ_empty(xmit) && count < size);
800 dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
801 count, size - count, jiffies);
806 static int handle_rx_to(struct eg20t_port *priv)
808 struct pch_uart_buffer *buf;
811 if (!priv->start_rx) {
812 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
817 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
818 ret = push_rx(priv, buf->buf, rx_size);
821 } while (rx_size == buf->size);
823 return PCH_UART_HANDLED_RX_INT;
826 static int handle_rx(struct eg20t_port *priv)
828 return handle_rx_to(priv);
831 static int dma_handle_rx(struct eg20t_port *priv)
833 struct uart_port *port = &priv->port;
834 struct dma_async_tx_descriptor *desc;
835 struct scatterlist *sg;
837 priv = container_of(port, struct eg20t_port, port);
840 sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
842 sg_dma_len(sg) = priv->trigger_level;
844 sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
845 sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
848 sg_dma_address(sg) = priv->rx_buf_dma;
850 desc = dmaengine_prep_slave_sg(priv->chan_rx,
851 sg, 1, DMA_DEV_TO_MEM,
852 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
857 priv->desc_rx = desc;
858 desc->callback = pch_dma_rx_complete;
859 desc->callback_param = priv;
860 desc->tx_submit(desc);
861 dma_async_issue_pending(priv->chan_rx);
863 return PCH_UART_HANDLED_RX_INT;
866 static unsigned int handle_tx(struct eg20t_port *priv)
868 struct uart_port *port = &priv->port;
869 struct circ_buf *xmit = &port->state->xmit;
875 if (!priv->start_tx) {
876 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
878 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
883 fifo_size = max(priv->fifo_size, 1);
885 if (pop_tx_x(priv, xmit->buf)) {
886 pch_uart_hal_write(priv, xmit->buf, 1);
891 size = min(xmit->head - xmit->tail, fifo_size);
895 tx_size = pop_tx(priv, size);
897 port->icount.tx += tx_size;
901 priv->tx_empty = tx_empty;
904 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
905 uart_write_wakeup(port);
908 return PCH_UART_HANDLED_TX_INT;
911 static unsigned int dma_handle_tx(struct eg20t_port *priv)
913 struct uart_port *port = &priv->port;
914 struct circ_buf *xmit = &port->state->xmit;
915 struct scatterlist *sg;
919 struct dma_async_tx_descriptor *desc;
926 if (!priv->start_tx) {
927 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
929 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
934 if (priv->tx_dma_use) {
935 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
937 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
942 fifo_size = max(priv->fifo_size, 1);
944 if (pop_tx_x(priv, xmit->buf)) {
945 pch_uart_hal_write(priv, xmit->buf, 1);
951 bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
952 UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
953 xmit->tail, UART_XMIT_SIZE));
955 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
956 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
957 uart_write_wakeup(port);
961 if (bytes > fifo_size) {
962 num = bytes / fifo_size + 1;
964 rem = bytes % fifo_size;
971 dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
972 __func__, num, size, rem);
974 priv->tx_dma_use = 1;
976 priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
978 sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
981 for (i = 0; i < num; i++, sg++) {
983 sg_set_page(sg, virt_to_page(xmit->buf),
986 sg_set_page(sg, virt_to_page(xmit->buf),
987 size, fifo_size * i);
991 nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
993 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
998 for (i = 0; i < nent; i++, sg++) {
999 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1001 sg_dma_address(sg) = (sg_dma_address(sg) &
1002 ~(UART_XMIT_SIZE - 1)) + sg->offset;
1003 if (i == (nent - 1))
1004 sg_dma_len(sg) = rem;
1006 sg_dma_len(sg) = size;
1009 desc = dmaengine_prep_slave_sg(priv->chan_tx,
1010 priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1011 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1013 dev_err(priv->port.dev, "%s:device_prep_slave_sg Failed\n",
1017 dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1018 priv->desc_tx = desc;
1019 desc->callback = pch_dma_tx_complete;
1020 desc->callback_param = priv;
1022 desc->tx_submit(desc);
1024 dma_async_issue_pending(priv->chan_tx);
1026 return PCH_UART_HANDLED_TX_INT;
1029 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1031 u8 fcr = ioread8(priv->membase + UART_FCR);
1034 fcr |= UART_FCR_CLEAR_RCVR;
1035 iowrite8(fcr, priv->membase + UART_FCR);
1037 if (lsr & PCH_UART_LSR_ERR)
1038 dev_err(&priv->pdev->dev, "Error data in FIFO\n");
1040 if (lsr & UART_LSR_FE)
1041 dev_err(&priv->pdev->dev, "Framing Error\n");
1043 if (lsr & UART_LSR_PE)
1044 dev_err(&priv->pdev->dev, "Parity Error\n");
1046 if (lsr & UART_LSR_OE)
1047 dev_err(&priv->pdev->dev, "Overrun Error\n");
1050 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1052 struct eg20t_port *priv = dev_id;
1053 unsigned int handled;
1057 unsigned long flags;
1059 spin_lock_irqsave(&priv->port.lock, flags);
1061 while ((iid = pch_uart_hal_get_iid(priv)) > 1) {
1063 case PCH_UART_IID_RLS: /* Receiver Line Status */
1064 lsr = pch_uart_hal_get_line_status(priv);
1065 if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1066 UART_LSR_PE | UART_LSR_OE)) {
1067 pch_uart_err_ir(priv, lsr);
1068 ret = PCH_UART_HANDLED_RX_ERR_INT;
1071 case PCH_UART_IID_RDR: /* Received Data Ready */
1072 if (priv->use_dma) {
1073 pch_uart_hal_disable_interrupt(priv,
1074 PCH_UART_HAL_RX_INT);
1075 ret = dma_handle_rx(priv);
1077 pch_uart_hal_enable_interrupt(priv,
1078 PCH_UART_HAL_RX_INT);
1080 ret = handle_rx(priv);
1083 case PCH_UART_IID_RDR_TO: /* Received Data Ready
1085 ret = handle_rx_to(priv);
1087 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1090 ret = dma_handle_tx(priv);
1092 ret = handle_tx(priv);
1094 case PCH_UART_IID_MS: /* Modem Status */
1095 ret = PCH_UART_HANDLED_MS_INT;
1097 default: /* Never junp to this label */
1098 dev_err(priv->port.dev, "%s:iid=%d (%lu)\n", __func__,
1103 handled |= (unsigned int)ret;
1105 if (handled == 0 && iid <= 1) {
1106 if (priv->int_dis_flag)
1107 priv->int_dis_flag = 0;
1110 spin_unlock_irqrestore(&priv->port.lock, flags);
1111 return IRQ_RETVAL(handled);
1114 /* This function tests whether the transmitter fifo and shifter for the port
1115 described by 'port' is empty. */
1116 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1118 struct eg20t_port *priv;
1120 priv = container_of(port, struct eg20t_port, port);
1122 return TIOCSER_TEMT;
1127 /* Returns the current state of modem control inputs. */
1128 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1130 struct eg20t_port *priv;
1132 unsigned int ret = 0;
1134 priv = container_of(port, struct eg20t_port, port);
1135 modem = pch_uart_hal_get_modem(priv);
1137 if (modem & UART_MSR_DCD)
1140 if (modem & UART_MSR_RI)
1143 if (modem & UART_MSR_DSR)
1146 if (modem & UART_MSR_CTS)
1152 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1155 struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1157 if (mctrl & TIOCM_DTR)
1158 mcr |= UART_MCR_DTR;
1159 if (mctrl & TIOCM_RTS)
1160 mcr |= UART_MCR_RTS;
1161 if (mctrl & TIOCM_LOOP)
1162 mcr |= UART_MCR_LOOP;
1164 if (priv->mcr & UART_MCR_AFE)
1165 mcr |= UART_MCR_AFE;
1168 iowrite8(mcr, priv->membase + UART_MCR);
1171 static void pch_uart_stop_tx(struct uart_port *port)
1173 struct eg20t_port *priv;
1174 priv = container_of(port, struct eg20t_port, port);
1176 priv->tx_dma_use = 0;
1179 static void pch_uart_start_tx(struct uart_port *port)
1181 struct eg20t_port *priv;
1183 priv = container_of(port, struct eg20t_port, port);
1185 if (priv->use_dma) {
1186 if (priv->tx_dma_use) {
1187 dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1194 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1197 static void pch_uart_stop_rx(struct uart_port *port)
1199 struct eg20t_port *priv;
1200 priv = container_of(port, struct eg20t_port, port);
1202 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT);
1203 priv->int_dis_flag = 1;
1206 /* Enable the modem status interrupts. */
1207 static void pch_uart_enable_ms(struct uart_port *port)
1209 struct eg20t_port *priv;
1210 priv = container_of(port, struct eg20t_port, port);
1211 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1214 /* Control the transmission of a break signal. */
1215 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1217 struct eg20t_port *priv;
1218 unsigned long flags;
1220 priv = container_of(port, struct eg20t_port, port);
1221 spin_lock_irqsave(&port->lock, flags);
1222 pch_uart_hal_set_break(priv, ctl);
1223 spin_unlock_irqrestore(&port->lock, flags);
1226 /* Grab any interrupt resources and initialise any low level driver state. */
1227 static int pch_uart_startup(struct uart_port *port)
1229 struct eg20t_port *priv;
1234 priv = container_of(port, struct eg20t_port, port);
1238 priv->uartclk = port->uartclk;
1240 port->uartclk = priv->uartclk;
1242 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1243 ret = pch_uart_hal_set_line(priv, default_baud,
1244 PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1249 switch (priv->fifo_size) {
1251 fifo_size = PCH_UART_HAL_FIFO256;
1254 fifo_size = PCH_UART_HAL_FIFO64;
1257 fifo_size = PCH_UART_HAL_FIFO16;
1260 fifo_size = PCH_UART_HAL_FIFO_DIS;
1264 switch (priv->trigger) {
1265 case PCH_UART_HAL_TRIGGER1:
1268 case PCH_UART_HAL_TRIGGER_L:
1269 trigger_level = priv->fifo_size / 4;
1271 case PCH_UART_HAL_TRIGGER_M:
1272 trigger_level = priv->fifo_size / 2;
1274 case PCH_UART_HAL_TRIGGER_H:
1276 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1280 priv->trigger_level = trigger_level;
1281 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1282 fifo_size, priv->trigger);
1286 ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1287 KBUILD_MODNAME, priv);
1292 pch_request_dma(port);
1295 pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT);
1296 uart_update_timeout(port, CS8, default_baud);
1301 static void pch_uart_shutdown(struct uart_port *port)
1303 struct eg20t_port *priv;
1306 priv = container_of(port, struct eg20t_port, port);
1307 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1308 pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1309 ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1310 PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1312 dev_err(priv->port.dev,
1313 "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1317 free_irq(priv->port.irq, priv);
1320 /* Change the port parameters, including word length, parity, stop
1321 *bits. Update read_status_mask and ignore_status_mask to indicate
1322 *the types of events we are interested in receiving. */
1323 static void pch_uart_set_termios(struct uart_port *port,
1324 struct ktermios *termios, struct ktermios *old)
1328 unsigned int parity, bits, stb;
1329 struct eg20t_port *priv;
1330 unsigned long flags;
1332 priv = container_of(port, struct eg20t_port, port);
1333 switch (termios->c_cflag & CSIZE) {
1335 bits = PCH_UART_HAL_5BIT;
1338 bits = PCH_UART_HAL_6BIT;
1341 bits = PCH_UART_HAL_7BIT;
1344 bits = PCH_UART_HAL_8BIT;
1347 if (termios->c_cflag & CSTOPB)
1348 stb = PCH_UART_HAL_STB2;
1350 stb = PCH_UART_HAL_STB1;
1352 if (termios->c_cflag & PARENB) {
1353 if (!(termios->c_cflag & PARODD))
1354 parity = PCH_UART_HAL_PARITY_ODD;
1356 parity = PCH_UART_HAL_PARITY_EVEN;
1359 parity = PCH_UART_HAL_PARITY_NONE;
1361 /* Only UART0 has auto hardware flow function */
1362 if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1363 priv->mcr |= UART_MCR_AFE;
1365 priv->mcr &= ~UART_MCR_AFE;
1367 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1369 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1371 spin_lock_irqsave(&port->lock, flags);
1373 uart_update_timeout(port, termios->c_cflag, baud);
1374 rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1378 pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1379 /* Don't rewrite B0 */
1380 if (tty_termios_baud_rate(termios))
1381 tty_termios_encode_baud_rate(termios, baud, baud);
1384 spin_unlock_irqrestore(&port->lock, flags);
1387 static const char *pch_uart_type(struct uart_port *port)
1389 return KBUILD_MODNAME;
1392 static void pch_uart_release_port(struct uart_port *port)
1394 struct eg20t_port *priv;
1396 priv = container_of(port, struct eg20t_port, port);
1397 pci_iounmap(priv->pdev, priv->membase);
1398 pci_release_regions(priv->pdev);
1401 static int pch_uart_request_port(struct uart_port *port)
1403 struct eg20t_port *priv;
1405 void __iomem *membase;
1407 priv = container_of(port, struct eg20t_port, port);
1408 ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1412 membase = pci_iomap(priv->pdev, 1, 0);
1414 pci_release_regions(priv->pdev);
1417 priv->membase = port->membase = membase;
1422 static void pch_uart_config_port(struct uart_port *port, int type)
1424 struct eg20t_port *priv;
1426 priv = container_of(port, struct eg20t_port, port);
1427 if (type & UART_CONFIG_TYPE) {
1428 port->type = priv->port_type;
1429 pch_uart_request_port(port);
1433 static int pch_uart_verify_port(struct uart_port *port,
1434 struct serial_struct *serinfo)
1436 struct eg20t_port *priv;
1438 priv = container_of(port, struct eg20t_port, port);
1439 if (serinfo->flags & UPF_LOW_LATENCY) {
1440 dev_info(priv->port.dev,
1441 "PCH UART : Use PIO Mode (without DMA)\n");
1443 serinfo->flags &= ~UPF_LOW_LATENCY;
1445 #ifndef CONFIG_PCH_DMA
1446 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1451 priv->use_dma_flag = 1;
1452 dev_info(priv->port.dev, "PCH UART : Use DMA Mode\n");
1458 static struct uart_ops pch_uart_ops = {
1459 .tx_empty = pch_uart_tx_empty,
1460 .set_mctrl = pch_uart_set_mctrl,
1461 .get_mctrl = pch_uart_get_mctrl,
1462 .stop_tx = pch_uart_stop_tx,
1463 .start_tx = pch_uart_start_tx,
1464 .stop_rx = pch_uart_stop_rx,
1465 .enable_ms = pch_uart_enable_ms,
1466 .break_ctl = pch_uart_break_ctl,
1467 .startup = pch_uart_startup,
1468 .shutdown = pch_uart_shutdown,
1469 .set_termios = pch_uart_set_termios,
1470 /* .pm = pch_uart_pm, Not supported yet */
1471 /* .set_wake = pch_uart_set_wake, Not supported yet */
1472 .type = pch_uart_type,
1473 .release_port = pch_uart_release_port,
1474 .request_port = pch_uart_request_port,
1475 .config_port = pch_uart_config_port,
1476 .verify_port = pch_uart_verify_port
1479 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1482 * Wait for transmitter & holding register to empty
1484 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1486 unsigned int status, tmout = 10000;
1488 /* Wait up to 10ms for the character(s) to be sent. */
1490 status = ioread8(up->membase + UART_LSR);
1492 if ((status & bits) == bits)
1499 /* Wait up to 1s for flow control if necessary */
1500 if (up->port.flags & UPF_CONS_FLOW) {
1502 for (tmout = 1000000; tmout; tmout--) {
1503 unsigned int msr = ioread8(up->membase + UART_MSR);
1504 if (msr & UART_MSR_CTS)
1507 touch_nmi_watchdog();
1512 static void pch_console_putchar(struct uart_port *port, int ch)
1514 struct eg20t_port *priv =
1515 container_of(port, struct eg20t_port, port);
1517 wait_for_xmitr(priv, UART_LSR_THRE);
1518 iowrite8(ch, priv->membase + PCH_UART_THR);
1522 * Print a string to the serial port trying not to disturb
1523 * any possible real use of the port...
1525 * The console_lock must be held when we get here.
1528 pch_console_write(struct console *co, const char *s, unsigned int count)
1530 struct eg20t_port *priv;
1531 unsigned long flags;
1535 priv = pch_uart_ports[co->index];
1537 touch_nmi_watchdog();
1539 local_irq_save(flags);
1540 if (priv->port.sysrq) {
1541 /* serial8250_handle_port() already took the lock */
1543 } else if (oops_in_progress) {
1544 locked = spin_trylock(&priv->port.lock);
1546 spin_lock(&priv->port.lock);
1549 * First save the IER then disable the interrupts
1551 ier = ioread8(priv->membase + UART_IER);
1553 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1555 uart_console_write(&priv->port, s, count, pch_console_putchar);
1558 * Finally, wait for transmitter to become empty
1559 * and restore the IER
1561 wait_for_xmitr(priv, BOTH_EMPTY);
1562 iowrite8(ier, priv->membase + UART_IER);
1565 spin_unlock(&priv->port.lock);
1566 local_irq_restore(flags);
1569 static int __init pch_console_setup(struct console *co, char *options)
1571 struct uart_port *port;
1572 int baud = default_baud;
1578 * Check whether an invalid uart number has been specified, and
1579 * if so, search for the first available port that does have
1582 if (co->index >= PCH_UART_NR)
1584 port = &pch_uart_ports[co->index]->port;
1586 if (!port || (!port->iobase && !port->membase))
1589 port->uartclk = pch_uart_get_uartclk();
1592 uart_parse_options(options, &baud, &parity, &bits, &flow);
1594 return uart_set_options(port, co, baud, parity, bits, flow);
1597 static struct uart_driver pch_uart_driver;
1599 static struct console pch_console = {
1600 .name = PCH_UART_DRIVER_DEVICE,
1601 .write = pch_console_write,
1602 .device = uart_console_device,
1603 .setup = pch_console_setup,
1604 .flags = CON_PRINTBUFFER | CON_ANYTIME,
1606 .data = &pch_uart_driver,
1609 #define PCH_CONSOLE (&pch_console)
1611 #define PCH_CONSOLE NULL
1614 static struct uart_driver pch_uart_driver = {
1615 .owner = THIS_MODULE,
1616 .driver_name = KBUILD_MODNAME,
1617 .dev_name = PCH_UART_DRIVER_DEVICE,
1621 .cons = PCH_CONSOLE,
1624 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1625 const struct pci_device_id *id)
1627 struct eg20t_port *priv;
1629 unsigned int iobase;
1630 unsigned int mapbase;
1631 unsigned char *rxbuf;
1634 struct pch_uart_driver_data *board;
1635 char name[32]; /* for debugfs file name */
1637 board = &drv_dat[id->driver_data];
1638 port_type = board->port_type;
1640 priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1642 goto init_port_alloc_err;
1644 rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1646 goto init_port_free_txbuf;
1648 switch (port_type) {
1650 fifosize = 256; /* EG20T/ML7213: UART0 */
1653 fifosize = 64; /* EG20T:UART1~3 ML7213: UART1~2*/
1656 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1657 goto init_port_hal_free;
1660 pci_enable_msi(pdev);
1661 pci_set_master(pdev);
1663 iobase = pci_resource_start(pdev, 0);
1664 mapbase = pci_resource_start(pdev, 1);
1665 priv->mapbase = mapbase;
1666 priv->iobase = iobase;
1669 priv->rxbuf.buf = rxbuf;
1670 priv->rxbuf.size = PAGE_SIZE;
1672 priv->fifo_size = fifosize;
1673 priv->uartclk = pch_uart_get_uartclk();
1674 priv->port_type = PORT_MAX_8250 + port_type + 1;
1675 priv->port.dev = &pdev->dev;
1676 priv->port.iobase = iobase;
1677 priv->port.membase = NULL;
1678 priv->port.mapbase = mapbase;
1679 priv->port.irq = pdev->irq;
1680 priv->port.iotype = UPIO_PORT;
1681 priv->port.ops = &pch_uart_ops;
1682 priv->port.flags = UPF_BOOT_AUTOCONF;
1683 priv->port.fifosize = fifosize;
1684 priv->port.line = board->line_no;
1685 priv->trigger = PCH_UART_HAL_TRIGGER_M;
1687 spin_lock_init(&priv->port.lock);
1689 pci_set_drvdata(pdev, priv);
1690 priv->trigger_level = 1;
1693 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1694 pch_uart_ports[board->line_no] = priv;
1696 ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1698 goto init_port_hal_free;
1700 #ifdef CONFIG_DEBUG_FS
1701 snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1702 priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1703 NULL, priv, &port_regs_ops);
1709 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1710 pch_uart_ports[board->line_no] = NULL;
1712 free_page((unsigned long)rxbuf);
1713 init_port_free_txbuf:
1715 init_port_alloc_err:
1720 static void pch_uart_exit_port(struct eg20t_port *priv)
1723 #ifdef CONFIG_DEBUG_FS
1725 debugfs_remove(priv->debugfs);
1727 uart_remove_one_port(&pch_uart_driver, &priv->port);
1728 pci_set_drvdata(priv->pdev, NULL);
1729 free_page((unsigned long)priv->rxbuf.buf);
1732 static void pch_uart_pci_remove(struct pci_dev *pdev)
1734 struct eg20t_port *priv = pci_get_drvdata(pdev);
1736 pci_disable_msi(pdev);
1738 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1739 pch_uart_ports[priv->port.line] = NULL;
1741 pch_uart_exit_port(priv);
1742 pci_disable_device(pdev);
1747 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1749 struct eg20t_port *priv = pci_get_drvdata(pdev);
1751 uart_suspend_port(&pch_uart_driver, &priv->port);
1753 pci_save_state(pdev);
1754 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1758 static int pch_uart_pci_resume(struct pci_dev *pdev)
1760 struct eg20t_port *priv = pci_get_drvdata(pdev);
1763 pci_set_power_state(pdev, PCI_D0);
1764 pci_restore_state(pdev);
1766 ret = pci_enable_device(pdev);
1769 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1773 uart_resume_port(&pch_uart_driver, &priv->port);
1778 #define pch_uart_pci_suspend NULL
1779 #define pch_uart_pci_resume NULL
1782 static DEFINE_PCI_DEVICE_TABLE(pch_uart_pci_id) = {
1783 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1784 .driver_data = pch_et20t_uart0},
1785 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1786 .driver_data = pch_et20t_uart1},
1787 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1788 .driver_data = pch_et20t_uart2},
1789 {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1790 .driver_data = pch_et20t_uart3},
1791 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1792 .driver_data = pch_ml7213_uart0},
1793 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1794 .driver_data = pch_ml7213_uart1},
1795 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1796 .driver_data = pch_ml7213_uart2},
1797 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1798 .driver_data = pch_ml7223_uart0},
1799 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1800 .driver_data = pch_ml7223_uart1},
1801 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1802 .driver_data = pch_ml7831_uart0},
1803 {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1804 .driver_data = pch_ml7831_uart1},
1808 static int __devinit pch_uart_pci_probe(struct pci_dev *pdev,
1809 const struct pci_device_id *id)
1812 struct eg20t_port *priv;
1814 ret = pci_enable_device(pdev);
1818 priv = pch_uart_init_port(pdev, id);
1821 goto probe_disable_device;
1823 pci_set_drvdata(pdev, priv);
1827 probe_disable_device:
1828 pci_disable_msi(pdev);
1829 pci_disable_device(pdev);
1834 static struct pci_driver pch_uart_pci_driver = {
1836 .id_table = pch_uart_pci_id,
1837 .probe = pch_uart_pci_probe,
1838 .remove = __devexit_p(pch_uart_pci_remove),
1839 .suspend = pch_uart_pci_suspend,
1840 .resume = pch_uart_pci_resume,
1843 static int __init pch_uart_module_init(void)
1847 /* register as UART driver */
1848 ret = uart_register_driver(&pch_uart_driver);
1852 /* register as PCI driver */
1853 ret = pci_register_driver(&pch_uart_pci_driver);
1855 uart_unregister_driver(&pch_uart_driver);
1859 module_init(pch_uart_module_init);
1861 static void __exit pch_uart_module_exit(void)
1863 pci_unregister_driver(&pch_uart_pci_driver);
1864 uart_unregister_driver(&pch_uart_driver);
1866 module_exit(pch_uart_module_exit);
1868 MODULE_LICENSE("GPL v2");
1869 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1870 module_param(default_baud, uint, S_IRUGO);
1871 MODULE_PARM_DESC(default_baud,
1872 "Default BAUD for initial driver state and console (default 9600)");
1873 module_param(user_uartclk, uint, S_IRUGO);
1874 MODULE_PARM_DESC(user_uartclk,
1875 "Override UART default or board specific UART clock");