1 // SPDX-License-Identifier: GPL-2.0+
3 * Actions Semi Owl family serial console
5 * Copyright 2013 Actions Semi Inc.
6 * Author: Actions Semi, Inc.
8 * Copyright (c) 2016-2017 Andreas Färber
11 #include <linux/clk.h>
12 #include <linux/console.h>
13 #include <linux/delay.h>
15 #include <linux/iopoll.h>
16 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/serial.h>
20 #include <linux/serial_core.h>
21 #include <linux/tty.h>
22 #include <linux/tty_flip.h>
24 #define OWL_UART_PORT_NUM 7
25 #define OWL_UART_DEV_NAME "ttyOWL"
27 #define OWL_UART_CTL 0x000
28 #define OWL_UART_RXDAT 0x004
29 #define OWL_UART_TXDAT 0x008
30 #define OWL_UART_STAT 0x00c
32 #define OWL_UART_CTL_DWLS_MASK GENMASK(1, 0)
33 #define OWL_UART_CTL_DWLS_5BITS (0x0 << 0)
34 #define OWL_UART_CTL_DWLS_6BITS (0x1 << 0)
35 #define OWL_UART_CTL_DWLS_7BITS (0x2 << 0)
36 #define OWL_UART_CTL_DWLS_8BITS (0x3 << 0)
37 #define OWL_UART_CTL_STPS_2BITS BIT(2)
38 #define OWL_UART_CTL_PRS_MASK GENMASK(6, 4)
39 #define OWL_UART_CTL_PRS_NONE (0x0 << 4)
40 #define OWL_UART_CTL_PRS_ODD (0x4 << 4)
41 #define OWL_UART_CTL_PRS_MARK (0x5 << 4)
42 #define OWL_UART_CTL_PRS_EVEN (0x6 << 4)
43 #define OWL_UART_CTL_PRS_SPACE (0x7 << 4)
44 #define OWL_UART_CTL_AFE BIT(12)
45 #define OWL_UART_CTL_TRFS_TX BIT(14)
46 #define OWL_UART_CTL_EN BIT(15)
47 #define OWL_UART_CTL_RXDE BIT(16)
48 #define OWL_UART_CTL_TXDE BIT(17)
49 #define OWL_UART_CTL_RXIE BIT(18)
50 #define OWL_UART_CTL_TXIE BIT(19)
51 #define OWL_UART_CTL_LBEN BIT(20)
53 #define OWL_UART_STAT_RIP BIT(0)
54 #define OWL_UART_STAT_TIP BIT(1)
55 #define OWL_UART_STAT_RXER BIT(2)
56 #define OWL_UART_STAT_TFER BIT(3)
57 #define OWL_UART_STAT_RXST BIT(4)
58 #define OWL_UART_STAT_RFEM BIT(5)
59 #define OWL_UART_STAT_TFFU BIT(6)
60 #define OWL_UART_STAT_CTSS BIT(7)
61 #define OWL_UART_STAT_RTSS BIT(8)
62 #define OWL_UART_STAT_TFES BIT(10)
63 #define OWL_UART_STAT_TRFL_MASK GENMASK(16, 11)
64 #define OWL_UART_STAT_UTBB BIT(17)
66 #define OWL_UART_POLL_USEC 5
67 #define OWL_UART_TIMEOUT_USEC 10000
69 static struct uart_driver owl_uart_driver;
71 struct owl_uart_info {
72 unsigned int tx_fifosize;
75 struct owl_uart_port {
76 struct uart_port port;
80 #define to_owl_uart_port(prt) container_of(prt, struct owl_uart_port, prt)
82 static struct owl_uart_port *owl_uart_ports[OWL_UART_PORT_NUM];
84 static inline void owl_uart_write(struct uart_port *port, u32 val, unsigned int off)
86 writel(val, port->membase + off);
89 static inline u32 owl_uart_read(struct uart_port *port, unsigned int off)
91 return readl(port->membase + off);
94 static void owl_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
98 ctl = owl_uart_read(port, OWL_UART_CTL);
100 if (mctrl & TIOCM_LOOP)
101 ctl |= OWL_UART_CTL_LBEN;
103 ctl &= ~OWL_UART_CTL_LBEN;
105 owl_uart_write(port, ctl, OWL_UART_CTL);
108 static unsigned int owl_uart_get_mctrl(struct uart_port *port)
110 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR;
113 ctl = owl_uart_read(port, OWL_UART_CTL);
114 stat = owl_uart_read(port, OWL_UART_STAT);
115 if (stat & OWL_UART_STAT_RTSS)
117 if ((stat & OWL_UART_STAT_CTSS) || !(ctl & OWL_UART_CTL_AFE))
122 static unsigned int owl_uart_tx_empty(struct uart_port *port)
128 spin_lock_irqsave(&port->lock, flags);
130 val = owl_uart_read(port, OWL_UART_STAT);
131 ret = (val & OWL_UART_STAT_TFES) ? TIOCSER_TEMT : 0;
133 spin_unlock_irqrestore(&port->lock, flags);
138 static void owl_uart_stop_rx(struct uart_port *port)
142 val = owl_uart_read(port, OWL_UART_CTL);
143 val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_RXDE);
144 owl_uart_write(port, val, OWL_UART_CTL);
146 val = owl_uart_read(port, OWL_UART_STAT);
147 val |= OWL_UART_STAT_RIP;
148 owl_uart_write(port, val, OWL_UART_STAT);
151 static void owl_uart_stop_tx(struct uart_port *port)
155 val = owl_uart_read(port, OWL_UART_CTL);
156 val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_TXDE);
157 owl_uart_write(port, val, OWL_UART_CTL);
159 val = owl_uart_read(port, OWL_UART_STAT);
160 val |= OWL_UART_STAT_TIP;
161 owl_uart_write(port, val, OWL_UART_STAT);
164 static void owl_uart_start_tx(struct uart_port *port)
168 if (uart_tx_stopped(port)) {
169 owl_uart_stop_tx(port);
173 val = owl_uart_read(port, OWL_UART_STAT);
174 val |= OWL_UART_STAT_TIP;
175 owl_uart_write(port, val, OWL_UART_STAT);
177 val = owl_uart_read(port, OWL_UART_CTL);
178 val |= OWL_UART_CTL_TXIE;
179 owl_uart_write(port, val, OWL_UART_CTL);
182 static void owl_uart_send_chars(struct uart_port *port)
186 uart_port_tx(port, ch,
187 !(owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU),
188 owl_uart_write(port, ch, OWL_UART_TXDAT));
191 static void owl_uart_receive_chars(struct uart_port *port)
195 val = owl_uart_read(port, OWL_UART_CTL);
196 val &= ~OWL_UART_CTL_TRFS_TX;
197 owl_uart_write(port, val, OWL_UART_CTL);
199 stat = owl_uart_read(port, OWL_UART_STAT);
200 while (!(stat & OWL_UART_STAT_RFEM)) {
201 char flag = TTY_NORMAL;
203 if (stat & OWL_UART_STAT_RXER)
204 port->icount.overrun++;
206 if (stat & OWL_UART_STAT_RXST) {
207 /* We are not able to distinguish the error type. */
209 port->icount.frame++;
211 stat &= port->read_status_mask;
212 if (stat & OWL_UART_STAT_RXST)
217 val = owl_uart_read(port, OWL_UART_RXDAT);
220 if ((stat & port->ignore_status_mask) == 0)
221 tty_insert_flip_char(&port->state->port, val, flag);
223 stat = owl_uart_read(port, OWL_UART_STAT);
226 tty_flip_buffer_push(&port->state->port);
229 static irqreturn_t owl_uart_irq(int irq, void *dev_id)
231 struct uart_port *port = dev_id;
235 spin_lock_irqsave(&port->lock, flags);
237 stat = owl_uart_read(port, OWL_UART_STAT);
239 if (stat & OWL_UART_STAT_RIP)
240 owl_uart_receive_chars(port);
242 if (stat & OWL_UART_STAT_TIP)
243 owl_uart_send_chars(port);
245 stat = owl_uart_read(port, OWL_UART_STAT);
246 stat |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP;
247 owl_uart_write(port, stat, OWL_UART_STAT);
249 spin_unlock_irqrestore(&port->lock, flags);
254 static void owl_uart_shutdown(struct uart_port *port)
259 spin_lock_irqsave(&port->lock, flags);
261 val = owl_uart_read(port, OWL_UART_CTL);
262 val &= ~(OWL_UART_CTL_TXIE | OWL_UART_CTL_RXIE
263 | OWL_UART_CTL_TXDE | OWL_UART_CTL_RXDE | OWL_UART_CTL_EN);
264 owl_uart_write(port, val, OWL_UART_CTL);
266 spin_unlock_irqrestore(&port->lock, flags);
268 free_irq(port->irq, port);
271 static int owl_uart_startup(struct uart_port *port)
277 ret = request_irq(port->irq, owl_uart_irq, IRQF_TRIGGER_HIGH,
282 spin_lock_irqsave(&port->lock, flags);
284 val = owl_uart_read(port, OWL_UART_STAT);
285 val |= OWL_UART_STAT_RIP | OWL_UART_STAT_TIP
286 | OWL_UART_STAT_RXER | OWL_UART_STAT_TFER | OWL_UART_STAT_RXST;
287 owl_uart_write(port, val, OWL_UART_STAT);
289 val = owl_uart_read(port, OWL_UART_CTL);
290 val |= OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE;
291 val |= OWL_UART_CTL_EN;
292 owl_uart_write(port, val, OWL_UART_CTL);
294 spin_unlock_irqrestore(&port->lock, flags);
299 static void owl_uart_change_baudrate(struct owl_uart_port *owl_port,
302 clk_set_rate(owl_port->clk, baud * 8);
305 static void owl_uart_set_termios(struct uart_port *port,
306 struct ktermios *termios,
307 const struct ktermios *old)
309 struct owl_uart_port *owl_port = to_owl_uart_port(port);
314 spin_lock_irqsave(&port->lock, flags);
316 ctl = owl_uart_read(port, OWL_UART_CTL);
318 ctl &= ~OWL_UART_CTL_DWLS_MASK;
319 switch (termios->c_cflag & CSIZE) {
321 ctl |= OWL_UART_CTL_DWLS_5BITS;
324 ctl |= OWL_UART_CTL_DWLS_6BITS;
327 ctl |= OWL_UART_CTL_DWLS_7BITS;
331 ctl |= OWL_UART_CTL_DWLS_8BITS;
335 if (termios->c_cflag & CSTOPB)
336 ctl |= OWL_UART_CTL_STPS_2BITS;
338 ctl &= ~OWL_UART_CTL_STPS_2BITS;
340 ctl &= ~OWL_UART_CTL_PRS_MASK;
341 if (termios->c_cflag & PARENB) {
342 if (termios->c_cflag & CMSPAR) {
343 if (termios->c_cflag & PARODD)
344 ctl |= OWL_UART_CTL_PRS_MARK;
346 ctl |= OWL_UART_CTL_PRS_SPACE;
347 } else if (termios->c_cflag & PARODD)
348 ctl |= OWL_UART_CTL_PRS_ODD;
350 ctl |= OWL_UART_CTL_PRS_EVEN;
352 ctl |= OWL_UART_CTL_PRS_NONE;
354 if (termios->c_cflag & CRTSCTS)
355 ctl |= OWL_UART_CTL_AFE;
357 ctl &= ~OWL_UART_CTL_AFE;
359 owl_uart_write(port, ctl, OWL_UART_CTL);
361 baud = uart_get_baud_rate(port, termios, old, 9600, 3200000);
362 owl_uart_change_baudrate(owl_port, baud);
364 /* Don't rewrite B0 */
365 if (tty_termios_baud_rate(termios))
366 tty_termios_encode_baud_rate(termios, baud, baud);
368 port->read_status_mask |= OWL_UART_STAT_RXER;
369 if (termios->c_iflag & INPCK)
370 port->read_status_mask |= OWL_UART_STAT_RXST;
372 uart_update_timeout(port, termios->c_cflag, baud);
374 spin_unlock_irqrestore(&port->lock, flags);
377 static void owl_uart_release_port(struct uart_port *port)
379 struct platform_device *pdev = to_platform_device(port->dev);
380 struct resource *res;
382 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
386 if (port->flags & UPF_IOREMAP) {
387 devm_release_mem_region(port->dev, port->mapbase,
389 devm_iounmap(port->dev, port->membase);
390 port->membase = NULL;
394 static int owl_uart_request_port(struct uart_port *port)
396 struct platform_device *pdev = to_platform_device(port->dev);
397 struct resource *res;
399 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
403 if (!devm_request_mem_region(port->dev, port->mapbase,
404 resource_size(res), dev_name(port->dev)))
407 if (port->flags & UPF_IOREMAP) {
408 port->membase = devm_ioremap(port->dev, port->mapbase,
417 static const char *owl_uart_type(struct uart_port *port)
419 return (port->type == PORT_OWL) ? "owl-uart" : NULL;
422 static int owl_uart_verify_port(struct uart_port *port,
423 struct serial_struct *ser)
425 if (port->type != PORT_OWL)
428 if (port->irq != ser->irq)
434 static void owl_uart_config_port(struct uart_port *port, int flags)
436 if (flags & UART_CONFIG_TYPE) {
437 port->type = PORT_OWL;
438 owl_uart_request_port(port);
442 #ifdef CONFIG_CONSOLE_POLL
444 static int owl_uart_poll_get_char(struct uart_port *port)
446 if (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_RFEM)
449 return owl_uart_read(port, OWL_UART_RXDAT);
452 static void owl_uart_poll_put_char(struct uart_port *port, unsigned char ch)
457 /* Wait while FIFO is full or timeout */
458 ret = readl_poll_timeout_atomic(port->membase + OWL_UART_STAT, reg,
459 !(reg & OWL_UART_STAT_TFFU),
461 OWL_UART_TIMEOUT_USEC);
462 if (ret == -ETIMEDOUT) {
463 dev_err(port->dev, "Timeout waiting while UART TX FULL\n");
467 owl_uart_write(port, ch, OWL_UART_TXDAT);
470 #endif /* CONFIG_CONSOLE_POLL */
472 static const struct uart_ops owl_uart_ops = {
473 .set_mctrl = owl_uart_set_mctrl,
474 .get_mctrl = owl_uart_get_mctrl,
475 .tx_empty = owl_uart_tx_empty,
476 .start_tx = owl_uart_start_tx,
477 .stop_rx = owl_uart_stop_rx,
478 .stop_tx = owl_uart_stop_tx,
479 .startup = owl_uart_startup,
480 .shutdown = owl_uart_shutdown,
481 .set_termios = owl_uart_set_termios,
482 .type = owl_uart_type,
483 .config_port = owl_uart_config_port,
484 .request_port = owl_uart_request_port,
485 .release_port = owl_uart_release_port,
486 .verify_port = owl_uart_verify_port,
487 #ifdef CONFIG_CONSOLE_POLL
488 .poll_get_char = owl_uart_poll_get_char,
489 .poll_put_char = owl_uart_poll_put_char,
493 #ifdef CONFIG_SERIAL_OWL_CONSOLE
495 static void owl_console_putchar(struct uart_port *port, unsigned char ch)
500 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TFFU)
503 owl_uart_write(port, ch, OWL_UART_TXDAT);
506 static void owl_uart_port_write(struct uart_port *port, const char *s,
513 local_irq_save(flags);
517 else if (oops_in_progress)
518 locked = spin_trylock(&port->lock);
520 spin_lock(&port->lock);
524 old_ctl = owl_uart_read(port, OWL_UART_CTL);
525 val = old_ctl | OWL_UART_CTL_TRFS_TX;
527 val &= ~(OWL_UART_CTL_RXIE | OWL_UART_CTL_TXIE);
528 owl_uart_write(port, val, OWL_UART_CTL);
530 uart_console_write(port, s, count, owl_console_putchar);
532 /* wait until all contents have been sent out */
533 while (owl_uart_read(port, OWL_UART_STAT) & OWL_UART_STAT_TRFL_MASK)
536 /* clear IRQ pending */
537 val = owl_uart_read(port, OWL_UART_STAT);
538 val |= OWL_UART_STAT_TIP | OWL_UART_STAT_RIP;
539 owl_uart_write(port, val, OWL_UART_STAT);
541 owl_uart_write(port, old_ctl, OWL_UART_CTL);
544 spin_unlock(&port->lock);
546 local_irq_restore(flags);
549 static void owl_uart_console_write(struct console *co, const char *s,
552 struct owl_uart_port *owl_port;
554 owl_port = owl_uart_ports[co->index];
558 owl_uart_port_write(&owl_port->port, s, count);
561 static int owl_uart_console_setup(struct console *co, char *options)
563 struct owl_uart_port *owl_port;
569 if (co->index < 0 || co->index >= OWL_UART_PORT_NUM)
572 owl_port = owl_uart_ports[co->index];
573 if (!owl_port || !owl_port->port.membase)
577 uart_parse_options(options, &baud, &parity, &bits, &flow);
579 return uart_set_options(&owl_port->port, co, baud, parity, bits, flow);
582 static struct console owl_uart_console = {
583 .name = OWL_UART_DEV_NAME,
584 .write = owl_uart_console_write,
585 .device = uart_console_device,
586 .setup = owl_uart_console_setup,
587 .flags = CON_PRINTBUFFER,
589 .data = &owl_uart_driver,
592 static int __init owl_uart_console_init(void)
594 register_console(&owl_uart_console);
598 console_initcall(owl_uart_console_init);
600 static void owl_uart_early_console_write(struct console *co,
604 struct earlycon_device *dev = co->data;
606 owl_uart_port_write(&dev->port, s, count);
610 owl_uart_early_console_setup(struct earlycon_device *device, const char *opt)
612 if (!device->port.membase)
615 device->con->write = owl_uart_early_console_write;
619 OF_EARLYCON_DECLARE(owl, "actions,owl-uart",
620 owl_uart_early_console_setup);
622 #define OWL_UART_CONSOLE (&owl_uart_console)
624 #define OWL_UART_CONSOLE NULL
627 static struct uart_driver owl_uart_driver = {
628 .owner = THIS_MODULE,
629 .driver_name = "owl-uart",
630 .dev_name = OWL_UART_DEV_NAME,
631 .nr = OWL_UART_PORT_NUM,
632 .cons = OWL_UART_CONSOLE,
635 static const struct owl_uart_info owl_s500_info = {
639 static const struct owl_uart_info owl_s900_info = {
643 static const struct of_device_id owl_uart_dt_matches[] = {
644 { .compatible = "actions,s500-uart", .data = &owl_s500_info },
645 { .compatible = "actions,s900-uart", .data = &owl_s900_info },
648 MODULE_DEVICE_TABLE(of, owl_uart_dt_matches);
650 static int owl_uart_probe(struct platform_device *pdev)
652 const struct of_device_id *match;
653 const struct owl_uart_info *info = NULL;
654 struct resource *res_mem;
655 struct owl_uart_port *owl_port;
658 if (pdev->dev.of_node) {
659 pdev->id = of_alias_get_id(pdev->dev.of_node, "serial");
660 match = of_match_node(owl_uart_dt_matches, pdev->dev.of_node);
665 if (pdev->id < 0 || pdev->id >= OWL_UART_PORT_NUM) {
666 dev_err(&pdev->dev, "id %d out of range\n", pdev->id);
670 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
672 dev_err(&pdev->dev, "could not get mem\n");
676 irq = platform_get_irq(pdev, 0);
680 if (owl_uart_ports[pdev->id]) {
681 dev_err(&pdev->dev, "port %d already allocated\n", pdev->id);
685 owl_port = devm_kzalloc(&pdev->dev, sizeof(*owl_port), GFP_KERNEL);
689 owl_port->clk = devm_clk_get(&pdev->dev, NULL);
690 if (IS_ERR(owl_port->clk)) {
691 dev_err(&pdev->dev, "could not get clk\n");
692 return PTR_ERR(owl_port->clk);
695 ret = clk_prepare_enable(owl_port->clk);
697 dev_err(&pdev->dev, "could not enable clk\n");
701 owl_port->port.dev = &pdev->dev;
702 owl_port->port.line = pdev->id;
703 owl_port->port.type = PORT_OWL;
704 owl_port->port.iotype = UPIO_MEM;
705 owl_port->port.mapbase = res_mem->start;
706 owl_port->port.irq = irq;
707 owl_port->port.uartclk = clk_get_rate(owl_port->clk);
708 if (owl_port->port.uartclk == 0) {
709 dev_err(&pdev->dev, "clock rate is zero\n");
710 clk_disable_unprepare(owl_port->clk);
713 owl_port->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP | UPF_LOW_LATENCY;
714 owl_port->port.x_char = 0;
715 owl_port->port.fifosize = (info) ? info->tx_fifosize : 16;
716 owl_port->port.ops = &owl_uart_ops;
718 owl_uart_ports[pdev->id] = owl_port;
719 platform_set_drvdata(pdev, owl_port);
721 ret = uart_add_one_port(&owl_uart_driver, &owl_port->port);
723 owl_uart_ports[pdev->id] = NULL;
728 static int owl_uart_remove(struct platform_device *pdev)
730 struct owl_uart_port *owl_port = platform_get_drvdata(pdev);
732 uart_remove_one_port(&owl_uart_driver, &owl_port->port);
733 owl_uart_ports[pdev->id] = NULL;
734 clk_disable_unprepare(owl_port->clk);
739 static struct platform_driver owl_uart_platform_driver = {
740 .probe = owl_uart_probe,
741 .remove = owl_uart_remove,
744 .of_match_table = owl_uart_dt_matches,
748 static int __init owl_uart_init(void)
752 ret = uart_register_driver(&owl_uart_driver);
756 ret = platform_driver_register(&owl_uart_platform_driver);
758 uart_unregister_driver(&owl_uart_driver);
763 static void __exit owl_uart_exit(void)
765 platform_driver_unregister(&owl_uart_platform_driver);
766 uart_unregister_driver(&owl_uart_driver);
769 module_init(owl_uart_init);
770 module_exit(owl_uart_exit);
772 MODULE_LICENSE("GPL");