drivers/tty/serial/omap-serial.c

   1 /*
   2  * Driver for OMAP-UART controller.
   3  * Based on drivers/serial/8250.c
   4  *
   5  * Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Authors:
   8  *      Govindraj R     <govindraj.raja@ti.com>
   9  *      Thara Gopinath  <thara@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  * Note: This driver is made separate from 8250 driver as we cannot
  17  * over load 8250 driver with omap platform specific configuration for
  18  * features like DMA, it makes easier to implement features like DMA and
  19  * hardware flow control and software flow control configuration with
  20  * this driver as required for the omap-platform.
  21  */
  22
  23 #if defined(CONFIG_SERIAL_OMAP_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  24 #define SUPPORT_SYSRQ
  25 #endif
  26
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/console.h>
  30 #include <linux/serial_reg.h>
  31 #include <linux/delay.h>
  32 #include <linux/slab.h>
  33 #include <linux/tty.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/platform_device.h>
  36 #include <linux/io.h>
  37 #include <linux/clk.h>
  38 #include <linux/serial_core.h>
  39 #include <linux/irq.h>
  40 #include <linux/pm_runtime.h>
  41 #include <linux/of.h>
  42 #include <linux/gpio.h>
  43 #include <linux/pinctrl/consumer.h>
  44
  45 #include <plat/omap-serial.h>
  46
  47 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  48
  49 #define OMAP_UART_REV_42 0x0402
  50 #define OMAP_UART_REV_46 0x0406
  51 #define OMAP_UART_REV_52 0x0502
  52 #define OMAP_UART_REV_63 0x0603
  53
  54 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
  55
  56 /* SCR register bitmasks */
  57 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  58
  59 /* FCR register bitmasks */
  60 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  61 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  62
  63 /* MVR register bitmasks */
  64 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  65
  66 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  67 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  68 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  69
  70 #define OMAP_UART_MVR_MAJ_MASK          0x700
  71 #define OMAP_UART_MVR_MAJ_SHIFT         8
  72 #define OMAP_UART_MVR_MIN_MASK          0x3f
  73
  74 struct uart_omap_port {
  75         struct uart_port        port;
  76         struct uart_omap_dma    uart_dma;
  77         struct device           *dev;
  78
  79         unsigned char           ier;
  80         unsigned char           lcr;
  81         unsigned char           mcr;
  82         unsigned char           fcr;
  83         unsigned char           efr;
  84         unsigned char           dll;
  85         unsigned char           dlh;
  86         unsigned char           mdr1;
  87         unsigned char           scr;
  88
  89         int                     use_dma;
  90         /*
  91          * Some bits in registers are cleared on a read, so they must
  92          * be saved whenever the register is read but the bits will not
  93          * be immediately processed.
  94          */
  95         unsigned int            lsr_break_flag;
  96         unsigned char           msr_saved_flags;
  97         char                    name[20];
  98         unsigned long           port_activity;
  99         int                     context_loss_cnt;
 100         u32                     errata;
 101         u8                      wakeups_enabled;
 102         unsigned int            irq_pending:1;
 103
 104         int                     DTR_gpio;
 105         int                     DTR_inverted;
 106         int                     DTR_active;
 107
 108         struct pm_qos_request   pm_qos_request;
 109         u32                     latency;
 110         u32                     calc_latency;
 111         struct work_struct      qos_work;
 112         struct pinctrl          *pins;
 113 };
 114
 115 #define to_uart_omap_port(p)    ((container_of((p), struct uart_omap_port, port)))
 116
 117 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 118
 119 /* Forward declaration of functions */
 120 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 121
 122 static struct workqueue_struct *serial_omap_uart_wq;
 123
 124 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 125 {
 126         offset <<= up->port.regshift;
 127         return readw(up->port.membase + offset);
 128 }
 129
 130 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 131 {
 132         offset <<= up->port.regshift;
 133         writew(value, up->port.membase + offset);
 134 }
 135
 136 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 137 {
 138         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 139         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 140                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 141         serial_out(up, UART_FCR, 0);
 142 }
 143
 144 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 145 {
 146         struct omap_uart_port_info *pdata = up->dev->platform_data;
 147
 148         if (!pdata || !pdata->get_context_loss_count)
 149                 return 0;
 150
 151         return pdata->get_context_loss_count(up->dev);
 152 }
 153
 154 static void serial_omap_set_forceidle(struct uart_omap_port *up)
 155 {
 156         struct omap_uart_port_info *pdata = up->dev->platform_data;
 157
 158         if (!pdata || !pdata->set_forceidle)
 159                 return;
 160
 161         pdata->set_forceidle(up->dev);
 162 }
 163
 164 static void serial_omap_set_noidle(struct uart_omap_port *up)
 165 {
 166         struct omap_uart_port_info *pdata = up->dev->platform_data;
 167
 168         if (!pdata || !pdata->set_noidle)
 169                 return;
 170
 171         pdata->set_noidle(up->dev);
 172 }
 173
 174 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 175 {
 176         struct omap_uart_port_info *pdata = up->dev->platform_data;
 177
 178         if (!pdata || !pdata->enable_wakeup)
 179                 return;
 180
 181         pdata->enable_wakeup(up->dev, enable);
 182 }
 183
 184 /*
 185  * serial_omap_get_divisor - calculate divisor value
 186  * @port: uart port info
 187  * @baud: baudrate for which divisor needs to be calculated.
 188  *
 189  * We have written our own function to get the divisor so as to support
 190  * 13x mode. 3Mbps Baudrate as an different divisor.
 191  * Reference OMAP TRM Chapter 17:
 192  * Table 17-1. UART Mode Baud Rates, Divisor Values, and Error Rates
 193  * referring to oversampling - divisor value
 194  * baudrate 460,800 to 3,686,400 all have divisor 13
 195  * except 3,000,000 which has divisor value 16
 196  */
 197 static unsigned int
 198 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 199 {
 200         unsigned int divisor;
 201
 202         if (baud > OMAP_MODE13X_SPEED && baud != 3000000)
 203                 divisor = 13;
 204         else
 205                 divisor = 16;
 206         return port->uartclk/(baud * divisor);
 207 }
 208
 209 static void serial_omap_enable_ms(struct uart_port *port)
 210 {
 211         struct uart_omap_port *up = to_uart_omap_port(port);
 212
 213         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 214
 215         pm_runtime_get_sync(up->dev);
 216         up->ier |= UART_IER_MSI;
 217         serial_out(up, UART_IER, up->ier);
 218         pm_runtime_mark_last_busy(up->dev);
 219         pm_runtime_put_autosuspend(up->dev);
 220 }
 221
 222 static void serial_omap_stop_tx(struct uart_port *port)
 223 {
 224         struct uart_omap_port *up = to_uart_omap_port(port);
 225
 226         pm_runtime_get_sync(up->dev);
 227         if (up->ier & UART_IER_THRI) {
 228                 up->ier &= ~UART_IER_THRI;
 229                 serial_out(up, UART_IER, up->ier);
 230         }
 231
 232         serial_omap_set_forceidle(up);
 233
 234         pm_runtime_mark_last_busy(up->dev);
 235         pm_runtime_put_autosuspend(up->dev);
 236 }
 237
 238 static void serial_omap_stop_rx(struct uart_port *port)
 239 {
 240         struct uart_omap_port *up = to_uart_omap_port(port);
 241
 242         pm_runtime_get_sync(up->dev);
 243         up->ier &= ~UART_IER_RLSI;
 244         up->port.read_status_mask &= ~UART_LSR_DR;
 245         serial_out(up, UART_IER, up->ier);
 246         pm_runtime_mark_last_busy(up->dev);
 247         pm_runtime_put_autosuspend(up->dev);
 248 }
 249
 250 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 251 {
 252         struct circ_buf *xmit = &up->port.state->xmit;
 253         int count;
 254
 255         if (!(lsr & UART_LSR_THRE))
 256                 return;
 257
 258         if (up->port.x_char) {
 259                 serial_out(up, UART_TX, up->port.x_char);
 260                 up->port.icount.tx++;
 261                 up->port.x_char = 0;
 262                 return;
 263         }
 264         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 265                 serial_omap_stop_tx(&up->port);
 266                 return;
 267         }
 268         count = up->port.fifosize / 4;
 269         do {
 270                 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
 271                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 272                 up->port.icount.tx++;
 273                 if (uart_circ_empty(xmit))
 274                         break;
 275         } while (--count > 0);
 276
 277         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) {
 278                 spin_unlock(&up->port.lock);
 279                 uart_write_wakeup(&up->port);
 280                 spin_lock(&up->port.lock);
 281         }
 282
 283         if (uart_circ_empty(xmit))
 284                 serial_omap_stop_tx(&up->port);
 285 }
 286
 287 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 288 {
 289         if (!(up->ier & UART_IER_THRI)) {
 290                 up->ier |= UART_IER_THRI;
 291                 serial_out(up, UART_IER, up->ier);
 292         }
 293 }
 294
 295 static void serial_omap_start_tx(struct uart_port *port)
 296 {
 297         struct uart_omap_port *up = to_uart_omap_port(port);
 298
 299         pm_runtime_get_sync(up->dev);
 300         serial_omap_enable_ier_thri(up);
 301         serial_omap_set_noidle(up);
 302         pm_runtime_mark_last_busy(up->dev);
 303         pm_runtime_put_autosuspend(up->dev);
 304 }
 305
 306 static unsigned int check_modem_status(struct uart_omap_port *up)
 307 {
 308         unsigned int status;
 309
 310         status = serial_in(up, UART_MSR);
 311         status |= up->msr_saved_flags;
 312         up->msr_saved_flags = 0;
 313         if ((status & UART_MSR_ANY_DELTA) == 0)
 314                 return status;
 315
 316         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 317             up->port.state != NULL) {
 318                 if (status & UART_MSR_TERI)
 319                         up->port.icount.rng++;
 320                 if (status & UART_MSR_DDSR)
 321                         up->port.icount.dsr++;
 322                 if (status & UART_MSR_DDCD)
 323                         uart_handle_dcd_change
 324                                 (&up->port, status & UART_MSR_DCD);
 325                 if (status & UART_MSR_DCTS)
 326                         uart_handle_cts_change
 327                                 (&up->port, status & UART_MSR_CTS);
 328                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 329         }
 330
 331         return status;
 332 }
 333
 334 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 335 {
 336         unsigned int flag;
 337         unsigned char ch = 0;
 338
 339         if (likely(lsr & UART_LSR_DR))
 340                 ch = serial_in(up, UART_RX);
 341
 342         up->port.icount.rx++;
 343         flag = TTY_NORMAL;
 344
 345         if (lsr & UART_LSR_BI) {
 346                 flag = TTY_BREAK;
 347                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 348                 up->port.icount.brk++;
 349                 /*
 350                  * We do the SysRQ and SAK checking
 351                  * here because otherwise the break
 352                  * may get masked by ignore_status_mask
 353                  * or read_status_mask.
 354                  */
 355                 if (uart_handle_break(&up->port))
 356                         return;
 357
 358         }
 359
 360         if (lsr & UART_LSR_PE) {
 361                 flag = TTY_PARITY;
 362                 up->port.icount.parity++;
 363         }
 364
 365         if (lsr & UART_LSR_FE) {
 366                 flag = TTY_FRAME;
 367                 up->port.icount.frame++;
 368         }
 369
 370         if (lsr & UART_LSR_OE)
 371                 up->port.icount.overrun++;
 372
 373 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 374         if (up->port.line == up->port.cons->index) {
 375                 /* Recover the break flag from console xmit */
 376                 lsr |= up->lsr_break_flag;
 377         }
 378 #endif
 379         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 380 }
 381
 382 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 383 {
 384         unsigned char ch = 0;
 385         unsigned int flag;
 386
 387         if (!(lsr & UART_LSR_DR))
 388                 return;
 389
 390         ch = serial_in(up, UART_RX);
 391         flag = TTY_NORMAL;
 392         up->port.icount.rx++;
 393
 394         if (uart_handle_sysrq_char(&up->port, ch))
 395                 return;
 396
 397         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 398 }
 399
 400 /**
 401  * serial_omap_irq() - This handles the interrupt from one port
 402  * @irq: uart port irq number
 403  * @dev_id: uart port info
 404  */
 405 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 406 {
 407         struct uart_omap_port *up = dev_id;
 408         struct tty_struct *tty = up->port.state->port.tty;
 409         unsigned int iir, lsr;
 410         unsigned int type;
 411         irqreturn_t ret = IRQ_NONE;
 412         int max_count = 256;
 413
 414         spin_lock(&up->port.lock);
 415         pm_runtime_get_sync(up->dev);
 416
 417         do {
 418                 iir = serial_in(up, UART_IIR);
 419                 if (iir & UART_IIR_NO_INT)
 420                         break;
 421
 422                 ret = IRQ_HANDLED;
 423                 lsr = serial_in(up, UART_LSR);
 424
 425                 /* extract IRQ type from IIR register */
 426                 type = iir & 0x3e;
 427
 428                 switch (type) {
 429                 case UART_IIR_MSI:
 430                         check_modem_status(up);
 431                         break;
 432                 case UART_IIR_THRI:
 433                         transmit_chars(up, lsr);
 434                         break;
 435                 case UART_IIR_RX_TIMEOUT:
 436                         /* FALLTHROUGH */
 437                 case UART_IIR_RDI:
 438                         serial_omap_rdi(up, lsr);
 439                         break;
 440                 case UART_IIR_RLSI:
 441                         serial_omap_rlsi(up, lsr);
 442                         break;
 443                 case UART_IIR_CTS_RTS_DSR:
 444                         /* simply try again */
 445                         break;
 446                 case UART_IIR_XOFF:
 447                         /* FALLTHROUGH */
 448                 default:
 449                         break;
 450                 }
 451         } while (!(iir & UART_IIR_NO_INT) && max_count--);
 452
 453         spin_unlock(&up->port.lock);
 454
 455         tty_flip_buffer_push(tty);
 456
 457         pm_runtime_mark_last_busy(up->dev);
 458         pm_runtime_put_autosuspend(up->dev);
 459         up->port_activity = jiffies;
 460
 461         return ret;
 462 }
 463
 464 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 465 {
 466         struct uart_omap_port *up = to_uart_omap_port(port);
 467         unsigned long flags = 0;
 468         unsigned int ret = 0;
 469
 470         pm_runtime_get_sync(up->dev);
 471         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 472         spin_lock_irqsave(&up->port.lock, flags);
 473         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 474         spin_unlock_irqrestore(&up->port.lock, flags);
 475         pm_runtime_mark_last_busy(up->dev);
 476         pm_runtime_put_autosuspend(up->dev);
 477         return ret;
 478 }
 479
 480 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 481 {
 482         struct uart_omap_port *up = to_uart_omap_port(port);
 483         unsigned int status;
 484         unsigned int ret = 0;
 485
 486         pm_runtime_get_sync(up->dev);
 487         status = check_modem_status(up);
 488         pm_runtime_mark_last_busy(up->dev);
 489         pm_runtime_put_autosuspend(up->dev);
 490
 491         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 492
 493         if (status & UART_MSR_DCD)
 494                 ret |= TIOCM_CAR;
 495         if (status & UART_MSR_RI)
 496                 ret |= TIOCM_RNG;
 497         if (status & UART_MSR_DSR)
 498                 ret |= TIOCM_DSR;
 499         if (status & UART_MSR_CTS)
 500                 ret |= TIOCM_CTS;
 501         return ret;
 502 }
 503
 504 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 505 {
 506         struct uart_omap_port *up = to_uart_omap_port(port);
 507         unsigned char mcr = 0;
 508
 509         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 510         if (mctrl & TIOCM_RTS)
 511                 mcr |= UART_MCR_RTS;
 512         if (mctrl & TIOCM_DTR)
 513                 mcr |= UART_MCR_DTR;
 514         if (mctrl & TIOCM_OUT1)
 515                 mcr |= UART_MCR_OUT1;
 516         if (mctrl & TIOCM_OUT2)
 517                 mcr |= UART_MCR_OUT2;
 518         if (mctrl & TIOCM_LOOP)
 519                 mcr |= UART_MCR_LOOP;
 520
 521         pm_runtime_get_sync(up->dev);
 522         up->mcr = serial_in(up, UART_MCR);
 523         up->mcr |= mcr;
 524         serial_out(up, UART_MCR, up->mcr);
 525         pm_runtime_mark_last_busy(up->dev);
 526         pm_runtime_put_autosuspend(up->dev);
 527
 528         if (gpio_is_valid(up->DTR_gpio) &&
 529             !!(mctrl & TIOCM_DTR) != up->DTR_active) {
 530                 up->DTR_active = !up->DTR_active;
 531                 if (gpio_cansleep(up->DTR_gpio))
 532                         schedule_work(&up->qos_work);
 533                 else
 534                         gpio_set_value(up->DTR_gpio,
 535                                        up->DTR_active != up->DTR_inverted);
 536         }
 537 }
 538
 539 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 540 {
 541         struct uart_omap_port *up = to_uart_omap_port(port);
 542         unsigned long flags = 0;
 543
 544         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 545         pm_runtime_get_sync(up->dev);
 546         spin_lock_irqsave(&up->port.lock, flags);
 547         if (break_state == -1)
 548                 up->lcr |= UART_LCR_SBC;
 549         else
 550                 up->lcr &= ~UART_LCR_SBC;
 551         serial_out(up, UART_LCR, up->lcr);
 552         spin_unlock_irqrestore(&up->port.lock, flags);
 553         pm_runtime_mark_last_busy(up->dev);
 554         pm_runtime_put_autosuspend(up->dev);
 555 }
 556
 557 static int serial_omap_startup(struct uart_port *port)
 558 {
 559         struct uart_omap_port *up = to_uart_omap_port(port);
 560         unsigned long flags = 0;
 561         int retval;
 562
 563         /*
 564          * Allocate the IRQ
 565          */
 566         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 567                                 up->name, up);
 568         if (retval)
 569                 return retval;
 570
 571         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 572
 573         pm_runtime_get_sync(up->dev);
 574         /*
 575          * Clear the FIFO buffers and disable them.
 576          * (they will be reenabled in set_termios())
 577          */
 578         serial_omap_clear_fifos(up);
 579         /* For Hardware flow control */
 580         serial_out(up, UART_MCR, UART_MCR_RTS);
 581
 582         /*
 583          * Clear the interrupt registers.
 584          */
 585         (void) serial_in(up, UART_LSR);
 586         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 587                 (void) serial_in(up, UART_RX);
 588         (void) serial_in(up, UART_IIR);
 589         (void) serial_in(up, UART_MSR);
 590
 591         /*
 592          * Now, initialize the UART
 593          */
 594         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 595         spin_lock_irqsave(&up->port.lock, flags);
 596         /*
 597          * Most PC uarts need OUT2 raised to enable interrupts.
 598          */
 599         up->port.mctrl |= TIOCM_OUT2;
 600         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 601         spin_unlock_irqrestore(&up->port.lock, flags);
 602
 603         up->msr_saved_flags = 0;
 604         /*
 605          * Finally, enable interrupts. Note: Modem status interrupts
 606          * are set via set_termios(), which will be occurring imminently
 607          * anyway, so we don't enable them here.
 608          */
 609         up->ier = UART_IER_RLSI | UART_IER_RDI;
 610         serial_out(up, UART_IER, up->ier);
 611
 612         /* Enable module level wake up */
 613         serial_out(up, UART_OMAP_WER, OMAP_UART_WER_MOD_WKUP);
 614
 615         pm_runtime_mark_last_busy(up->dev);
 616         pm_runtime_put_autosuspend(up->dev);
 617         up->port_activity = jiffies;
 618         return 0;
 619 }
 620
 621 static void serial_omap_shutdown(struct uart_port *port)
 622 {
 623         struct uart_omap_port *up = to_uart_omap_port(port);
 624         unsigned long flags = 0;
 625
 626         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 627
 628         pm_runtime_get_sync(up->dev);
 629         /*
 630          * Disable interrupts from this port
 631          */
 632         up->ier = 0;
 633         serial_out(up, UART_IER, 0);
 634
 635         spin_lock_irqsave(&up->port.lock, flags);
 636         up->port.mctrl &= ~TIOCM_OUT2;
 637         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 638         spin_unlock_irqrestore(&up->port.lock, flags);
 639
 640         /*
 641          * Disable break condition and FIFOs
 642          */
 643         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 644         serial_omap_clear_fifos(up);
 645
 646         /*
 647          * Read data port to reset things, and then free the irq
 648          */
 649         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 650                 (void) serial_in(up, UART_RX);
 651
 652         pm_runtime_mark_last_busy(up->dev);
 653         pm_runtime_put_autosuspend(up->dev);
 654         free_irq(up->port.irq, up);
 655 }
 656
 657 static inline void
 658 serial_omap_configure_xonxoff
 659                 (struct uart_omap_port *up, struct ktermios *termios)
 660 {
 661         up->lcr = serial_in(up, UART_LCR);
 662         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 663         up->efr = serial_in(up, UART_EFR);
 664         serial_out(up, UART_EFR, up->efr & ~UART_EFR_ECB);
 665
 666         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
 667         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
 668
 669         /* clear SW control mode bits */
 670         up->efr &= OMAP_UART_SW_CLR;
 671
 672         /*
 673          * IXON Flag:
 674          * Enable XON/XOFF flow control on output.
 675          * Transmit XON1, XOFF1
 676          */
 677         if (termios->c_iflag & IXON)
 678                 up->efr |= OMAP_UART_SW_TX;
 679
 680         /*
 681          * IXOFF Flag:
 682          * Enable XON/XOFF flow control on input.
 683          * Receiver compares XON1, XOFF1.
 684          */
 685         if (termios->c_iflag & IXOFF)
 686                 up->efr |= OMAP_UART_SW_RX;
 687
 688         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 689         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 690
 691         up->mcr = serial_in(up, UART_MCR);
 692
 693         /*
 694          * IXANY Flag:
 695          * Enable any character to restart output.
 696          * Operation resumes after receiving any
 697          * character after recognition of the XOFF character
 698          */
 699         if (termios->c_iflag & IXANY)
 700                 up->mcr |= UART_MCR_XONANY;
 701
 702         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 703         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 704         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 705
 706         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 707
 708         serial_out(up, UART_MCR, up->mcr & ~UART_MCR_TCRTLR);
 709         serial_out(up, UART_LCR, up->lcr);
 710 }
 711
 712 static void serial_omap_uart_qos_work(struct work_struct *work)
 713 {
 714         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 715                                                 qos_work);
 716
 717         pm_qos_update_request(&up->pm_qos_request, up->latency);
 718         if (gpio_is_valid(up->DTR_gpio))
 719                 gpio_set_value_cansleep(up->DTR_gpio,
 720                                         up->DTR_active != up->DTR_inverted);
 721 }
 722
 723 static void
 724 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 725                         struct ktermios *old)
 726 {
 727         struct uart_omap_port *up = to_uart_omap_port(port);
 728         unsigned char cval = 0;
 729         unsigned char efr = 0;
 730         unsigned long flags = 0;
 731         unsigned int baud, quot;
 732
 733         switch (termios->c_cflag & CSIZE) {
 734         case CS5:
 735                 cval = UART_LCR_WLEN5;
 736                 break;
 737         case CS6:
 738                 cval = UART_LCR_WLEN6;
 739                 break;
 740         case CS7:
 741                 cval = UART_LCR_WLEN7;
 742                 break;
 743         default:
 744         case CS8:
 745                 cval = UART_LCR_WLEN8;
 746                 break;
 747         }
 748
 749         if (termios->c_cflag & CSTOPB)
 750                 cval |= UART_LCR_STOP;
 751         if (termios->c_cflag & PARENB)
 752                 cval |= UART_LCR_PARITY;
 753         if (!(termios->c_cflag & PARODD))
 754                 cval |= UART_LCR_EPAR;
 755
 756         /*
 757          * Ask the core to calculate the divisor for us.
 758          */
 759
 760         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 761         quot = serial_omap_get_divisor(port, baud);
 762
 763         /* calculate wakeup latency constraint */
 764         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 765         up->latency = up->calc_latency;
 766         schedule_work(&up->qos_work);
 767
 768         up->dll = quot & 0xff;
 769         up->dlh = quot >> 8;
 770         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 771
 772         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 773                         UART_FCR_ENABLE_FIFO;
 774
 775         /*
 776          * Ok, we're now changing the port state. Do it with
 777          * interrupts disabled.
 778          */
 779         pm_runtime_get_sync(up->dev);
 780         spin_lock_irqsave(&up->port.lock, flags);
 781
 782         /*
 783          * Update the per-port timeout.
 784          */
 785         uart_update_timeout(port, termios->c_cflag, baud);
 786
 787         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 788         if (termios->c_iflag & INPCK)
 789                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 790         if (termios->c_iflag & (BRKINT | PARMRK))
 791                 up->port.read_status_mask |= UART_LSR_BI;
 792
 793         /*
 794          * Characters to ignore
 795          */
 796         up->port.ignore_status_mask = 0;
 797         if (termios->c_iflag & IGNPAR)
 798                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 799         if (termios->c_iflag & IGNBRK) {
 800                 up->port.ignore_status_mask |= UART_LSR_BI;
 801                 /*
 802                  * If we're ignoring parity and break indicators,
 803                  * ignore overruns too (for real raw support).
 804                  */
 805                 if (termios->c_iflag & IGNPAR)
 806                         up->port.ignore_status_mask |= UART_LSR_OE;
 807         }
 808
 809         /*
 810          * ignore all characters if CREAD is not set
 811          */
 812         if ((termios->c_cflag & CREAD) == 0)
 813                 up->port.ignore_status_mask |= UART_LSR_DR;
 814
 815         /*
 816          * Modem status interrupts
 817          */
 818         up->ier &= ~UART_IER_MSI;
 819         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 820                 up->ier |= UART_IER_MSI;
 821         serial_out(up, UART_IER, up->ier);
 822         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 823         up->lcr = cval;
 824         up->scr = OMAP_UART_SCR_TX_EMPTY;
 825
 826         /* FIFOs and DMA Settings */
 827
 828         /* FCR can be changed only when the
 829          * baud clock is not running
 830          * DLL_REG and DLH_REG set to 0.
 831          */
 832         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 833         serial_out(up, UART_DLL, 0);
 834         serial_out(up, UART_DLM, 0);
 835         serial_out(up, UART_LCR, 0);
 836
 837         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 838
 839         up->efr = serial_in(up, UART_EFR);
 840         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 841
 842         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 843         up->mcr = serial_in(up, UART_MCR);
 844         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 845         /* FIFO ENABLE, DMA MODE */
 846
 847         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 848
 849         /* Set receive FIFO threshold to 16 characters and
 850          * transmit FIFO threshold to 16 spaces
 851          */
 852         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 853         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 854         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 855                 UART_FCR_ENABLE_FIFO;
 856
 857         serial_out(up, UART_FCR, up->fcr);
 858         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 859
 860         serial_out(up, UART_OMAP_SCR, up->scr);
 861
 862         serial_out(up, UART_EFR, up->efr);
 863         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 864         serial_out(up, UART_MCR, up->mcr);
 865
 866         /* Protocol, Baud Rate, and Interrupt Settings */
 867
 868         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 869                 serial_omap_mdr1_errataset(up, up->mdr1);
 870         else
 871                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 872
 873         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 874
 875         up->efr = serial_in(up, UART_EFR);
 876         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 877
 878         serial_out(up, UART_LCR, 0);
 879         serial_out(up, UART_IER, 0);
 880         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 881
 882         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
 883         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
 884
 885         serial_out(up, UART_LCR, 0);
 886         serial_out(up, UART_IER, up->ier);
 887         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 888
 889         serial_out(up, UART_EFR, up->efr);
 890         serial_out(up, UART_LCR, cval);
 891
 892         if (baud > 230400 && baud != 3000000)
 893                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
 894         else
 895                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
 896
 897         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 898                 serial_omap_mdr1_errataset(up, up->mdr1);
 899         else
 900                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 901
 902         /* Hardware Flow Control Configuration */
 903
 904         if (termios->c_cflag & CRTSCTS) {
 905                 efr |= (UART_EFR_CTS | UART_EFR_RTS);
 906                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 907
 908                 up->mcr = serial_in(up, UART_MCR);
 909                 serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 910
 911                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 912                 up->efr = serial_in(up, UART_EFR);
 913                 serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 914
 915                 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 916                 serial_out(up, UART_EFR, efr); /* Enable AUTORTS and AUTOCTS */
 917                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 918                 serial_out(up, UART_MCR, up->mcr | UART_MCR_RTS);
 919                 serial_out(up, UART_LCR, cval);
 920         }
 921
 922         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 923         /* Software Flow Control Configuration */
 924         serial_omap_configure_xonxoff(up, termios);
 925
 926         spin_unlock_irqrestore(&up->port.lock, flags);
 927         pm_runtime_mark_last_busy(up->dev);
 928         pm_runtime_put_autosuspend(up->dev);
 929         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
 930 }
 931
 932 static int serial_omap_set_wake(struct uart_port *port, unsigned int state)
 933 {
 934         struct uart_omap_port *up = to_uart_omap_port(port);
 935
 936         serial_omap_enable_wakeup(up, state);
 937
 938         return 0;
 939 }
 940
 941 static void
 942 serial_omap_pm(struct uart_port *port, unsigned int state,
 943                unsigned int oldstate)
 944 {
 945         struct uart_omap_port *up = to_uart_omap_port(port);
 946         unsigned char efr;
 947
 948         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
 949
 950         pm_runtime_get_sync(up->dev);
 951         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 952         efr = serial_in(up, UART_EFR);
 953         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 954         serial_out(up, UART_LCR, 0);
 955
 956         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 957         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 958         serial_out(up, UART_EFR, efr);
 959         serial_out(up, UART_LCR, 0);
 960
 961         if (!device_may_wakeup(up->dev)) {
 962                 if (!state)
 963                         pm_runtime_forbid(up->dev);
 964                 else
 965                         pm_runtime_allow(up->dev);
 966         }
 967
 968         pm_runtime_mark_last_busy(up->dev);
 969         pm_runtime_put_autosuspend(up->dev);
 970 }
 971
 972 static void serial_omap_release_port(struct uart_port *port)
 973 {
 974         dev_dbg(port->dev, "serial_omap_release_port+\n");
 975 }
 976
 977 static int serial_omap_request_port(struct uart_port *port)
 978 {
 979         dev_dbg(port->dev, "serial_omap_request_port+\n");
 980         return 0;
 981 }
 982
 983 static void serial_omap_config_port(struct uart_port *port, int flags)
 984 {
 985         struct uart_omap_port *up = to_uart_omap_port(port);
 986
 987         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
 988                                                         up->port.line);
 989         up->port.type = PORT_OMAP;
 990 }
 991
 992 static int
 993 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
 994 {
 995         /* we don't want the core code to modify any port params */
 996         dev_dbg(port->dev, "serial_omap_verify_port+\n");
 997         return -EINVAL;
 998 }
 999
1000 static const char *
1001 serial_omap_type(struct uart_port *port)
1002 {
1003         struct uart_omap_port *up = to_uart_omap_port(port);
1004
1005         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1006         return up->name;
1007 }
1008
1009 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1010
1011 static inline void wait_for_xmitr(struct uart_omap_port *up)
1012 {
1013         unsigned int status, tmout = 10000;
1014
1015         /* Wait up to 10ms for the character(s) to be sent. */
1016         do {
1017                 status = serial_in(up, UART_LSR);
1018
1019                 if (status & UART_LSR_BI)
1020                         up->lsr_break_flag = UART_LSR_BI;
1021
1022                 if (--tmout == 0)
1023                         break;
1024                 udelay(1);
1025         } while ((status & BOTH_EMPTY) != BOTH_EMPTY);
1026
1027         /* Wait up to 1s for flow control if necessary */
1028         if (up->port.flags & UPF_CONS_FLOW) {
1029                 tmout = 1000000;
1030                 for (tmout = 1000000; tmout; tmout--) {
1031                         unsigned int msr = serial_in(up, UART_MSR);
1032
1033                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1034                         if (msr & UART_MSR_CTS)
1035                                 break;
1036
1037                         udelay(1);
1038                 }
1039         }
1040 }
1041
1042 #ifdef CONFIG_CONSOLE_POLL
1043
1044 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1045 {
1046         struct uart_omap_port *up = to_uart_omap_port(port);
1047
1048         pm_runtime_get_sync(up->dev);
1049         wait_for_xmitr(up);
1050         serial_out(up, UART_TX, ch);
1051         pm_runtime_mark_last_busy(up->dev);
1052         pm_runtime_put_autosuspend(up->dev);
1053 }
1054
1055 static int serial_omap_poll_get_char(struct uart_port *port)
1056 {
1057         struct uart_omap_port *up = to_uart_omap_port(port);
1058         unsigned int status;
1059
1060         pm_runtime_get_sync(up->dev);
1061         status = serial_in(up, UART_LSR);
1062         if (!(status & UART_LSR_DR)) {
1063                 status = NO_POLL_CHAR;
1064                 goto out;
1065         }
1066
1067         status = serial_in(up, UART_RX);
1068
1069 out:
1070         pm_runtime_mark_last_busy(up->dev);
1071         pm_runtime_put_autosuspend(up->dev);
1072
1073         return status;
1074 }
1075
1076 #endif /* CONFIG_CONSOLE_POLL */
1077
1078 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1079
1080 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1081
1082 static struct uart_driver serial_omap_reg;
1083
1084 static void serial_omap_console_putchar(struct uart_port *port, int ch)
1085 {
1086         struct uart_omap_port *up = to_uart_omap_port(port);
1087
1088         wait_for_xmitr(up);
1089         serial_out(up, UART_TX, ch);
1090 }
1091
1092 static void
1093 serial_omap_console_write(struct console *co, const char *s,
1094                 unsigned int count)
1095 {
1096         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1097         unsigned long flags;
1098         unsigned int ier;
1099         int locked = 1;
1100
1101         pm_runtime_get_sync(up->dev);
1102
1103         local_irq_save(flags);
1104         if (up->port.sysrq)
1105                 locked = 0;
1106         else if (oops_in_progress)
1107                 locked = spin_trylock(&up->port.lock);
1108         else
1109                 spin_lock(&up->port.lock);
1110
1111         /*
1112          * First save the IER then disable the interrupts
1113          */
1114         ier = serial_in(up, UART_IER);
1115         serial_out(up, UART_IER, 0);
1116
1117         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1118
1119         /*
1120          * Finally, wait for transmitter to become empty
1121          * and restore the IER
1122          */
1123         wait_for_xmitr(up);
1124         serial_out(up, UART_IER, ier);
1125         /*
1126          * The receive handling will happen properly because the
1127          * receive ready bit will still be set; it is not cleared
1128          * on read.  However, modem control will not, we must
1129          * call it if we have saved something in the saved flags
1130          * while processing with interrupts off.
1131          */
1132         if (up->msr_saved_flags)
1133                 check_modem_status(up);
1134
1135         pm_runtime_mark_last_busy(up->dev);
1136         pm_runtime_put_autosuspend(up->dev);
1137         if (locked)
1138                 spin_unlock(&up->port.lock);
1139         local_irq_restore(flags);
1140 }
1141
1142 static int __init
1143 serial_omap_console_setup(struct console *co, char *options)
1144 {
1145         struct uart_omap_port *up;
1146         int baud = 115200;
1147         int bits = 8;
1148         int parity = 'n';
1149         int flow = 'n';
1150
1151         if (serial_omap_console_ports[co->index] == NULL)
1152                 return -ENODEV;
1153         up = serial_omap_console_ports[co->index];
1154
1155         if (options)
1156                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1157
1158         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1159 }
1160
1161 static struct console serial_omap_console = {
1162         .name           = OMAP_SERIAL_NAME,
1163         .write          = serial_omap_console_write,
1164         .device         = uart_console_device,
1165         .setup          = serial_omap_console_setup,
1166         .flags          = CON_PRINTBUFFER,
1167         .index          = -1,
1168         .data           = &serial_omap_reg,
1169 };
1170
1171 static void serial_omap_add_console_port(struct uart_omap_port *up)
1172 {
1173         serial_omap_console_ports[up->port.line] = up;
1174 }
1175
1176 #define OMAP_CONSOLE    (&serial_omap_console)
1177
1178 #else
1179
1180 #define OMAP_CONSOLE    NULL
1181
1182 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1183 {}
1184
1185 #endif
1186
1187 static struct uart_ops serial_omap_pops = {
1188         .tx_empty       = serial_omap_tx_empty,
1189         .set_mctrl      = serial_omap_set_mctrl,
1190         .get_mctrl      = serial_omap_get_mctrl,
1191         .stop_tx        = serial_omap_stop_tx,
1192         .start_tx       = serial_omap_start_tx,
1193         .stop_rx        = serial_omap_stop_rx,
1194         .enable_ms      = serial_omap_enable_ms,
1195         .break_ctl      = serial_omap_break_ctl,
1196         .startup        = serial_omap_startup,
1197         .shutdown       = serial_omap_shutdown,
1198         .set_termios    = serial_omap_set_termios,
1199         .pm             = serial_omap_pm,
1200         .set_wake       = serial_omap_set_wake,
1201         .type           = serial_omap_type,
1202         .release_port   = serial_omap_release_port,
1203         .request_port   = serial_omap_request_port,
1204         .config_port    = serial_omap_config_port,
1205         .verify_port    = serial_omap_verify_port,
1206 #ifdef CONFIG_CONSOLE_POLL
1207         .poll_put_char  = serial_omap_poll_put_char,
1208         .poll_get_char  = serial_omap_poll_get_char,
1209 #endif
1210 };
1211
1212 static struct uart_driver serial_omap_reg = {
1213         .owner          = THIS_MODULE,
1214         .driver_name    = "OMAP-SERIAL",
1215         .dev_name       = OMAP_SERIAL_NAME,
1216         .nr             = OMAP_MAX_HSUART_PORTS,
1217         .cons           = OMAP_CONSOLE,
1218 };
1219
1220 #ifdef CONFIG_PM_SLEEP
1221 static int serial_omap_suspend(struct device *dev)
1222 {
1223         struct uart_omap_port *up = dev_get_drvdata(dev);
1224
1225         uart_suspend_port(&serial_omap_reg, &up->port);
1226         flush_work(&up->qos_work);
1227
1228         return 0;
1229 }
1230
1231 static int serial_omap_resume(struct device *dev)
1232 {
1233         struct uart_omap_port *up = dev_get_drvdata(dev);
1234
1235         uart_resume_port(&serial_omap_reg, &up->port);
1236
1237         return 0;
1238 }
1239 #endif
1240
1241 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1242 {
1243         u32 mvr, scheme;
1244         u16 revision, major, minor;
1245
1246         mvr = serial_in(up, UART_OMAP_MVER);
1247
1248         /* Check revision register scheme */
1249         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1250
1251         switch (scheme) {
1252         case 0: /* Legacy Scheme: OMAP2/3 */
1253                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1254                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1255                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1256                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1257                 break;
1258         case 1:
1259                 /* New Scheme: OMAP4+ */
1260                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1261                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1262                                         OMAP_UART_MVR_MAJ_SHIFT;
1263                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1264                 break;
1265         default:
1266                 dev_warn(up->dev,
1267                         "Unknown %s revision, defaulting to highest\n",
1268                         up->name);
1269                 /* highest possible revision */
1270                 major = 0xff;
1271                 minor = 0xff;
1272         }
1273
1274         /* normalize revision for the driver */
1275         revision = UART_BUILD_REVISION(major, minor);
1276
1277         switch (revision) {
1278         case OMAP_UART_REV_46:
1279                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1280                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1281                 break;
1282         case OMAP_UART_REV_52:
1283                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1284                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1285                 break;
1286         case OMAP_UART_REV_63:
1287                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1288                 break;
1289         default:
1290                 break;
1291         }
1292 }
1293
1294 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1295 {
1296         struct omap_uart_port_info *omap_up_info;
1297
1298         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1299         if (!omap_up_info)
1300                 return NULL; /* out of memory */
1301
1302         of_property_read_u32(dev->of_node, "clock-frequency",
1303                                          &omap_up_info->uartclk);
1304         return omap_up_info;
1305 }
1306
1307 static int serial_omap_probe(struct platform_device *pdev)
1308 {
1309         struct uart_omap_port   *up;
1310         struct resource         *mem, *irq;
1311         struct omap_uart_port_info *omap_up_info = pdev->dev.platform_data;
1312         int ret;
1313
1314         if (pdev->dev.of_node)
1315                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1316
1317         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1318         if (!mem) {
1319                 dev_err(&pdev->dev, "no mem resource?\n");
1320                 return -ENODEV;
1321         }
1322
1323         irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1324         if (!irq) {
1325                 dev_err(&pdev->dev, "no irq resource?\n");
1326                 return -ENODEV;
1327         }
1328
1329         if (!devm_request_mem_region(&pdev->dev, mem->start, resource_size(mem),
1330                                 pdev->dev.driver->name)) {
1331                 dev_err(&pdev->dev, "memory region already claimed\n");
1332                 return -EBUSY;
1333         }
1334
1335         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1336             omap_up_info->DTR_present) {
1337                 ret = gpio_request(omap_up_info->DTR_gpio, "omap-serial");
1338                 if (ret < 0)
1339                         return ret;
1340                 ret = gpio_direction_output(omap_up_info->DTR_gpio,
1341                                             omap_up_info->DTR_inverted);
1342                 if (ret < 0)
1343                         return ret;
1344         }
1345
1346         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1347         if (!up)
1348                 return -ENOMEM;
1349
1350         if (gpio_is_valid(omap_up_info->DTR_gpio) &&
1351             omap_up_info->DTR_present) {
1352                 up->DTR_gpio = omap_up_info->DTR_gpio;
1353                 up->DTR_inverted = omap_up_info->DTR_inverted;
1354         } else
1355                 up->DTR_gpio = -EINVAL;
1356         up->DTR_active = 0;
1357
1358         up->dev = &pdev->dev;
1359         up->port.dev = &pdev->dev;
1360         up->port.type = PORT_OMAP;
1361         up->port.iotype = UPIO_MEM;
1362         up->port.irq = irq->start;
1363
1364         up->port.regshift = 2;
1365         up->port.fifosize = 64;
1366         up->port.ops = &serial_omap_pops;
1367
1368         if (pdev->dev.of_node)
1369                 up->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
1370         else
1371                 up->port.line = pdev->id;
1372
1373         if (up->port.line < 0) {
1374                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1375                                                                 up->port.line);
1376                 ret = -ENODEV;
1377                 goto err_port_line;
1378         }
1379
1380         up->pins = devm_pinctrl_get_select_default(&pdev->dev);
1381         if (IS_ERR(up->pins)) {
1382                 dev_warn(&pdev->dev, "did not get pins for uart%i error: %li\n",
1383                          up->port.line, PTR_ERR(up->pins));
1384                 up->pins = NULL;
1385         }
1386
1387         sprintf(up->name, "OMAP UART%d", up->port.line);
1388         up->port.mapbase = mem->start;
1389         up->port.membase = devm_ioremap(&pdev->dev, mem->start,
1390                                                 resource_size(mem));
1391         if (!up->port.membase) {
1392                 dev_err(&pdev->dev, "can't ioremap UART\n");
1393                 ret = -ENOMEM;
1394                 goto err_ioremap;
1395         }
1396
1397         up->port.flags = omap_up_info->flags;
1398         up->port.uartclk = omap_up_info->uartclk;
1399         if (!up->port.uartclk) {
1400                 up->port.uartclk = DEFAULT_CLK_SPEED;
1401                 dev_warn(&pdev->dev, "No clock speed specified: using default:"
1402                                                 "%d\n", DEFAULT_CLK_SPEED);
1403         }
1404
1405         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1406         up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1407         pm_qos_add_request(&up->pm_qos_request,
1408                 PM_QOS_CPU_DMA_LATENCY, up->latency);
1409         serial_omap_uart_wq = create_singlethread_workqueue(up->name);
1410         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1411
1412         platform_set_drvdata(pdev, up);
1413         pm_runtime_enable(&pdev->dev);
1414         pm_runtime_use_autosuspend(&pdev->dev);
1415         pm_runtime_set_autosuspend_delay(&pdev->dev,
1416                         omap_up_info->autosuspend_timeout);
1417
1418         pm_runtime_irq_safe(&pdev->dev);
1419         pm_runtime_get_sync(&pdev->dev);
1420
1421         omap_serial_fill_features_erratas(up);
1422
1423         ui[up->port.line] = up;
1424         serial_omap_add_console_port(up);
1425
1426         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1427         if (ret != 0)
1428                 goto err_add_port;
1429
1430         pm_runtime_mark_last_busy(up->dev);
1431         pm_runtime_put_autosuspend(up->dev);
1432         return 0;
1433
1434 err_add_port:
1435         pm_runtime_put(&pdev->dev);
1436         pm_runtime_disable(&pdev->dev);
1437 err_ioremap:
1438 err_port_line:
1439         dev_err(&pdev->dev, "[UART%d]: failure [%s]: %d\n",
1440                                 pdev->id, __func__, ret);
1441         return ret;
1442 }
1443
1444 static int serial_omap_remove(struct platform_device *dev)
1445 {
1446         struct uart_omap_port *up = platform_get_drvdata(dev);
1447
1448         pm_runtime_put_sync(up->dev);
1449         pm_runtime_disable(up->dev);
1450         uart_remove_one_port(&serial_omap_reg, &up->port);
1451         pm_qos_remove_request(&up->pm_qos_request);
1452
1453         return 0;
1454 }
1455
1456 /*
1457  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1458  * The access to uart register after MDR1 Access
1459  * causes UART to corrupt data.
1460  *
1461  * Need a delay =
1462  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1463  * give 10 times as much
1464  */
1465 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1466 {
1467         u8 timeout = 255;
1468
1469         serial_out(up, UART_OMAP_MDR1, mdr1);
1470         udelay(2);
1471         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1472                         UART_FCR_CLEAR_RCVR);
1473         /*
1474          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1475          * TX_FIFO_E bit is 1.
1476          */
1477         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1478                                 (UART_LSR_THRE | UART_LSR_DR))) {
1479                 timeout--;
1480                 if (!timeout) {
1481                         /* Should *never* happen. we warn and carry on */
1482                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1483                                                 serial_in(up, UART_LSR));
1484                         break;
1485                 }
1486                 udelay(1);
1487         }
1488 }
1489
1490 #ifdef CONFIG_PM_RUNTIME
1491 static void serial_omap_restore_context(struct uart_omap_port *up)
1492 {
1493         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1494                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1495         else
1496                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1497
1498         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1499         serial_out(up, UART_EFR, UART_EFR_ECB);
1500         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1501         serial_out(up, UART_IER, 0x0);
1502         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1503         serial_out(up, UART_DLL, up->dll);
1504         serial_out(up, UART_DLM, up->dlh);
1505         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1506         serial_out(up, UART_IER, up->ier);
1507         serial_out(up, UART_FCR, up->fcr);
1508         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1509         serial_out(up, UART_MCR, up->mcr);
1510         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1511         serial_out(up, UART_OMAP_SCR, up->scr);
1512         serial_out(up, UART_EFR, up->efr);
1513         serial_out(up, UART_LCR, up->lcr);
1514         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1515                 serial_omap_mdr1_errataset(up, up->mdr1);
1516         else
1517                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1518 }
1519
1520 static int serial_omap_runtime_suspend(struct device *dev)
1521 {
1522         struct uart_omap_port *up = dev_get_drvdata(dev);
1523         struct omap_uart_port_info *pdata = dev->platform_data;
1524
1525         if (!up)
1526                 return -EINVAL;
1527
1528         if (!pdata)
1529                 return 0;
1530
1531         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1532
1533         if (device_may_wakeup(dev)) {
1534                 if (!up->wakeups_enabled) {
1535                         serial_omap_enable_wakeup(up, true);
1536                         up->wakeups_enabled = true;
1537                 }
1538         } else {
1539                 if (up->wakeups_enabled) {
1540                         serial_omap_enable_wakeup(up, false);
1541                         up->wakeups_enabled = false;
1542                 }
1543         }
1544
1545         up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1546         schedule_work(&up->qos_work);
1547
1548         return 0;
1549 }
1550
1551 static int serial_omap_runtime_resume(struct device *dev)
1552 {
1553         struct uart_omap_port *up = dev_get_drvdata(dev);
1554
1555         int loss_cnt = serial_omap_get_context_loss_count(up);
1556
1557         if (loss_cnt < 0) {
1558                 dev_err(dev, "serial_omap_get_context_loss_count failed : %d\n",
1559                         loss_cnt);
1560                 serial_omap_restore_context(up);
1561         } else if (up->context_loss_cnt != loss_cnt) {
1562                 serial_omap_restore_context(up);
1563         }
1564         up->latency = up->calc_latency;
1565         schedule_work(&up->qos_work);
1566
1567         return 0;
1568 }
1569 #endif
1570
1571 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1572         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1573         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1574                                 serial_omap_runtime_resume, NULL)
1575 };
1576
1577 #if defined(CONFIG_OF)
1578 static const struct of_device_id omap_serial_of_match[] = {
1579         { .compatible = "ti,omap2-uart" },
1580         { .compatible = "ti,omap3-uart" },
1581         { .compatible = "ti,omap4-uart" },
1582         {},
1583 };
1584 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1585 #endif
1586
1587 static struct platform_driver serial_omap_driver = {
1588         .probe          = serial_omap_probe,
1589         .remove         = serial_omap_remove,
1590         .driver         = {
1591                 .name   = DRIVER_NAME,
1592                 .pm     = &serial_omap_dev_pm_ops,
1593                 .of_match_table = of_match_ptr(omap_serial_of_match),
1594         },
1595 };
1596
1597 static int __init serial_omap_init(void)
1598 {
1599         int ret;
1600
1601         ret = uart_register_driver(&serial_omap_reg);
1602         if (ret != 0)
1603                 return ret;
1604         ret = platform_driver_register(&serial_omap_driver);
1605         if (ret != 0)
1606                 uart_unregister_driver(&serial_omap_reg);
1607         return ret;
1608 }
1609
1610 static void __exit serial_omap_exit(void)
1611 {
1612         platform_driver_unregister(&serial_omap_driver);
1613         uart_unregister_driver(&serial_omap_reg);
1614 }
1615
1616 module_init(serial_omap_init);
1617 module_exit(serial_omap_exit);
1618
1619 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1620 MODULE_LICENSE("GPL");
1621 MODULE_AUTHOR("Texas Instruments Inc");