drivers/tty/serial/fsl_lpuart.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Freescale lpuart serial port driver
   4  *
   5  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/bits.h>
  10 #include <linux/clk.h>
  11 #include <linux/console.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/dmapool.h>
  16 #include <linux/io.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/irq.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_dma.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/slab.h>
  27 #include <linux/tty_flip.h>
  28
  29 /* All registers are 8-bit width */
  30 #define UARTBDH                 0x00
  31 #define UARTBDL                 0x01
  32 #define UARTCR1                 0x02
  33 #define UARTCR2                 0x03
  34 #define UARTSR1                 0x04
  35 #define UARTCR3                 0x06
  36 #define UARTDR                  0x07
  37 #define UARTCR4                 0x0a
  38 #define UARTCR5                 0x0b
  39 #define UARTMODEM               0x0d
  40 #define UARTPFIFO               0x10
  41 #define UARTCFIFO               0x11
  42 #define UARTSFIFO               0x12
  43 #define UARTTWFIFO              0x13
  44 #define UARTTCFIFO              0x14
  45 #define UARTRWFIFO              0x15
  46
  47 #define UARTBDH_LBKDIE          0x80
  48 #define UARTBDH_RXEDGIE         0x40
  49 #define UARTBDH_SBR_MASK        0x1f
  50
  51 #define UARTCR1_LOOPS           0x80
  52 #define UARTCR1_RSRC            0x20
  53 #define UARTCR1_M               0x10
  54 #define UARTCR1_WAKE            0x08
  55 #define UARTCR1_ILT             0x04
  56 #define UARTCR1_PE              0x02
  57 #define UARTCR1_PT              0x01
  58
  59 #define UARTCR2_TIE             0x80
  60 #define UARTCR2_TCIE            0x40
  61 #define UARTCR2_RIE             0x20
  62 #define UARTCR2_ILIE            0x10
  63 #define UARTCR2_TE              0x08
  64 #define UARTCR2_RE              0x04
  65 #define UARTCR2_RWU             0x02
  66 #define UARTCR2_SBK             0x01
  67
  68 #define UARTSR1_TDRE            0x80
  69 #define UARTSR1_TC              0x40
  70 #define UARTSR1_RDRF            0x20
  71 #define UARTSR1_IDLE            0x10
  72 #define UARTSR1_OR              0x08
  73 #define UARTSR1_NF              0x04
  74 #define UARTSR1_FE              0x02
  75 #define UARTSR1_PE              0x01
  76
  77 #define UARTCR3_R8              0x80
  78 #define UARTCR3_T8              0x40
  79 #define UARTCR3_TXDIR           0x20
  80 #define UARTCR3_TXINV           0x10
  81 #define UARTCR3_ORIE            0x08
  82 #define UARTCR3_NEIE            0x04
  83 #define UARTCR3_FEIE            0x02
  84 #define UARTCR3_PEIE            0x01
  85
  86 #define UARTCR4_MAEN1           0x80
  87 #define UARTCR4_MAEN2           0x40
  88 #define UARTCR4_M10             0x20
  89 #define UARTCR4_BRFA_MASK       0x1f
  90 #define UARTCR4_BRFA_OFF        0
  91
  92 #define UARTCR5_TDMAS           0x80
  93 #define UARTCR5_RDMAS           0x20
  94
  95 #define UARTMODEM_RXRTSE        0x08
  96 #define UARTMODEM_TXRTSPOL      0x04
  97 #define UARTMODEM_TXRTSE        0x02
  98 #define UARTMODEM_TXCTSE        0x01
  99
 100 #define UARTPFIFO_TXFE          0x80
 101 #define UARTPFIFO_FIFOSIZE_MASK 0x7
 102 #define UARTPFIFO_TXSIZE_OFF    4
 103 #define UARTPFIFO_RXFE          0x08
 104 #define UARTPFIFO_RXSIZE_OFF    0
 105
 106 #define UARTCFIFO_TXFLUSH       0x80
 107 #define UARTCFIFO_RXFLUSH       0x40
 108 #define UARTCFIFO_RXOFE         0x04
 109 #define UARTCFIFO_TXOFE         0x02
 110 #define UARTCFIFO_RXUFE         0x01
 111
 112 #define UARTSFIFO_TXEMPT        0x80
 113 #define UARTSFIFO_RXEMPT        0x40
 114 #define UARTSFIFO_RXOF          0x04
 115 #define UARTSFIFO_TXOF          0x02
 116 #define UARTSFIFO_RXUF          0x01
 117
 118 /* 32-bit global registers only for i.MX7ULP/i.MX8x
 119  * Used to reset all internal logic and registers, except the Global Register.
 120  */
 121 #define UART_GLOBAL             0x8
 122
 123 /* 32-bit register definition */
 124 #define UARTBAUD                0x00
 125 #define UARTSTAT                0x04
 126 #define UARTCTRL                0x08
 127 #define UARTDATA                0x0C
 128 #define UARTMATCH               0x10
 129 #define UARTMODIR               0x14
 130 #define UARTFIFO                0x18
 131 #define UARTWATER               0x1c
 132
 133 #define UARTBAUD_MAEN1          0x80000000
 134 #define UARTBAUD_MAEN2          0x40000000
 135 #define UARTBAUD_M10            0x20000000
 136 #define UARTBAUD_TDMAE          0x00800000
 137 #define UARTBAUD_RDMAE          0x00200000
 138 #define UARTBAUD_MATCFG         0x00400000
 139 #define UARTBAUD_BOTHEDGE       0x00020000
 140 #define UARTBAUD_RESYNCDIS      0x00010000
 141 #define UARTBAUD_LBKDIE         0x00008000
 142 #define UARTBAUD_RXEDGIE        0x00004000
 143 #define UARTBAUD_SBNS           0x00002000
 144 #define UARTBAUD_SBR            0x00000000
 145 #define UARTBAUD_SBR_MASK       0x1fff
 146 #define UARTBAUD_OSR_MASK       0x1f
 147 #define UARTBAUD_OSR_SHIFT      24
 148
 149 #define UARTSTAT_LBKDIF         0x80000000
 150 #define UARTSTAT_RXEDGIF        0x40000000
 151 #define UARTSTAT_MSBF           0x20000000
 152 #define UARTSTAT_RXINV          0x10000000
 153 #define UARTSTAT_RWUID          0x08000000
 154 #define UARTSTAT_BRK13          0x04000000
 155 #define UARTSTAT_LBKDE          0x02000000
 156 #define UARTSTAT_RAF            0x01000000
 157 #define UARTSTAT_TDRE           0x00800000
 158 #define UARTSTAT_TC             0x00400000
 159 #define UARTSTAT_RDRF           0x00200000
 160 #define UARTSTAT_IDLE           0x00100000
 161 #define UARTSTAT_OR             0x00080000
 162 #define UARTSTAT_NF             0x00040000
 163 #define UARTSTAT_FE             0x00020000
 164 #define UARTSTAT_PE             0x00010000
 165 #define UARTSTAT_MA1F           0x00008000
 166 #define UARTSTAT_M21F           0x00004000
 167
 168 #define UARTCTRL_R8T9           0x80000000
 169 #define UARTCTRL_R9T8           0x40000000
 170 #define UARTCTRL_TXDIR          0x20000000
 171 #define UARTCTRL_TXINV          0x10000000
 172 #define UARTCTRL_ORIE           0x08000000
 173 #define UARTCTRL_NEIE           0x04000000
 174 #define UARTCTRL_FEIE           0x02000000
 175 #define UARTCTRL_PEIE           0x01000000
 176 #define UARTCTRL_TIE            0x00800000
 177 #define UARTCTRL_TCIE           0x00400000
 178 #define UARTCTRL_RIE            0x00200000
 179 #define UARTCTRL_ILIE           0x00100000
 180 #define UARTCTRL_TE             0x00080000
 181 #define UARTCTRL_RE             0x00040000
 182 #define UARTCTRL_RWU            0x00020000
 183 #define UARTCTRL_SBK            0x00010000
 184 #define UARTCTRL_MA1IE          0x00008000
 185 #define UARTCTRL_MA2IE          0x00004000
 186 #define UARTCTRL_IDLECFG        GENMASK(10, 8)
 187 #define UARTCTRL_LOOPS          0x00000080
 188 #define UARTCTRL_DOZEEN         0x00000040
 189 #define UARTCTRL_RSRC           0x00000020
 190 #define UARTCTRL_M              0x00000010
 191 #define UARTCTRL_WAKE           0x00000008
 192 #define UARTCTRL_ILT            0x00000004
 193 #define UARTCTRL_PE             0x00000002
 194 #define UARTCTRL_PT             0x00000001
 195
 196 #define UARTDATA_NOISY          0x00008000
 197 #define UARTDATA_PARITYE        0x00004000
 198 #define UARTDATA_FRETSC         0x00002000
 199 #define UARTDATA_RXEMPT         0x00001000
 200 #define UARTDATA_IDLINE         0x00000800
 201 #define UARTDATA_MASK           0x3ff
 202
 203 #define UARTMODIR_IREN          0x00020000
 204 #define UARTMODIR_RTSWATER      GENMASK(10, 8)
 205 #define UARTMODIR_TXCTSSRC      0x00000020
 206 #define UARTMODIR_TXCTSC        0x00000010
 207 #define UARTMODIR_RXRTSE        0x00000008
 208 #define UARTMODIR_TXRTSPOL      0x00000004
 209 #define UARTMODIR_TXRTSE        0x00000002
 210 #define UARTMODIR_TXCTSE        0x00000001
 211
 212 #define UARTFIFO_TXEMPT         0x00800000
 213 #define UARTFIFO_RXEMPT         0x00400000
 214 #define UARTFIFO_TXOF           0x00020000
 215 #define UARTFIFO_RXUF           0x00010000
 216 #define UARTFIFO_TXFLUSH        0x00008000
 217 #define UARTFIFO_RXFLUSH        0x00004000
 218 #define UARTFIFO_RXIDEN GENMASK(12, 10)
 219 #define UARTFIFO_TXOFE          0x00000200
 220 #define UARTFIFO_RXUFE          0x00000100
 221 #define UARTFIFO_TXFE           0x00000080
 222 #define UARTFIFO_FIFOSIZE_MASK  0x7
 223 #define UARTFIFO_TXSIZE_OFF     4
 224 #define UARTFIFO_RXFE           0x00000008
 225 #define UARTFIFO_RXSIZE_OFF     0
 226 #define UARTFIFO_DEPTH(x)       (0x1 << ((x) ? ((x) + 1) : 0))
 227
 228 #define UARTWATER_COUNT_MASK    0xff
 229 #define UARTWATER_TXCNT_OFF     8
 230 #define UARTWATER_RXCNT_OFF     24
 231 #define UARTWATER_WATER_MASK    0xff
 232 #define UARTWATER_TXWATER_OFF   0
 233 #define UARTWATER_RXWATER_OFF   16
 234
 235 #define UART_GLOBAL_RST 0x2
 236 #define GLOBAL_RST_MIN_US       20
 237 #define GLOBAL_RST_MAX_US       40
 238
 239 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
 240 #define DMA_RX_TIMEOUT          (10)
 241 #define UART_AUTOSUSPEND_TIMEOUT        3000
 242
 243 #define DRIVER_NAME     "fsl-lpuart"
 244 #define DEV_NAME        "ttyLP"
 245 #define UART_NR         8
 246
 247 /* IMX lpuart has four extra unused regs located at the beginning */
 248 #define IMX_REG_OFF     0x10
 249
 250 enum lpuart_type {
 251         VF610_LPUART,
 252         LS1021A_LPUART,
 253         LS1028A_LPUART,
 254         IMX7ULP_LPUART,
 255         IMX8ULP_LPUART,
 256         IMX8QXP_LPUART,
 257         IMXRT1050_LPUART,
 258 };
 259
 260 struct lpuart_port {
 261         struct uart_port        port;
 262         enum lpuart_type        devtype;
 263         struct clk              *ipg_clk;
 264         struct clk              *baud_clk;
 265         unsigned int            txfifo_size;
 266         unsigned int            rxfifo_size;
 267
 268         u8                      rx_watermark;
 269         bool                    lpuart_dma_tx_use;
 270         bool                    lpuart_dma_rx_use;
 271         struct dma_chan         *dma_tx_chan;
 272         struct dma_chan         *dma_rx_chan;
 273         struct dma_async_tx_descriptor  *dma_tx_desc;
 274         struct dma_async_tx_descriptor  *dma_rx_desc;
 275         dma_cookie_t            dma_tx_cookie;
 276         dma_cookie_t            dma_rx_cookie;
 277         unsigned int            dma_tx_bytes;
 278         unsigned int            dma_rx_bytes;
 279         bool                    dma_tx_in_progress;
 280         unsigned int            dma_rx_timeout;
 281         struct timer_list       lpuart_timer;
 282         struct scatterlist      rx_sgl, tx_sgl[2];
 283         struct circ_buf         rx_ring;
 284         int                     rx_dma_rng_buf_len;
 285         unsigned int            dma_tx_nents;
 286         wait_queue_head_t       dma_wait;
 287         bool                    is_cs7; /* Set to true when character size is 7 */
 288                                         /* and the parity is enabled            */
 289 };
 290
 291 struct lpuart_soc_data {
 292         enum lpuart_type devtype;
 293         char iotype;
 294         u8 reg_off;
 295         u8 rx_watermark;
 296 };
 297
 298 static const struct lpuart_soc_data vf_data = {
 299         .devtype = VF610_LPUART,
 300         .iotype = UPIO_MEM,
 301         .rx_watermark = 1,
 302 };
 303
 304 static const struct lpuart_soc_data ls1021a_data = {
 305         .devtype = LS1021A_LPUART,
 306         .iotype = UPIO_MEM32BE,
 307         .rx_watermark = 1,
 308 };
 309
 310 static const struct lpuart_soc_data ls1028a_data = {
 311         .devtype = LS1028A_LPUART,
 312         .iotype = UPIO_MEM32,
 313         .rx_watermark = 0,
 314 };
 315
 316 static struct lpuart_soc_data imx7ulp_data = {
 317         .devtype = IMX7ULP_LPUART,
 318         .iotype = UPIO_MEM32,
 319         .reg_off = IMX_REG_OFF,
 320         .rx_watermark = 1,
 321 };
 322
 323 static struct lpuart_soc_data imx8ulp_data = {
 324         .devtype = IMX8ULP_LPUART,
 325         .iotype = UPIO_MEM32,
 326         .reg_off = IMX_REG_OFF,
 327         .rx_watermark = 3,
 328 };
 329
 330 static struct lpuart_soc_data imx8qxp_data = {
 331         .devtype = IMX8QXP_LPUART,
 332         .iotype = UPIO_MEM32,
 333         .reg_off = IMX_REG_OFF,
 334         .rx_watermark = 31,
 335 };
 336 static struct lpuart_soc_data imxrt1050_data = {
 337         .devtype = IMXRT1050_LPUART,
 338         .iotype = UPIO_MEM32,
 339         .reg_off = IMX_REG_OFF,
 340         .rx_watermark = 1,
 341 };
 342
 343 static const struct of_device_id lpuart_dt_ids[] = {
 344         { .compatible = "fsl,vf610-lpuart",     .data = &vf_data, },
 345         { .compatible = "fsl,ls1021a-lpuart",   .data = &ls1021a_data, },
 346         { .compatible = "fsl,ls1028a-lpuart",   .data = &ls1028a_data, },
 347         { .compatible = "fsl,imx7ulp-lpuart",   .data = &imx7ulp_data, },
 348         { .compatible = "fsl,imx8ulp-lpuart",   .data = &imx8ulp_data, },
 349         { .compatible = "fsl,imx8qxp-lpuart",   .data = &imx8qxp_data, },
 350         { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data},
 351         { /* sentinel */ }
 352 };
 353 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 354
 355 /* Forward declare this for the dma callbacks*/
 356 static void lpuart_dma_tx_complete(void *arg);
 357
 358 static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
 359 {
 360         return (sport->devtype == LS1021A_LPUART ||
 361                 sport->devtype == LS1028A_LPUART);
 362 }
 363
 364 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport)
 365 {
 366         return sport->devtype == IMX7ULP_LPUART;
 367 }
 368
 369 static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport)
 370 {
 371         return sport->devtype == IMX8ULP_LPUART;
 372 }
 373
 374 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
 375 {
 376         return sport->devtype == IMX8QXP_LPUART;
 377 }
 378
 379 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
 380 {
 381         switch (port->iotype) {
 382         case UPIO_MEM32:
 383                 return readl(port->membase + off);
 384         case UPIO_MEM32BE:
 385                 return ioread32be(port->membase + off);
 386         default:
 387                 return 0;
 388         }
 389 }
 390
 391 static inline void lpuart32_write(struct uart_port *port, u32 val,
 392                                   u32 off)
 393 {
 394         switch (port->iotype) {
 395         case UPIO_MEM32:
 396                 writel(val, port->membase + off);
 397                 break;
 398         case UPIO_MEM32BE:
 399                 iowrite32be(val, port->membase + off);
 400                 break;
 401         }
 402 }
 403
 404 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
 405 {
 406         int ret = 0;
 407
 408         if (is_en) {
 409                 ret = clk_prepare_enable(sport->ipg_clk);
 410                 if (ret)
 411                         return ret;
 412
 413                 ret = clk_prepare_enable(sport->baud_clk);
 414                 if (ret) {
 415                         clk_disable_unprepare(sport->ipg_clk);
 416                         return ret;
 417                 }
 418         } else {
 419                 clk_disable_unprepare(sport->baud_clk);
 420                 clk_disable_unprepare(sport->ipg_clk);
 421         }
 422
 423         return 0;
 424 }
 425
 426 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
 427 {
 428         if (is_imx8qxp_lpuart(sport))
 429                 return clk_get_rate(sport->baud_clk);
 430
 431         return clk_get_rate(sport->ipg_clk);
 432 }
 433
 434 #define lpuart_enable_clks(x)   __lpuart_enable_clks(x, true)
 435 #define lpuart_disable_clks(x)  __lpuart_enable_clks(x, false)
 436
 437 static void lpuart_stop_tx(struct uart_port *port)
 438 {
 439         unsigned char temp;
 440
 441         temp = readb(port->membase + UARTCR2);
 442         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 443         writeb(temp, port->membase + UARTCR2);
 444 }
 445
 446 static void lpuart32_stop_tx(struct uart_port *port)
 447 {
 448         unsigned long temp;
 449
 450         temp = lpuart32_read(port, UARTCTRL);
 451         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 452         lpuart32_write(port, temp, UARTCTRL);
 453 }
 454
 455 static void lpuart_stop_rx(struct uart_port *port)
 456 {
 457         unsigned char temp;
 458
 459         temp = readb(port->membase + UARTCR2);
 460         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 461 }
 462
 463 static void lpuart32_stop_rx(struct uart_port *port)
 464 {
 465         unsigned long temp;
 466
 467         temp = lpuart32_read(port, UARTCTRL);
 468         lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
 469 }
 470
 471 static void lpuart_dma_tx(struct lpuart_port *sport)
 472 {
 473         struct circ_buf *xmit = &sport->port.state->xmit;
 474         struct scatterlist *sgl = sport->tx_sgl;
 475         struct device *dev = sport->port.dev;
 476         struct dma_chan *chan = sport->dma_tx_chan;
 477         int ret;
 478
 479         if (sport->dma_tx_in_progress)
 480                 return;
 481
 482         sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
 483
 484         if (xmit->tail < xmit->head || xmit->head == 0) {
 485                 sport->dma_tx_nents = 1;
 486                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
 487         } else {
 488                 sport->dma_tx_nents = 2;
 489                 sg_init_table(sgl, 2);
 490                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 491                                 UART_XMIT_SIZE - xmit->tail);
 492                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 493         }
 494
 495         ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 496                          DMA_TO_DEVICE);
 497         if (!ret) {
 498                 dev_err(dev, "DMA mapping error for TX.\n");
 499                 return;
 500         }
 501
 502         sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
 503                                         ret, DMA_MEM_TO_DEV,
 504                                         DMA_PREP_INTERRUPT);
 505         if (!sport->dma_tx_desc) {
 506                 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 507                               DMA_TO_DEVICE);
 508                 dev_err(dev, "Cannot prepare TX slave DMA!\n");
 509                 return;
 510         }
 511
 512         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 513         sport->dma_tx_desc->callback_param = sport;
 514         sport->dma_tx_in_progress = true;
 515         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 516         dma_async_issue_pending(chan);
 517 }
 518
 519 static bool lpuart_stopped_or_empty(struct uart_port *port)
 520 {
 521         return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
 522 }
 523
 524 static void lpuart_dma_tx_complete(void *arg)
 525 {
 526         struct lpuart_port *sport = arg;
 527         struct scatterlist *sgl = &sport->tx_sgl[0];
 528         struct circ_buf *xmit = &sport->port.state->xmit;
 529         struct dma_chan *chan = sport->dma_tx_chan;
 530         unsigned long flags;
 531
 532         spin_lock_irqsave(&sport->port.lock, flags);
 533         if (!sport->dma_tx_in_progress) {
 534                 spin_unlock_irqrestore(&sport->port.lock, flags);
 535                 return;
 536         }
 537
 538         dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 539                      DMA_TO_DEVICE);
 540
 541         uart_xmit_advance(&sport->port, sport->dma_tx_bytes);
 542         sport->dma_tx_in_progress = false;
 543         spin_unlock_irqrestore(&sport->port.lock, flags);
 544
 545         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 546                 uart_write_wakeup(&sport->port);
 547
 548         if (waitqueue_active(&sport->dma_wait)) {
 549                 wake_up(&sport->dma_wait);
 550                 return;
 551         }
 552
 553         spin_lock_irqsave(&sport->port.lock, flags);
 554
 555         if (!lpuart_stopped_or_empty(&sport->port))
 556                 lpuart_dma_tx(sport);
 557
 558         spin_unlock_irqrestore(&sport->port.lock, flags);
 559 }
 560
 561 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
 562 {
 563         switch (sport->port.iotype) {
 564         case UPIO_MEM32:
 565                 return sport->port.mapbase + UARTDATA;
 566         case UPIO_MEM32BE:
 567                 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
 568         }
 569         return sport->port.mapbase + UARTDR;
 570 }
 571
 572 static int lpuart_dma_tx_request(struct uart_port *port)
 573 {
 574         struct lpuart_port *sport = container_of(port,
 575                                         struct lpuart_port, port);
 576         struct dma_slave_config dma_tx_sconfig = {};
 577         int ret;
 578
 579         dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
 580         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 581         dma_tx_sconfig.dst_maxburst = 1;
 582         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 583         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 584
 585         if (ret) {
 586                 dev_err(sport->port.dev,
 587                                 "DMA slave config failed, err = %d\n", ret);
 588                 return ret;
 589         }
 590
 591         return 0;
 592 }
 593
 594 static bool lpuart_is_32(struct lpuart_port *sport)
 595 {
 596         return sport->port.iotype == UPIO_MEM32 ||
 597                sport->port.iotype ==  UPIO_MEM32BE;
 598 }
 599
 600 static void lpuart_flush_buffer(struct uart_port *port)
 601 {
 602         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 603         struct dma_chan *chan = sport->dma_tx_chan;
 604         u32 val;
 605
 606         if (sport->lpuart_dma_tx_use) {
 607                 if (sport->dma_tx_in_progress) {
 608                         dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
 609                                 sport->dma_tx_nents, DMA_TO_DEVICE);
 610                         sport->dma_tx_in_progress = false;
 611                 }
 612                 dmaengine_terminate_async(chan);
 613         }
 614
 615         if (lpuart_is_32(sport)) {
 616                 val = lpuart32_read(&sport->port, UARTFIFO);
 617                 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
 618                 lpuart32_write(&sport->port, val, UARTFIFO);
 619         } else {
 620                 val = readb(sport->port.membase + UARTCFIFO);
 621                 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
 622                 writeb(val, sport->port.membase + UARTCFIFO);
 623         }
 624 }
 625
 626 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
 627                                 u8 bit)
 628 {
 629         while (!(readb(port->membase + offset) & bit))
 630                 cpu_relax();
 631 }
 632
 633 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
 634                                   u32 bit)
 635 {
 636         while (!(lpuart32_read(port, offset) & bit))
 637                 cpu_relax();
 638 }
 639
 640 #if defined(CONFIG_CONSOLE_POLL)
 641
 642 static int lpuart_poll_init(struct uart_port *port)
 643 {
 644         struct lpuart_port *sport = container_of(port,
 645                                         struct lpuart_port, port);
 646         unsigned long flags;
 647         unsigned char temp;
 648
 649         sport->port.fifosize = 0;
 650
 651         spin_lock_irqsave(&sport->port.lock, flags);
 652         /* Disable Rx & Tx */
 653         writeb(0, sport->port.membase + UARTCR2);
 654
 655         temp = readb(sport->port.membase + UARTPFIFO);
 656         /* Enable Rx and Tx FIFO */
 657         writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
 658                         sport->port.membase + UARTPFIFO);
 659
 660         /* flush Tx and Rx FIFO */
 661         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 662                         sport->port.membase + UARTCFIFO);
 663
 664         /* explicitly clear RDRF */
 665         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
 666                 readb(sport->port.membase + UARTDR);
 667                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
 668         }
 669
 670         writeb(0, sport->port.membase + UARTTWFIFO);
 671         writeb(1, sport->port.membase + UARTRWFIFO);
 672
 673         /* Enable Rx and Tx */
 674         writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
 675         spin_unlock_irqrestore(&sport->port.lock, flags);
 676
 677         return 0;
 678 }
 679
 680 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
 681 {
 682         /* drain */
 683         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
 684         writeb(c, port->membase + UARTDR);
 685 }
 686
 687 static int lpuart_poll_get_char(struct uart_port *port)
 688 {
 689         if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
 690                 return NO_POLL_CHAR;
 691
 692         return readb(port->membase + UARTDR);
 693 }
 694
 695 static int lpuart32_poll_init(struct uart_port *port)
 696 {
 697         unsigned long flags;
 698         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 699         u32 temp;
 700
 701         sport->port.fifosize = 0;
 702
 703         spin_lock_irqsave(&sport->port.lock, flags);
 704
 705         /* Disable Rx & Tx */
 706         lpuart32_write(&sport->port, 0, UARTCTRL);
 707
 708         temp = lpuart32_read(&sport->port, UARTFIFO);
 709
 710         /* Enable Rx and Tx FIFO */
 711         lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
 712
 713         /* flush Tx and Rx FIFO */
 714         lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
 715
 716         /* explicitly clear RDRF */
 717         if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
 718                 lpuart32_read(&sport->port, UARTDATA);
 719                 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
 720         }
 721
 722         /* Enable Rx and Tx */
 723         lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
 724         spin_unlock_irqrestore(&sport->port.lock, flags);
 725
 726         return 0;
 727 }
 728
 729 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
 730 {
 731         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
 732         lpuart32_write(port, c, UARTDATA);
 733 }
 734
 735 static int lpuart32_poll_get_char(struct uart_port *port)
 736 {
 737         if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
 738                 return NO_POLL_CHAR;
 739
 740         return lpuart32_read(port, UARTDATA);
 741 }
 742 #endif
 743
 744 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 745 {
 746         struct uart_port *port = &sport->port;
 747         u8 ch;
 748
 749         uart_port_tx(port, ch,
 750                 readb(port->membase + UARTTCFIFO) < sport->txfifo_size,
 751                 writeb(ch, port->membase + UARTDR));
 752 }
 753
 754 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 755 {
 756         struct circ_buf *xmit = &sport->port.state->xmit;
 757         unsigned long txcnt;
 758
 759         if (sport->port.x_char) {
 760                 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
 761                 sport->port.icount.tx++;
 762                 sport->port.x_char = 0;
 763                 return;
 764         }
 765
 766         if (lpuart_stopped_or_empty(&sport->port)) {
 767                 lpuart32_stop_tx(&sport->port);
 768                 return;
 769         }
 770
 771         txcnt = lpuart32_read(&sport->port, UARTWATER);
 772         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 773         txcnt &= UARTWATER_COUNT_MASK;
 774         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 775                 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
 776                 uart_xmit_advance(&sport->port, 1);
 777                 txcnt = lpuart32_read(&sport->port, UARTWATER);
 778                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 779                 txcnt &= UARTWATER_COUNT_MASK;
 780         }
 781
 782         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 783                 uart_write_wakeup(&sport->port);
 784
 785         if (uart_circ_empty(xmit))
 786                 lpuart32_stop_tx(&sport->port);
 787 }
 788
 789 static void lpuart_start_tx(struct uart_port *port)
 790 {
 791         struct lpuart_port *sport = container_of(port,
 792                         struct lpuart_port, port);
 793         unsigned char temp;
 794
 795         temp = readb(port->membase + UARTCR2);
 796         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 797
 798         if (sport->lpuart_dma_tx_use) {
 799                 if (!lpuart_stopped_or_empty(port))
 800                         lpuart_dma_tx(sport);
 801         } else {
 802                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 803                         lpuart_transmit_buffer(sport);
 804         }
 805 }
 806
 807 static void lpuart32_start_tx(struct uart_port *port)
 808 {
 809         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 810         unsigned long temp;
 811
 812         if (sport->lpuart_dma_tx_use) {
 813                 if (!lpuart_stopped_or_empty(port))
 814                         lpuart_dma_tx(sport);
 815         } else {
 816                 temp = lpuart32_read(port, UARTCTRL);
 817                 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
 818
 819                 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
 820                         lpuart32_transmit_buffer(sport);
 821         }
 822 }
 823
 824 static void
 825 lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
 826 {
 827         switch (state) {
 828         case UART_PM_STATE_OFF:
 829                 pm_runtime_mark_last_busy(port->dev);
 830                 pm_runtime_put_autosuspend(port->dev);
 831                 break;
 832         default:
 833                 pm_runtime_get_sync(port->dev);
 834                 break;
 835         }
 836 }
 837
 838 /* return TIOCSER_TEMT when transmitter is not busy */
 839 static unsigned int lpuart_tx_empty(struct uart_port *port)
 840 {
 841         struct lpuart_port *sport = container_of(port,
 842                         struct lpuart_port, port);
 843         unsigned char sr1 = readb(port->membase + UARTSR1);
 844         unsigned char sfifo = readb(port->membase + UARTSFIFO);
 845
 846         if (sport->dma_tx_in_progress)
 847                 return 0;
 848
 849         if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
 850                 return TIOCSER_TEMT;
 851
 852         return 0;
 853 }
 854
 855 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 856 {
 857         struct lpuart_port *sport = container_of(port,
 858                         struct lpuart_port, port);
 859         unsigned long stat = lpuart32_read(port, UARTSTAT);
 860         unsigned long sfifo = lpuart32_read(port, UARTFIFO);
 861         unsigned long ctrl = lpuart32_read(port, UARTCTRL);
 862
 863         if (sport->dma_tx_in_progress)
 864                 return 0;
 865
 866         /*
 867          * LPUART Transmission Complete Flag may never be set while queuing a break
 868          * character, so avoid checking for transmission complete when UARTCTRL_SBK
 869          * is asserted.
 870          */
 871         if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) || ctrl & UARTCTRL_SBK)
 872                 return TIOCSER_TEMT;
 873
 874         return 0;
 875 }
 876
 877 static void lpuart_txint(struct lpuart_port *sport)
 878 {
 879         spin_lock(&sport->port.lock);
 880         lpuart_transmit_buffer(sport);
 881         spin_unlock(&sport->port.lock);
 882 }
 883
 884 static void lpuart_rxint(struct lpuart_port *sport)
 885 {
 886         unsigned int flg, ignored = 0, overrun = 0;
 887         struct tty_port *port = &sport->port.state->port;
 888         unsigned char rx, sr;
 889
 890         spin_lock(&sport->port.lock);
 891
 892         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 893                 flg = TTY_NORMAL;
 894                 sport->port.icount.rx++;
 895                 /*
 896                  * to clear the FE, OR, NF, FE, PE flags,
 897                  * read SR1 then read DR
 898                  */
 899                 sr = readb(sport->port.membase + UARTSR1);
 900                 rx = readb(sport->port.membase + UARTDR);
 901
 902                 if (uart_prepare_sysrq_char(&sport->port, rx))
 903                         continue;
 904
 905                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 906                         if (sr & UARTSR1_PE)
 907                                 sport->port.icount.parity++;
 908                         else if (sr & UARTSR1_FE)
 909                                 sport->port.icount.frame++;
 910
 911                         if (sr & UARTSR1_OR)
 912                                 overrun++;
 913
 914                         if (sr & sport->port.ignore_status_mask) {
 915                                 if (++ignored > 100)
 916                                         goto out;
 917                                 continue;
 918                         }
 919
 920                         sr &= sport->port.read_status_mask;
 921
 922                         if (sr & UARTSR1_PE)
 923                                 flg = TTY_PARITY;
 924                         else if (sr & UARTSR1_FE)
 925                                 flg = TTY_FRAME;
 926
 927                         if (sr & UARTSR1_OR)
 928                                 flg = TTY_OVERRUN;
 929
 930                         sport->port.sysrq = 0;
 931                 }
 932
 933                 if (tty_insert_flip_char(port, rx, flg) == 0)
 934                         sport->port.icount.buf_overrun++;
 935         }
 936
 937 out:
 938         if (overrun) {
 939                 sport->port.icount.overrun += overrun;
 940
 941                 /*
 942                  * Overruns cause FIFO pointers to become missaligned.
 943                  * Flushing the receive FIFO reinitializes the pointers.
 944                  */
 945                 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
 946                 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
 947         }
 948
 949         uart_unlock_and_check_sysrq(&sport->port);
 950
 951         tty_flip_buffer_push(port);
 952 }
 953
 954 static void lpuart32_txint(struct lpuart_port *sport)
 955 {
 956         spin_lock(&sport->port.lock);
 957         lpuart32_transmit_buffer(sport);
 958         spin_unlock(&sport->port.lock);
 959 }
 960
 961 static void lpuart32_rxint(struct lpuart_port *sport)
 962 {
 963         unsigned int flg, ignored = 0;
 964         struct tty_port *port = &sport->port.state->port;
 965         unsigned long rx, sr;
 966         bool is_break;
 967
 968         spin_lock(&sport->port.lock);
 969
 970         while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
 971                 flg = TTY_NORMAL;
 972                 sport->port.icount.rx++;
 973                 /*
 974                  * to clear the FE, OR, NF, FE, PE flags,
 975                  * read STAT then read DATA reg
 976                  */
 977                 sr = lpuart32_read(&sport->port, UARTSTAT);
 978                 rx = lpuart32_read(&sport->port, UARTDATA);
 979                 rx &= UARTDATA_MASK;
 980
 981                 /*
 982                  * The LPUART can't distinguish between a break and a framing error,
 983                  * thus we assume it is a break if the received data is zero.
 984                  */
 985                 is_break = (sr & UARTSTAT_FE) && !rx;
 986
 987                 if (is_break && uart_handle_break(&sport->port))
 988                         continue;
 989
 990                 if (uart_prepare_sysrq_char(&sport->port, rx))
 991                         continue;
 992
 993                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 994                         if (sr & UARTSTAT_PE) {
 995                                 sport->port.icount.parity++;
 996                         } else if (sr & UARTSTAT_FE) {
 997                                 if (is_break)
 998                                         sport->port.icount.brk++;
 999                                 else
1000                                         sport->port.icount.frame++;
1001                         }
1002
1003                         if (sr & UARTSTAT_OR)
1004                                 sport->port.icount.overrun++;
1005
1006                         if (sr & sport->port.ignore_status_mask) {
1007                                 if (++ignored > 100)
1008                                         goto out;
1009                                 continue;
1010                         }
1011
1012                         sr &= sport->port.read_status_mask;
1013
1014                         if (sr & UARTSTAT_PE) {
1015                                 flg = TTY_PARITY;
1016                         } else if (sr & UARTSTAT_FE) {
1017                                 if (is_break)
1018                                         flg = TTY_BREAK;
1019                                 else
1020                                         flg = TTY_FRAME;
1021                         }
1022
1023                         if (sr & UARTSTAT_OR)
1024                                 flg = TTY_OVERRUN;
1025                 }
1026
1027                 if (sport->is_cs7)
1028                         rx &= 0x7F;
1029
1030                 if (tty_insert_flip_char(port, rx, flg) == 0)
1031                         sport->port.icount.buf_overrun++;
1032         }
1033
1034 out:
1035         uart_unlock_and_check_sysrq(&sport->port);
1036
1037         tty_flip_buffer_push(port);
1038 }
1039
1040 static irqreturn_t lpuart_int(int irq, void *dev_id)
1041 {
1042         struct lpuart_port *sport = dev_id;
1043         unsigned char sts;
1044
1045         sts = readb(sport->port.membase + UARTSR1);
1046
1047         /* SysRq, using dma, check for linebreak by framing err. */
1048         if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
1049                 readb(sport->port.membase + UARTDR);
1050                 uart_handle_break(&sport->port);
1051                 /* linebreak produces some garbage, removing it */
1052                 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
1053                 return IRQ_HANDLED;
1054         }
1055
1056         if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
1057                 lpuart_rxint(sport);
1058
1059         if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
1060                 lpuart_txint(sport);
1061
1062         return IRQ_HANDLED;
1063 }
1064
1065 static irqreturn_t lpuart32_int(int irq, void *dev_id)
1066 {
1067         struct lpuart_port *sport = dev_id;
1068         unsigned long sts, rxcount;
1069
1070         sts = lpuart32_read(&sport->port, UARTSTAT);
1071         rxcount = lpuart32_read(&sport->port, UARTWATER);
1072         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
1073
1074         if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1075                 lpuart32_rxint(sport);
1076
1077         if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1078                 lpuart32_txint(sport);
1079
1080         lpuart32_write(&sport->port, sts, UARTSTAT);
1081         return IRQ_HANDLED;
1082 }
1083
1084
1085 static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1086                                              unsigned char *p, int count)
1087 {
1088         while (count--) {
1089                 if (*p && uart_handle_sysrq_char(port, *p))
1090                         return;
1091                 p++;
1092         }
1093 }
1094
1095 static void lpuart_handle_sysrq(struct lpuart_port *sport)
1096 {
1097         struct circ_buf *ring = &sport->rx_ring;
1098         int count;
1099
1100         if (ring->head < ring->tail) {
1101                 count = sport->rx_sgl.length - ring->tail;
1102                 lpuart_handle_sysrq_chars(&sport->port,
1103                                           ring->buf + ring->tail, count);
1104                 ring->tail = 0;
1105         }
1106
1107         if (ring->head > ring->tail) {
1108                 count = ring->head - ring->tail;
1109                 lpuart_handle_sysrq_chars(&sport->port,
1110                                           ring->buf + ring->tail, count);
1111                 ring->tail = ring->head;
1112         }
1113 }
1114
1115 static int lpuart_tty_insert_flip_string(struct tty_port *port,
1116         unsigned char *chars, size_t size, bool is_cs7)
1117 {
1118         int i;
1119
1120         if (is_cs7)
1121                 for (i = 0; i < size; i++)
1122                         chars[i] &= 0x7F;
1123         return tty_insert_flip_string(port, chars, size);
1124 }
1125
1126 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1127 {
1128         struct tty_port *port = &sport->port.state->port;
1129         struct dma_tx_state state;
1130         enum dma_status dmastat;
1131         struct dma_chan *chan = sport->dma_rx_chan;
1132         struct circ_buf *ring = &sport->rx_ring;
1133         unsigned long flags;
1134         int count, copied;
1135
1136         if (lpuart_is_32(sport)) {
1137                 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1138
1139                 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1140                         /* Read DR to clear the error flags */
1141                         lpuart32_read(&sport->port, UARTDATA);
1142
1143                         if (sr & UARTSTAT_PE)
1144                                 sport->port.icount.parity++;
1145                         else if (sr & UARTSTAT_FE)
1146                                 sport->port.icount.frame++;
1147                 }
1148         } else {
1149                 unsigned char sr = readb(sport->port.membase + UARTSR1);
1150
1151                 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1152                         unsigned char cr2;
1153
1154                         /* Disable receiver during this operation... */
1155                         cr2 = readb(sport->port.membase + UARTCR2);
1156                         cr2 &= ~UARTCR2_RE;
1157                         writeb(cr2, sport->port.membase + UARTCR2);
1158
1159                         /* Read DR to clear the error flags */
1160                         readb(sport->port.membase + UARTDR);
1161
1162                         if (sr & UARTSR1_PE)
1163                                 sport->port.icount.parity++;
1164                         else if (sr & UARTSR1_FE)
1165                                 sport->port.icount.frame++;
1166                         /*
1167                          * At this point parity/framing error is
1168                          * cleared However, since the DMA already read
1169                          * the data register and we had to read it
1170                          * again after reading the status register to
1171                          * properly clear the flags, the FIFO actually
1172                          * underflowed... This requires a clearing of
1173                          * the FIFO...
1174                          */
1175                         if (readb(sport->port.membase + UARTSFIFO) &
1176                             UARTSFIFO_RXUF) {
1177                                 writeb(UARTSFIFO_RXUF,
1178                                        sport->port.membase + UARTSFIFO);
1179                                 writeb(UARTCFIFO_RXFLUSH,
1180                                        sport->port.membase + UARTCFIFO);
1181                         }
1182
1183                         cr2 |= UARTCR2_RE;
1184                         writeb(cr2, sport->port.membase + UARTCR2);
1185                 }
1186         }
1187
1188         async_tx_ack(sport->dma_rx_desc);
1189
1190         spin_lock_irqsave(&sport->port.lock, flags);
1191
1192         dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1193         if (dmastat == DMA_ERROR) {
1194                 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1195                 spin_unlock_irqrestore(&sport->port.lock, flags);
1196                 return;
1197         }
1198
1199         /* CPU claims ownership of RX DMA buffer */
1200         dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1201                             DMA_FROM_DEVICE);
1202
1203         /*
1204          * ring->head points to the end of data already written by the DMA.
1205          * ring->tail points to the beginning of data to be read by the
1206          * framework.
1207          * The current transfer size should not be larger than the dma buffer
1208          * length.
1209          */
1210         ring->head = sport->rx_sgl.length - state.residue;
1211         BUG_ON(ring->head > sport->rx_sgl.length);
1212
1213         /*
1214          * Silent handling of keys pressed in the sysrq timeframe
1215          */
1216         if (sport->port.sysrq) {
1217                 lpuart_handle_sysrq(sport);
1218                 goto exit;
1219         }
1220
1221         /*
1222          * At this point ring->head may point to the first byte right after the
1223          * last byte of the dma buffer:
1224          * 0 <= ring->head <= sport->rx_sgl.length
1225          *
1226          * However ring->tail must always points inside the dma buffer:
1227          * 0 <= ring->tail <= sport->rx_sgl.length - 1
1228          *
1229          * Since we use a ring buffer, we have to handle the case
1230          * where head is lower than tail. In such a case, we first read from
1231          * tail to the end of the buffer then reset tail.
1232          */
1233         if (ring->head < ring->tail) {
1234                 count = sport->rx_sgl.length - ring->tail;
1235
1236                 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1237                                         count, sport->is_cs7);
1238                 if (copied != count)
1239                         sport->port.icount.buf_overrun++;
1240                 ring->tail = 0;
1241                 sport->port.icount.rx += copied;
1242         }
1243
1244         /* Finally we read data from tail to head */
1245         if (ring->tail < ring->head) {
1246                 count = ring->head - ring->tail;
1247                 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1248                                         count, sport->is_cs7);
1249                 if (copied != count)
1250                         sport->port.icount.buf_overrun++;
1251                 /* Wrap ring->head if needed */
1252                 if (ring->head >= sport->rx_sgl.length)
1253                         ring->head = 0;
1254                 ring->tail = ring->head;
1255                 sport->port.icount.rx += copied;
1256         }
1257
1258 exit:
1259         dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1260                                DMA_FROM_DEVICE);
1261
1262         spin_unlock_irqrestore(&sport->port.lock, flags);
1263
1264         tty_flip_buffer_push(port);
1265         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1266 }
1267
1268 static void lpuart_dma_rx_complete(void *arg)
1269 {
1270         struct lpuart_port *sport = arg;
1271
1272         lpuart_copy_rx_to_tty(sport);
1273 }
1274
1275 static void lpuart_timer_func(struct timer_list *t)
1276 {
1277         struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1278
1279         lpuart_copy_rx_to_tty(sport);
1280 }
1281
1282 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1283 {
1284         struct dma_slave_config dma_rx_sconfig = {};
1285         struct circ_buf *ring = &sport->rx_ring;
1286         int ret, nent;
1287         struct tty_port *port = &sport->port.state->port;
1288         struct tty_struct *tty = port->tty;
1289         struct ktermios *termios = &tty->termios;
1290         struct dma_chan *chan = sport->dma_rx_chan;
1291         unsigned int bits = tty_get_frame_size(termios->c_cflag);
1292         unsigned int baud = tty_get_baud_rate(tty);
1293
1294         /*
1295          * Calculate length of one DMA buffer size to keep latency below
1296          * 10ms at any baud rate.
1297          */
1298         sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
1299         sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len));
1300         if (sport->rx_dma_rng_buf_len < 16)
1301                 sport->rx_dma_rng_buf_len = 16;
1302
1303         ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1304         if (!ring->buf)
1305                 return -ENOMEM;
1306
1307         sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1308         nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1309                           DMA_FROM_DEVICE);
1310
1311         if (!nent) {
1312                 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1313                 return -EINVAL;
1314         }
1315
1316         dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1317         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1318         dma_rx_sconfig.src_maxburst = 1;
1319         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1320         ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1321
1322         if (ret < 0) {
1323                 dev_err(sport->port.dev,
1324                                 "DMA Rx slave config failed, err = %d\n", ret);
1325                 return ret;
1326         }
1327
1328         sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1329                                  sg_dma_address(&sport->rx_sgl),
1330                                  sport->rx_sgl.length,
1331                                  sport->rx_sgl.length / 2,
1332                                  DMA_DEV_TO_MEM,
1333                                  DMA_PREP_INTERRUPT);
1334         if (!sport->dma_rx_desc) {
1335                 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1336                 return -EFAULT;
1337         }
1338
1339         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1340         sport->dma_rx_desc->callback_param = sport;
1341         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1342         dma_async_issue_pending(chan);
1343
1344         if (lpuart_is_32(sport)) {
1345                 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1346
1347                 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1348         } else {
1349                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1350                        sport->port.membase + UARTCR5);
1351         }
1352
1353         return 0;
1354 }
1355
1356 static void lpuart_dma_rx_free(struct uart_port *port)
1357 {
1358         struct lpuart_port *sport = container_of(port,
1359                                         struct lpuart_port, port);
1360         struct dma_chan *chan = sport->dma_rx_chan;
1361
1362         dmaengine_terminate_sync(chan);
1363         del_timer_sync(&sport->lpuart_timer);
1364         dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1365         kfree(sport->rx_ring.buf);
1366         sport->rx_ring.tail = 0;
1367         sport->rx_ring.head = 0;
1368         sport->dma_rx_desc = NULL;
1369         sport->dma_rx_cookie = -EINVAL;
1370 }
1371
1372 static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios,
1373                         struct serial_rs485 *rs485)
1374 {
1375         struct lpuart_port *sport = container_of(port,
1376                         struct lpuart_port, port);
1377
1378         u8 modem = readb(sport->port.membase + UARTMODEM) &
1379                 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1380         writeb(modem, sport->port.membase + UARTMODEM);
1381
1382         if (rs485->flags & SER_RS485_ENABLED) {
1383                 /* Enable auto RS-485 RTS mode */
1384                 modem |= UARTMODEM_TXRTSE;
1385
1386                 /*
1387                  * The hardware defaults to RTS logic HIGH while transfer.
1388                  * Switch polarity in case RTS shall be logic HIGH
1389                  * after transfer.
1390                  * Note: UART is assumed to be active high.
1391                  */
1392                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1393                         modem |= UARTMODEM_TXRTSPOL;
1394                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1395                         modem &= ~UARTMODEM_TXRTSPOL;
1396         }
1397
1398         writeb(modem, sport->port.membase + UARTMODEM);
1399         return 0;
1400 }
1401
1402 static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios,
1403                         struct serial_rs485 *rs485)
1404 {
1405         struct lpuart_port *sport = container_of(port,
1406                         struct lpuart_port, port);
1407
1408         unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1409                                 & ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE);
1410         lpuart32_write(&sport->port, modem, UARTMODIR);
1411
1412         if (rs485->flags & SER_RS485_ENABLED) {
1413                 /* Enable auto RS-485 RTS mode */
1414                 modem |= UARTMODIR_TXRTSE;
1415
1416                 /*
1417                  * The hardware defaults to RTS logic HIGH while transfer.
1418                  * Switch polarity in case RTS shall be logic HIGH
1419                  * after transfer.
1420                  * Note: UART is assumed to be active high.
1421                  */
1422                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1423                         modem |= UARTMODIR_TXRTSPOL;
1424                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1425                         modem &= ~UARTMODIR_TXRTSPOL;
1426         }
1427
1428         lpuart32_write(&sport->port, modem, UARTMODIR);
1429         return 0;
1430 }
1431
1432 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1433 {
1434         unsigned int mctrl = 0;
1435         u8 reg;
1436
1437         reg = readb(port->membase + UARTCR1);
1438         if (reg & UARTCR1_LOOPS)
1439                 mctrl |= TIOCM_LOOP;
1440
1441         return mctrl;
1442 }
1443
1444 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1445 {
1446         unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1447         u32 reg;
1448
1449         reg = lpuart32_read(port, UARTCTRL);
1450         if (reg & UARTCTRL_LOOPS)
1451                 mctrl |= TIOCM_LOOP;
1452
1453         return mctrl;
1454 }
1455
1456 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1457 {
1458         u8 reg;
1459
1460         reg = readb(port->membase + UARTCR1);
1461
1462         /* for internal loopback we need LOOPS=1 and RSRC=0 */
1463         reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
1464         if (mctrl & TIOCM_LOOP)
1465                 reg |= UARTCR1_LOOPS;
1466
1467         writeb(reg, port->membase + UARTCR1);
1468 }
1469
1470 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1471 {
1472         u32 reg;
1473
1474         reg = lpuart32_read(port, UARTCTRL);
1475
1476         /* for internal loopback we need LOOPS=1 and RSRC=0 */
1477         reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
1478         if (mctrl & TIOCM_LOOP)
1479                 reg |= UARTCTRL_LOOPS;
1480
1481         lpuart32_write(port, reg, UARTCTRL);
1482 }
1483
1484 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1485 {
1486         unsigned char temp;
1487
1488         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1489
1490         if (break_state != 0)
1491                 temp |= UARTCR2_SBK;
1492
1493         writeb(temp, port->membase + UARTCR2);
1494 }
1495
1496 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1497 {
1498         unsigned long temp;
1499
1500         temp = lpuart32_read(port, UARTCTRL);
1501
1502         /*
1503          * LPUART IP now has two known bugs, one is CTS has higher priority than the
1504          * break signal, which causes the break signal sending through UARTCTRL_SBK
1505          * may impacted by the CTS input if the HW flow control is enabled. It
1506          * exists on all platforms we support in this driver.
1507          * Another bug is i.MX8QM LPUART may have an additional break character
1508          * being sent after SBK was cleared.
1509          * To avoid above two bugs, we use Transmit Data Inversion function to send
1510          * the break signal instead of UARTCTRL_SBK.
1511          */
1512         if (break_state != 0) {
1513                 /*
1514                  * Disable the transmitter to prevent any data from being sent out
1515                  * during break, then invert the TX line to send break.
1516                  */
1517                 temp &= ~UARTCTRL_TE;
1518                 lpuart32_write(port, temp, UARTCTRL);
1519                 temp |= UARTCTRL_TXINV;
1520                 lpuart32_write(port, temp, UARTCTRL);
1521         } else {
1522                 /* Disable the TXINV to turn off break and re-enable transmitter. */
1523                 temp &= ~UARTCTRL_TXINV;
1524                 lpuart32_write(port, temp, UARTCTRL);
1525                 temp |= UARTCTRL_TE;
1526                 lpuart32_write(port, temp, UARTCTRL);
1527         }
1528 }
1529
1530 static void lpuart_setup_watermark(struct lpuart_port *sport)
1531 {
1532         unsigned char val, cr2;
1533         unsigned char cr2_saved;
1534
1535         cr2 = readb(sport->port.membase + UARTCR2);
1536         cr2_saved = cr2;
1537         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1538                         UARTCR2_RIE | UARTCR2_RE);
1539         writeb(cr2, sport->port.membase + UARTCR2);
1540
1541         val = readb(sport->port.membase + UARTPFIFO);
1542         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1543                         sport->port.membase + UARTPFIFO);
1544
1545         /* flush Tx and Rx FIFO */
1546         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1547                         sport->port.membase + UARTCFIFO);
1548
1549         /* explicitly clear RDRF */
1550         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1551                 readb(sport->port.membase + UARTDR);
1552                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1553         }
1554
1555         if (uart_console(&sport->port))
1556                 sport->rx_watermark = 1;
1557         writeb(0, sport->port.membase + UARTTWFIFO);
1558         writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO);
1559
1560         /* Restore cr2 */
1561         writeb(cr2_saved, sport->port.membase + UARTCR2);
1562 }
1563
1564 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1565 {
1566         unsigned char cr2;
1567
1568         lpuart_setup_watermark(sport);
1569
1570         cr2 = readb(sport->port.membase + UARTCR2);
1571         cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1572         writeb(cr2, sport->port.membase + UARTCR2);
1573 }
1574
1575 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1576 {
1577         unsigned long val, ctrl;
1578         unsigned long ctrl_saved;
1579
1580         ctrl = lpuart32_read(&sport->port, UARTCTRL);
1581         ctrl_saved = ctrl;
1582         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1583                         UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE);
1584         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1585
1586         /* enable FIFO mode */
1587         val = lpuart32_read(&sport->port, UARTFIFO);
1588         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1589         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1590         val |= FIELD_PREP(UARTFIFO_RXIDEN, 0x3);
1591         lpuart32_write(&sport->port, val, UARTFIFO);
1592
1593         /* set the watermark */
1594         if (uart_console(&sport->port))
1595                 sport->rx_watermark = 1;
1596         val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) |
1597               (0x0 << UARTWATER_TXWATER_OFF);
1598         lpuart32_write(&sport->port, val, UARTWATER);
1599
1600         /* set RTS watermark */
1601         if (!uart_console(&sport->port)) {
1602                 val = lpuart32_read(&sport->port, UARTMODIR);
1603                 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1);
1604                 lpuart32_write(&sport->port, val, UARTMODIR);
1605         }
1606
1607         /* Restore cr2 */
1608         lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1609 }
1610
1611 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1612 {
1613         u32 temp;
1614
1615         lpuart32_setup_watermark(sport);
1616
1617         temp = lpuart32_read(&sport->port, UARTCTRL);
1618         temp |= UARTCTRL_RE | UARTCTRL_TE;
1619         temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7);
1620         lpuart32_write(&sport->port, temp, UARTCTRL);
1621 }
1622
1623 static void rx_dma_timer_init(struct lpuart_port *sport)
1624 {
1625         timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1626         sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1627         add_timer(&sport->lpuart_timer);
1628 }
1629
1630 static void lpuart_request_dma(struct lpuart_port *sport)
1631 {
1632         sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1633         if (IS_ERR(sport->dma_tx_chan)) {
1634                 dev_dbg_once(sport->port.dev,
1635                              "DMA tx channel request failed, operating without tx DMA (%ld)\n",
1636                              PTR_ERR(sport->dma_tx_chan));
1637                 sport->dma_tx_chan = NULL;
1638         }
1639
1640         sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1641         if (IS_ERR(sport->dma_rx_chan)) {
1642                 dev_dbg_once(sport->port.dev,
1643                              "DMA rx channel request failed, operating without rx DMA (%ld)\n",
1644                              PTR_ERR(sport->dma_rx_chan));
1645                 sport->dma_rx_chan = NULL;
1646         }
1647 }
1648
1649 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1650 {
1651         u32 uartbaud;
1652         int ret;
1653
1654         if (uart_console(&sport->port))
1655                 goto err;
1656
1657         if (!sport->dma_tx_chan)
1658                 goto err;
1659
1660         ret = lpuart_dma_tx_request(&sport->port);
1661         if (ret)
1662                 goto err;
1663
1664         init_waitqueue_head(&sport->dma_wait);
1665         sport->lpuart_dma_tx_use = true;
1666         if (lpuart_is_32(sport)) {
1667                 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1668                 lpuart32_write(&sport->port,
1669                                uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1670         } else {
1671                 writeb(readb(sport->port.membase + UARTCR5) |
1672                        UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1673         }
1674
1675         return;
1676
1677 err:
1678         sport->lpuart_dma_tx_use = false;
1679 }
1680
1681 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1682 {
1683         int ret;
1684         unsigned char cr3;
1685
1686         if (uart_console(&sport->port))
1687                 goto err;
1688
1689         if (!sport->dma_rx_chan)
1690                 goto err;
1691
1692         ret = lpuart_start_rx_dma(sport);
1693         if (ret)
1694                 goto err;
1695
1696         /* set Rx DMA timeout */
1697         sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1698         if (!sport->dma_rx_timeout)
1699                 sport->dma_rx_timeout = 1;
1700
1701         sport->lpuart_dma_rx_use = true;
1702         rx_dma_timer_init(sport);
1703
1704         if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1705                 cr3 = readb(sport->port.membase + UARTCR3);
1706                 cr3 |= UARTCR3_FEIE;
1707                 writeb(cr3, sport->port.membase + UARTCR3);
1708         }
1709
1710         return;
1711
1712 err:
1713         sport->lpuart_dma_rx_use = false;
1714 }
1715
1716 static void lpuart_hw_setup(struct lpuart_port *sport)
1717 {
1718         unsigned long flags;
1719
1720         spin_lock_irqsave(&sport->port.lock, flags);
1721
1722         lpuart_setup_watermark_enable(sport);
1723
1724         lpuart_rx_dma_startup(sport);
1725         lpuart_tx_dma_startup(sport);
1726
1727         spin_unlock_irqrestore(&sport->port.lock, flags);
1728 }
1729
1730 static int lpuart_startup(struct uart_port *port)
1731 {
1732         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1733         unsigned char temp;
1734
1735         /* determine FIFO size and enable FIFO mode */
1736         temp = readb(sport->port.membase + UARTPFIFO);
1737
1738         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1739                                             UARTPFIFO_FIFOSIZE_MASK);
1740         sport->port.fifosize = sport->txfifo_size;
1741
1742         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1743                                             UARTPFIFO_FIFOSIZE_MASK);
1744
1745         lpuart_request_dma(sport);
1746         lpuart_hw_setup(sport);
1747
1748         return 0;
1749 }
1750
1751 static void lpuart32_hw_disable(struct lpuart_port *sport)
1752 {
1753         unsigned long temp;
1754
1755         temp = lpuart32_read(&sport->port, UARTCTRL);
1756         temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE |
1757                   UARTCTRL_TIE | UARTCTRL_TE);
1758         lpuart32_write(&sport->port, temp, UARTCTRL);
1759 }
1760
1761 static void lpuart32_configure(struct lpuart_port *sport)
1762 {
1763         unsigned long temp;
1764
1765         temp = lpuart32_read(&sport->port, UARTCTRL);
1766         if (!sport->lpuart_dma_rx_use)
1767                 temp |= UARTCTRL_RIE | UARTCTRL_ILIE;
1768         if (!sport->lpuart_dma_tx_use)
1769                 temp |= UARTCTRL_TIE;
1770         lpuart32_write(&sport->port, temp, UARTCTRL);
1771 }
1772
1773 static void lpuart32_hw_setup(struct lpuart_port *sport)
1774 {
1775         unsigned long flags;
1776
1777         spin_lock_irqsave(&sport->port.lock, flags);
1778
1779         lpuart32_hw_disable(sport);
1780
1781         lpuart_rx_dma_startup(sport);
1782         lpuart_tx_dma_startup(sport);
1783
1784         lpuart32_setup_watermark_enable(sport);
1785         lpuart32_configure(sport);
1786
1787         spin_unlock_irqrestore(&sport->port.lock, flags);
1788 }
1789
1790 static int lpuart32_startup(struct uart_port *port)
1791 {
1792         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1793         unsigned long temp;
1794
1795         /* determine FIFO size */
1796         temp = lpuart32_read(&sport->port, UARTFIFO);
1797
1798         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1799                                             UARTFIFO_FIFOSIZE_MASK);
1800         sport->port.fifosize = sport->txfifo_size;
1801
1802         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1803                                             UARTFIFO_FIFOSIZE_MASK);
1804
1805         /*
1806          * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
1807          * Although they support the RX/TXSIZE fields, their encoding is
1808          * different. Eg the reference manual states 0b101 is 16 words.
1809          */
1810         if (is_layerscape_lpuart(sport)) {
1811                 sport->rxfifo_size = 16;
1812                 sport->txfifo_size = 16;
1813                 sport->port.fifosize = sport->txfifo_size;
1814         }
1815
1816         lpuart_request_dma(sport);
1817         lpuart32_hw_setup(sport);
1818
1819         return 0;
1820 }
1821
1822 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1823 {
1824         if (sport->lpuart_dma_rx_use) {
1825                 lpuart_dma_rx_free(&sport->port);
1826                 sport->lpuart_dma_rx_use = false;
1827         }
1828
1829         if (sport->lpuart_dma_tx_use) {
1830                 if (wait_event_interruptible_timeout(sport->dma_wait,
1831                         !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) {
1832                         sport->dma_tx_in_progress = false;
1833                         dmaengine_terminate_sync(sport->dma_tx_chan);
1834                 }
1835                 sport->lpuart_dma_tx_use = false;
1836         }
1837
1838         if (sport->dma_tx_chan)
1839                 dma_release_channel(sport->dma_tx_chan);
1840         if (sport->dma_rx_chan)
1841                 dma_release_channel(sport->dma_rx_chan);
1842 }
1843
1844 static void lpuart_shutdown(struct uart_port *port)
1845 {
1846         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1847         unsigned char temp;
1848         unsigned long flags;
1849
1850         spin_lock_irqsave(&port->lock, flags);
1851
1852         /* disable Rx/Tx and interrupts */
1853         temp = readb(port->membase + UARTCR2);
1854         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1855                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1856         writeb(temp, port->membase + UARTCR2);
1857
1858         spin_unlock_irqrestore(&port->lock, flags);
1859
1860         lpuart_dma_shutdown(sport);
1861 }
1862
1863 static void lpuart32_shutdown(struct uart_port *port)
1864 {
1865         struct lpuart_port *sport =
1866                 container_of(port, struct lpuart_port, port);
1867         unsigned long temp;
1868         unsigned long flags;
1869
1870         spin_lock_irqsave(&port->lock, flags);
1871
1872         /* clear status */
1873         temp = lpuart32_read(&sport->port, UARTSTAT);
1874         lpuart32_write(&sport->port, temp, UARTSTAT);
1875
1876         /* disable Rx/Tx DMA */
1877         temp = lpuart32_read(port, UARTBAUD);
1878         temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1879         lpuart32_write(port, temp, UARTBAUD);
1880
1881         /* disable Rx/Tx and interrupts and break condition */
1882         temp = lpuart32_read(port, UARTCTRL);
1883         temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE |
1884                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK);
1885         lpuart32_write(port, temp, UARTCTRL);
1886
1887         spin_unlock_irqrestore(&port->lock, flags);
1888
1889         lpuart_dma_shutdown(sport);
1890 }
1891
1892 static void
1893 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1894                    const struct ktermios *old)
1895 {
1896         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1897         unsigned long flags;
1898         unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1899         unsigned int  baud;
1900         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1901         unsigned int sbr, brfa;
1902
1903         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1904         old_cr2 = readb(sport->port.membase + UARTCR2);
1905         cr3 = readb(sport->port.membase + UARTCR3);
1906         cr4 = readb(sport->port.membase + UARTCR4);
1907         bdh = readb(sport->port.membase + UARTBDH);
1908         modem = readb(sport->port.membase + UARTMODEM);
1909         /*
1910          * only support CS8 and CS7, and for CS7 must enable PE.
1911          * supported mode:
1912          *  - (7,e/o,1)
1913          *  - (8,n,1)
1914          *  - (8,m/s,1)
1915          *  - (8,e/o,1)
1916          */
1917         while ((termios->c_cflag & CSIZE) != CS8 &&
1918                 (termios->c_cflag & CSIZE) != CS7) {
1919                 termios->c_cflag &= ~CSIZE;
1920                 termios->c_cflag |= old_csize;
1921                 old_csize = CS8;
1922         }
1923
1924         if ((termios->c_cflag & CSIZE) == CS8 ||
1925                 (termios->c_cflag & CSIZE) == CS7)
1926                 cr1 = old_cr1 & ~UARTCR1_M;
1927
1928         if (termios->c_cflag & CMSPAR) {
1929                 if ((termios->c_cflag & CSIZE) != CS8) {
1930                         termios->c_cflag &= ~CSIZE;
1931                         termios->c_cflag |= CS8;
1932                 }
1933                 cr1 |= UARTCR1_M;
1934         }
1935
1936         /*
1937          * When auto RS-485 RTS mode is enabled,
1938          * hardware flow control need to be disabled.
1939          */
1940         if (sport->port.rs485.flags & SER_RS485_ENABLED)
1941                 termios->c_cflag &= ~CRTSCTS;
1942
1943         if (termios->c_cflag & CRTSCTS)
1944                 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1945         else
1946                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1947
1948         termios->c_cflag &= ~CSTOPB;
1949
1950         /* parity must be enabled when CS7 to match 8-bits format */
1951         if ((termios->c_cflag & CSIZE) == CS7)
1952                 termios->c_cflag |= PARENB;
1953
1954         if (termios->c_cflag & PARENB) {
1955                 if (termios->c_cflag & CMSPAR) {
1956                         cr1 &= ~UARTCR1_PE;
1957                         if (termios->c_cflag & PARODD)
1958                                 cr3 |= UARTCR3_T8;
1959                         else
1960                                 cr3 &= ~UARTCR3_T8;
1961                 } else {
1962                         cr1 |= UARTCR1_PE;
1963                         if ((termios->c_cflag & CSIZE) == CS8)
1964                                 cr1 |= UARTCR1_M;
1965                         if (termios->c_cflag & PARODD)
1966                                 cr1 |= UARTCR1_PT;
1967                         else
1968                                 cr1 &= ~UARTCR1_PT;
1969                 }
1970         } else {
1971                 cr1 &= ~UARTCR1_PE;
1972         }
1973
1974         /* ask the core to calculate the divisor */
1975         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1976
1977         /*
1978          * Need to update the Ring buffer length according to the selected
1979          * baud rate and restart Rx DMA path.
1980          *
1981          * Since timer function acqures sport->port.lock, need to stop before
1982          * acquring same lock because otherwise del_timer_sync() can deadlock.
1983          */
1984         if (old && sport->lpuart_dma_rx_use)
1985                 lpuart_dma_rx_free(&sport->port);
1986
1987         spin_lock_irqsave(&sport->port.lock, flags);
1988
1989         sport->port.read_status_mask = 0;
1990         if (termios->c_iflag & INPCK)
1991                 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
1992         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1993                 sport->port.read_status_mask |= UARTSR1_FE;
1994
1995         /* characters to ignore */
1996         sport->port.ignore_status_mask = 0;
1997         if (termios->c_iflag & IGNPAR)
1998                 sport->port.ignore_status_mask |= UARTSR1_PE;
1999         if (termios->c_iflag & IGNBRK) {
2000                 sport->port.ignore_status_mask |= UARTSR1_FE;
2001                 /*
2002                  * if we're ignoring parity and break indicators,
2003                  * ignore overruns too (for real raw support).
2004                  */
2005                 if (termios->c_iflag & IGNPAR)
2006                         sport->port.ignore_status_mask |= UARTSR1_OR;
2007         }
2008
2009         /* update the per-port timeout */
2010         uart_update_timeout(port, termios->c_cflag, baud);
2011
2012         /* wait transmit engin complete */
2013         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2014
2015         /* disable transmit and receive */
2016         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
2017                         sport->port.membase + UARTCR2);
2018
2019         sbr = sport->port.uartclk / (16 * baud);
2020         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
2021         bdh &= ~UARTBDH_SBR_MASK;
2022         bdh |= (sbr >> 8) & 0x1F;
2023         cr4 &= ~UARTCR4_BRFA_MASK;
2024         brfa &= UARTCR4_BRFA_MASK;
2025         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
2026         writeb(bdh, sport->port.membase + UARTBDH);
2027         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
2028         writeb(cr3, sport->port.membase + UARTCR3);
2029         writeb(cr1, sport->port.membase + UARTCR1);
2030         writeb(modem, sport->port.membase + UARTMODEM);
2031
2032         /* restore control register */
2033         writeb(old_cr2, sport->port.membase + UARTCR2);
2034
2035         if (old && sport->lpuart_dma_rx_use) {
2036                 if (!lpuart_start_rx_dma(sport))
2037                         rx_dma_timer_init(sport);
2038                 else
2039                         sport->lpuart_dma_rx_use = false;
2040         }
2041
2042         spin_unlock_irqrestore(&sport->port.lock, flags);
2043 }
2044
2045 static void __lpuart32_serial_setbrg(struct uart_port *port,
2046                                      unsigned int baudrate, bool use_rx_dma,
2047                                      bool use_tx_dma)
2048 {
2049         u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
2050         u32 clk = port->uartclk;
2051
2052         /*
2053          * The idea is to use the best OSR (over-sampling rate) possible.
2054          * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
2055          * Loop to find the best OSR value possible, one that generates minimum
2056          * baud_diff iterate through the rest of the supported values of OSR.
2057          *
2058          * Calculation Formula:
2059          *  Baud Rate = baud clock / ((OSR+1) × SBR)
2060          */
2061         baud_diff = baudrate;
2062         osr = 0;
2063         sbr = 0;
2064
2065         for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
2066                 /* calculate the temporary sbr value  */
2067                 tmp_sbr = (clk / (baudrate * tmp_osr));
2068                 if (tmp_sbr == 0)
2069                         tmp_sbr = 1;
2070
2071                 /*
2072                  * calculate the baud rate difference based on the temporary
2073                  * osr and sbr values
2074                  */
2075                 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
2076
2077                 /* select best values between sbr and sbr+1 */
2078                 tmp = clk / (tmp_osr * (tmp_sbr + 1));
2079                 if (tmp_diff > (baudrate - tmp)) {
2080                         tmp_diff = baudrate - tmp;
2081                         tmp_sbr++;
2082                 }
2083
2084                 if (tmp_sbr > UARTBAUD_SBR_MASK)
2085                         continue;
2086
2087                 if (tmp_diff <= baud_diff) {
2088                         baud_diff = tmp_diff;
2089                         osr = tmp_osr;
2090                         sbr = tmp_sbr;
2091
2092                         if (!baud_diff)
2093                                 break;
2094                 }
2095         }
2096
2097         /* handle buadrate outside acceptable rate */
2098         if (baud_diff > ((baudrate / 100) * 3))
2099                 dev_warn(port->dev,
2100                          "unacceptable baud rate difference of more than 3%%\n");
2101
2102         tmp = lpuart32_read(port, UARTBAUD);
2103
2104         if ((osr > 3) && (osr < 8))
2105                 tmp |= UARTBAUD_BOTHEDGE;
2106
2107         tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
2108         tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
2109
2110         tmp &= ~UARTBAUD_SBR_MASK;
2111         tmp |= sbr & UARTBAUD_SBR_MASK;
2112
2113         if (!use_rx_dma)
2114                 tmp &= ~UARTBAUD_RDMAE;
2115         if (!use_tx_dma)
2116                 tmp &= ~UARTBAUD_TDMAE;
2117
2118         lpuart32_write(port, tmp, UARTBAUD);
2119 }
2120
2121 static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2122                                    unsigned int baudrate)
2123 {
2124         __lpuart32_serial_setbrg(&sport->port, baudrate,
2125                                  sport->lpuart_dma_rx_use,
2126                                  sport->lpuart_dma_tx_use);
2127 }
2128
2129
2130 static void
2131 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2132                      const struct ktermios *old)
2133 {
2134         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2135         unsigned long flags;
2136         unsigned long ctrl, old_ctrl, bd, modem;
2137         unsigned int  baud;
2138         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
2139
2140         ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2141         bd = lpuart32_read(&sport->port, UARTBAUD);
2142         modem = lpuart32_read(&sport->port, UARTMODIR);
2143         sport->is_cs7 = false;
2144         /*
2145          * only support CS8 and CS7, and for CS7 must enable PE.
2146          * supported mode:
2147          *  - (7,e/o,1)
2148          *  - (8,n,1)
2149          *  - (8,m/s,1)
2150          *  - (8,e/o,1)
2151          */
2152         while ((termios->c_cflag & CSIZE) != CS8 &&
2153                 (termios->c_cflag & CSIZE) != CS7) {
2154                 termios->c_cflag &= ~CSIZE;
2155                 termios->c_cflag |= old_csize;
2156                 old_csize = CS8;
2157         }
2158
2159         if ((termios->c_cflag & CSIZE) == CS8 ||
2160                 (termios->c_cflag & CSIZE) == CS7)
2161                 ctrl = old_ctrl & ~UARTCTRL_M;
2162
2163         if (termios->c_cflag & CMSPAR) {
2164                 if ((termios->c_cflag & CSIZE) != CS8) {
2165                         termios->c_cflag &= ~CSIZE;
2166                         termios->c_cflag |= CS8;
2167                 }
2168                 ctrl |= UARTCTRL_M;
2169         }
2170
2171         /*
2172          * When auto RS-485 RTS mode is enabled,
2173          * hardware flow control need to be disabled.
2174          */
2175         if (sport->port.rs485.flags & SER_RS485_ENABLED)
2176                 termios->c_cflag &= ~CRTSCTS;
2177
2178         if (termios->c_cflag & CRTSCTS)
2179                 modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE;
2180         else
2181                 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2182
2183         if (termios->c_cflag & CSTOPB)
2184                 bd |= UARTBAUD_SBNS;
2185         else
2186                 bd &= ~UARTBAUD_SBNS;
2187
2188         /* parity must be enabled when CS7 to match 8-bits format */
2189         if ((termios->c_cflag & CSIZE) == CS7)
2190                 termios->c_cflag |= PARENB;
2191
2192         if ((termios->c_cflag & PARENB)) {
2193                 if (termios->c_cflag & CMSPAR) {
2194                         ctrl &= ~UARTCTRL_PE;
2195                         ctrl |= UARTCTRL_M;
2196                 } else {
2197                         ctrl |= UARTCTRL_PE;
2198                         if ((termios->c_cflag & CSIZE) == CS8)
2199                                 ctrl |= UARTCTRL_M;
2200                         if (termios->c_cflag & PARODD)
2201                                 ctrl |= UARTCTRL_PT;
2202                         else
2203                                 ctrl &= ~UARTCTRL_PT;
2204                 }
2205         } else {
2206                 ctrl &= ~UARTCTRL_PE;
2207         }
2208
2209         /* ask the core to calculate the divisor */
2210         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2211
2212         /*
2213          * Need to update the Ring buffer length according to the selected
2214          * baud rate and restart Rx DMA path.
2215          *
2216          * Since timer function acqures sport->port.lock, need to stop before
2217          * acquring same lock because otherwise del_timer_sync() can deadlock.
2218          */
2219         if (old && sport->lpuart_dma_rx_use)
2220                 lpuart_dma_rx_free(&sport->port);
2221
2222         spin_lock_irqsave(&sport->port.lock, flags);
2223
2224         sport->port.read_status_mask = 0;
2225         if (termios->c_iflag & INPCK)
2226                 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2227         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2228                 sport->port.read_status_mask |= UARTSTAT_FE;
2229
2230         /* characters to ignore */
2231         sport->port.ignore_status_mask = 0;
2232         if (termios->c_iflag & IGNPAR)
2233                 sport->port.ignore_status_mask |= UARTSTAT_PE;
2234         if (termios->c_iflag & IGNBRK) {
2235                 sport->port.ignore_status_mask |= UARTSTAT_FE;
2236                 /*
2237                  * if we're ignoring parity and break indicators,
2238                  * ignore overruns too (for real raw support).
2239                  */
2240                 if (termios->c_iflag & IGNPAR)
2241                         sport->port.ignore_status_mask |= UARTSTAT_OR;
2242         }
2243
2244         /* update the per-port timeout */
2245         uart_update_timeout(port, termios->c_cflag, baud);
2246
2247         /*
2248          * LPUART Transmission Complete Flag may never be set while queuing a break
2249          * character, so skip waiting for transmission complete when UARTCTRL_SBK is
2250          * asserted.
2251          */
2252         if (!(old_ctrl & UARTCTRL_SBK)) {
2253                 lpuart32_write(&sport->port, 0, UARTMODIR);
2254                 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2255         }
2256
2257         /* disable transmit and receive */
2258         lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2259                        UARTCTRL);
2260
2261         lpuart32_write(&sport->port, bd, UARTBAUD);
2262         lpuart32_serial_setbrg(sport, baud);
2263         lpuart32_write(&sport->port, modem, UARTMODIR);
2264         lpuart32_write(&sport->port, ctrl, UARTCTRL);
2265         /* restore control register */
2266
2267         if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE)
2268                 sport->is_cs7 = true;
2269
2270         if (old && sport->lpuart_dma_rx_use) {
2271                 if (!lpuart_start_rx_dma(sport))
2272                         rx_dma_timer_init(sport);
2273                 else
2274                         sport->lpuart_dma_rx_use = false;
2275         }
2276
2277         spin_unlock_irqrestore(&sport->port.lock, flags);
2278 }
2279
2280 static const char *lpuart_type(struct uart_port *port)
2281 {
2282         return "FSL_LPUART";
2283 }
2284
2285 static void lpuart_release_port(struct uart_port *port)
2286 {
2287         /* nothing to do */
2288 }
2289
2290 static int lpuart_request_port(struct uart_port *port)
2291 {
2292         return  0;
2293 }
2294
2295 /* configure/autoconfigure the port */
2296 static void lpuart_config_port(struct uart_port *port, int flags)
2297 {
2298         if (flags & UART_CONFIG_TYPE)
2299                 port->type = PORT_LPUART;
2300 }
2301
2302 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2303 {
2304         int ret = 0;
2305
2306         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2307                 ret = -EINVAL;
2308         if (port->irq != ser->irq)
2309                 ret = -EINVAL;
2310         if (ser->io_type != UPIO_MEM)
2311                 ret = -EINVAL;
2312         if (port->uartclk / 16 != ser->baud_base)
2313                 ret = -EINVAL;
2314         if (port->iobase != ser->port)
2315                 ret = -EINVAL;
2316         if (ser->hub6 != 0)
2317                 ret = -EINVAL;
2318         return ret;
2319 }
2320
2321 static const struct uart_ops lpuart_pops = {
2322         .tx_empty       = lpuart_tx_empty,
2323         .set_mctrl      = lpuart_set_mctrl,
2324         .get_mctrl      = lpuart_get_mctrl,
2325         .stop_tx        = lpuart_stop_tx,
2326         .start_tx       = lpuart_start_tx,
2327         .stop_rx        = lpuart_stop_rx,
2328         .break_ctl      = lpuart_break_ctl,
2329         .startup        = lpuart_startup,
2330         .shutdown       = lpuart_shutdown,
2331         .set_termios    = lpuart_set_termios,
2332         .pm             = lpuart_uart_pm,
2333         .type           = lpuart_type,
2334         .request_port   = lpuart_request_port,
2335         .release_port   = lpuart_release_port,
2336         .config_port    = lpuart_config_port,
2337         .verify_port    = lpuart_verify_port,
2338         .flush_buffer   = lpuart_flush_buffer,
2339 #if defined(CONFIG_CONSOLE_POLL)
2340         .poll_init      = lpuart_poll_init,
2341         .poll_get_char  = lpuart_poll_get_char,
2342         .poll_put_char  = lpuart_poll_put_char,
2343 #endif
2344 };
2345
2346 static const struct uart_ops lpuart32_pops = {
2347         .tx_empty       = lpuart32_tx_empty,
2348         .set_mctrl      = lpuart32_set_mctrl,
2349         .get_mctrl      = lpuart32_get_mctrl,
2350         .stop_tx        = lpuart32_stop_tx,
2351         .start_tx       = lpuart32_start_tx,
2352         .stop_rx        = lpuart32_stop_rx,
2353         .break_ctl      = lpuart32_break_ctl,
2354         .startup        = lpuart32_startup,
2355         .shutdown       = lpuart32_shutdown,
2356         .set_termios    = lpuart32_set_termios,
2357         .pm             = lpuart_uart_pm,
2358         .type           = lpuart_type,
2359         .request_port   = lpuart_request_port,
2360         .release_port   = lpuart_release_port,
2361         .config_port    = lpuart_config_port,
2362         .verify_port    = lpuart_verify_port,
2363         .flush_buffer   = lpuart_flush_buffer,
2364 #if defined(CONFIG_CONSOLE_POLL)
2365         .poll_init      = lpuart32_poll_init,
2366         .poll_get_char  = lpuart32_poll_get_char,
2367         .poll_put_char  = lpuart32_poll_put_char,
2368 #endif
2369 };
2370
2371 static struct lpuart_port *lpuart_ports[UART_NR];
2372
2373 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2374 static void lpuart_console_putchar(struct uart_port *port, unsigned char ch)
2375 {
2376         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2377         writeb(ch, port->membase + UARTDR);
2378 }
2379
2380 static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch)
2381 {
2382         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2383         lpuart32_write(port, ch, UARTDATA);
2384 }
2385
2386 static void
2387 lpuart_console_write(struct console *co, const char *s, unsigned int count)
2388 {
2389         struct lpuart_port *sport = lpuart_ports[co->index];
2390         unsigned char  old_cr2, cr2;
2391         unsigned long flags;
2392         int locked = 1;
2393
2394         if (oops_in_progress)
2395                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2396         else
2397                 spin_lock_irqsave(&sport->port.lock, flags);
2398
2399         /* first save CR2 and then disable interrupts */
2400         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2401         cr2 |= UARTCR2_TE | UARTCR2_RE;
2402         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2403         writeb(cr2, sport->port.membase + UARTCR2);
2404
2405         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2406
2407         /* wait for transmitter finish complete and restore CR2 */
2408         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2409
2410         writeb(old_cr2, sport->port.membase + UARTCR2);
2411
2412         if (locked)
2413                 spin_unlock_irqrestore(&sport->port.lock, flags);
2414 }
2415
2416 static void
2417 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2418 {
2419         struct lpuart_port *sport = lpuart_ports[co->index];
2420         unsigned long  old_cr, cr;
2421         unsigned long flags;
2422         int locked = 1;
2423
2424         if (oops_in_progress)
2425                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2426         else
2427                 spin_lock_irqsave(&sport->port.lock, flags);
2428
2429         /* first save CR2 and then disable interrupts */
2430         cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2431         cr |= UARTCTRL_TE | UARTCTRL_RE;
2432         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2433         lpuart32_write(&sport->port, cr, UARTCTRL);
2434
2435         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2436
2437         /* wait for transmitter finish complete and restore CR2 */
2438         lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2439
2440         lpuart32_write(&sport->port, old_cr, UARTCTRL);
2441
2442         if (locked)
2443                 spin_unlock_irqrestore(&sport->port.lock, flags);
2444 }
2445
2446 /*
2447  * if the port was already initialised (eg, by a boot loader),
2448  * try to determine the current setup.
2449  */
2450 static void __init
2451 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2452                            int *parity, int *bits)
2453 {
2454         unsigned char cr, bdh, bdl, brfa;
2455         unsigned int sbr, uartclk, baud_raw;
2456
2457         cr = readb(sport->port.membase + UARTCR2);
2458         cr &= UARTCR2_TE | UARTCR2_RE;
2459         if (!cr)
2460                 return;
2461
2462         /* ok, the port was enabled */
2463
2464         cr = readb(sport->port.membase + UARTCR1);
2465
2466         *parity = 'n';
2467         if (cr & UARTCR1_PE) {
2468                 if (cr & UARTCR1_PT)
2469                         *parity = 'o';
2470                 else
2471                         *parity = 'e';
2472         }
2473
2474         if (cr & UARTCR1_M)
2475                 *bits = 9;
2476         else
2477                 *bits = 8;
2478
2479         bdh = readb(sport->port.membase + UARTBDH);
2480         bdh &= UARTBDH_SBR_MASK;
2481         bdl = readb(sport->port.membase + UARTBDL);
2482         sbr = bdh;
2483         sbr <<= 8;
2484         sbr |= bdl;
2485         brfa = readb(sport->port.membase + UARTCR4);
2486         brfa &= UARTCR4_BRFA_MASK;
2487
2488         uartclk = lpuart_get_baud_clk_rate(sport);
2489         /*
2490          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2491          */
2492         baud_raw = uartclk / (16 * (sbr + brfa / 32));
2493
2494         if (*baud != baud_raw)
2495                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2496                                 "from %d to %d\n", baud_raw, *baud);
2497 }
2498
2499 static void __init
2500 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2501                            int *parity, int *bits)
2502 {
2503         unsigned long cr, bd;
2504         unsigned int sbr, uartclk, baud_raw;
2505
2506         cr = lpuart32_read(&sport->port, UARTCTRL);
2507         cr &= UARTCTRL_TE | UARTCTRL_RE;
2508         if (!cr)
2509                 return;
2510
2511         /* ok, the port was enabled */
2512
2513         cr = lpuart32_read(&sport->port, UARTCTRL);
2514
2515         *parity = 'n';
2516         if (cr & UARTCTRL_PE) {
2517                 if (cr & UARTCTRL_PT)
2518                         *parity = 'o';
2519                 else
2520                         *parity = 'e';
2521         }
2522
2523         if (cr & UARTCTRL_M)
2524                 *bits = 9;
2525         else
2526                 *bits = 8;
2527
2528         bd = lpuart32_read(&sport->port, UARTBAUD);
2529         bd &= UARTBAUD_SBR_MASK;
2530         if (!bd)
2531                 return;
2532
2533         sbr = bd;
2534         uartclk = lpuart_get_baud_clk_rate(sport);
2535         /*
2536          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2537          */
2538         baud_raw = uartclk / (16 * sbr);
2539
2540         if (*baud != baud_raw)
2541                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2542                                 "from %d to %d\n", baud_raw, *baud);
2543 }
2544
2545 static int __init lpuart_console_setup(struct console *co, char *options)
2546 {
2547         struct lpuart_port *sport;
2548         int baud = 115200;
2549         int bits = 8;
2550         int parity = 'n';
2551         int flow = 'n';
2552
2553         /*
2554          * check whether an invalid uart number has been specified, and
2555          * if so, search for the first available port that does have
2556          * console support.
2557          */
2558         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2559                 co->index = 0;
2560
2561         sport = lpuart_ports[co->index];
2562         if (sport == NULL)
2563                 return -ENODEV;
2564
2565         if (options)
2566                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2567         else
2568                 if (lpuart_is_32(sport))
2569                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
2570                 else
2571                         lpuart_console_get_options(sport, &baud, &parity, &bits);
2572
2573         if (lpuart_is_32(sport))
2574                 lpuart32_setup_watermark(sport);
2575         else
2576                 lpuart_setup_watermark(sport);
2577
2578         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2579 }
2580
2581 static struct uart_driver lpuart_reg;
2582 static struct console lpuart_console = {
2583         .name           = DEV_NAME,
2584         .write          = lpuart_console_write,
2585         .device         = uart_console_device,
2586         .setup          = lpuart_console_setup,
2587         .flags          = CON_PRINTBUFFER,
2588         .index          = -1,
2589         .data           = &lpuart_reg,
2590 };
2591
2592 static struct console lpuart32_console = {
2593         .name           = DEV_NAME,
2594         .write          = lpuart32_console_write,
2595         .device         = uart_console_device,
2596         .setup          = lpuart_console_setup,
2597         .flags          = CON_PRINTBUFFER,
2598         .index          = -1,
2599         .data           = &lpuart_reg,
2600 };
2601
2602 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2603 {
2604         struct earlycon_device *dev = con->data;
2605
2606         uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2607 }
2608
2609 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2610 {
2611         struct earlycon_device *dev = con->data;
2612
2613         uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2614 }
2615
2616 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2617                                           const char *opt)
2618 {
2619         if (!device->port.membase)
2620                 return -ENODEV;
2621
2622         device->con->write = lpuart_early_write;
2623         return 0;
2624 }
2625
2626 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2627                                           const char *opt)
2628 {
2629         if (!device->port.membase)
2630                 return -ENODEV;
2631
2632         if (device->port.iotype != UPIO_MEM32)
2633                 device->port.iotype = UPIO_MEM32BE;
2634
2635         device->con->write = lpuart32_early_write;
2636         return 0;
2637 }
2638
2639 static int __init ls1028a_early_console_setup(struct earlycon_device *device,
2640                                               const char *opt)
2641 {
2642         u32 cr;
2643
2644         if (!device->port.membase)
2645                 return -ENODEV;
2646
2647         device->port.iotype = UPIO_MEM32;
2648         device->con->write = lpuart32_early_write;
2649
2650         /* set the baudrate */
2651         if (device->port.uartclk && device->baud)
2652                 __lpuart32_serial_setbrg(&device->port, device->baud,
2653                                          false, false);
2654
2655         /* enable transmitter */
2656         cr = lpuart32_read(&device->port, UARTCTRL);
2657         cr |= UARTCTRL_TE;
2658         lpuart32_write(&device->port, cr, UARTCTRL);
2659
2660         return 0;
2661 }
2662
2663 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2664                                                    const char *opt)
2665 {
2666         if (!device->port.membase)
2667                 return -ENODEV;
2668
2669         device->port.iotype = UPIO_MEM32;
2670         device->port.membase += IMX_REG_OFF;
2671         device->con->write = lpuart32_early_write;
2672
2673         return 0;
2674 }
2675 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2676 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2677 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2678 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2679 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2680 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);
2681 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2682 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2683
2684 #define LPUART_CONSOLE  (&lpuart_console)
2685 #define LPUART32_CONSOLE        (&lpuart32_console)
2686 #else
2687 #define LPUART_CONSOLE  NULL
2688 #define LPUART32_CONSOLE        NULL
2689 #endif
2690
2691 static struct uart_driver lpuart_reg = {
2692         .owner          = THIS_MODULE,
2693         .driver_name    = DRIVER_NAME,
2694         .dev_name       = DEV_NAME,
2695         .nr             = ARRAY_SIZE(lpuart_ports),
2696         .cons           = LPUART_CONSOLE,
2697 };
2698
2699 static const struct serial_rs485 lpuart_rs485_supported = {
2700         .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
2701         /* delay_rts_* and RX_DURING_TX are not supported */
2702 };
2703
2704 static int lpuart_global_reset(struct lpuart_port *sport)
2705 {
2706         struct uart_port *port = &sport->port;
2707         void __iomem *global_addr;
2708         unsigned long ctrl, bd;
2709         unsigned int val = 0;
2710         int ret;
2711
2712         ret = clk_prepare_enable(sport->ipg_clk);
2713         if (ret) {
2714                 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
2715                 return ret;
2716         }
2717
2718         if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
2719                 /*
2720                  * If the transmitter is used by earlycon, wait for transmit engine to
2721                  * complete and then reset.
2722                  */
2723                 ctrl = lpuart32_read(port, UARTCTRL);
2724                 if (ctrl & UARTCTRL_TE) {
2725                         bd = lpuart32_read(&sport->port, UARTBAUD);
2726                         if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false,
2727                                               port)) {
2728                                 dev_warn(sport->port.dev,
2729                                          "timeout waiting for transmit engine to complete\n");
2730                                 clk_disable_unprepare(sport->ipg_clk);
2731                                 return 0;
2732                         }
2733                 }
2734
2735                 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
2736                 writel(UART_GLOBAL_RST, global_addr);
2737                 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
2738                 writel(0, global_addr);
2739                 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
2740
2741                 /* Recover the transmitter for earlycon. */
2742                 if (ctrl & UARTCTRL_TE) {
2743                         lpuart32_write(port, bd, UARTBAUD);
2744                         lpuart32_write(port, ctrl, UARTCTRL);
2745                 }
2746         }
2747
2748         clk_disable_unprepare(sport->ipg_clk);
2749         return 0;
2750 }
2751
2752 static int lpuart_probe(struct platform_device *pdev)
2753 {
2754         const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);
2755         struct device_node *np = pdev->dev.of_node;
2756         struct lpuart_port *sport;
2757         struct resource *res;
2758         irq_handler_t handler;
2759         int ret;
2760
2761         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2762         if (!sport)
2763                 return -ENOMEM;
2764
2765         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2766         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2767         if (IS_ERR(sport->port.membase))
2768                 return PTR_ERR(sport->port.membase);
2769
2770         sport->port.membase += sdata->reg_off;
2771         sport->port.mapbase = res->start + sdata->reg_off;
2772         sport->port.dev = &pdev->dev;
2773         sport->port.type = PORT_LPUART;
2774         sport->devtype = sdata->devtype;
2775         sport->rx_watermark = sdata->rx_watermark;
2776         ret = platform_get_irq(pdev, 0);
2777         if (ret < 0)
2778                 return ret;
2779         sport->port.irq = ret;
2780         sport->port.iotype = sdata->iotype;
2781         if (lpuart_is_32(sport))
2782                 sport->port.ops = &lpuart32_pops;
2783         else
2784                 sport->port.ops = &lpuart_pops;
2785         sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2786         sport->port.flags = UPF_BOOT_AUTOCONF;
2787
2788         if (lpuart_is_32(sport))
2789                 sport->port.rs485_config = lpuart32_config_rs485;
2790         else
2791                 sport->port.rs485_config = lpuart_config_rs485;
2792         sport->port.rs485_supported = lpuart_rs485_supported;
2793
2794         sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2795         if (IS_ERR(sport->ipg_clk)) {
2796                 ret = PTR_ERR(sport->ipg_clk);
2797                 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2798                 return ret;
2799         }
2800
2801         sport->baud_clk = NULL;
2802         if (is_imx8qxp_lpuart(sport)) {
2803                 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2804                 if (IS_ERR(sport->baud_clk)) {
2805                         ret = PTR_ERR(sport->baud_clk);
2806                         dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2807                         return ret;
2808                 }
2809         }
2810
2811         ret = of_alias_get_id(np, "serial");
2812         if (ret < 0) {
2813                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2814                 return ret;
2815         }
2816         if (ret >= ARRAY_SIZE(lpuart_ports)) {
2817                 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2818                 return -EINVAL;
2819         }
2820         sport->port.line = ret;
2821
2822         ret = lpuart_enable_clks(sport);
2823         if (ret)
2824                 return ret;
2825         sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2826
2827         lpuart_ports[sport->port.line] = sport;
2828
2829         platform_set_drvdata(pdev, &sport->port);
2830
2831         if (lpuart_is_32(sport)) {
2832                 lpuart_reg.cons = LPUART32_CONSOLE;
2833                 handler = lpuart32_int;
2834         } else {
2835                 lpuart_reg.cons = LPUART_CONSOLE;
2836                 handler = lpuart_int;
2837         }
2838
2839         pm_runtime_use_autosuspend(&pdev->dev);
2840         pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
2841         pm_runtime_set_active(&pdev->dev);
2842         pm_runtime_enable(&pdev->dev);
2843
2844         ret = lpuart_global_reset(sport);
2845         if (ret)
2846                 goto failed_reset;
2847
2848         ret = uart_get_rs485_mode(&sport->port);
2849         if (ret)
2850                 goto failed_get_rs485;
2851
2852         ret = uart_add_one_port(&lpuart_reg, &sport->port);
2853         if (ret)
2854                 goto failed_attach_port;
2855
2856         ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2857                                 DRIVER_NAME, sport);
2858         if (ret)
2859                 goto failed_irq_request;
2860
2861         return 0;
2862
2863 failed_irq_request:
2864         uart_remove_one_port(&lpuart_reg, &sport->port);
2865 failed_attach_port:
2866 failed_get_rs485:
2867 failed_reset:
2868         pm_runtime_disable(&pdev->dev);
2869         pm_runtime_set_suspended(&pdev->dev);
2870         pm_runtime_dont_use_autosuspend(&pdev->dev);
2871         lpuart_disable_clks(sport);
2872         return ret;
2873 }
2874
2875 static int lpuart_remove(struct platform_device *pdev)
2876 {
2877         struct lpuart_port *sport = platform_get_drvdata(pdev);
2878
2879         uart_remove_one_port(&lpuart_reg, &sport->port);
2880
2881         lpuart_disable_clks(sport);
2882
2883         if (sport->dma_tx_chan)
2884                 dma_release_channel(sport->dma_tx_chan);
2885
2886         if (sport->dma_rx_chan)
2887                 dma_release_channel(sport->dma_rx_chan);
2888
2889         pm_runtime_disable(&pdev->dev);
2890         pm_runtime_set_suspended(&pdev->dev);
2891         pm_runtime_dont_use_autosuspend(&pdev->dev);
2892         return 0;
2893 }
2894
2895 static int lpuart_runtime_suspend(struct device *dev)
2896 {
2897         struct platform_device *pdev = to_platform_device(dev);
2898         struct lpuart_port *sport = platform_get_drvdata(pdev);
2899
2900         lpuart_disable_clks(sport);
2901
2902         return 0;
2903 };
2904
2905 static int lpuart_runtime_resume(struct device *dev)
2906 {
2907         struct platform_device *pdev = to_platform_device(dev);
2908         struct lpuart_port *sport = platform_get_drvdata(pdev);
2909
2910         return lpuart_enable_clks(sport);
2911 };
2912
2913 static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on)
2914 {
2915         unsigned int val, baud;
2916
2917         if (lpuart_is_32(sport)) {
2918                 val = lpuart32_read(&sport->port, UARTCTRL);
2919                 baud = lpuart32_read(&sport->port, UARTBAUD);
2920                 if (on) {
2921                         /* set rx_watermark to 0 in wakeup source mode */
2922                         lpuart32_write(&sport->port, 0, UARTWATER);
2923                         val |= UARTCTRL_RIE;
2924                         /* clear RXEDGIF flag before enable RXEDGIE interrupt */
2925                         lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT);
2926                         baud |= UARTBAUD_RXEDGIE;
2927                 } else {
2928                         val &= ~UARTCTRL_RIE;
2929                         baud &= ~UARTBAUD_RXEDGIE;
2930                 }
2931                 lpuart32_write(&sport->port, val, UARTCTRL);
2932                 lpuart32_write(&sport->port, baud, UARTBAUD);
2933         } else {
2934                 val = readb(sport->port.membase + UARTCR2);
2935                 if (on)
2936                         val |= UARTCR2_RIE;
2937                 else
2938                         val &= ~UARTCR2_RIE;
2939                 writeb(val, sport->port.membase + UARTCR2);
2940         }
2941 }
2942
2943 static bool lpuart_uport_is_active(struct lpuart_port *sport)
2944 {
2945         struct tty_port *port = &sport->port.state->port;
2946         struct tty_struct *tty;
2947         struct device *tty_dev;
2948         int may_wake = 0;
2949
2950         tty = tty_port_tty_get(port);
2951         if (tty) {
2952                 tty_dev = tty->dev;
2953                 may_wake = tty_dev && device_may_wakeup(tty_dev);
2954                 tty_kref_put(tty);
2955         }
2956
2957         if ((tty_port_initialized(port) && may_wake) ||
2958             (!console_suspend_enabled && uart_console(&sport->port)))
2959                 return true;
2960
2961         return false;
2962 }
2963
2964 static int lpuart_suspend_noirq(struct device *dev)
2965 {
2966         struct lpuart_port *sport = dev_get_drvdata(dev);
2967         bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
2968
2969         if (lpuart_uport_is_active(sport))
2970                 serial_lpuart_enable_wakeup(sport, !!irq_wake);
2971
2972         pinctrl_pm_select_sleep_state(dev);
2973
2974         return 0;
2975 }
2976
2977 static int lpuart_resume_noirq(struct device *dev)
2978 {
2979         struct lpuart_port *sport = dev_get_drvdata(dev);
2980         unsigned int val;
2981
2982         pinctrl_pm_select_default_state(dev);
2983
2984         if (lpuart_uport_is_active(sport)) {
2985                 serial_lpuart_enable_wakeup(sport, false);
2986
2987                 /* clear the wakeup flags */
2988                 if (lpuart_is_32(sport)) {
2989                         val = lpuart32_read(&sport->port, UARTSTAT);
2990                         lpuart32_write(&sport->port, val, UARTSTAT);
2991                 }
2992         }
2993
2994         return 0;
2995 }
2996
2997 static int lpuart_suspend(struct device *dev)
2998 {
2999         struct lpuart_port *sport = dev_get_drvdata(dev);
3000         unsigned long temp, flags;
3001
3002         uart_suspend_port(&lpuart_reg, &sport->port);
3003
3004         if (lpuart_uport_is_active(sport)) {
3005                 spin_lock_irqsave(&sport->port.lock, flags);
3006                 if (lpuart_is_32(sport)) {
3007                         /* disable Rx/Tx and interrupts */
3008                         temp = lpuart32_read(&sport->port, UARTCTRL);
3009                         temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
3010                         lpuart32_write(&sport->port, temp, UARTCTRL);
3011                 } else {
3012                         /* disable Rx/Tx and interrupts */
3013                         temp = readb(sport->port.membase + UARTCR2);
3014                         temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
3015                         writeb(temp, sport->port.membase + UARTCR2);
3016                 }
3017                 spin_unlock_irqrestore(&sport->port.lock, flags);
3018
3019                 if (sport->lpuart_dma_rx_use) {
3020                         /*
3021                          * EDMA driver during suspend will forcefully release any
3022                          * non-idle DMA channels. If port wakeup is enabled or if port
3023                          * is console port or 'no_console_suspend' is set the Rx DMA
3024                          * cannot resume as expected, hence gracefully release the
3025                          * Rx DMA path before suspend and start Rx DMA path on resume.
3026                          */
3027                         lpuart_dma_rx_free(&sport->port);
3028
3029                         /* Disable Rx DMA to use UART port as wakeup source */
3030                         spin_lock_irqsave(&sport->port.lock, flags);
3031                         if (lpuart_is_32(sport)) {
3032                                 temp = lpuart32_read(&sport->port, UARTBAUD);
3033                                 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
3034                                                UARTBAUD);
3035                         } else {
3036                                 writeb(readb(sport->port.membase + UARTCR5) &
3037                                        ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
3038                         }
3039                         spin_unlock_irqrestore(&sport->port.lock, flags);
3040                 }
3041
3042                 if (sport->lpuart_dma_tx_use) {
3043                         spin_lock_irqsave(&sport->port.lock, flags);
3044                         if (lpuart_is_32(sport)) {
3045                                 temp = lpuart32_read(&sport->port, UARTBAUD);
3046                                 temp &= ~UARTBAUD_TDMAE;
3047                                 lpuart32_write(&sport->port, temp, UARTBAUD);
3048                         } else {
3049                                 temp = readb(sport->port.membase + UARTCR5);
3050                                 temp &= ~UARTCR5_TDMAS;
3051                                 writeb(temp, sport->port.membase + UARTCR5);
3052                         }
3053                         spin_unlock_irqrestore(&sport->port.lock, flags);
3054                         sport->dma_tx_in_progress = false;
3055                         dmaengine_terminate_sync(sport->dma_tx_chan);
3056                 }
3057         } else if (pm_runtime_active(sport->port.dev)) {
3058                 lpuart_disable_clks(sport);
3059                 pm_runtime_disable(sport->port.dev);
3060                 pm_runtime_set_suspended(sport->port.dev);
3061         }
3062
3063         return 0;
3064 }
3065
3066 static void lpuart_console_fixup(struct lpuart_port *sport)
3067 {
3068         struct tty_port *port = &sport->port.state->port;
3069         struct uart_port *uport = &sport->port;
3070         struct ktermios termios;
3071
3072         /* i.MX7ULP enter VLLS mode that lpuart module power off and registers
3073          * all lost no matter the port is wakeup source.
3074          * For console port, console baud rate setting lost and print messy
3075          * log when enable the console port as wakeup source. To avoid the
3076          * issue happen, user should not enable uart port as wakeup source
3077          * in VLLS mode, or restore console setting here.
3078          */
3079         if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) &&
3080             console_suspend_enabled && uart_console(&sport->port)) {
3081
3082                 mutex_lock(&port->mutex);
3083                 memset(&termios, 0, sizeof(struct ktermios));
3084                 termios.c_cflag = uport->cons->cflag;
3085                 if (port->tty && termios.c_cflag == 0)
3086                         termios = port->tty->termios;
3087                 uport->ops->set_termios(uport, &termios, NULL);
3088                 mutex_unlock(&port->mutex);
3089         }
3090 }
3091
3092 static int lpuart_resume(struct device *dev)
3093 {
3094         struct lpuart_port *sport = dev_get_drvdata(dev);
3095         int ret;
3096
3097         if (lpuart_uport_is_active(sport)) {
3098                 if (lpuart_is_32(sport))
3099                         lpuart32_hw_setup(sport);
3100                 else
3101                         lpuart_hw_setup(sport);
3102         } else if (pm_runtime_active(sport->port.dev)) {
3103                 ret = lpuart_enable_clks(sport);
3104                 if (ret)
3105                         return ret;
3106                 pm_runtime_set_active(sport->port.dev);
3107                 pm_runtime_enable(sport->port.dev);
3108         }
3109
3110         lpuart_console_fixup(sport);
3111         uart_resume_port(&lpuart_reg, &sport->port);
3112
3113         return 0;
3114 }
3115
3116 static const struct dev_pm_ops lpuart_pm_ops = {
3117         RUNTIME_PM_OPS(lpuart_runtime_suspend,
3118                            lpuart_runtime_resume, NULL)
3119         NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq,
3120                                       lpuart_resume_noirq)
3121         SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume)
3122 };
3123
3124 static struct platform_driver lpuart_driver = {
3125         .probe          = lpuart_probe,
3126         .remove         = lpuart_remove,
3127         .driver         = {
3128                 .name   = "fsl-lpuart",
3129                 .of_match_table = lpuart_dt_ids,
3130                 .pm     = pm_ptr(&lpuart_pm_ops),
3131         },
3132 };
3133
3134 static int __init lpuart_serial_init(void)
3135 {
3136         int ret = uart_register_driver(&lpuart_reg);
3137
3138         if (ret)
3139                 return ret;
3140
3141         ret = platform_driver_register(&lpuart_driver);
3142         if (ret)
3143                 uart_unregister_driver(&lpuart_reg);
3144
3145         return ret;
3146 }
3147
3148 static void __exit lpuart_serial_exit(void)
3149 {
3150         platform_driver_unregister(&lpuart_driver);
3151         uart_unregister_driver(&lpuart_reg);
3152 }
3153
3154 module_init(lpuart_serial_init);
3155 module_exit(lpuart_serial_exit);
3156
3157 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
3158 MODULE_LICENSE("GPL v2");