drivers/tty/serial/fsl_lpuart.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  *  Freescale lpuart serial port driver
   4  *
   5  *  Copyright 2012-2014 Freescale Semiconductor, Inc.
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/bits.h>
  10 #include <linux/clk.h>
  11 #include <linux/console.h>
  12 #include <linux/delay.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/dmaengine.h>
  15 #include <linux/dmapool.h>
  16 #include <linux/io.h>
  17 #include <linux/iopoll.h>
  18 #include <linux/irq.h>
  19 #include <linux/module.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_dma.h>
  23 #include <linux/pinctrl/consumer.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/serial_core.h>
  26 #include <linux/slab.h>
  27 #include <linux/tty_flip.h>
  28
  29 /* All registers are 8-bit width */
  30 #define UARTBDH                 0x00
  31 #define UARTBDL                 0x01
  32 #define UARTCR1                 0x02
  33 #define UARTCR2                 0x03
  34 #define UARTSR1                 0x04
  35 #define UARTCR3                 0x06
  36 #define UARTDR                  0x07
  37 #define UARTCR4                 0x0a
  38 #define UARTCR5                 0x0b
  39 #define UARTMODEM               0x0d
  40 #define UARTPFIFO               0x10
  41 #define UARTCFIFO               0x11
  42 #define UARTSFIFO               0x12
  43 #define UARTTWFIFO              0x13
  44 #define UARTTCFIFO              0x14
  45 #define UARTRWFIFO              0x15
  46
  47 #define UARTBDH_LBKDIE          0x80
  48 #define UARTBDH_RXEDGIE         0x40
  49 #define UARTBDH_SBR_MASK        0x1f
  50
  51 #define UARTCR1_LOOPS           0x80
  52 #define UARTCR1_RSRC            0x20
  53 #define UARTCR1_M               0x10
  54 #define UARTCR1_WAKE            0x08
  55 #define UARTCR1_ILT             0x04
  56 #define UARTCR1_PE              0x02
  57 #define UARTCR1_PT              0x01
  58
  59 #define UARTCR2_TIE             0x80
  60 #define UARTCR2_TCIE            0x40
  61 #define UARTCR2_RIE             0x20
  62 #define UARTCR2_ILIE            0x10
  63 #define UARTCR2_TE              0x08
  64 #define UARTCR2_RE              0x04
  65 #define UARTCR2_RWU             0x02
  66 #define UARTCR2_SBK             0x01
  67
  68 #define UARTSR1_TDRE            0x80
  69 #define UARTSR1_TC              0x40
  70 #define UARTSR1_RDRF            0x20
  71 #define UARTSR1_IDLE            0x10
  72 #define UARTSR1_OR              0x08
  73 #define UARTSR1_NF              0x04
  74 #define UARTSR1_FE              0x02
  75 #define UARTSR1_PE              0x01
  76
  77 #define UARTCR3_R8              0x80
  78 #define UARTCR3_T8              0x40
  79 #define UARTCR3_TXDIR           0x20
  80 #define UARTCR3_TXINV           0x10
  81 #define UARTCR3_ORIE            0x08
  82 #define UARTCR3_NEIE            0x04
  83 #define UARTCR3_FEIE            0x02
  84 #define UARTCR3_PEIE            0x01
  85
  86 #define UARTCR4_MAEN1           0x80
  87 #define UARTCR4_MAEN2           0x40
  88 #define UARTCR4_M10             0x20
  89 #define UARTCR4_BRFA_MASK       0x1f
  90 #define UARTCR4_BRFA_OFF        0
  91
  92 #define UARTCR5_TDMAS           0x80
  93 #define UARTCR5_RDMAS           0x20
  94
  95 #define UARTMODEM_RXRTSE        0x08
  96 #define UARTMODEM_TXRTSPOL      0x04
  97 #define UARTMODEM_TXRTSE        0x02
  98 #define UARTMODEM_TXCTSE        0x01
  99
 100 #define UARTPFIFO_TXFE          0x80
 101 #define UARTPFIFO_FIFOSIZE_MASK 0x7
 102 #define UARTPFIFO_TXSIZE_OFF    4
 103 #define UARTPFIFO_RXFE          0x08
 104 #define UARTPFIFO_RXSIZE_OFF    0
 105
 106 #define UARTCFIFO_TXFLUSH       0x80
 107 #define UARTCFIFO_RXFLUSH       0x40
 108 #define UARTCFIFO_RXOFE         0x04
 109 #define UARTCFIFO_TXOFE         0x02
 110 #define UARTCFIFO_RXUFE         0x01
 111
 112 #define UARTSFIFO_TXEMPT        0x80
 113 #define UARTSFIFO_RXEMPT        0x40
 114 #define UARTSFIFO_RXOF          0x04
 115 #define UARTSFIFO_TXOF          0x02
 116 #define UARTSFIFO_RXUF          0x01
 117
 118 /* 32-bit global registers only for i.MX7ULP/i.MX8x
 119  * Used to reset all internal logic and registers, except the Global Register.
 120  */
 121 #define UART_GLOBAL             0x8
 122
 123 /* 32-bit register definition */
 124 #define UARTBAUD                0x00
 125 #define UARTSTAT                0x04
 126 #define UARTCTRL                0x08
 127 #define UARTDATA                0x0C
 128 #define UARTMATCH               0x10
 129 #define UARTMODIR               0x14
 130 #define UARTFIFO                0x18
 131 #define UARTWATER               0x1c
 132
 133 #define UARTBAUD_MAEN1          0x80000000
 134 #define UARTBAUD_MAEN2          0x40000000
 135 #define UARTBAUD_M10            0x20000000
 136 #define UARTBAUD_TDMAE          0x00800000
 137 #define UARTBAUD_RDMAE          0x00200000
 138 #define UARTBAUD_MATCFG         0x00400000
 139 #define UARTBAUD_BOTHEDGE       0x00020000
 140 #define UARTBAUD_RESYNCDIS      0x00010000
 141 #define UARTBAUD_LBKDIE         0x00008000
 142 #define UARTBAUD_RXEDGIE        0x00004000
 143 #define UARTBAUD_SBNS           0x00002000
 144 #define UARTBAUD_SBR            0x00000000
 145 #define UARTBAUD_SBR_MASK       0x1fff
 146 #define UARTBAUD_OSR_MASK       0x1f
 147 #define UARTBAUD_OSR_SHIFT      24
 148
 149 #define UARTSTAT_LBKDIF         0x80000000
 150 #define UARTSTAT_RXEDGIF        0x40000000
 151 #define UARTSTAT_MSBF           0x20000000
 152 #define UARTSTAT_RXINV          0x10000000
 153 #define UARTSTAT_RWUID          0x08000000
 154 #define UARTSTAT_BRK13          0x04000000
 155 #define UARTSTAT_LBKDE          0x02000000
 156 #define UARTSTAT_RAF            0x01000000
 157 #define UARTSTAT_TDRE           0x00800000
 158 #define UARTSTAT_TC             0x00400000
 159 #define UARTSTAT_RDRF           0x00200000
 160 #define UARTSTAT_IDLE           0x00100000
 161 #define UARTSTAT_OR             0x00080000
 162 #define UARTSTAT_NF             0x00040000
 163 #define UARTSTAT_FE             0x00020000
 164 #define UARTSTAT_PE             0x00010000
 165 #define UARTSTAT_MA1F           0x00008000
 166 #define UARTSTAT_M21F           0x00004000
 167
 168 #define UARTCTRL_R8T9           0x80000000
 169 #define UARTCTRL_R9T8           0x40000000
 170 #define UARTCTRL_TXDIR          0x20000000
 171 #define UARTCTRL_TXINV          0x10000000
 172 #define UARTCTRL_ORIE           0x08000000
 173 #define UARTCTRL_NEIE           0x04000000
 174 #define UARTCTRL_FEIE           0x02000000
 175 #define UARTCTRL_PEIE           0x01000000
 176 #define UARTCTRL_TIE            0x00800000
 177 #define UARTCTRL_TCIE           0x00400000
 178 #define UARTCTRL_RIE            0x00200000
 179 #define UARTCTRL_ILIE           0x00100000
 180 #define UARTCTRL_TE             0x00080000
 181 #define UARTCTRL_RE             0x00040000
 182 #define UARTCTRL_RWU            0x00020000
 183 #define UARTCTRL_SBK            0x00010000
 184 #define UARTCTRL_MA1IE          0x00008000
 185 #define UARTCTRL_MA2IE          0x00004000
 186 #define UARTCTRL_IDLECFG        GENMASK(10, 8)
 187 #define UARTCTRL_LOOPS          0x00000080
 188 #define UARTCTRL_DOZEEN         0x00000040
 189 #define UARTCTRL_RSRC           0x00000020
 190 #define UARTCTRL_M              0x00000010
 191 #define UARTCTRL_WAKE           0x00000008
 192 #define UARTCTRL_ILT            0x00000004
 193 #define UARTCTRL_PE             0x00000002
 194 #define UARTCTRL_PT             0x00000001
 195
 196 #define UARTDATA_NOISY          0x00008000
 197 #define UARTDATA_PARITYE        0x00004000
 198 #define UARTDATA_FRETSC         0x00002000
 199 #define UARTDATA_RXEMPT         0x00001000
 200 #define UARTDATA_IDLINE         0x00000800
 201 #define UARTDATA_MASK           0x3ff
 202
 203 #define UARTMODIR_IREN          0x00020000
 204 #define UARTMODIR_RTSWATER      GENMASK(10, 8)
 205 #define UARTMODIR_TXCTSSRC      0x00000020
 206 #define UARTMODIR_TXCTSC        0x00000010
 207 #define UARTMODIR_RXRTSE        0x00000008
 208 #define UARTMODIR_TXRTSPOL      0x00000004
 209 #define UARTMODIR_TXRTSE        0x00000002
 210 #define UARTMODIR_TXCTSE        0x00000001
 211
 212 #define UARTFIFO_TXEMPT         0x00800000
 213 #define UARTFIFO_RXEMPT         0x00400000
 214 #define UARTFIFO_TXOF           0x00020000
 215 #define UARTFIFO_RXUF           0x00010000
 216 #define UARTFIFO_TXFLUSH        0x00008000
 217 #define UARTFIFO_RXFLUSH        0x00004000
 218 #define UARTFIFO_RXIDEN GENMASK(12, 10)
 219 #define UARTFIFO_TXOFE          0x00000200
 220 #define UARTFIFO_RXUFE          0x00000100
 221 #define UARTFIFO_TXFE           0x00000080
 222 #define UARTFIFO_FIFOSIZE_MASK  0x7
 223 #define UARTFIFO_TXSIZE_OFF     4
 224 #define UARTFIFO_RXFE           0x00000008
 225 #define UARTFIFO_RXSIZE_OFF     0
 226 #define UARTFIFO_DEPTH(x)       (0x1 << ((x) ? ((x) + 1) : 0))
 227
 228 #define UARTWATER_COUNT_MASK    0xff
 229 #define UARTWATER_TXCNT_OFF     8
 230 #define UARTWATER_RXCNT_OFF     24
 231 #define UARTWATER_WATER_MASK    0xff
 232 #define UARTWATER_TXWATER_OFF   0
 233 #define UARTWATER_RXWATER_OFF   16
 234
 235 #define UART_GLOBAL_RST 0x2
 236 #define GLOBAL_RST_MIN_US       20
 237 #define GLOBAL_RST_MAX_US       40
 238
 239 /* Rx DMA timeout in ms, which is used to calculate Rx ring buffer size */
 240 #define DMA_RX_TIMEOUT          (10)
 241 #define DMA_RX_IDLE_CHARS       8
 242 #define UART_AUTOSUSPEND_TIMEOUT        3000
 243
 244 #define DRIVER_NAME     "fsl-lpuart"
 245 #define DEV_NAME        "ttyLP"
 246 #define UART_NR         8
 247
 248 /* IMX lpuart has four extra unused regs located at the beginning */
 249 #define IMX_REG_OFF     0x10
 250
 251 enum lpuart_type {
 252         VF610_LPUART,
 253         LS1021A_LPUART,
 254         LS1028A_LPUART,
 255         IMX7ULP_LPUART,
 256         IMX8ULP_LPUART,
 257         IMX8QXP_LPUART,
 258         IMXRT1050_LPUART,
 259 };
 260
 261 struct lpuart_port {
 262         struct uart_port        port;
 263         enum lpuart_type        devtype;
 264         struct clk              *ipg_clk;
 265         struct clk              *baud_clk;
 266         unsigned int            txfifo_size;
 267         unsigned int            rxfifo_size;
 268
 269         u8                      rx_watermark;
 270         bool                    lpuart_dma_tx_use;
 271         bool                    lpuart_dma_rx_use;
 272         struct dma_chan         *dma_tx_chan;
 273         struct dma_chan         *dma_rx_chan;
 274         struct dma_async_tx_descriptor  *dma_tx_desc;
 275         struct dma_async_tx_descriptor  *dma_rx_desc;
 276         dma_cookie_t            dma_tx_cookie;
 277         dma_cookie_t            dma_rx_cookie;
 278         unsigned int            dma_tx_bytes;
 279         unsigned int            dma_rx_bytes;
 280         bool                    dma_tx_in_progress;
 281         unsigned int            dma_rx_timeout;
 282         struct timer_list       lpuart_timer;
 283         struct scatterlist      rx_sgl, tx_sgl[2];
 284         struct circ_buf         rx_ring;
 285         int                     rx_dma_rng_buf_len;
 286         int                     last_residue;
 287         unsigned int            dma_tx_nents;
 288         wait_queue_head_t       dma_wait;
 289         bool                    is_cs7; /* Set to true when character size is 7 */
 290                                         /* and the parity is enabled            */
 291 };
 292
 293 struct lpuart_soc_data {
 294         enum lpuart_type devtype;
 295         char iotype;
 296         u8 reg_off;
 297         u8 rx_watermark;
 298 };
 299
 300 static const struct lpuart_soc_data vf_data = {
 301         .devtype = VF610_LPUART,
 302         .iotype = UPIO_MEM,
 303         .rx_watermark = 1,
 304 };
 305
 306 static const struct lpuart_soc_data ls1021a_data = {
 307         .devtype = LS1021A_LPUART,
 308         .iotype = UPIO_MEM32BE,
 309         .rx_watermark = 1,
 310 };
 311
 312 static const struct lpuart_soc_data ls1028a_data = {
 313         .devtype = LS1028A_LPUART,
 314         .iotype = UPIO_MEM32,
 315         .rx_watermark = 0,
 316 };
 317
 318 static struct lpuart_soc_data imx7ulp_data = {
 319         .devtype = IMX7ULP_LPUART,
 320         .iotype = UPIO_MEM32,
 321         .reg_off = IMX_REG_OFF,
 322         .rx_watermark = 1,
 323 };
 324
 325 static struct lpuart_soc_data imx8ulp_data = {
 326         .devtype = IMX8ULP_LPUART,
 327         .iotype = UPIO_MEM32,
 328         .reg_off = IMX_REG_OFF,
 329         .rx_watermark = 3,
 330 };
 331
 332 static struct lpuart_soc_data imx8qxp_data = {
 333         .devtype = IMX8QXP_LPUART,
 334         .iotype = UPIO_MEM32,
 335         .reg_off = IMX_REG_OFF,
 336         .rx_watermark = 7, /* A lower watermark is ideal for low baud rates. */
 337 };
 338 static struct lpuart_soc_data imxrt1050_data = {
 339         .devtype = IMXRT1050_LPUART,
 340         .iotype = UPIO_MEM32,
 341         .reg_off = IMX_REG_OFF,
 342         .rx_watermark = 1,
 343 };
 344
 345 static const struct of_device_id lpuart_dt_ids[] = {
 346         { .compatible = "fsl,vf610-lpuart",     .data = &vf_data, },
 347         { .compatible = "fsl,ls1021a-lpuart",   .data = &ls1021a_data, },
 348         { .compatible = "fsl,ls1028a-lpuart",   .data = &ls1028a_data, },
 349         { .compatible = "fsl,imx7ulp-lpuart",   .data = &imx7ulp_data, },
 350         { .compatible = "fsl,imx8ulp-lpuart",   .data = &imx8ulp_data, },
 351         { .compatible = "fsl,imx8qxp-lpuart",   .data = &imx8qxp_data, },
 352         { .compatible = "fsl,imxrt1050-lpuart", .data = &imxrt1050_data},
 353         { /* sentinel */ }
 354 };
 355 MODULE_DEVICE_TABLE(of, lpuart_dt_ids);
 356
 357 /* Forward declare this for the dma callbacks*/
 358 static void lpuart_dma_tx_complete(void *arg);
 359
 360 static inline bool is_layerscape_lpuart(struct lpuart_port *sport)
 361 {
 362         return (sport->devtype == LS1021A_LPUART ||
 363                 sport->devtype == LS1028A_LPUART);
 364 }
 365
 366 static inline bool is_imx7ulp_lpuart(struct lpuart_port *sport)
 367 {
 368         return sport->devtype == IMX7ULP_LPUART;
 369 }
 370
 371 static inline bool is_imx8ulp_lpuart(struct lpuart_port *sport)
 372 {
 373         return sport->devtype == IMX8ULP_LPUART;
 374 }
 375
 376 static inline bool is_imx8qxp_lpuart(struct lpuart_port *sport)
 377 {
 378         return sport->devtype == IMX8QXP_LPUART;
 379 }
 380
 381 static inline u32 lpuart32_read(struct uart_port *port, u32 off)
 382 {
 383         switch (port->iotype) {
 384         case UPIO_MEM32:
 385                 return readl(port->membase + off);
 386         case UPIO_MEM32BE:
 387                 return ioread32be(port->membase + off);
 388         default:
 389                 return 0;
 390         }
 391 }
 392
 393 static inline void lpuart32_write(struct uart_port *port, u32 val,
 394                                   u32 off)
 395 {
 396         switch (port->iotype) {
 397         case UPIO_MEM32:
 398                 writel(val, port->membase + off);
 399                 break;
 400         case UPIO_MEM32BE:
 401                 iowrite32be(val, port->membase + off);
 402                 break;
 403         }
 404 }
 405
 406 static int __lpuart_enable_clks(struct lpuart_port *sport, bool is_en)
 407 {
 408         int ret = 0;
 409
 410         if (is_en) {
 411                 ret = clk_prepare_enable(sport->ipg_clk);
 412                 if (ret)
 413                         return ret;
 414
 415                 ret = clk_prepare_enable(sport->baud_clk);
 416                 if (ret) {
 417                         clk_disable_unprepare(sport->ipg_clk);
 418                         return ret;
 419                 }
 420         } else {
 421                 clk_disable_unprepare(sport->baud_clk);
 422                 clk_disable_unprepare(sport->ipg_clk);
 423         }
 424
 425         return 0;
 426 }
 427
 428 static unsigned int lpuart_get_baud_clk_rate(struct lpuart_port *sport)
 429 {
 430         if (is_imx8qxp_lpuart(sport))
 431                 return clk_get_rate(sport->baud_clk);
 432
 433         return clk_get_rate(sport->ipg_clk);
 434 }
 435
 436 #define lpuart_enable_clks(x)   __lpuart_enable_clks(x, true)
 437 #define lpuart_disable_clks(x)  __lpuart_enable_clks(x, false)
 438
 439 static void lpuart_stop_tx(struct uart_port *port)
 440 {
 441         unsigned char temp;
 442
 443         temp = readb(port->membase + UARTCR2);
 444         temp &= ~(UARTCR2_TIE | UARTCR2_TCIE);
 445         writeb(temp, port->membase + UARTCR2);
 446 }
 447
 448 static void lpuart32_stop_tx(struct uart_port *port)
 449 {
 450         unsigned long temp;
 451
 452         temp = lpuart32_read(port, UARTCTRL);
 453         temp &= ~(UARTCTRL_TIE | UARTCTRL_TCIE);
 454         lpuart32_write(port, temp, UARTCTRL);
 455 }
 456
 457 static void lpuart_stop_rx(struct uart_port *port)
 458 {
 459         unsigned char temp;
 460
 461         temp = readb(port->membase + UARTCR2);
 462         writeb(temp & ~UARTCR2_RE, port->membase + UARTCR2);
 463 }
 464
 465 static void lpuart32_stop_rx(struct uart_port *port)
 466 {
 467         unsigned long temp;
 468
 469         temp = lpuart32_read(port, UARTCTRL);
 470         lpuart32_write(port, temp & ~UARTCTRL_RE, UARTCTRL);
 471 }
 472
 473 static void lpuart_dma_tx(struct lpuart_port *sport)
 474 {
 475         struct circ_buf *xmit = &sport->port.state->xmit;
 476         struct scatterlist *sgl = sport->tx_sgl;
 477         struct device *dev = sport->port.dev;
 478         struct dma_chan *chan = sport->dma_tx_chan;
 479         int ret;
 480
 481         if (sport->dma_tx_in_progress)
 482                 return;
 483
 484         sport->dma_tx_bytes = uart_circ_chars_pending(xmit);
 485
 486         if (xmit->tail < xmit->head || xmit->head == 0) {
 487                 sport->dma_tx_nents = 1;
 488                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->dma_tx_bytes);
 489         } else {
 490                 sport->dma_tx_nents = 2;
 491                 sg_init_table(sgl, 2);
 492                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 493                                 UART_XMIT_SIZE - xmit->tail);
 494                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 495         }
 496
 497         ret = dma_map_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 498                          DMA_TO_DEVICE);
 499         if (!ret) {
 500                 dev_err(dev, "DMA mapping error for TX.\n");
 501                 return;
 502         }
 503
 504         sport->dma_tx_desc = dmaengine_prep_slave_sg(chan, sgl,
 505                                         ret, DMA_MEM_TO_DEV,
 506                                         DMA_PREP_INTERRUPT);
 507         if (!sport->dma_tx_desc) {
 508                 dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 509                               DMA_TO_DEVICE);
 510                 dev_err(dev, "Cannot prepare TX slave DMA!\n");
 511                 return;
 512         }
 513
 514         sport->dma_tx_desc->callback = lpuart_dma_tx_complete;
 515         sport->dma_tx_desc->callback_param = sport;
 516         sport->dma_tx_in_progress = true;
 517         sport->dma_tx_cookie = dmaengine_submit(sport->dma_tx_desc);
 518         dma_async_issue_pending(chan);
 519 }
 520
 521 static bool lpuart_stopped_or_empty(struct uart_port *port)
 522 {
 523         return uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port);
 524 }
 525
 526 static void lpuart_dma_tx_complete(void *arg)
 527 {
 528         struct lpuart_port *sport = arg;
 529         struct scatterlist *sgl = &sport->tx_sgl[0];
 530         struct circ_buf *xmit = &sport->port.state->xmit;
 531         struct dma_chan *chan = sport->dma_tx_chan;
 532         unsigned long flags;
 533
 534         spin_lock_irqsave(&sport->port.lock, flags);
 535         if (!sport->dma_tx_in_progress) {
 536                 spin_unlock_irqrestore(&sport->port.lock, flags);
 537                 return;
 538         }
 539
 540         dma_unmap_sg(chan->device->dev, sgl, sport->dma_tx_nents,
 541                      DMA_TO_DEVICE);
 542
 543         uart_xmit_advance(&sport->port, sport->dma_tx_bytes);
 544         sport->dma_tx_in_progress = false;
 545         spin_unlock_irqrestore(&sport->port.lock, flags);
 546
 547         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 548                 uart_write_wakeup(&sport->port);
 549
 550         if (waitqueue_active(&sport->dma_wait)) {
 551                 wake_up(&sport->dma_wait);
 552                 return;
 553         }
 554
 555         spin_lock_irqsave(&sport->port.lock, flags);
 556
 557         if (!lpuart_stopped_or_empty(&sport->port))
 558                 lpuart_dma_tx(sport);
 559
 560         spin_unlock_irqrestore(&sport->port.lock, flags);
 561 }
 562
 563 static dma_addr_t lpuart_dma_datareg_addr(struct lpuart_port *sport)
 564 {
 565         switch (sport->port.iotype) {
 566         case UPIO_MEM32:
 567                 return sport->port.mapbase + UARTDATA;
 568         case UPIO_MEM32BE:
 569                 return sport->port.mapbase + UARTDATA + sizeof(u32) - 1;
 570         }
 571         return sport->port.mapbase + UARTDR;
 572 }
 573
 574 static int lpuart_dma_tx_request(struct uart_port *port)
 575 {
 576         struct lpuart_port *sport = container_of(port,
 577                                         struct lpuart_port, port);
 578         struct dma_slave_config dma_tx_sconfig = {};
 579         int ret;
 580
 581         dma_tx_sconfig.dst_addr = lpuart_dma_datareg_addr(sport);
 582         dma_tx_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 583         dma_tx_sconfig.dst_maxburst = 1;
 584         dma_tx_sconfig.direction = DMA_MEM_TO_DEV;
 585         ret = dmaengine_slave_config(sport->dma_tx_chan, &dma_tx_sconfig);
 586
 587         if (ret) {
 588                 dev_err(sport->port.dev,
 589                                 "DMA slave config failed, err = %d\n", ret);
 590                 return ret;
 591         }
 592
 593         return 0;
 594 }
 595
 596 static bool lpuart_is_32(struct lpuart_port *sport)
 597 {
 598         return sport->port.iotype == UPIO_MEM32 ||
 599                sport->port.iotype ==  UPIO_MEM32BE;
 600 }
 601
 602 static void lpuart_flush_buffer(struct uart_port *port)
 603 {
 604         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 605         struct dma_chan *chan = sport->dma_tx_chan;
 606         u32 val;
 607
 608         if (sport->lpuart_dma_tx_use) {
 609                 if (sport->dma_tx_in_progress) {
 610                         dma_unmap_sg(chan->device->dev, &sport->tx_sgl[0],
 611                                 sport->dma_tx_nents, DMA_TO_DEVICE);
 612                         sport->dma_tx_in_progress = false;
 613                 }
 614                 dmaengine_terminate_async(chan);
 615         }
 616
 617         if (lpuart_is_32(sport)) {
 618                 val = lpuart32_read(&sport->port, UARTFIFO);
 619                 val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
 620                 lpuart32_write(&sport->port, val, UARTFIFO);
 621         } else {
 622                 val = readb(sport->port.membase + UARTCFIFO);
 623                 val |= UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH;
 624                 writeb(val, sport->port.membase + UARTCFIFO);
 625         }
 626 }
 627
 628 static void lpuart_wait_bit_set(struct uart_port *port, unsigned int offset,
 629                                 u8 bit)
 630 {
 631         while (!(readb(port->membase + offset) & bit))
 632                 cpu_relax();
 633 }
 634
 635 static void lpuart32_wait_bit_set(struct uart_port *port, unsigned int offset,
 636                                   u32 bit)
 637 {
 638         while (!(lpuart32_read(port, offset) & bit))
 639                 cpu_relax();
 640 }
 641
 642 #if defined(CONFIG_CONSOLE_POLL)
 643
 644 static int lpuart_poll_init(struct uart_port *port)
 645 {
 646         struct lpuart_port *sport = container_of(port,
 647                                         struct lpuart_port, port);
 648         unsigned long flags;
 649         unsigned char temp;
 650
 651         sport->port.fifosize = 0;
 652
 653         spin_lock_irqsave(&sport->port.lock, flags);
 654         /* Disable Rx & Tx */
 655         writeb(0, sport->port.membase + UARTCR2);
 656
 657         temp = readb(sport->port.membase + UARTPFIFO);
 658         /* Enable Rx and Tx FIFO */
 659         writeb(temp | UARTPFIFO_RXFE | UARTPFIFO_TXFE,
 660                         sport->port.membase + UARTPFIFO);
 661
 662         /* flush Tx and Rx FIFO */
 663         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
 664                         sport->port.membase + UARTCFIFO);
 665
 666         /* explicitly clear RDRF */
 667         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
 668                 readb(sport->port.membase + UARTDR);
 669                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
 670         }
 671
 672         writeb(0, sport->port.membase + UARTTWFIFO);
 673         writeb(1, sport->port.membase + UARTRWFIFO);
 674
 675         /* Enable Rx and Tx */
 676         writeb(UARTCR2_RE | UARTCR2_TE, sport->port.membase + UARTCR2);
 677         spin_unlock_irqrestore(&sport->port.lock, flags);
 678
 679         return 0;
 680 }
 681
 682 static void lpuart_poll_put_char(struct uart_port *port, unsigned char c)
 683 {
 684         /* drain */
 685         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
 686         writeb(c, port->membase + UARTDR);
 687 }
 688
 689 static int lpuart_poll_get_char(struct uart_port *port)
 690 {
 691         if (!(readb(port->membase + UARTSR1) & UARTSR1_RDRF))
 692                 return NO_POLL_CHAR;
 693
 694         return readb(port->membase + UARTDR);
 695 }
 696
 697 static int lpuart32_poll_init(struct uart_port *port)
 698 {
 699         unsigned long flags;
 700         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 701         u32 temp;
 702
 703         sport->port.fifosize = 0;
 704
 705         spin_lock_irqsave(&sport->port.lock, flags);
 706
 707         /* Disable Rx & Tx */
 708         lpuart32_write(&sport->port, 0, UARTCTRL);
 709
 710         temp = lpuart32_read(&sport->port, UARTFIFO);
 711
 712         /* Enable Rx and Tx FIFO */
 713         lpuart32_write(&sport->port, temp | UARTFIFO_RXFE | UARTFIFO_TXFE, UARTFIFO);
 714
 715         /* flush Tx and Rx FIFO */
 716         lpuart32_write(&sport->port, UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH, UARTFIFO);
 717
 718         /* explicitly clear RDRF */
 719         if (lpuart32_read(&sport->port, UARTSTAT) & UARTSTAT_RDRF) {
 720                 lpuart32_read(&sport->port, UARTDATA);
 721                 lpuart32_write(&sport->port, UARTFIFO_RXUF, UARTFIFO);
 722         }
 723
 724         /* Enable Rx and Tx */
 725         lpuart32_write(&sport->port, UARTCTRL_RE | UARTCTRL_TE, UARTCTRL);
 726         spin_unlock_irqrestore(&sport->port.lock, flags);
 727
 728         return 0;
 729 }
 730
 731 static void lpuart32_poll_put_char(struct uart_port *port, unsigned char c)
 732 {
 733         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
 734         lpuart32_write(port, c, UARTDATA);
 735 }
 736
 737 static int lpuart32_poll_get_char(struct uart_port *port)
 738 {
 739         if (!(lpuart32_read(port, UARTWATER) >> UARTWATER_RXCNT_OFF))
 740                 return NO_POLL_CHAR;
 741
 742         return lpuart32_read(port, UARTDATA);
 743 }
 744 #endif
 745
 746 static inline void lpuart_transmit_buffer(struct lpuart_port *sport)
 747 {
 748         struct uart_port *port = &sport->port;
 749         u8 ch;
 750
 751         uart_port_tx(port, ch,
 752                 readb(port->membase + UARTTCFIFO) < sport->txfifo_size,
 753                 writeb(ch, port->membase + UARTDR));
 754 }
 755
 756 static inline void lpuart32_transmit_buffer(struct lpuart_port *sport)
 757 {
 758         struct circ_buf *xmit = &sport->port.state->xmit;
 759         unsigned long txcnt;
 760
 761         if (sport->port.x_char) {
 762                 lpuart32_write(&sport->port, sport->port.x_char, UARTDATA);
 763                 sport->port.icount.tx++;
 764                 sport->port.x_char = 0;
 765                 return;
 766         }
 767
 768         if (lpuart_stopped_or_empty(&sport->port)) {
 769                 lpuart32_stop_tx(&sport->port);
 770                 return;
 771         }
 772
 773         txcnt = lpuart32_read(&sport->port, UARTWATER);
 774         txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 775         txcnt &= UARTWATER_COUNT_MASK;
 776         while (!uart_circ_empty(xmit) && (txcnt < sport->txfifo_size)) {
 777                 lpuart32_write(&sport->port, xmit->buf[xmit->tail], UARTDATA);
 778                 uart_xmit_advance(&sport->port, 1);
 779                 txcnt = lpuart32_read(&sport->port, UARTWATER);
 780                 txcnt = txcnt >> UARTWATER_TXCNT_OFF;
 781                 txcnt &= UARTWATER_COUNT_MASK;
 782         }
 783
 784         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 785                 uart_write_wakeup(&sport->port);
 786
 787         if (uart_circ_empty(xmit))
 788                 lpuart32_stop_tx(&sport->port);
 789 }
 790
 791 static void lpuart_start_tx(struct uart_port *port)
 792 {
 793         struct lpuart_port *sport = container_of(port,
 794                         struct lpuart_port, port);
 795         unsigned char temp;
 796
 797         temp = readb(port->membase + UARTCR2);
 798         writeb(temp | UARTCR2_TIE, port->membase + UARTCR2);
 799
 800         if (sport->lpuart_dma_tx_use) {
 801                 if (!lpuart_stopped_or_empty(port))
 802                         lpuart_dma_tx(sport);
 803         } else {
 804                 if (readb(port->membase + UARTSR1) & UARTSR1_TDRE)
 805                         lpuart_transmit_buffer(sport);
 806         }
 807 }
 808
 809 static void lpuart32_start_tx(struct uart_port *port)
 810 {
 811         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
 812         unsigned long temp;
 813
 814         if (sport->lpuart_dma_tx_use) {
 815                 if (!lpuart_stopped_or_empty(port))
 816                         lpuart_dma_tx(sport);
 817         } else {
 818                 temp = lpuart32_read(port, UARTCTRL);
 819                 lpuart32_write(port, temp | UARTCTRL_TIE, UARTCTRL);
 820
 821                 if (lpuart32_read(port, UARTSTAT) & UARTSTAT_TDRE)
 822                         lpuart32_transmit_buffer(sport);
 823         }
 824 }
 825
 826 static void
 827 lpuart_uart_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
 828 {
 829         switch (state) {
 830         case UART_PM_STATE_OFF:
 831                 pm_runtime_mark_last_busy(port->dev);
 832                 pm_runtime_put_autosuspend(port->dev);
 833                 break;
 834         default:
 835                 pm_runtime_get_sync(port->dev);
 836                 break;
 837         }
 838 }
 839
 840 /* return TIOCSER_TEMT when transmitter is not busy */
 841 static unsigned int lpuart_tx_empty(struct uart_port *port)
 842 {
 843         struct lpuart_port *sport = container_of(port,
 844                         struct lpuart_port, port);
 845         unsigned char sr1 = readb(port->membase + UARTSR1);
 846         unsigned char sfifo = readb(port->membase + UARTSFIFO);
 847
 848         if (sport->dma_tx_in_progress)
 849                 return 0;
 850
 851         if (sr1 & UARTSR1_TC && sfifo & UARTSFIFO_TXEMPT)
 852                 return TIOCSER_TEMT;
 853
 854         return 0;
 855 }
 856
 857 static unsigned int lpuart32_tx_empty(struct uart_port *port)
 858 {
 859         struct lpuart_port *sport = container_of(port,
 860                         struct lpuart_port, port);
 861         unsigned long stat = lpuart32_read(port, UARTSTAT);
 862         unsigned long sfifo = lpuart32_read(port, UARTFIFO);
 863         unsigned long ctrl = lpuart32_read(port, UARTCTRL);
 864
 865         if (sport->dma_tx_in_progress)
 866                 return 0;
 867
 868         /*
 869          * LPUART Transmission Complete Flag may never be set while queuing a break
 870          * character, so avoid checking for transmission complete when UARTCTRL_SBK
 871          * is asserted.
 872          */
 873         if ((stat & UARTSTAT_TC && sfifo & UARTFIFO_TXEMPT) || ctrl & UARTCTRL_SBK)
 874                 return TIOCSER_TEMT;
 875
 876         return 0;
 877 }
 878
 879 static void lpuart_txint(struct lpuart_port *sport)
 880 {
 881         spin_lock(&sport->port.lock);
 882         lpuart_transmit_buffer(sport);
 883         spin_unlock(&sport->port.lock);
 884 }
 885
 886 static void lpuart_rxint(struct lpuart_port *sport)
 887 {
 888         unsigned int flg, ignored = 0, overrun = 0;
 889         struct tty_port *port = &sport->port.state->port;
 890         unsigned char rx, sr;
 891
 892         spin_lock(&sport->port.lock);
 893
 894         while (!(readb(sport->port.membase + UARTSFIFO) & UARTSFIFO_RXEMPT)) {
 895                 flg = TTY_NORMAL;
 896                 sport->port.icount.rx++;
 897                 /*
 898                  * to clear the FE, OR, NF, FE, PE flags,
 899                  * read SR1 then read DR
 900                  */
 901                 sr = readb(sport->port.membase + UARTSR1);
 902                 rx = readb(sport->port.membase + UARTDR);
 903
 904                 if (uart_prepare_sysrq_char(&sport->port, rx))
 905                         continue;
 906
 907                 if (sr & (UARTSR1_PE | UARTSR1_OR | UARTSR1_FE)) {
 908                         if (sr & UARTSR1_PE)
 909                                 sport->port.icount.parity++;
 910                         else if (sr & UARTSR1_FE)
 911                                 sport->port.icount.frame++;
 912
 913                         if (sr & UARTSR1_OR)
 914                                 overrun++;
 915
 916                         if (sr & sport->port.ignore_status_mask) {
 917                                 if (++ignored > 100)
 918                                         goto out;
 919                                 continue;
 920                         }
 921
 922                         sr &= sport->port.read_status_mask;
 923
 924                         if (sr & UARTSR1_PE)
 925                                 flg = TTY_PARITY;
 926                         else if (sr & UARTSR1_FE)
 927                                 flg = TTY_FRAME;
 928
 929                         if (sr & UARTSR1_OR)
 930                                 flg = TTY_OVERRUN;
 931
 932                         sport->port.sysrq = 0;
 933                 }
 934
 935                 if (tty_insert_flip_char(port, rx, flg) == 0)
 936                         sport->port.icount.buf_overrun++;
 937         }
 938
 939 out:
 940         if (overrun) {
 941                 sport->port.icount.overrun += overrun;
 942
 943                 /*
 944                  * Overruns cause FIFO pointers to become missaligned.
 945                  * Flushing the receive FIFO reinitializes the pointers.
 946                  */
 947                 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
 948                 writeb(UARTSFIFO_RXOF, sport->port.membase + UARTSFIFO);
 949         }
 950
 951         uart_unlock_and_check_sysrq(&sport->port);
 952
 953         tty_flip_buffer_push(port);
 954 }
 955
 956 static void lpuart32_txint(struct lpuart_port *sport)
 957 {
 958         spin_lock(&sport->port.lock);
 959         lpuart32_transmit_buffer(sport);
 960         spin_unlock(&sport->port.lock);
 961 }
 962
 963 static void lpuart32_rxint(struct lpuart_port *sport)
 964 {
 965         unsigned int flg, ignored = 0;
 966         struct tty_port *port = &sport->port.state->port;
 967         unsigned long rx, sr;
 968         bool is_break;
 969
 970         spin_lock(&sport->port.lock);
 971
 972         while (!(lpuart32_read(&sport->port, UARTFIFO) & UARTFIFO_RXEMPT)) {
 973                 flg = TTY_NORMAL;
 974                 sport->port.icount.rx++;
 975                 /*
 976                  * to clear the FE, OR, NF, FE, PE flags,
 977                  * read STAT then read DATA reg
 978                  */
 979                 sr = lpuart32_read(&sport->port, UARTSTAT);
 980                 rx = lpuart32_read(&sport->port, UARTDATA);
 981                 rx &= UARTDATA_MASK;
 982
 983                 /*
 984                  * The LPUART can't distinguish between a break and a framing error,
 985                  * thus we assume it is a break if the received data is zero.
 986                  */
 987                 is_break = (sr & UARTSTAT_FE) && !rx;
 988
 989                 if (is_break && uart_handle_break(&sport->port))
 990                         continue;
 991
 992                 if (uart_prepare_sysrq_char(&sport->port, rx))
 993                         continue;
 994
 995                 if (sr & (UARTSTAT_PE | UARTSTAT_OR | UARTSTAT_FE)) {
 996                         if (sr & UARTSTAT_PE) {
 997                                 sport->port.icount.parity++;
 998                         } else if (sr & UARTSTAT_FE) {
 999                                 if (is_break)
1000                                         sport->port.icount.brk++;
1001                                 else
1002                                         sport->port.icount.frame++;
1003                         }
1004
1005                         if (sr & UARTSTAT_OR)
1006                                 sport->port.icount.overrun++;
1007
1008                         if (sr & sport->port.ignore_status_mask) {
1009                                 if (++ignored > 100)
1010                                         goto out;
1011                                 continue;
1012                         }
1013
1014                         sr &= sport->port.read_status_mask;
1015
1016                         if (sr & UARTSTAT_PE) {
1017                                 flg = TTY_PARITY;
1018                         } else if (sr & UARTSTAT_FE) {
1019                                 if (is_break)
1020                                         flg = TTY_BREAK;
1021                                 else
1022                                         flg = TTY_FRAME;
1023                         }
1024
1025                         if (sr & UARTSTAT_OR)
1026                                 flg = TTY_OVERRUN;
1027                 }
1028
1029                 if (sport->is_cs7)
1030                         rx &= 0x7F;
1031
1032                 if (tty_insert_flip_char(port, rx, flg) == 0)
1033                         sport->port.icount.buf_overrun++;
1034         }
1035
1036 out:
1037         uart_unlock_and_check_sysrq(&sport->port);
1038
1039         tty_flip_buffer_push(port);
1040 }
1041
1042 static irqreturn_t lpuart_int(int irq, void *dev_id)
1043 {
1044         struct lpuart_port *sport = dev_id;
1045         unsigned char sts;
1046
1047         sts = readb(sport->port.membase + UARTSR1);
1048
1049         /* SysRq, using dma, check for linebreak by framing err. */
1050         if (sts & UARTSR1_FE && sport->lpuart_dma_rx_use) {
1051                 readb(sport->port.membase + UARTDR);
1052                 uart_handle_break(&sport->port);
1053                 /* linebreak produces some garbage, removing it */
1054                 writeb(UARTCFIFO_RXFLUSH, sport->port.membase + UARTCFIFO);
1055                 return IRQ_HANDLED;
1056         }
1057
1058         if (sts & UARTSR1_RDRF && !sport->lpuart_dma_rx_use)
1059                 lpuart_rxint(sport);
1060
1061         if (sts & UARTSR1_TDRE && !sport->lpuart_dma_tx_use)
1062                 lpuart_txint(sport);
1063
1064         return IRQ_HANDLED;
1065 }
1066
1067 static irqreturn_t lpuart32_int(int irq, void *dev_id)
1068 {
1069         struct lpuart_port *sport = dev_id;
1070         unsigned long sts, rxcount;
1071
1072         sts = lpuart32_read(&sport->port, UARTSTAT);
1073         rxcount = lpuart32_read(&sport->port, UARTWATER);
1074         rxcount = rxcount >> UARTWATER_RXCNT_OFF;
1075
1076         if ((sts & UARTSTAT_RDRF || rxcount > 0) && !sport->lpuart_dma_rx_use)
1077                 lpuart32_rxint(sport);
1078
1079         if ((sts & UARTSTAT_TDRE) && !sport->lpuart_dma_tx_use)
1080                 lpuart32_txint(sport);
1081
1082         lpuart32_write(&sport->port, sts, UARTSTAT);
1083         return IRQ_HANDLED;
1084 }
1085
1086
1087 static inline void lpuart_handle_sysrq_chars(struct uart_port *port,
1088                                              unsigned char *p, int count)
1089 {
1090         while (count--) {
1091                 if (*p && uart_handle_sysrq_char(port, *p))
1092                         return;
1093                 p++;
1094         }
1095 }
1096
1097 static void lpuart_handle_sysrq(struct lpuart_port *sport)
1098 {
1099         struct circ_buf *ring = &sport->rx_ring;
1100         int count;
1101
1102         if (ring->head < ring->tail) {
1103                 count = sport->rx_sgl.length - ring->tail;
1104                 lpuart_handle_sysrq_chars(&sport->port,
1105                                           ring->buf + ring->tail, count);
1106                 ring->tail = 0;
1107         }
1108
1109         if (ring->head > ring->tail) {
1110                 count = ring->head - ring->tail;
1111                 lpuart_handle_sysrq_chars(&sport->port,
1112                                           ring->buf + ring->tail, count);
1113                 ring->tail = ring->head;
1114         }
1115 }
1116
1117 static int lpuart_tty_insert_flip_string(struct tty_port *port,
1118         unsigned char *chars, size_t size, bool is_cs7)
1119 {
1120         int i;
1121
1122         if (is_cs7)
1123                 for (i = 0; i < size; i++)
1124                         chars[i] &= 0x7F;
1125         return tty_insert_flip_string(port, chars, size);
1126 }
1127
1128 static void lpuart_copy_rx_to_tty(struct lpuart_port *sport)
1129 {
1130         struct tty_port *port = &sport->port.state->port;
1131         struct dma_tx_state state;
1132         enum dma_status dmastat;
1133         struct dma_chan *chan = sport->dma_rx_chan;
1134         struct circ_buf *ring = &sport->rx_ring;
1135         unsigned long flags;
1136         int count, copied;
1137
1138         if (lpuart_is_32(sport)) {
1139                 unsigned long sr = lpuart32_read(&sport->port, UARTSTAT);
1140
1141                 if (sr & (UARTSTAT_PE | UARTSTAT_FE)) {
1142                         /* Read DR to clear the error flags */
1143                         lpuart32_read(&sport->port, UARTDATA);
1144
1145                         if (sr & UARTSTAT_PE)
1146                                 sport->port.icount.parity++;
1147                         else if (sr & UARTSTAT_FE)
1148                                 sport->port.icount.frame++;
1149                 }
1150         } else {
1151                 unsigned char sr = readb(sport->port.membase + UARTSR1);
1152
1153                 if (sr & (UARTSR1_PE | UARTSR1_FE)) {
1154                         unsigned char cr2;
1155
1156                         /* Disable receiver during this operation... */
1157                         cr2 = readb(sport->port.membase + UARTCR2);
1158                         cr2 &= ~UARTCR2_RE;
1159                         writeb(cr2, sport->port.membase + UARTCR2);
1160
1161                         /* Read DR to clear the error flags */
1162                         readb(sport->port.membase + UARTDR);
1163
1164                         if (sr & UARTSR1_PE)
1165                                 sport->port.icount.parity++;
1166                         else if (sr & UARTSR1_FE)
1167                                 sport->port.icount.frame++;
1168                         /*
1169                          * At this point parity/framing error is
1170                          * cleared However, since the DMA already read
1171                          * the data register and we had to read it
1172                          * again after reading the status register to
1173                          * properly clear the flags, the FIFO actually
1174                          * underflowed... This requires a clearing of
1175                          * the FIFO...
1176                          */
1177                         if (readb(sport->port.membase + UARTSFIFO) &
1178                             UARTSFIFO_RXUF) {
1179                                 writeb(UARTSFIFO_RXUF,
1180                                        sport->port.membase + UARTSFIFO);
1181                                 writeb(UARTCFIFO_RXFLUSH,
1182                                        sport->port.membase + UARTCFIFO);
1183                         }
1184
1185                         cr2 |= UARTCR2_RE;
1186                         writeb(cr2, sport->port.membase + UARTCR2);
1187                 }
1188         }
1189
1190         async_tx_ack(sport->dma_rx_desc);
1191
1192         spin_lock_irqsave(&sport->port.lock, flags);
1193
1194         dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1195         if (dmastat == DMA_ERROR) {
1196                 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1197                 spin_unlock_irqrestore(&sport->port.lock, flags);
1198                 return;
1199         }
1200
1201         /* CPU claims ownership of RX DMA buffer */
1202         dma_sync_sg_for_cpu(chan->device->dev, &sport->rx_sgl, 1,
1203                             DMA_FROM_DEVICE);
1204
1205         /*
1206          * ring->head points to the end of data already written by the DMA.
1207          * ring->tail points to the beginning of data to be read by the
1208          * framework.
1209          * The current transfer size should not be larger than the dma buffer
1210          * length.
1211          */
1212         ring->head = sport->rx_sgl.length - state.residue;
1213         BUG_ON(ring->head > sport->rx_sgl.length);
1214
1215         /*
1216          * Silent handling of keys pressed in the sysrq timeframe
1217          */
1218         if (sport->port.sysrq) {
1219                 lpuart_handle_sysrq(sport);
1220                 goto exit;
1221         }
1222
1223         /*
1224          * At this point ring->head may point to the first byte right after the
1225          * last byte of the dma buffer:
1226          * 0 <= ring->head <= sport->rx_sgl.length
1227          *
1228          * However ring->tail must always points inside the dma buffer:
1229          * 0 <= ring->tail <= sport->rx_sgl.length - 1
1230          *
1231          * Since we use a ring buffer, we have to handle the case
1232          * where head is lower than tail. In such a case, we first read from
1233          * tail to the end of the buffer then reset tail.
1234          */
1235         if (ring->head < ring->tail) {
1236                 count = sport->rx_sgl.length - ring->tail;
1237
1238                 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1239                                         count, sport->is_cs7);
1240                 if (copied != count)
1241                         sport->port.icount.buf_overrun++;
1242                 ring->tail = 0;
1243                 sport->port.icount.rx += copied;
1244         }
1245
1246         /* Finally we read data from tail to head */
1247         if (ring->tail < ring->head) {
1248                 count = ring->head - ring->tail;
1249                 copied = lpuart_tty_insert_flip_string(port, ring->buf + ring->tail,
1250                                         count, sport->is_cs7);
1251                 if (copied != count)
1252                         sport->port.icount.buf_overrun++;
1253                 /* Wrap ring->head if needed */
1254                 if (ring->head >= sport->rx_sgl.length)
1255                         ring->head = 0;
1256                 ring->tail = ring->head;
1257                 sport->port.icount.rx += copied;
1258         }
1259
1260         sport->last_residue = state.residue;
1261
1262 exit:
1263         dma_sync_sg_for_device(chan->device->dev, &sport->rx_sgl, 1,
1264                                DMA_FROM_DEVICE);
1265
1266         spin_unlock_irqrestore(&sport->port.lock, flags);
1267
1268         tty_flip_buffer_push(port);
1269         mod_timer(&sport->lpuart_timer, jiffies + sport->dma_rx_timeout);
1270 }
1271
1272 static void lpuart_dma_rx_complete(void *arg)
1273 {
1274         struct lpuart_port *sport = arg;
1275
1276         lpuart_copy_rx_to_tty(sport);
1277 }
1278
1279 /*
1280  * Timer function to simulate the hardware EOP (End Of Package) event.
1281  * The timer callback is to check for new RX data and copy to TTY buffer.
1282  * If no new data are received since last interval, the EOP condition is
1283  * met, complete the DMA transfer by copying the data. Otherwise, just
1284  * restart timer.
1285  */
1286 static void lpuart_timer_func(struct timer_list *t)
1287 {
1288         struct lpuart_port *sport = from_timer(sport, t, lpuart_timer);
1289         enum dma_status dmastat;
1290         struct dma_chan *chan = sport->dma_rx_chan;
1291         struct circ_buf *ring = &sport->rx_ring;
1292         struct dma_tx_state state;
1293         unsigned long flags;
1294         int count;
1295
1296         dmastat = dmaengine_tx_status(chan, sport->dma_rx_cookie, &state);
1297         if (dmastat == DMA_ERROR) {
1298                 dev_err(sport->port.dev, "Rx DMA transfer failed!\n");
1299                 return;
1300         }
1301
1302         ring->head = sport->rx_sgl.length - state.residue;
1303         count = CIRC_CNT(ring->head, ring->tail, sport->rx_sgl.length);
1304
1305         /* Check if new data received before copying */
1306         if ((count != 0) && (sport->last_residue == state.residue))
1307                 lpuart_copy_rx_to_tty(sport);
1308         else
1309                 mod_timer(&sport->lpuart_timer,
1310                           jiffies + sport->dma_rx_timeout);
1311
1312         if (spin_trylock_irqsave(&sport->port.lock, flags)) {
1313                 sport->last_residue = state.residue;
1314                 spin_unlock_irqrestore(&sport->port.lock, flags);
1315         }
1316 }
1317
1318 static inline int lpuart_start_rx_dma(struct lpuart_port *sport)
1319 {
1320         struct dma_slave_config dma_rx_sconfig = {};
1321         struct circ_buf *ring = &sport->rx_ring;
1322         int ret, nent;
1323         struct tty_port *port = &sport->port.state->port;
1324         struct tty_struct *tty = port->tty;
1325         struct ktermios *termios = &tty->termios;
1326         struct dma_chan *chan = sport->dma_rx_chan;
1327         unsigned int bits = tty_get_frame_size(termios->c_cflag);
1328         unsigned int baud = tty_get_baud_rate(tty);
1329
1330         /*
1331          * Calculate length of one DMA buffer size to keep latency below
1332          * 10ms at any baud rate.
1333          */
1334         sport->rx_dma_rng_buf_len = (DMA_RX_TIMEOUT * baud /  bits / 1000) * 2;
1335         sport->rx_dma_rng_buf_len = (1 << fls(sport->rx_dma_rng_buf_len));
1336         sport->rx_dma_rng_buf_len = max_t(int,
1337                                           sport->rxfifo_size * 2,
1338                                           sport->rx_dma_rng_buf_len);
1339         /*
1340          * Keep this condition check in case rxfifo_size is unavailable
1341          * for some SoCs.
1342          */
1343         if (sport->rx_dma_rng_buf_len < 16)
1344                 sport->rx_dma_rng_buf_len = 16;
1345
1346         sport->last_residue = 0;
1347         sport->dma_rx_timeout = max(nsecs_to_jiffies(
1348                 sport->port.frame_time * DMA_RX_IDLE_CHARS), 1UL);
1349
1350         ring->buf = kzalloc(sport->rx_dma_rng_buf_len, GFP_ATOMIC);
1351         if (!ring->buf)
1352                 return -ENOMEM;
1353
1354         sg_init_one(&sport->rx_sgl, ring->buf, sport->rx_dma_rng_buf_len);
1355         nent = dma_map_sg(chan->device->dev, &sport->rx_sgl, 1,
1356                           DMA_FROM_DEVICE);
1357
1358         if (!nent) {
1359                 dev_err(sport->port.dev, "DMA Rx mapping error\n");
1360                 return -EINVAL;
1361         }
1362
1363         dma_rx_sconfig.src_addr = lpuart_dma_datareg_addr(sport);
1364         dma_rx_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1365         dma_rx_sconfig.src_maxburst = 1;
1366         dma_rx_sconfig.direction = DMA_DEV_TO_MEM;
1367         ret = dmaengine_slave_config(chan, &dma_rx_sconfig);
1368
1369         if (ret < 0) {
1370                 dev_err(sport->port.dev,
1371                                 "DMA Rx slave config failed, err = %d\n", ret);
1372                 return ret;
1373         }
1374
1375         sport->dma_rx_desc = dmaengine_prep_dma_cyclic(chan,
1376                                  sg_dma_address(&sport->rx_sgl),
1377                                  sport->rx_sgl.length,
1378                                  sport->rx_sgl.length / 2,
1379                                  DMA_DEV_TO_MEM,
1380                                  DMA_PREP_INTERRUPT);
1381         if (!sport->dma_rx_desc) {
1382                 dev_err(sport->port.dev, "Cannot prepare cyclic DMA\n");
1383                 return -EFAULT;
1384         }
1385
1386         sport->dma_rx_desc->callback = lpuart_dma_rx_complete;
1387         sport->dma_rx_desc->callback_param = sport;
1388         sport->dma_rx_cookie = dmaengine_submit(sport->dma_rx_desc);
1389         dma_async_issue_pending(chan);
1390
1391         if (lpuart_is_32(sport)) {
1392                 unsigned long temp = lpuart32_read(&sport->port, UARTBAUD);
1393
1394                 lpuart32_write(&sport->port, temp | UARTBAUD_RDMAE, UARTBAUD);
1395         } else {
1396                 writeb(readb(sport->port.membase + UARTCR5) | UARTCR5_RDMAS,
1397                        sport->port.membase + UARTCR5);
1398         }
1399
1400         return 0;
1401 }
1402
1403 static void lpuart_dma_rx_free(struct uart_port *port)
1404 {
1405         struct lpuart_port *sport = container_of(port,
1406                                         struct lpuart_port, port);
1407         struct dma_chan *chan = sport->dma_rx_chan;
1408
1409         dmaengine_terminate_sync(chan);
1410         del_timer_sync(&sport->lpuart_timer);
1411         dma_unmap_sg(chan->device->dev, &sport->rx_sgl, 1, DMA_FROM_DEVICE);
1412         kfree(sport->rx_ring.buf);
1413         sport->rx_ring.tail = 0;
1414         sport->rx_ring.head = 0;
1415         sport->dma_rx_desc = NULL;
1416         sport->dma_rx_cookie = -EINVAL;
1417 }
1418
1419 static int lpuart_config_rs485(struct uart_port *port, struct ktermios *termios,
1420                         struct serial_rs485 *rs485)
1421 {
1422         struct lpuart_port *sport = container_of(port,
1423                         struct lpuart_port, port);
1424
1425         u8 modem = readb(sport->port.membase + UARTMODEM) &
1426                 ~(UARTMODEM_TXRTSPOL | UARTMODEM_TXRTSE);
1427         writeb(modem, sport->port.membase + UARTMODEM);
1428
1429         if (rs485->flags & SER_RS485_ENABLED) {
1430                 /* Enable auto RS-485 RTS mode */
1431                 modem |= UARTMODEM_TXRTSE;
1432
1433                 /*
1434                  * The hardware defaults to RTS logic HIGH while transfer.
1435                  * Switch polarity in case RTS shall be logic HIGH
1436                  * after transfer.
1437                  * Note: UART is assumed to be active high.
1438                  */
1439                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1440                         modem |= UARTMODEM_TXRTSPOL;
1441                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1442                         modem &= ~UARTMODEM_TXRTSPOL;
1443         }
1444
1445         writeb(modem, sport->port.membase + UARTMODEM);
1446         return 0;
1447 }
1448
1449 static int lpuart32_config_rs485(struct uart_port *port, struct ktermios *termios,
1450                         struct serial_rs485 *rs485)
1451 {
1452         struct lpuart_port *sport = container_of(port,
1453                         struct lpuart_port, port);
1454
1455         unsigned long modem = lpuart32_read(&sport->port, UARTMODIR)
1456                                 & ~(UARTMODIR_TXRTSPOL | UARTMODIR_TXRTSE);
1457         lpuart32_write(&sport->port, modem, UARTMODIR);
1458
1459         if (rs485->flags & SER_RS485_ENABLED) {
1460                 /* Enable auto RS-485 RTS mode */
1461                 modem |= UARTMODIR_TXRTSE;
1462
1463                 /*
1464                  * The hardware defaults to RTS logic HIGH while transfer.
1465                  * Switch polarity in case RTS shall be logic HIGH
1466                  * after transfer.
1467                  * Note: UART is assumed to be active high.
1468                  */
1469                 if (rs485->flags & SER_RS485_RTS_ON_SEND)
1470                         modem |= UARTMODIR_TXRTSPOL;
1471                 else if (rs485->flags & SER_RS485_RTS_AFTER_SEND)
1472                         modem &= ~UARTMODIR_TXRTSPOL;
1473         }
1474
1475         lpuart32_write(&sport->port, modem, UARTMODIR);
1476         return 0;
1477 }
1478
1479 static unsigned int lpuart_get_mctrl(struct uart_port *port)
1480 {
1481         unsigned int mctrl = 0;
1482         u8 reg;
1483
1484         reg = readb(port->membase + UARTCR1);
1485         if (reg & UARTCR1_LOOPS)
1486                 mctrl |= TIOCM_LOOP;
1487
1488         return mctrl;
1489 }
1490
1491 static unsigned int lpuart32_get_mctrl(struct uart_port *port)
1492 {
1493         unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
1494         u32 reg;
1495
1496         reg = lpuart32_read(port, UARTCTRL);
1497         if (reg & UARTCTRL_LOOPS)
1498                 mctrl |= TIOCM_LOOP;
1499
1500         return mctrl;
1501 }
1502
1503 static void lpuart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1504 {
1505         u8 reg;
1506
1507         reg = readb(port->membase + UARTCR1);
1508
1509         /* for internal loopback we need LOOPS=1 and RSRC=0 */
1510         reg &= ~(UARTCR1_LOOPS | UARTCR1_RSRC);
1511         if (mctrl & TIOCM_LOOP)
1512                 reg |= UARTCR1_LOOPS;
1513
1514         writeb(reg, port->membase + UARTCR1);
1515 }
1516
1517 static void lpuart32_set_mctrl(struct uart_port *port, unsigned int mctrl)
1518 {
1519         u32 reg;
1520
1521         reg = lpuart32_read(port, UARTCTRL);
1522
1523         /* for internal loopback we need LOOPS=1 and RSRC=0 */
1524         reg &= ~(UARTCTRL_LOOPS | UARTCTRL_RSRC);
1525         if (mctrl & TIOCM_LOOP)
1526                 reg |= UARTCTRL_LOOPS;
1527
1528         lpuart32_write(port, reg, UARTCTRL);
1529 }
1530
1531 static void lpuart_break_ctl(struct uart_port *port, int break_state)
1532 {
1533         unsigned char temp;
1534
1535         temp = readb(port->membase + UARTCR2) & ~UARTCR2_SBK;
1536
1537         if (break_state != 0)
1538                 temp |= UARTCR2_SBK;
1539
1540         writeb(temp, port->membase + UARTCR2);
1541 }
1542
1543 static void lpuart32_break_ctl(struct uart_port *port, int break_state)
1544 {
1545         unsigned long temp;
1546
1547         temp = lpuart32_read(port, UARTCTRL);
1548
1549         /*
1550          * LPUART IP now has two known bugs, one is CTS has higher priority than the
1551          * break signal, which causes the break signal sending through UARTCTRL_SBK
1552          * may impacted by the CTS input if the HW flow control is enabled. It
1553          * exists on all platforms we support in this driver.
1554          * Another bug is i.MX8QM LPUART may have an additional break character
1555          * being sent after SBK was cleared.
1556          * To avoid above two bugs, we use Transmit Data Inversion function to send
1557          * the break signal instead of UARTCTRL_SBK.
1558          */
1559         if (break_state != 0) {
1560                 /*
1561                  * Disable the transmitter to prevent any data from being sent out
1562                  * during break, then invert the TX line to send break.
1563                  */
1564                 temp &= ~UARTCTRL_TE;
1565                 lpuart32_write(port, temp, UARTCTRL);
1566                 temp |= UARTCTRL_TXINV;
1567                 lpuart32_write(port, temp, UARTCTRL);
1568         } else {
1569                 /* Disable the TXINV to turn off break and re-enable transmitter. */
1570                 temp &= ~UARTCTRL_TXINV;
1571                 lpuart32_write(port, temp, UARTCTRL);
1572                 temp |= UARTCTRL_TE;
1573                 lpuart32_write(port, temp, UARTCTRL);
1574         }
1575 }
1576
1577 static void lpuart_setup_watermark(struct lpuart_port *sport)
1578 {
1579         unsigned char val, cr2;
1580         unsigned char cr2_saved;
1581
1582         cr2 = readb(sport->port.membase + UARTCR2);
1583         cr2_saved = cr2;
1584         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_TE |
1585                         UARTCR2_RIE | UARTCR2_RE);
1586         writeb(cr2, sport->port.membase + UARTCR2);
1587
1588         val = readb(sport->port.membase + UARTPFIFO);
1589         writeb(val | UARTPFIFO_TXFE | UARTPFIFO_RXFE,
1590                         sport->port.membase + UARTPFIFO);
1591
1592         /* flush Tx and Rx FIFO */
1593         writeb(UARTCFIFO_TXFLUSH | UARTCFIFO_RXFLUSH,
1594                         sport->port.membase + UARTCFIFO);
1595
1596         /* explicitly clear RDRF */
1597         if (readb(sport->port.membase + UARTSR1) & UARTSR1_RDRF) {
1598                 readb(sport->port.membase + UARTDR);
1599                 writeb(UARTSFIFO_RXUF, sport->port.membase + UARTSFIFO);
1600         }
1601
1602         if (uart_console(&sport->port))
1603                 sport->rx_watermark = 1;
1604         writeb(0, sport->port.membase + UARTTWFIFO);
1605         writeb(sport->rx_watermark, sport->port.membase + UARTRWFIFO);
1606
1607         /* Restore cr2 */
1608         writeb(cr2_saved, sport->port.membase + UARTCR2);
1609 }
1610
1611 static void lpuart_setup_watermark_enable(struct lpuart_port *sport)
1612 {
1613         unsigned char cr2;
1614
1615         lpuart_setup_watermark(sport);
1616
1617         cr2 = readb(sport->port.membase + UARTCR2);
1618         cr2 |= UARTCR2_RIE | UARTCR2_RE | UARTCR2_TE;
1619         writeb(cr2, sport->port.membase + UARTCR2);
1620 }
1621
1622 static void lpuart32_setup_watermark(struct lpuart_port *sport)
1623 {
1624         unsigned long val, ctrl;
1625         unsigned long ctrl_saved;
1626
1627         ctrl = lpuart32_read(&sport->port, UARTCTRL);
1628         ctrl_saved = ctrl;
1629         ctrl &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_TE |
1630                         UARTCTRL_RIE | UARTCTRL_RE | UARTCTRL_ILIE);
1631         lpuart32_write(&sport->port, ctrl, UARTCTRL);
1632
1633         /* enable FIFO mode */
1634         val = lpuart32_read(&sport->port, UARTFIFO);
1635         val |= UARTFIFO_TXFE | UARTFIFO_RXFE;
1636         val |= UARTFIFO_TXFLUSH | UARTFIFO_RXFLUSH;
1637         val |= FIELD_PREP(UARTFIFO_RXIDEN, 0x3);
1638         lpuart32_write(&sport->port, val, UARTFIFO);
1639
1640         /* set the watermark */
1641         if (uart_console(&sport->port))
1642                 sport->rx_watermark = 1;
1643         val = (sport->rx_watermark << UARTWATER_RXWATER_OFF) |
1644               (0x0 << UARTWATER_TXWATER_OFF);
1645         lpuart32_write(&sport->port, val, UARTWATER);
1646
1647         /* set RTS watermark */
1648         if (!uart_console(&sport->port)) {
1649                 val = lpuart32_read(&sport->port, UARTMODIR);
1650                 val |= FIELD_PREP(UARTMODIR_RTSWATER, sport->rxfifo_size >> 1);
1651                 lpuart32_write(&sport->port, val, UARTMODIR);
1652         }
1653
1654         /* Restore cr2 */
1655         lpuart32_write(&sport->port, ctrl_saved, UARTCTRL);
1656 }
1657
1658 static void lpuart32_setup_watermark_enable(struct lpuart_port *sport)
1659 {
1660         u32 temp;
1661
1662         lpuart32_setup_watermark(sport);
1663
1664         temp = lpuart32_read(&sport->port, UARTCTRL);
1665         temp |= UARTCTRL_RE | UARTCTRL_TE;
1666         temp |= FIELD_PREP(UARTCTRL_IDLECFG, 0x7);
1667         lpuart32_write(&sport->port, temp, UARTCTRL);
1668 }
1669
1670 static void rx_dma_timer_init(struct lpuart_port *sport)
1671 {
1672         timer_setup(&sport->lpuart_timer, lpuart_timer_func, 0);
1673         sport->lpuart_timer.expires = jiffies + sport->dma_rx_timeout;
1674         add_timer(&sport->lpuart_timer);
1675 }
1676
1677 static void lpuart_request_dma(struct lpuart_port *sport)
1678 {
1679         sport->dma_tx_chan = dma_request_chan(sport->port.dev, "tx");
1680         if (IS_ERR(sport->dma_tx_chan)) {
1681                 dev_dbg_once(sport->port.dev,
1682                              "DMA tx channel request failed, operating without tx DMA (%ld)\n",
1683                              PTR_ERR(sport->dma_tx_chan));
1684                 sport->dma_tx_chan = NULL;
1685         }
1686
1687         sport->dma_rx_chan = dma_request_chan(sport->port.dev, "rx");
1688         if (IS_ERR(sport->dma_rx_chan)) {
1689                 dev_dbg_once(sport->port.dev,
1690                              "DMA rx channel request failed, operating without rx DMA (%ld)\n",
1691                              PTR_ERR(sport->dma_rx_chan));
1692                 sport->dma_rx_chan = NULL;
1693         }
1694 }
1695
1696 static void lpuart_tx_dma_startup(struct lpuart_port *sport)
1697 {
1698         u32 uartbaud;
1699         int ret;
1700
1701         if (uart_console(&sport->port))
1702                 goto err;
1703
1704         if (!sport->dma_tx_chan)
1705                 goto err;
1706
1707         ret = lpuart_dma_tx_request(&sport->port);
1708         if (ret)
1709                 goto err;
1710
1711         init_waitqueue_head(&sport->dma_wait);
1712         sport->lpuart_dma_tx_use = true;
1713         if (lpuart_is_32(sport)) {
1714                 uartbaud = lpuart32_read(&sport->port, UARTBAUD);
1715                 lpuart32_write(&sport->port,
1716                                uartbaud | UARTBAUD_TDMAE, UARTBAUD);
1717         } else {
1718                 writeb(readb(sport->port.membase + UARTCR5) |
1719                        UARTCR5_TDMAS, sport->port.membase + UARTCR5);
1720         }
1721
1722         return;
1723
1724 err:
1725         sport->lpuart_dma_tx_use = false;
1726 }
1727
1728 static void lpuart_rx_dma_startup(struct lpuart_port *sport)
1729 {
1730         int ret;
1731         unsigned char cr3;
1732
1733         if (uart_console(&sport->port))
1734                 goto err;
1735
1736         if (!sport->dma_rx_chan)
1737                 goto err;
1738
1739         /* set default Rx DMA timeout */
1740         sport->dma_rx_timeout = msecs_to_jiffies(DMA_RX_TIMEOUT);
1741
1742         ret = lpuart_start_rx_dma(sport);
1743         if (ret)
1744                 goto err;
1745
1746         if (!sport->dma_rx_timeout)
1747                 sport->dma_rx_timeout = 1;
1748
1749         sport->lpuart_dma_rx_use = true;
1750         rx_dma_timer_init(sport);
1751
1752         if (sport->port.has_sysrq && !lpuart_is_32(sport)) {
1753                 cr3 = readb(sport->port.membase + UARTCR3);
1754                 cr3 |= UARTCR3_FEIE;
1755                 writeb(cr3, sport->port.membase + UARTCR3);
1756         }
1757
1758         return;
1759
1760 err:
1761         sport->lpuart_dma_rx_use = false;
1762 }
1763
1764 static void lpuart_hw_setup(struct lpuart_port *sport)
1765 {
1766         unsigned long flags;
1767
1768         spin_lock_irqsave(&sport->port.lock, flags);
1769
1770         lpuart_setup_watermark_enable(sport);
1771
1772         lpuart_rx_dma_startup(sport);
1773         lpuart_tx_dma_startup(sport);
1774
1775         spin_unlock_irqrestore(&sport->port.lock, flags);
1776 }
1777
1778 static int lpuart_startup(struct uart_port *port)
1779 {
1780         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1781         unsigned char temp;
1782
1783         /* determine FIFO size and enable FIFO mode */
1784         temp = readb(sport->port.membase + UARTPFIFO);
1785
1786         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_TXSIZE_OFF) &
1787                                             UARTPFIFO_FIFOSIZE_MASK);
1788         sport->port.fifosize = sport->txfifo_size;
1789
1790         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTPFIFO_RXSIZE_OFF) &
1791                                             UARTPFIFO_FIFOSIZE_MASK);
1792
1793         lpuart_request_dma(sport);
1794         lpuart_hw_setup(sport);
1795
1796         return 0;
1797 }
1798
1799 static void lpuart32_hw_disable(struct lpuart_port *sport)
1800 {
1801         unsigned long temp;
1802
1803         temp = lpuart32_read(&sport->port, UARTCTRL);
1804         temp &= ~(UARTCTRL_RIE | UARTCTRL_ILIE | UARTCTRL_RE |
1805                   UARTCTRL_TIE | UARTCTRL_TE);
1806         lpuart32_write(&sport->port, temp, UARTCTRL);
1807 }
1808
1809 static void lpuart32_configure(struct lpuart_port *sport)
1810 {
1811         unsigned long temp;
1812
1813         temp = lpuart32_read(&sport->port, UARTCTRL);
1814         if (!sport->lpuart_dma_rx_use)
1815                 temp |= UARTCTRL_RIE | UARTCTRL_ILIE;
1816         if (!sport->lpuart_dma_tx_use)
1817                 temp |= UARTCTRL_TIE;
1818         lpuart32_write(&sport->port, temp, UARTCTRL);
1819 }
1820
1821 static void lpuart32_hw_setup(struct lpuart_port *sport)
1822 {
1823         unsigned long flags;
1824
1825         spin_lock_irqsave(&sport->port.lock, flags);
1826
1827         lpuart32_hw_disable(sport);
1828
1829         lpuart_rx_dma_startup(sport);
1830         lpuart_tx_dma_startup(sport);
1831
1832         lpuart32_setup_watermark_enable(sport);
1833         lpuart32_configure(sport);
1834
1835         spin_unlock_irqrestore(&sport->port.lock, flags);
1836 }
1837
1838 static int lpuart32_startup(struct uart_port *port)
1839 {
1840         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1841         unsigned long temp;
1842
1843         /* determine FIFO size */
1844         temp = lpuart32_read(&sport->port, UARTFIFO);
1845
1846         sport->txfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_TXSIZE_OFF) &
1847                                             UARTFIFO_FIFOSIZE_MASK);
1848         sport->port.fifosize = sport->txfifo_size;
1849
1850         sport->rxfifo_size = UARTFIFO_DEPTH((temp >> UARTFIFO_RXSIZE_OFF) &
1851                                             UARTFIFO_FIFOSIZE_MASK);
1852
1853         /*
1854          * The LS1021A and LS1028A have a fixed FIFO depth of 16 words.
1855          * Although they support the RX/TXSIZE fields, their encoding is
1856          * different. Eg the reference manual states 0b101 is 16 words.
1857          */
1858         if (is_layerscape_lpuart(sport)) {
1859                 sport->rxfifo_size = 16;
1860                 sport->txfifo_size = 16;
1861                 sport->port.fifosize = sport->txfifo_size;
1862         }
1863
1864         lpuart_request_dma(sport);
1865         lpuart32_hw_setup(sport);
1866
1867         return 0;
1868 }
1869
1870 static void lpuart_dma_shutdown(struct lpuart_port *sport)
1871 {
1872         if (sport->lpuart_dma_rx_use) {
1873                 lpuart_dma_rx_free(&sport->port);
1874                 sport->lpuart_dma_rx_use = false;
1875         }
1876
1877         if (sport->lpuart_dma_tx_use) {
1878                 if (wait_event_interruptible_timeout(sport->dma_wait,
1879                         !sport->dma_tx_in_progress, msecs_to_jiffies(300)) <= 0) {
1880                         sport->dma_tx_in_progress = false;
1881                         dmaengine_terminate_sync(sport->dma_tx_chan);
1882                 }
1883                 sport->lpuart_dma_tx_use = false;
1884         }
1885
1886         if (sport->dma_tx_chan)
1887                 dma_release_channel(sport->dma_tx_chan);
1888         if (sport->dma_rx_chan)
1889                 dma_release_channel(sport->dma_rx_chan);
1890 }
1891
1892 static void lpuart_shutdown(struct uart_port *port)
1893 {
1894         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1895         unsigned char temp;
1896         unsigned long flags;
1897
1898         spin_lock_irqsave(&port->lock, flags);
1899
1900         /* disable Rx/Tx and interrupts */
1901         temp = readb(port->membase + UARTCR2);
1902         temp &= ~(UARTCR2_TE | UARTCR2_RE |
1903                         UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
1904         writeb(temp, port->membase + UARTCR2);
1905
1906         spin_unlock_irqrestore(&port->lock, flags);
1907
1908         lpuart_dma_shutdown(sport);
1909 }
1910
1911 static void lpuart32_shutdown(struct uart_port *port)
1912 {
1913         struct lpuart_port *sport =
1914                 container_of(port, struct lpuart_port, port);
1915         unsigned long temp;
1916         unsigned long flags;
1917
1918         spin_lock_irqsave(&port->lock, flags);
1919
1920         /* clear status */
1921         temp = lpuart32_read(&sport->port, UARTSTAT);
1922         lpuart32_write(&sport->port, temp, UARTSTAT);
1923
1924         /* disable Rx/Tx DMA */
1925         temp = lpuart32_read(port, UARTBAUD);
1926         temp &= ~(UARTBAUD_TDMAE | UARTBAUD_RDMAE);
1927         lpuart32_write(port, temp, UARTBAUD);
1928
1929         /* disable Rx/Tx and interrupts and break condition */
1930         temp = lpuart32_read(port, UARTCTRL);
1931         temp &= ~(UARTCTRL_TE | UARTCTRL_RE | UARTCTRL_ILIE |
1932                         UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE | UARTCTRL_SBK);
1933         lpuart32_write(port, temp, UARTCTRL);
1934
1935         spin_unlock_irqrestore(&port->lock, flags);
1936
1937         lpuart_dma_shutdown(sport);
1938 }
1939
1940 static void
1941 lpuart_set_termios(struct uart_port *port, struct ktermios *termios,
1942                    const struct ktermios *old)
1943 {
1944         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
1945         unsigned long flags;
1946         unsigned char cr1, old_cr1, old_cr2, cr3, cr4, bdh, modem;
1947         unsigned int  baud;
1948         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1949         unsigned int sbr, brfa;
1950
1951         cr1 = old_cr1 = readb(sport->port.membase + UARTCR1);
1952         old_cr2 = readb(sport->port.membase + UARTCR2);
1953         cr3 = readb(sport->port.membase + UARTCR3);
1954         cr4 = readb(sport->port.membase + UARTCR4);
1955         bdh = readb(sport->port.membase + UARTBDH);
1956         modem = readb(sport->port.membase + UARTMODEM);
1957         /*
1958          * only support CS8 and CS7, and for CS7 must enable PE.
1959          * supported mode:
1960          *  - (7,e/o,1)
1961          *  - (8,n,1)
1962          *  - (8,m/s,1)
1963          *  - (8,e/o,1)
1964          */
1965         while ((termios->c_cflag & CSIZE) != CS8 &&
1966                 (termios->c_cflag & CSIZE) != CS7) {
1967                 termios->c_cflag &= ~CSIZE;
1968                 termios->c_cflag |= old_csize;
1969                 old_csize = CS8;
1970         }
1971
1972         if ((termios->c_cflag & CSIZE) == CS8 ||
1973                 (termios->c_cflag & CSIZE) == CS7)
1974                 cr1 = old_cr1 & ~UARTCR1_M;
1975
1976         if (termios->c_cflag & CMSPAR) {
1977                 if ((termios->c_cflag & CSIZE) != CS8) {
1978                         termios->c_cflag &= ~CSIZE;
1979                         termios->c_cflag |= CS8;
1980                 }
1981                 cr1 |= UARTCR1_M;
1982         }
1983
1984         /*
1985          * When auto RS-485 RTS mode is enabled,
1986          * hardware flow control need to be disabled.
1987          */
1988         if (sport->port.rs485.flags & SER_RS485_ENABLED)
1989                 termios->c_cflag &= ~CRTSCTS;
1990
1991         if (termios->c_cflag & CRTSCTS)
1992                 modem |= UARTMODEM_RXRTSE | UARTMODEM_TXCTSE;
1993         else
1994                 modem &= ~(UARTMODEM_RXRTSE | UARTMODEM_TXCTSE);
1995
1996         termios->c_cflag &= ~CSTOPB;
1997
1998         /* parity must be enabled when CS7 to match 8-bits format */
1999         if ((termios->c_cflag & CSIZE) == CS7)
2000                 termios->c_cflag |= PARENB;
2001
2002         if (termios->c_cflag & PARENB) {
2003                 if (termios->c_cflag & CMSPAR) {
2004                         cr1 &= ~UARTCR1_PE;
2005                         if (termios->c_cflag & PARODD)
2006                                 cr3 |= UARTCR3_T8;
2007                         else
2008                                 cr3 &= ~UARTCR3_T8;
2009                 } else {
2010                         cr1 |= UARTCR1_PE;
2011                         if ((termios->c_cflag & CSIZE) == CS8)
2012                                 cr1 |= UARTCR1_M;
2013                         if (termios->c_cflag & PARODD)
2014                                 cr1 |= UARTCR1_PT;
2015                         else
2016                                 cr1 &= ~UARTCR1_PT;
2017                 }
2018         } else {
2019                 cr1 &= ~UARTCR1_PE;
2020         }
2021
2022         /* ask the core to calculate the divisor */
2023         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
2024
2025         /*
2026          * Need to update the Ring buffer length according to the selected
2027          * baud rate and restart Rx DMA path.
2028          *
2029          * Since timer function acqures sport->port.lock, need to stop before
2030          * acquring same lock because otherwise del_timer_sync() can deadlock.
2031          */
2032         if (old && sport->lpuart_dma_rx_use)
2033                 lpuart_dma_rx_free(&sport->port);
2034
2035         spin_lock_irqsave(&sport->port.lock, flags);
2036
2037         sport->port.read_status_mask = 0;
2038         if (termios->c_iflag & INPCK)
2039                 sport->port.read_status_mask |= UARTSR1_FE | UARTSR1_PE;
2040         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2041                 sport->port.read_status_mask |= UARTSR1_FE;
2042
2043         /* characters to ignore */
2044         sport->port.ignore_status_mask = 0;
2045         if (termios->c_iflag & IGNPAR)
2046                 sport->port.ignore_status_mask |= UARTSR1_PE;
2047         if (termios->c_iflag & IGNBRK) {
2048                 sport->port.ignore_status_mask |= UARTSR1_FE;
2049                 /*
2050                  * if we're ignoring parity and break indicators,
2051                  * ignore overruns too (for real raw support).
2052                  */
2053                 if (termios->c_iflag & IGNPAR)
2054                         sport->port.ignore_status_mask |= UARTSR1_OR;
2055         }
2056
2057         /* update the per-port timeout */
2058         uart_update_timeout(port, termios->c_cflag, baud);
2059
2060         /* wait transmit engin complete */
2061         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2062
2063         /* disable transmit and receive */
2064         writeb(old_cr2 & ~(UARTCR2_TE | UARTCR2_RE),
2065                         sport->port.membase + UARTCR2);
2066
2067         sbr = sport->port.uartclk / (16 * baud);
2068         brfa = ((sport->port.uartclk - (16 * sbr * baud)) * 2) / baud;
2069         bdh &= ~UARTBDH_SBR_MASK;
2070         bdh |= (sbr >> 8) & 0x1F;
2071         cr4 &= ~UARTCR4_BRFA_MASK;
2072         brfa &= UARTCR4_BRFA_MASK;
2073         writeb(cr4 | brfa, sport->port.membase + UARTCR4);
2074         writeb(bdh, sport->port.membase + UARTBDH);
2075         writeb(sbr & 0xFF, sport->port.membase + UARTBDL);
2076         writeb(cr3, sport->port.membase + UARTCR3);
2077         writeb(cr1, sport->port.membase + UARTCR1);
2078         writeb(modem, sport->port.membase + UARTMODEM);
2079
2080         /* restore control register */
2081         writeb(old_cr2, sport->port.membase + UARTCR2);
2082
2083         if (old && sport->lpuart_dma_rx_use) {
2084                 if (!lpuart_start_rx_dma(sport))
2085                         rx_dma_timer_init(sport);
2086                 else
2087                         sport->lpuart_dma_rx_use = false;
2088         }
2089
2090         spin_unlock_irqrestore(&sport->port.lock, flags);
2091 }
2092
2093 static void __lpuart32_serial_setbrg(struct uart_port *port,
2094                                      unsigned int baudrate, bool use_rx_dma,
2095                                      bool use_tx_dma)
2096 {
2097         u32 sbr, osr, baud_diff, tmp_osr, tmp_sbr, tmp_diff, tmp;
2098         u32 clk = port->uartclk;
2099
2100         /*
2101          * The idea is to use the best OSR (over-sampling rate) possible.
2102          * Note, OSR is typically hard-set to 16 in other LPUART instantiations.
2103          * Loop to find the best OSR value possible, one that generates minimum
2104          * baud_diff iterate through the rest of the supported values of OSR.
2105          *
2106          * Calculation Formula:
2107          *  Baud Rate = baud clock / ((OSR+1) × SBR)
2108          */
2109         baud_diff = baudrate;
2110         osr = 0;
2111         sbr = 0;
2112
2113         for (tmp_osr = 4; tmp_osr <= 32; tmp_osr++) {
2114                 /* calculate the temporary sbr value  */
2115                 tmp_sbr = (clk / (baudrate * tmp_osr));
2116                 if (tmp_sbr == 0)
2117                         tmp_sbr = 1;
2118
2119                 /*
2120                  * calculate the baud rate difference based on the temporary
2121                  * osr and sbr values
2122                  */
2123                 tmp_diff = clk / (tmp_osr * tmp_sbr) - baudrate;
2124
2125                 /* select best values between sbr and sbr+1 */
2126                 tmp = clk / (tmp_osr * (tmp_sbr + 1));
2127                 if (tmp_diff > (baudrate - tmp)) {
2128                         tmp_diff = baudrate - tmp;
2129                         tmp_sbr++;
2130                 }
2131
2132                 if (tmp_sbr > UARTBAUD_SBR_MASK)
2133                         continue;
2134
2135                 if (tmp_diff <= baud_diff) {
2136                         baud_diff = tmp_diff;
2137                         osr = tmp_osr;
2138                         sbr = tmp_sbr;
2139
2140                         if (!baud_diff)
2141                                 break;
2142                 }
2143         }
2144
2145         /* handle buadrate outside acceptable rate */
2146         if (baud_diff > ((baudrate / 100) * 3))
2147                 dev_warn(port->dev,
2148                          "unacceptable baud rate difference of more than 3%%\n");
2149
2150         tmp = lpuart32_read(port, UARTBAUD);
2151
2152         if ((osr > 3) && (osr < 8))
2153                 tmp |= UARTBAUD_BOTHEDGE;
2154
2155         tmp &= ~(UARTBAUD_OSR_MASK << UARTBAUD_OSR_SHIFT);
2156         tmp |= ((osr-1) & UARTBAUD_OSR_MASK) << UARTBAUD_OSR_SHIFT;
2157
2158         tmp &= ~UARTBAUD_SBR_MASK;
2159         tmp |= sbr & UARTBAUD_SBR_MASK;
2160
2161         if (!use_rx_dma)
2162                 tmp &= ~UARTBAUD_RDMAE;
2163         if (!use_tx_dma)
2164                 tmp &= ~UARTBAUD_TDMAE;
2165
2166         lpuart32_write(port, tmp, UARTBAUD);
2167 }
2168
2169 static void lpuart32_serial_setbrg(struct lpuart_port *sport,
2170                                    unsigned int baudrate)
2171 {
2172         __lpuart32_serial_setbrg(&sport->port, baudrate,
2173                                  sport->lpuart_dma_rx_use,
2174                                  sport->lpuart_dma_tx_use);
2175 }
2176
2177
2178 static void
2179 lpuart32_set_termios(struct uart_port *port, struct ktermios *termios,
2180                      const struct ktermios *old)
2181 {
2182         struct lpuart_port *sport = container_of(port, struct lpuart_port, port);
2183         unsigned long flags;
2184         unsigned long ctrl, old_ctrl, bd, modem;
2185         unsigned int  baud;
2186         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
2187
2188         ctrl = old_ctrl = lpuart32_read(&sport->port, UARTCTRL);
2189         bd = lpuart32_read(&sport->port, UARTBAUD);
2190         modem = lpuart32_read(&sport->port, UARTMODIR);
2191         sport->is_cs7 = false;
2192         /*
2193          * only support CS8 and CS7, and for CS7 must enable PE.
2194          * supported mode:
2195          *  - (7,e/o,1)
2196          *  - (8,n,1)
2197          *  - (8,m/s,1)
2198          *  - (8,e/o,1)
2199          */
2200         while ((termios->c_cflag & CSIZE) != CS8 &&
2201                 (termios->c_cflag & CSIZE) != CS7) {
2202                 termios->c_cflag &= ~CSIZE;
2203                 termios->c_cflag |= old_csize;
2204                 old_csize = CS8;
2205         }
2206
2207         if ((termios->c_cflag & CSIZE) == CS8 ||
2208                 (termios->c_cflag & CSIZE) == CS7)
2209                 ctrl = old_ctrl & ~UARTCTRL_M;
2210
2211         if (termios->c_cflag & CMSPAR) {
2212                 if ((termios->c_cflag & CSIZE) != CS8) {
2213                         termios->c_cflag &= ~CSIZE;
2214                         termios->c_cflag |= CS8;
2215                 }
2216                 ctrl |= UARTCTRL_M;
2217         }
2218
2219         /*
2220          * When auto RS-485 RTS mode is enabled,
2221          * hardware flow control need to be disabled.
2222          */
2223         if (sport->port.rs485.flags & SER_RS485_ENABLED)
2224                 termios->c_cflag &= ~CRTSCTS;
2225
2226         if (termios->c_cflag & CRTSCTS)
2227                 modem |= UARTMODIR_RXRTSE | UARTMODIR_TXCTSE;
2228         else
2229                 modem &= ~(UARTMODIR_RXRTSE | UARTMODIR_TXCTSE);
2230
2231         if (termios->c_cflag & CSTOPB)
2232                 bd |= UARTBAUD_SBNS;
2233         else
2234                 bd &= ~UARTBAUD_SBNS;
2235
2236         /* parity must be enabled when CS7 to match 8-bits format */
2237         if ((termios->c_cflag & CSIZE) == CS7)
2238                 termios->c_cflag |= PARENB;
2239
2240         if ((termios->c_cflag & PARENB)) {
2241                 if (termios->c_cflag & CMSPAR) {
2242                         ctrl &= ~UARTCTRL_PE;
2243                         ctrl |= UARTCTRL_M;
2244                 } else {
2245                         ctrl |= UARTCTRL_PE;
2246                         if ((termios->c_cflag & CSIZE) == CS8)
2247                                 ctrl |= UARTCTRL_M;
2248                         if (termios->c_cflag & PARODD)
2249                                 ctrl |= UARTCTRL_PT;
2250                         else
2251                                 ctrl &= ~UARTCTRL_PT;
2252                 }
2253         } else {
2254                 ctrl &= ~UARTCTRL_PE;
2255         }
2256
2257         /* ask the core to calculate the divisor */
2258         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 4);
2259
2260         /*
2261          * Need to update the Ring buffer length according to the selected
2262          * baud rate and restart Rx DMA path.
2263          *
2264          * Since timer function acqures sport->port.lock, need to stop before
2265          * acquring same lock because otherwise del_timer_sync() can deadlock.
2266          */
2267         if (old && sport->lpuart_dma_rx_use)
2268                 lpuart_dma_rx_free(&sport->port);
2269
2270         spin_lock_irqsave(&sport->port.lock, flags);
2271
2272         sport->port.read_status_mask = 0;
2273         if (termios->c_iflag & INPCK)
2274                 sport->port.read_status_mask |= UARTSTAT_FE | UARTSTAT_PE;
2275         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2276                 sport->port.read_status_mask |= UARTSTAT_FE;
2277
2278         /* characters to ignore */
2279         sport->port.ignore_status_mask = 0;
2280         if (termios->c_iflag & IGNPAR)
2281                 sport->port.ignore_status_mask |= UARTSTAT_PE;
2282         if (termios->c_iflag & IGNBRK) {
2283                 sport->port.ignore_status_mask |= UARTSTAT_FE;
2284                 /*
2285                  * if we're ignoring parity and break indicators,
2286                  * ignore overruns too (for real raw support).
2287                  */
2288                 if (termios->c_iflag & IGNPAR)
2289                         sport->port.ignore_status_mask |= UARTSTAT_OR;
2290         }
2291
2292         /* update the per-port timeout */
2293         uart_update_timeout(port, termios->c_cflag, baud);
2294
2295         /*
2296          * LPUART Transmission Complete Flag may never be set while queuing a break
2297          * character, so skip waiting for transmission complete when UARTCTRL_SBK is
2298          * asserted.
2299          */
2300         if (!(old_ctrl & UARTCTRL_SBK)) {
2301                 lpuart32_write(&sport->port, 0, UARTMODIR);
2302                 lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2303         }
2304
2305         /* disable transmit and receive */
2306         lpuart32_write(&sport->port, old_ctrl & ~(UARTCTRL_TE | UARTCTRL_RE),
2307                        UARTCTRL);
2308
2309         lpuart32_write(&sport->port, bd, UARTBAUD);
2310         lpuart32_serial_setbrg(sport, baud);
2311         lpuart32_write(&sport->port, modem, UARTMODIR);
2312         lpuart32_write(&sport->port, ctrl, UARTCTRL);
2313         /* restore control register */
2314
2315         if ((ctrl & (UARTCTRL_PE | UARTCTRL_M)) == UARTCTRL_PE)
2316                 sport->is_cs7 = true;
2317
2318         if (old && sport->lpuart_dma_rx_use) {
2319                 if (!lpuart_start_rx_dma(sport))
2320                         rx_dma_timer_init(sport);
2321                 else
2322                         sport->lpuart_dma_rx_use = false;
2323         }
2324
2325         spin_unlock_irqrestore(&sport->port.lock, flags);
2326 }
2327
2328 static const char *lpuart_type(struct uart_port *port)
2329 {
2330         return "FSL_LPUART";
2331 }
2332
2333 static void lpuart_release_port(struct uart_port *port)
2334 {
2335         /* nothing to do */
2336 }
2337
2338 static int lpuart_request_port(struct uart_port *port)
2339 {
2340         return  0;
2341 }
2342
2343 /* configure/autoconfigure the port */
2344 static void lpuart_config_port(struct uart_port *port, int flags)
2345 {
2346         if (flags & UART_CONFIG_TYPE)
2347                 port->type = PORT_LPUART;
2348 }
2349
2350 static int lpuart_verify_port(struct uart_port *port, struct serial_struct *ser)
2351 {
2352         int ret = 0;
2353
2354         if (ser->type != PORT_UNKNOWN && ser->type != PORT_LPUART)
2355                 ret = -EINVAL;
2356         if (port->irq != ser->irq)
2357                 ret = -EINVAL;
2358         if (ser->io_type != UPIO_MEM)
2359                 ret = -EINVAL;
2360         if (port->uartclk / 16 != ser->baud_base)
2361                 ret = -EINVAL;
2362         if (port->iobase != ser->port)
2363                 ret = -EINVAL;
2364         if (ser->hub6 != 0)
2365                 ret = -EINVAL;
2366         return ret;
2367 }
2368
2369 static const struct uart_ops lpuart_pops = {
2370         .tx_empty       = lpuart_tx_empty,
2371         .set_mctrl      = lpuart_set_mctrl,
2372         .get_mctrl      = lpuart_get_mctrl,
2373         .stop_tx        = lpuart_stop_tx,
2374         .start_tx       = lpuart_start_tx,
2375         .stop_rx        = lpuart_stop_rx,
2376         .break_ctl      = lpuart_break_ctl,
2377         .startup        = lpuart_startup,
2378         .shutdown       = lpuart_shutdown,
2379         .set_termios    = lpuart_set_termios,
2380         .pm             = lpuart_uart_pm,
2381         .type           = lpuart_type,
2382         .request_port   = lpuart_request_port,
2383         .release_port   = lpuart_release_port,
2384         .config_port    = lpuart_config_port,
2385         .verify_port    = lpuart_verify_port,
2386         .flush_buffer   = lpuart_flush_buffer,
2387 #if defined(CONFIG_CONSOLE_POLL)
2388         .poll_init      = lpuart_poll_init,
2389         .poll_get_char  = lpuart_poll_get_char,
2390         .poll_put_char  = lpuart_poll_put_char,
2391 #endif
2392 };
2393
2394 static const struct uart_ops lpuart32_pops = {
2395         .tx_empty       = lpuart32_tx_empty,
2396         .set_mctrl      = lpuart32_set_mctrl,
2397         .get_mctrl      = lpuart32_get_mctrl,
2398         .stop_tx        = lpuart32_stop_tx,
2399         .start_tx       = lpuart32_start_tx,
2400         .stop_rx        = lpuart32_stop_rx,
2401         .break_ctl      = lpuart32_break_ctl,
2402         .startup        = lpuart32_startup,
2403         .shutdown       = lpuart32_shutdown,
2404         .set_termios    = lpuart32_set_termios,
2405         .pm             = lpuart_uart_pm,
2406         .type           = lpuart_type,
2407         .request_port   = lpuart_request_port,
2408         .release_port   = lpuart_release_port,
2409         .config_port    = lpuart_config_port,
2410         .verify_port    = lpuart_verify_port,
2411         .flush_buffer   = lpuart_flush_buffer,
2412 #if defined(CONFIG_CONSOLE_POLL)
2413         .poll_init      = lpuart32_poll_init,
2414         .poll_get_char  = lpuart32_poll_get_char,
2415         .poll_put_char  = lpuart32_poll_put_char,
2416 #endif
2417 };
2418
2419 static struct lpuart_port *lpuart_ports[UART_NR];
2420
2421 #ifdef CONFIG_SERIAL_FSL_LPUART_CONSOLE
2422 static void lpuart_console_putchar(struct uart_port *port, unsigned char ch)
2423 {
2424         lpuart_wait_bit_set(port, UARTSR1, UARTSR1_TDRE);
2425         writeb(ch, port->membase + UARTDR);
2426 }
2427
2428 static void lpuart32_console_putchar(struct uart_port *port, unsigned char ch)
2429 {
2430         lpuart32_wait_bit_set(port, UARTSTAT, UARTSTAT_TDRE);
2431         lpuart32_write(port, ch, UARTDATA);
2432 }
2433
2434 static void
2435 lpuart_console_write(struct console *co, const char *s, unsigned int count)
2436 {
2437         struct lpuart_port *sport = lpuart_ports[co->index];
2438         unsigned char  old_cr2, cr2;
2439         unsigned long flags;
2440         int locked = 1;
2441
2442         if (oops_in_progress)
2443                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2444         else
2445                 spin_lock_irqsave(&sport->port.lock, flags);
2446
2447         /* first save CR2 and then disable interrupts */
2448         cr2 = old_cr2 = readb(sport->port.membase + UARTCR2);
2449         cr2 |= UARTCR2_TE | UARTCR2_RE;
2450         cr2 &= ~(UARTCR2_TIE | UARTCR2_TCIE | UARTCR2_RIE);
2451         writeb(cr2, sport->port.membase + UARTCR2);
2452
2453         uart_console_write(&sport->port, s, count, lpuart_console_putchar);
2454
2455         /* wait for transmitter finish complete and restore CR2 */
2456         lpuart_wait_bit_set(&sport->port, UARTSR1, UARTSR1_TC);
2457
2458         writeb(old_cr2, sport->port.membase + UARTCR2);
2459
2460         if (locked)
2461                 spin_unlock_irqrestore(&sport->port.lock, flags);
2462 }
2463
2464 static void
2465 lpuart32_console_write(struct console *co, const char *s, unsigned int count)
2466 {
2467         struct lpuart_port *sport = lpuart_ports[co->index];
2468         unsigned long  old_cr, cr;
2469         unsigned long flags;
2470         int locked = 1;
2471
2472         if (oops_in_progress)
2473                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2474         else
2475                 spin_lock_irqsave(&sport->port.lock, flags);
2476
2477         /* first save CR2 and then disable interrupts */
2478         cr = old_cr = lpuart32_read(&sport->port, UARTCTRL);
2479         cr |= UARTCTRL_TE | UARTCTRL_RE;
2480         cr &= ~(UARTCTRL_TIE | UARTCTRL_TCIE | UARTCTRL_RIE);
2481         lpuart32_write(&sport->port, cr, UARTCTRL);
2482
2483         uart_console_write(&sport->port, s, count, lpuart32_console_putchar);
2484
2485         /* wait for transmitter finish complete and restore CR2 */
2486         lpuart32_wait_bit_set(&sport->port, UARTSTAT, UARTSTAT_TC);
2487
2488         lpuart32_write(&sport->port, old_cr, UARTCTRL);
2489
2490         if (locked)
2491                 spin_unlock_irqrestore(&sport->port.lock, flags);
2492 }
2493
2494 /*
2495  * if the port was already initialised (eg, by a boot loader),
2496  * try to determine the current setup.
2497  */
2498 static void __init
2499 lpuart_console_get_options(struct lpuart_port *sport, int *baud,
2500                            int *parity, int *bits)
2501 {
2502         unsigned char cr, bdh, bdl, brfa;
2503         unsigned int sbr, uartclk, baud_raw;
2504
2505         cr = readb(sport->port.membase + UARTCR2);
2506         cr &= UARTCR2_TE | UARTCR2_RE;
2507         if (!cr)
2508                 return;
2509
2510         /* ok, the port was enabled */
2511
2512         cr = readb(sport->port.membase + UARTCR1);
2513
2514         *parity = 'n';
2515         if (cr & UARTCR1_PE) {
2516                 if (cr & UARTCR1_PT)
2517                         *parity = 'o';
2518                 else
2519                         *parity = 'e';
2520         }
2521
2522         if (cr & UARTCR1_M)
2523                 *bits = 9;
2524         else
2525                 *bits = 8;
2526
2527         bdh = readb(sport->port.membase + UARTBDH);
2528         bdh &= UARTBDH_SBR_MASK;
2529         bdl = readb(sport->port.membase + UARTBDL);
2530         sbr = bdh;
2531         sbr <<= 8;
2532         sbr |= bdl;
2533         brfa = readb(sport->port.membase + UARTCR4);
2534         brfa &= UARTCR4_BRFA_MASK;
2535
2536         uartclk = lpuart_get_baud_clk_rate(sport);
2537         /*
2538          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2539          */
2540         baud_raw = uartclk / (16 * (sbr + brfa / 32));
2541
2542         if (*baud != baud_raw)
2543                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2544                                 "from %d to %d\n", baud_raw, *baud);
2545 }
2546
2547 static void __init
2548 lpuart32_console_get_options(struct lpuart_port *sport, int *baud,
2549                            int *parity, int *bits)
2550 {
2551         unsigned long cr, bd;
2552         unsigned int sbr, uartclk, baud_raw;
2553
2554         cr = lpuart32_read(&sport->port, UARTCTRL);
2555         cr &= UARTCTRL_TE | UARTCTRL_RE;
2556         if (!cr)
2557                 return;
2558
2559         /* ok, the port was enabled */
2560
2561         cr = lpuart32_read(&sport->port, UARTCTRL);
2562
2563         *parity = 'n';
2564         if (cr & UARTCTRL_PE) {
2565                 if (cr & UARTCTRL_PT)
2566                         *parity = 'o';
2567                 else
2568                         *parity = 'e';
2569         }
2570
2571         if (cr & UARTCTRL_M)
2572                 *bits = 9;
2573         else
2574                 *bits = 8;
2575
2576         bd = lpuart32_read(&sport->port, UARTBAUD);
2577         bd &= UARTBAUD_SBR_MASK;
2578         if (!bd)
2579                 return;
2580
2581         sbr = bd;
2582         uartclk = lpuart_get_baud_clk_rate(sport);
2583         /*
2584          * baud = mod_clk/(16*(sbr[13]+(brfa)/32)
2585          */
2586         baud_raw = uartclk / (16 * sbr);
2587
2588         if (*baud != baud_raw)
2589                 dev_info(sport->port.dev, "Serial: Console lpuart rounded baud rate"
2590                                 "from %d to %d\n", baud_raw, *baud);
2591 }
2592
2593 static int __init lpuart_console_setup(struct console *co, char *options)
2594 {
2595         struct lpuart_port *sport;
2596         int baud = 115200;
2597         int bits = 8;
2598         int parity = 'n';
2599         int flow = 'n';
2600
2601         /*
2602          * check whether an invalid uart number has been specified, and
2603          * if so, search for the first available port that does have
2604          * console support.
2605          */
2606         if (co->index == -1 || co->index >= ARRAY_SIZE(lpuart_ports))
2607                 co->index = 0;
2608
2609         sport = lpuart_ports[co->index];
2610         if (sport == NULL)
2611                 return -ENODEV;
2612
2613         if (options)
2614                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2615         else
2616                 if (lpuart_is_32(sport))
2617                         lpuart32_console_get_options(sport, &baud, &parity, &bits);
2618                 else
2619                         lpuart_console_get_options(sport, &baud, &parity, &bits);
2620
2621         if (lpuart_is_32(sport))
2622                 lpuart32_setup_watermark(sport);
2623         else
2624                 lpuart_setup_watermark(sport);
2625
2626         return uart_set_options(&sport->port, co, baud, parity, bits, flow);
2627 }
2628
2629 static struct uart_driver lpuart_reg;
2630 static struct console lpuart_console = {
2631         .name           = DEV_NAME,
2632         .write          = lpuart_console_write,
2633         .device         = uart_console_device,
2634         .setup          = lpuart_console_setup,
2635         .flags          = CON_PRINTBUFFER,
2636         .index          = -1,
2637         .data           = &lpuart_reg,
2638 };
2639
2640 static struct console lpuart32_console = {
2641         .name           = DEV_NAME,
2642         .write          = lpuart32_console_write,
2643         .device         = uart_console_device,
2644         .setup          = lpuart_console_setup,
2645         .flags          = CON_PRINTBUFFER,
2646         .index          = -1,
2647         .data           = &lpuart_reg,
2648 };
2649
2650 static void lpuart_early_write(struct console *con, const char *s, unsigned n)
2651 {
2652         struct earlycon_device *dev = con->data;
2653
2654         uart_console_write(&dev->port, s, n, lpuart_console_putchar);
2655 }
2656
2657 static void lpuart32_early_write(struct console *con, const char *s, unsigned n)
2658 {
2659         struct earlycon_device *dev = con->data;
2660
2661         uart_console_write(&dev->port, s, n, lpuart32_console_putchar);
2662 }
2663
2664 static int __init lpuart_early_console_setup(struct earlycon_device *device,
2665                                           const char *opt)
2666 {
2667         if (!device->port.membase)
2668                 return -ENODEV;
2669
2670         device->con->write = lpuart_early_write;
2671         return 0;
2672 }
2673
2674 static int __init lpuart32_early_console_setup(struct earlycon_device *device,
2675                                           const char *opt)
2676 {
2677         if (!device->port.membase)
2678                 return -ENODEV;
2679
2680         if (device->port.iotype != UPIO_MEM32)
2681                 device->port.iotype = UPIO_MEM32BE;
2682
2683         device->con->write = lpuart32_early_write;
2684         return 0;
2685 }
2686
2687 static int __init ls1028a_early_console_setup(struct earlycon_device *device,
2688                                               const char *opt)
2689 {
2690         u32 cr;
2691
2692         if (!device->port.membase)
2693                 return -ENODEV;
2694
2695         device->port.iotype = UPIO_MEM32;
2696         device->con->write = lpuart32_early_write;
2697
2698         /* set the baudrate */
2699         if (device->port.uartclk && device->baud)
2700                 __lpuart32_serial_setbrg(&device->port, device->baud,
2701                                          false, false);
2702
2703         /* enable transmitter */
2704         cr = lpuart32_read(&device->port, UARTCTRL);
2705         cr |= UARTCTRL_TE;
2706         lpuart32_write(&device->port, cr, UARTCTRL);
2707
2708         return 0;
2709 }
2710
2711 static int __init lpuart32_imx_early_console_setup(struct earlycon_device *device,
2712                                                    const char *opt)
2713 {
2714         if (!device->port.membase)
2715                 return -ENODEV;
2716
2717         device->port.iotype = UPIO_MEM32;
2718         device->port.membase += IMX_REG_OFF;
2719         device->con->write = lpuart32_early_write;
2720
2721         return 0;
2722 }
2723 OF_EARLYCON_DECLARE(lpuart, "fsl,vf610-lpuart", lpuart_early_console_setup);
2724 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1021a-lpuart", lpuart32_early_console_setup);
2725 OF_EARLYCON_DECLARE(lpuart32, "fsl,ls1028a-lpuart", ls1028a_early_console_setup);
2726 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx7ulp-lpuart", lpuart32_imx_early_console_setup);
2727 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8ulp-lpuart", lpuart32_imx_early_console_setup);
2728 OF_EARLYCON_DECLARE(lpuart32, "fsl,imx8qxp-lpuart", lpuart32_imx_early_console_setup);
2729 OF_EARLYCON_DECLARE(lpuart32, "fsl,imxrt1050-lpuart", lpuart32_imx_early_console_setup);
2730 EARLYCON_DECLARE(lpuart, lpuart_early_console_setup);
2731 EARLYCON_DECLARE(lpuart32, lpuart32_early_console_setup);
2732
2733 #define LPUART_CONSOLE  (&lpuart_console)
2734 #define LPUART32_CONSOLE        (&lpuart32_console)
2735 #else
2736 #define LPUART_CONSOLE  NULL
2737 #define LPUART32_CONSOLE        NULL
2738 #endif
2739
2740 static struct uart_driver lpuart_reg = {
2741         .owner          = THIS_MODULE,
2742         .driver_name    = DRIVER_NAME,
2743         .dev_name       = DEV_NAME,
2744         .nr             = ARRAY_SIZE(lpuart_ports),
2745         .cons           = LPUART_CONSOLE,
2746 };
2747
2748 static const struct serial_rs485 lpuart_rs485_supported = {
2749         .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND,
2750         /* delay_rts_* and RX_DURING_TX are not supported */
2751 };
2752
2753 static int lpuart_global_reset(struct lpuart_port *sport)
2754 {
2755         struct uart_port *port = &sport->port;
2756         void __iomem *global_addr;
2757         unsigned long ctrl, bd;
2758         unsigned int val = 0;
2759         int ret;
2760
2761         ret = clk_prepare_enable(sport->ipg_clk);
2762         if (ret) {
2763                 dev_err(sport->port.dev, "failed to enable uart ipg clk: %d\n", ret);
2764                 return ret;
2765         }
2766
2767         if (is_imx7ulp_lpuart(sport) || is_imx8ulp_lpuart(sport) || is_imx8qxp_lpuart(sport)) {
2768                 /*
2769                  * If the transmitter is used by earlycon, wait for transmit engine to
2770                  * complete and then reset.
2771                  */
2772                 ctrl = lpuart32_read(port, UARTCTRL);
2773                 if (ctrl & UARTCTRL_TE) {
2774                         bd = lpuart32_read(&sport->port, UARTBAUD);
2775                         if (read_poll_timeout(lpuart32_tx_empty, val, val, 1, 100000, false,
2776                                               port)) {
2777                                 dev_warn(sport->port.dev,
2778                                          "timeout waiting for transmit engine to complete\n");
2779                                 clk_disable_unprepare(sport->ipg_clk);
2780                                 return 0;
2781                         }
2782                 }
2783
2784                 global_addr = port->membase + UART_GLOBAL - IMX_REG_OFF;
2785                 writel(UART_GLOBAL_RST, global_addr);
2786                 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
2787                 writel(0, global_addr);
2788                 usleep_range(GLOBAL_RST_MIN_US, GLOBAL_RST_MAX_US);
2789
2790                 /* Recover the transmitter for earlycon. */
2791                 if (ctrl & UARTCTRL_TE) {
2792                         lpuart32_write(port, bd, UARTBAUD);
2793                         lpuart32_write(port, ctrl, UARTCTRL);
2794                 }
2795         }
2796
2797         clk_disable_unprepare(sport->ipg_clk);
2798         return 0;
2799 }
2800
2801 static int lpuart_probe(struct platform_device *pdev)
2802 {
2803         const struct lpuart_soc_data *sdata = of_device_get_match_data(&pdev->dev);
2804         struct device_node *np = pdev->dev.of_node;
2805         struct lpuart_port *sport;
2806         struct resource *res;
2807         irq_handler_t handler;
2808         int ret;
2809
2810         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2811         if (!sport)
2812                 return -ENOMEM;
2813
2814         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2815         sport->port.membase = devm_ioremap_resource(&pdev->dev, res);
2816         if (IS_ERR(sport->port.membase))
2817                 return PTR_ERR(sport->port.membase);
2818
2819         sport->port.membase += sdata->reg_off;
2820         sport->port.mapbase = res->start + sdata->reg_off;
2821         sport->port.dev = &pdev->dev;
2822         sport->port.type = PORT_LPUART;
2823         sport->devtype = sdata->devtype;
2824         sport->rx_watermark = sdata->rx_watermark;
2825         ret = platform_get_irq(pdev, 0);
2826         if (ret < 0)
2827                 return ret;
2828         sport->port.irq = ret;
2829         sport->port.iotype = sdata->iotype;
2830         if (lpuart_is_32(sport))
2831                 sport->port.ops = &lpuart32_pops;
2832         else
2833                 sport->port.ops = &lpuart_pops;
2834         sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_FSL_LPUART_CONSOLE);
2835         sport->port.flags = UPF_BOOT_AUTOCONF;
2836
2837         if (lpuart_is_32(sport))
2838                 sport->port.rs485_config = lpuart32_config_rs485;
2839         else
2840                 sport->port.rs485_config = lpuart_config_rs485;
2841         sport->port.rs485_supported = lpuart_rs485_supported;
2842
2843         sport->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
2844         if (IS_ERR(sport->ipg_clk)) {
2845                 ret = PTR_ERR(sport->ipg_clk);
2846                 dev_err(&pdev->dev, "failed to get uart ipg clk: %d\n", ret);
2847                 return ret;
2848         }
2849
2850         sport->baud_clk = NULL;
2851         if (is_imx8qxp_lpuart(sport)) {
2852                 sport->baud_clk = devm_clk_get(&pdev->dev, "baud");
2853                 if (IS_ERR(sport->baud_clk)) {
2854                         ret = PTR_ERR(sport->baud_clk);
2855                         dev_err(&pdev->dev, "failed to get uart baud clk: %d\n", ret);
2856                         return ret;
2857                 }
2858         }
2859
2860         ret = of_alias_get_id(np, "serial");
2861         if (ret < 0) {
2862                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2863                 return ret;
2864         }
2865         if (ret >= ARRAY_SIZE(lpuart_ports)) {
2866                 dev_err(&pdev->dev, "serial%d out of range\n", ret);
2867                 return -EINVAL;
2868         }
2869         sport->port.line = ret;
2870
2871         ret = lpuart_enable_clks(sport);
2872         if (ret)
2873                 return ret;
2874         sport->port.uartclk = lpuart_get_baud_clk_rate(sport);
2875
2876         lpuart_ports[sport->port.line] = sport;
2877
2878         platform_set_drvdata(pdev, &sport->port);
2879
2880         if (lpuart_is_32(sport)) {
2881                 lpuart_reg.cons = LPUART32_CONSOLE;
2882                 handler = lpuart32_int;
2883         } else {
2884                 lpuart_reg.cons = LPUART_CONSOLE;
2885                 handler = lpuart_int;
2886         }
2887
2888         pm_runtime_use_autosuspend(&pdev->dev);
2889         pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
2890         pm_runtime_set_active(&pdev->dev);
2891         pm_runtime_enable(&pdev->dev);
2892
2893         ret = lpuart_global_reset(sport);
2894         if (ret)
2895                 goto failed_reset;
2896
2897         ret = uart_get_rs485_mode(&sport->port);
2898         if (ret)
2899                 goto failed_get_rs485;
2900
2901         ret = uart_add_one_port(&lpuart_reg, &sport->port);
2902         if (ret)
2903                 goto failed_attach_port;
2904
2905         ret = devm_request_irq(&pdev->dev, sport->port.irq, handler, 0,
2906                                 DRIVER_NAME, sport);
2907         if (ret)
2908                 goto failed_irq_request;
2909
2910         return 0;
2911
2912 failed_irq_request:
2913         uart_remove_one_port(&lpuart_reg, &sport->port);
2914 failed_attach_port:
2915 failed_get_rs485:
2916 failed_reset:
2917         pm_runtime_disable(&pdev->dev);
2918         pm_runtime_set_suspended(&pdev->dev);
2919         pm_runtime_dont_use_autosuspend(&pdev->dev);
2920         lpuart_disable_clks(sport);
2921         return ret;
2922 }
2923
2924 static int lpuart_remove(struct platform_device *pdev)
2925 {
2926         struct lpuart_port *sport = platform_get_drvdata(pdev);
2927
2928         uart_remove_one_port(&lpuart_reg, &sport->port);
2929
2930         lpuart_disable_clks(sport);
2931
2932         if (sport->dma_tx_chan)
2933                 dma_release_channel(sport->dma_tx_chan);
2934
2935         if (sport->dma_rx_chan)
2936                 dma_release_channel(sport->dma_rx_chan);
2937
2938         pm_runtime_disable(&pdev->dev);
2939         pm_runtime_set_suspended(&pdev->dev);
2940         pm_runtime_dont_use_autosuspend(&pdev->dev);
2941         return 0;
2942 }
2943
2944 static int lpuart_runtime_suspend(struct device *dev)
2945 {
2946         struct platform_device *pdev = to_platform_device(dev);
2947         struct lpuart_port *sport = platform_get_drvdata(pdev);
2948
2949         lpuart_disable_clks(sport);
2950
2951         return 0;
2952 };
2953
2954 static int lpuart_runtime_resume(struct device *dev)
2955 {
2956         struct platform_device *pdev = to_platform_device(dev);
2957         struct lpuart_port *sport = platform_get_drvdata(pdev);
2958
2959         return lpuart_enable_clks(sport);
2960 };
2961
2962 static void serial_lpuart_enable_wakeup(struct lpuart_port *sport, bool on)
2963 {
2964         unsigned int val, baud;
2965
2966         if (lpuart_is_32(sport)) {
2967                 val = lpuart32_read(&sport->port, UARTCTRL);
2968                 baud = lpuart32_read(&sport->port, UARTBAUD);
2969                 if (on) {
2970                         /* set rx_watermark to 0 in wakeup source mode */
2971                         lpuart32_write(&sport->port, 0, UARTWATER);
2972                         val |= UARTCTRL_RIE;
2973                         /* clear RXEDGIF flag before enable RXEDGIE interrupt */
2974                         lpuart32_write(&sport->port, UARTSTAT_RXEDGIF, UARTSTAT);
2975                         baud |= UARTBAUD_RXEDGIE;
2976                 } else {
2977                         val &= ~UARTCTRL_RIE;
2978                         baud &= ~UARTBAUD_RXEDGIE;
2979                 }
2980                 lpuart32_write(&sport->port, val, UARTCTRL);
2981                 lpuart32_write(&sport->port, baud, UARTBAUD);
2982         } else {
2983                 val = readb(sport->port.membase + UARTCR2);
2984                 if (on)
2985                         val |= UARTCR2_RIE;
2986                 else
2987                         val &= ~UARTCR2_RIE;
2988                 writeb(val, sport->port.membase + UARTCR2);
2989         }
2990 }
2991
2992 static bool lpuart_uport_is_active(struct lpuart_port *sport)
2993 {
2994         struct tty_port *port = &sport->port.state->port;
2995         struct tty_struct *tty;
2996         struct device *tty_dev;
2997         int may_wake = 0;
2998
2999         tty = tty_port_tty_get(port);
3000         if (tty) {
3001                 tty_dev = tty->dev;
3002                 may_wake = tty_dev && device_may_wakeup(tty_dev);
3003                 tty_kref_put(tty);
3004         }
3005
3006         if ((tty_port_initialized(port) && may_wake) ||
3007             (!console_suspend_enabled && uart_console(&sport->port)))
3008                 return true;
3009
3010         return false;
3011 }
3012
3013 static int lpuart_suspend_noirq(struct device *dev)
3014 {
3015         struct lpuart_port *sport = dev_get_drvdata(dev);
3016         bool irq_wake = irqd_is_wakeup_set(irq_get_irq_data(sport->port.irq));
3017
3018         if (lpuart_uport_is_active(sport))
3019                 serial_lpuart_enable_wakeup(sport, !!irq_wake);
3020
3021         pinctrl_pm_select_sleep_state(dev);
3022
3023         return 0;
3024 }
3025
3026 static int lpuart_resume_noirq(struct device *dev)
3027 {
3028         struct lpuart_port *sport = dev_get_drvdata(dev);
3029         unsigned int val;
3030
3031         pinctrl_pm_select_default_state(dev);
3032
3033         if (lpuart_uport_is_active(sport)) {
3034                 serial_lpuart_enable_wakeup(sport, false);
3035
3036                 /* clear the wakeup flags */
3037                 if (lpuart_is_32(sport)) {
3038                         val = lpuart32_read(&sport->port, UARTSTAT);
3039                         lpuart32_write(&sport->port, val, UARTSTAT);
3040                 }
3041         }
3042
3043         return 0;
3044 }
3045
3046 static int lpuart_suspend(struct device *dev)
3047 {
3048         struct lpuart_port *sport = dev_get_drvdata(dev);
3049         unsigned long temp, flags;
3050
3051         uart_suspend_port(&lpuart_reg, &sport->port);
3052
3053         if (lpuart_uport_is_active(sport)) {
3054                 spin_lock_irqsave(&sport->port.lock, flags);
3055                 if (lpuart_is_32(sport)) {
3056                         /* disable Rx/Tx and interrupts */
3057                         temp = lpuart32_read(&sport->port, UARTCTRL);
3058                         temp &= ~(UARTCTRL_TE | UARTCTRL_TIE | UARTCTRL_TCIE);
3059                         lpuart32_write(&sport->port, temp, UARTCTRL);
3060                 } else {
3061                         /* disable Rx/Tx and interrupts */
3062                         temp = readb(sport->port.membase + UARTCR2);
3063                         temp &= ~(UARTCR2_TE | UARTCR2_TIE | UARTCR2_TCIE);
3064                         writeb(temp, sport->port.membase + UARTCR2);
3065                 }
3066                 spin_unlock_irqrestore(&sport->port.lock, flags);
3067
3068                 if (sport->lpuart_dma_rx_use) {
3069                         /*
3070                          * EDMA driver during suspend will forcefully release any
3071                          * non-idle DMA channels. If port wakeup is enabled or if port
3072                          * is console port or 'no_console_suspend' is set the Rx DMA
3073                          * cannot resume as expected, hence gracefully release the
3074                          * Rx DMA path before suspend and start Rx DMA path on resume.
3075                          */
3076                         lpuart_dma_rx_free(&sport->port);
3077
3078                         /* Disable Rx DMA to use UART port as wakeup source */
3079                         spin_lock_irqsave(&sport->port.lock, flags);
3080                         if (lpuart_is_32(sport)) {
3081                                 temp = lpuart32_read(&sport->port, UARTBAUD);
3082                                 lpuart32_write(&sport->port, temp & ~UARTBAUD_RDMAE,
3083                                                UARTBAUD);
3084                         } else {
3085                                 writeb(readb(sport->port.membase + UARTCR5) &
3086                                        ~UARTCR5_RDMAS, sport->port.membase + UARTCR5);
3087                         }
3088                         spin_unlock_irqrestore(&sport->port.lock, flags);
3089                 }
3090
3091                 if (sport->lpuart_dma_tx_use) {
3092                         spin_lock_irqsave(&sport->port.lock, flags);
3093                         if (lpuart_is_32(sport)) {
3094                                 temp = lpuart32_read(&sport->port, UARTBAUD);
3095                                 temp &= ~UARTBAUD_TDMAE;
3096                                 lpuart32_write(&sport->port, temp, UARTBAUD);
3097                         } else {
3098                                 temp = readb(sport->port.membase + UARTCR5);
3099                                 temp &= ~UARTCR5_TDMAS;
3100                                 writeb(temp, sport->port.membase + UARTCR5);
3101                         }
3102                         spin_unlock_irqrestore(&sport->port.lock, flags);
3103                         sport->dma_tx_in_progress = false;
3104                         dmaengine_terminate_sync(sport->dma_tx_chan);
3105                 }
3106         } else if (pm_runtime_active(sport->port.dev)) {
3107                 lpuart_disable_clks(sport);
3108                 pm_runtime_disable(sport->port.dev);
3109                 pm_runtime_set_suspended(sport->port.dev);
3110         }
3111
3112         return 0;
3113 }
3114
3115 static void lpuart_console_fixup(struct lpuart_port *sport)
3116 {
3117         struct tty_port *port = &sport->port.state->port;
3118         struct uart_port *uport = &sport->port;
3119         struct ktermios termios;
3120
3121         /* i.MX7ULP enter VLLS mode that lpuart module power off and registers
3122          * all lost no matter the port is wakeup source.
3123          * For console port, console baud rate setting lost and print messy
3124          * log when enable the console port as wakeup source. To avoid the
3125          * issue happen, user should not enable uart port as wakeup source
3126          * in VLLS mode, or restore console setting here.
3127          */
3128         if (is_imx7ulp_lpuart(sport) && lpuart_uport_is_active(sport) &&
3129             console_suspend_enabled && uart_console(&sport->port)) {
3130
3131                 mutex_lock(&port->mutex);
3132                 memset(&termios, 0, sizeof(struct ktermios));
3133                 termios.c_cflag = uport->cons->cflag;
3134                 if (port->tty && termios.c_cflag == 0)
3135                         termios = port->tty->termios;
3136                 uport->ops->set_termios(uport, &termios, NULL);
3137                 mutex_unlock(&port->mutex);
3138         }
3139 }
3140
3141 static int lpuart_resume(struct device *dev)
3142 {
3143         struct lpuart_port *sport = dev_get_drvdata(dev);
3144         int ret;
3145
3146         if (lpuart_uport_is_active(sport)) {
3147                 if (lpuart_is_32(sport))
3148                         lpuart32_hw_setup(sport);
3149                 else
3150                         lpuart_hw_setup(sport);
3151         } else if (pm_runtime_active(sport->port.dev)) {
3152                 ret = lpuart_enable_clks(sport);
3153                 if (ret)
3154                         return ret;
3155                 pm_runtime_set_active(sport->port.dev);
3156                 pm_runtime_enable(sport->port.dev);
3157         }
3158
3159         lpuart_console_fixup(sport);
3160         uart_resume_port(&lpuart_reg, &sport->port);
3161
3162         return 0;
3163 }
3164
3165 static const struct dev_pm_ops lpuart_pm_ops = {
3166         RUNTIME_PM_OPS(lpuart_runtime_suspend,
3167                            lpuart_runtime_resume, NULL)
3168         NOIRQ_SYSTEM_SLEEP_PM_OPS(lpuart_suspend_noirq,
3169                                       lpuart_resume_noirq)
3170         SYSTEM_SLEEP_PM_OPS(lpuart_suspend, lpuart_resume)
3171 };
3172
3173 static struct platform_driver lpuart_driver = {
3174         .probe          = lpuart_probe,
3175         .remove         = lpuart_remove,
3176         .driver         = {
3177                 .name   = "fsl-lpuart",
3178                 .of_match_table = lpuart_dt_ids,
3179                 .pm     = pm_ptr(&lpuart_pm_ops),
3180         },
3181 };
3182
3183 static int __init lpuart_serial_init(void)
3184 {
3185         int ret = uart_register_driver(&lpuart_reg);
3186
3187         if (ret)
3188                 return ret;
3189
3190         ret = platform_driver_register(&lpuart_driver);
3191         if (ret)
3192                 uart_unregister_driver(&lpuart_reg);
3193
3194         return ret;
3195 }
3196
3197 static void __exit lpuart_serial_exit(void)
3198 {
3199         platform_driver_unregister(&lpuart_driver);
3200         uart_unregister_driver(&lpuart_reg);
3201 }
3202
3203 module_init(lpuart_serial_init);
3204 module_exit(lpuart_serial_exit);
3205
3206 MODULE_DESCRIPTION("Freescale lpuart serial port driver");
3207 MODULE_LICENSE("GPL v2");