1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 * DMA support added by Chip Coldwell.
11 #include <linux/circ_buf.h>
12 #include <linux/tty.h>
13 #include <linux/ioport.h>
14 #include <linux/slab.h>
15 #include <linux/init.h>
16 #include <linux/serial.h>
17 #include <linux/clk.h>
18 #include <linux/console.h>
19 #include <linux/sysrq.h>
20 #include <linux/tty_flip.h>
21 #include <linux/platform_device.h>
23 #include <linux/of_device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/atmel_pdc.h>
27 #include <linux/uaccess.h>
28 #include <linux/platform_data/atmel.h>
29 #include <linux/timer.h>
30 #include <linux/err.h>
31 #include <linux/irq.h>
32 #include <linux/suspend.h>
36 #include <asm/div64.h>
37 #include <asm/ioctls.h>
39 #define PDC_BUFFER_SIZE 512
40 /* Revisit: We should calculate this based on the actual port settings */
41 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
43 /* The minium number of data FIFOs should be able to contain */
44 #define ATMEL_MIN_FIFO_SIZE 8
46 * These two offsets are substracted from the RX FIFO size to define the RTS
47 * high and low thresholds
49 #define ATMEL_RTS_HIGH_OFFSET 16
50 #define ATMEL_RTS_LOW_OFFSET 20
52 #include <linux/serial_core.h>
54 #include "serial_mctrl_gpio.h"
55 #include "atmel_serial.h"
57 static void atmel_start_rx(struct uart_port *port);
58 static void atmel_stop_rx(struct uart_port *port);
60 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
62 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
63 * should coexist with the 8250 driver, such as if we have an external 16C550
65 #define SERIAL_ATMEL_MAJOR 204
66 #define MINOR_START 154
67 #define ATMEL_DEVICENAME "ttyAT"
71 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
72 * name, but it is legally reserved for the 8250 driver. */
73 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
74 #define MINOR_START 64
75 #define ATMEL_DEVICENAME "ttyS"
79 #define ATMEL_ISR_PASS_LIMIT 256
81 struct atmel_dma_buffer {
84 unsigned int dma_size;
88 struct atmel_uart_char {
94 * Be careful, the real size of the ring buffer is
95 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
96 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
99 #define ATMEL_SERIAL_RINGSIZE 1024
102 * at91: 6 USARTs and one DBGU port (SAM9260)
103 * samx7: 3 USARTs and 5 UARTs
105 #define ATMEL_MAX_UART 8
108 * We wrap our port structure around the generic uart_port.
110 struct atmel_uart_port {
111 struct uart_port uart; /* uart */
112 struct clk *clk; /* uart clock */
113 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
114 u32 backup_imr; /* IMR saved during suspend */
115 int break_active; /* break being received */
117 bool use_dma_rx; /* enable DMA receiver */
118 bool use_pdc_rx; /* enable PDC receiver */
119 short pdc_rx_idx; /* current PDC RX buffer */
120 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
122 bool use_dma_tx; /* enable DMA transmitter */
123 bool use_pdc_tx; /* enable PDC transmitter */
124 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
126 spinlock_t lock_tx; /* port lock */
127 spinlock_t lock_rx; /* port lock */
128 struct dma_chan *chan_tx;
129 struct dma_chan *chan_rx;
130 struct dma_async_tx_descriptor *desc_tx;
131 struct dma_async_tx_descriptor *desc_rx;
132 dma_cookie_t cookie_tx;
133 dma_cookie_t cookie_rx;
134 struct scatterlist sg_tx;
135 struct scatterlist sg_rx;
136 struct tasklet_struct tasklet_rx;
137 struct tasklet_struct tasklet_tx;
138 atomic_t tasklet_shutdown;
139 unsigned int irq_status_prev;
142 struct circ_buf rx_ring;
144 struct mctrl_gpios *gpios;
145 u32 backup_mode; /* MR saved during iso7816 operations */
146 u32 backup_brgr; /* BRGR saved during iso7816 operations */
147 unsigned int tx_done_mask;
152 u32 rtor; /* address of receiver timeout register if it exists */
153 bool has_frac_baudrate;
155 struct timer_list uart_timer;
159 unsigned int pending;
160 unsigned int pending_status;
161 spinlock_t lock_suspended;
163 bool hd_start_rx; /* can start RX during half-duplex operation */
166 unsigned int fidi_min;
167 unsigned int fidi_max;
180 int (*prepare_rx)(struct uart_port *port);
181 int (*prepare_tx)(struct uart_port *port);
182 void (*schedule_rx)(struct uart_port *port);
183 void (*schedule_tx)(struct uart_port *port);
184 void (*release_rx)(struct uart_port *port);
185 void (*release_tx)(struct uart_port *port);
188 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
189 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
191 #if defined(CONFIG_OF)
192 static const struct of_device_id atmel_serial_dt_ids[] = {
193 { .compatible = "atmel,at91rm9200-usart-serial" },
198 static inline struct atmel_uart_port *
199 to_atmel_uart_port(struct uart_port *uart)
201 return container_of(uart, struct atmel_uart_port, uart);
204 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
206 return __raw_readl(port->membase + reg);
209 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
211 __raw_writel(value, port->membase + reg);
214 static inline u8 atmel_uart_read_char(struct uart_port *port)
216 return __raw_readb(port->membase + ATMEL_US_RHR);
219 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
221 __raw_writeb(value, port->membase + ATMEL_US_THR);
224 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
226 return ((port->rs485.flags & SER_RS485_ENABLED) &&
227 !(port->rs485.flags & SER_RS485_RX_DURING_TX)) ||
228 (port->iso7816.flags & SER_ISO7816_ENABLED);
231 #ifdef CONFIG_SERIAL_ATMEL_PDC
232 static bool atmel_use_pdc_rx(struct uart_port *port)
234 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
236 return atmel_port->use_pdc_rx;
239 static bool atmel_use_pdc_tx(struct uart_port *port)
241 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
243 return atmel_port->use_pdc_tx;
246 static bool atmel_use_pdc_rx(struct uart_port *port)
251 static bool atmel_use_pdc_tx(struct uart_port *port)
257 static bool atmel_use_dma_tx(struct uart_port *port)
259 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
261 return atmel_port->use_dma_tx;
264 static bool atmel_use_dma_rx(struct uart_port *port)
266 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
268 return atmel_port->use_dma_rx;
271 static bool atmel_use_fifo(struct uart_port *port)
273 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
275 return atmel_port->fifo_size;
278 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
279 struct tasklet_struct *t)
281 if (!atomic_read(&atmel_port->tasklet_shutdown))
285 /* Enable or disable the rs485 support */
286 static int atmel_config_rs485(struct uart_port *port, struct ktermios *termios,
287 struct serial_rs485 *rs485conf)
289 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
292 /* Disable interrupts */
293 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
295 mode = atmel_uart_readl(port, ATMEL_US_MR);
297 if (rs485conf->flags & SER_RS485_ENABLED) {
298 dev_dbg(port->dev, "Setting UART to RS485\n");
299 if (rs485conf->flags & SER_RS485_RX_DURING_TX)
300 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
302 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
304 atmel_uart_writel(port, ATMEL_US_TTGR,
305 rs485conf->delay_rts_after_send);
306 mode &= ~ATMEL_US_USMODE;
307 mode |= ATMEL_US_USMODE_RS485;
309 dev_dbg(port->dev, "Setting UART to RS232\n");
310 if (atmel_use_pdc_tx(port))
311 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
314 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
316 atmel_uart_writel(port, ATMEL_US_MR, mode);
318 /* Enable interrupts */
319 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
324 static unsigned int atmel_calc_cd(struct uart_port *port,
325 struct serial_iso7816 *iso7816conf)
327 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
331 mck_rate = (u64)clk_get_rate(atmel_port->clk);
332 do_div(mck_rate, iso7816conf->clk);
337 static unsigned int atmel_calc_fidi(struct uart_port *port,
338 struct serial_iso7816 *iso7816conf)
342 if (iso7816conf->sc_fi && iso7816conf->sc_di) {
343 fidi = (u64)iso7816conf->sc_fi;
344 do_div(fidi, iso7816conf->sc_di);
349 /* Enable or disable the iso7816 support */
350 /* Called with interrupts disabled */
351 static int atmel_config_iso7816(struct uart_port *port,
352 struct serial_iso7816 *iso7816conf)
354 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
356 unsigned int cd, fidi;
359 /* Disable interrupts */
360 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
362 mode = atmel_uart_readl(port, ATMEL_US_MR);
364 if (iso7816conf->flags & SER_ISO7816_ENABLED) {
365 mode &= ~ATMEL_US_USMODE;
367 if (iso7816conf->tg > 255) {
368 dev_err(port->dev, "ISO7816: Timeguard exceeding 255\n");
369 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
374 if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
375 == SER_ISO7816_T(0)) {
376 mode |= ATMEL_US_USMODE_ISO7816_T0 | ATMEL_US_DSNACK;
377 } else if ((iso7816conf->flags & SER_ISO7816_T_PARAM)
378 == SER_ISO7816_T(1)) {
379 mode |= ATMEL_US_USMODE_ISO7816_T1 | ATMEL_US_INACK;
381 dev_err(port->dev, "ISO7816: Type not supported\n");
382 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
387 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_NBSTOP | ATMEL_US_PAR);
389 /* select mck clock, and output */
390 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
391 /* set parity for normal/inverse mode + max iterations */
392 mode |= ATMEL_US_PAR_EVEN | ATMEL_US_NBSTOP_1 | ATMEL_US_MAX_ITER(3);
394 cd = atmel_calc_cd(port, iso7816conf);
395 fidi = atmel_calc_fidi(port, iso7816conf);
397 dev_warn(port->dev, "ISO7816 fidi = 0, Generator generates no signal\n");
398 } else if (fidi < atmel_port->fidi_min
399 || fidi > atmel_port->fidi_max) {
400 dev_err(port->dev, "ISO7816 fidi = %u, value not supported\n", fidi);
401 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
406 if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) {
407 /* port not yet in iso7816 mode: store configuration */
408 atmel_port->backup_mode = atmel_uart_readl(port, ATMEL_US_MR);
409 atmel_port->backup_brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
412 atmel_uart_writel(port, ATMEL_US_TTGR, iso7816conf->tg);
413 atmel_uart_writel(port, ATMEL_US_BRGR, cd);
414 atmel_uart_writel(port, ATMEL_US_FIDI, fidi);
416 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXEN);
417 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY | ATMEL_US_NACK | ATMEL_US_ITERATION;
419 dev_dbg(port->dev, "Setting UART back to RS232\n");
420 /* back to last RS232 settings */
421 mode = atmel_port->backup_mode;
422 memset(iso7816conf, 0, sizeof(struct serial_iso7816));
423 atmel_uart_writel(port, ATMEL_US_TTGR, 0);
424 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->backup_brgr);
425 atmel_uart_writel(port, ATMEL_US_FIDI, 0x174);
427 if (atmel_use_pdc_tx(port))
428 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
431 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
434 port->iso7816 = *iso7816conf;
436 atmel_uart_writel(port, ATMEL_US_MR, mode);
439 /* Enable interrupts */
440 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
446 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
448 static u_int atmel_tx_empty(struct uart_port *port)
450 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
452 if (atmel_port->tx_stopped)
454 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
460 * Set state of the modem control output lines
462 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
464 unsigned int control = 0;
465 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
466 unsigned int rts_paused, rts_ready;
467 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
469 /* override mode to RS485 if needed, otherwise keep the current mode */
470 if (port->rs485.flags & SER_RS485_ENABLED) {
471 atmel_uart_writel(port, ATMEL_US_TTGR,
472 port->rs485.delay_rts_after_send);
473 mode &= ~ATMEL_US_USMODE;
474 mode |= ATMEL_US_USMODE_RS485;
477 /* set the RTS line state according to the mode */
478 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
479 /* force RTS line to high level */
480 rts_paused = ATMEL_US_RTSEN;
482 /* give the control of the RTS line back to the hardware */
483 rts_ready = ATMEL_US_RTSDIS;
485 /* force RTS line to high level */
486 rts_paused = ATMEL_US_RTSDIS;
488 /* force RTS line to low level */
489 rts_ready = ATMEL_US_RTSEN;
492 if (mctrl & TIOCM_RTS)
493 control |= rts_ready;
495 control |= rts_paused;
497 if (mctrl & TIOCM_DTR)
498 control |= ATMEL_US_DTREN;
500 control |= ATMEL_US_DTRDIS;
502 atmel_uart_writel(port, ATMEL_US_CR, control);
504 mctrl_gpio_set(atmel_port->gpios, mctrl);
506 /* Local loopback mode? */
507 mode &= ~ATMEL_US_CHMODE;
508 if (mctrl & TIOCM_LOOP)
509 mode |= ATMEL_US_CHMODE_LOC_LOOP;
511 mode |= ATMEL_US_CHMODE_NORMAL;
513 atmel_uart_writel(port, ATMEL_US_MR, mode);
517 * Get state of the modem control input lines
519 static u_int atmel_get_mctrl(struct uart_port *port)
521 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
522 unsigned int ret = 0, status;
524 status = atmel_uart_readl(port, ATMEL_US_CSR);
527 * The control signals are active low.
529 if (!(status & ATMEL_US_DCD))
531 if (!(status & ATMEL_US_CTS))
533 if (!(status & ATMEL_US_DSR))
535 if (!(status & ATMEL_US_RI))
538 return mctrl_gpio_get(atmel_port->gpios, &ret);
544 static void atmel_stop_tx(struct uart_port *port)
546 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
548 if (atmel_use_pdc_tx(port)) {
549 /* disable PDC transmit */
550 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
554 * Disable the transmitter.
555 * This is mandatory when DMA is used, otherwise the DMA buffer
556 * is fully transmitted.
558 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
559 atmel_port->tx_stopped = true;
561 /* Disable interrupts */
562 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
564 if (atmel_uart_is_half_duplex(port))
565 if (!atomic_read(&atmel_port->tasklet_shutdown))
566 atmel_start_rx(port);
571 * Start transmitting.
573 static void atmel_start_tx(struct uart_port *port)
575 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
577 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
579 /* The transmitter is already running. Yes, we
583 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
584 if (atmel_uart_is_half_duplex(port))
587 if (atmel_use_pdc_tx(port))
588 /* re-enable PDC transmit */
589 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
591 /* Enable interrupts */
592 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
594 /* re-enable the transmitter */
595 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
596 atmel_port->tx_stopped = false;
600 * start receiving - port is in process of being opened.
602 static void atmel_start_rx(struct uart_port *port)
604 /* reset status and receiver */
605 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
607 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
609 if (atmel_use_pdc_rx(port)) {
610 /* enable PDC controller */
611 atmel_uart_writel(port, ATMEL_US_IER,
612 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
613 port->read_status_mask);
614 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
616 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
621 * Stop receiving - port is in process of being closed.
623 static void atmel_stop_rx(struct uart_port *port)
625 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
627 if (atmel_use_pdc_rx(port)) {
628 /* disable PDC receive */
629 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
630 atmel_uart_writel(port, ATMEL_US_IDR,
631 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
632 port->read_status_mask);
634 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
639 * Enable modem status interrupts
641 static void atmel_enable_ms(struct uart_port *port)
643 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
647 * Interrupt should not be enabled twice
649 if (atmel_port->ms_irq_enabled)
652 atmel_port->ms_irq_enabled = true;
654 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
655 ier |= ATMEL_US_CTSIC;
657 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
658 ier |= ATMEL_US_DSRIC;
660 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
661 ier |= ATMEL_US_RIIC;
663 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
664 ier |= ATMEL_US_DCDIC;
666 atmel_uart_writel(port, ATMEL_US_IER, ier);
668 mctrl_gpio_enable_ms(atmel_port->gpios);
672 * Disable modem status interrupts
674 static void atmel_disable_ms(struct uart_port *port)
676 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
680 * Interrupt should not be disabled twice
682 if (!atmel_port->ms_irq_enabled)
685 atmel_port->ms_irq_enabled = false;
687 mctrl_gpio_disable_ms(atmel_port->gpios);
689 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
690 idr |= ATMEL_US_CTSIC;
692 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
693 idr |= ATMEL_US_DSRIC;
695 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
696 idr |= ATMEL_US_RIIC;
698 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
699 idr |= ATMEL_US_DCDIC;
701 atmel_uart_writel(port, ATMEL_US_IDR, idr);
705 * Control the transmission of a break signal
707 static void atmel_break_ctl(struct uart_port *port, int break_state)
709 if (break_state != 0)
711 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
714 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
718 * Stores the incoming character in the ring buffer
721 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
724 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
725 struct circ_buf *ring = &atmel_port->rx_ring;
726 struct atmel_uart_char *c;
728 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
729 /* Buffer overflow, ignore char */
732 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
736 /* Make sure the character is stored before we update head. */
739 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
743 * Deal with parity, framing and overrun errors.
745 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
748 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
750 if (status & ATMEL_US_RXBRK) {
751 /* ignore side-effect */
752 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
755 if (status & ATMEL_US_PARE)
756 port->icount.parity++;
757 if (status & ATMEL_US_FRAME)
758 port->icount.frame++;
759 if (status & ATMEL_US_OVRE)
760 port->icount.overrun++;
764 * Characters received (called from interrupt handler)
766 static void atmel_rx_chars(struct uart_port *port)
768 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
769 unsigned int status, ch;
771 status = atmel_uart_readl(port, ATMEL_US_CSR);
772 while (status & ATMEL_US_RXRDY) {
773 ch = atmel_uart_read_char(port);
776 * note that the error handling code is
777 * out of the main execution path
779 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
780 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
781 || atmel_port->break_active)) {
784 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
786 if (status & ATMEL_US_RXBRK
787 && !atmel_port->break_active) {
788 atmel_port->break_active = 1;
789 atmel_uart_writel(port, ATMEL_US_IER,
793 * This is either the end-of-break
794 * condition or we've received at
795 * least one character without RXBRK
796 * being set. In both cases, the next
797 * RXBRK will indicate start-of-break.
799 atmel_uart_writel(port, ATMEL_US_IDR,
801 status &= ~ATMEL_US_RXBRK;
802 atmel_port->break_active = 0;
806 atmel_buffer_rx_char(port, status, ch);
807 status = atmel_uart_readl(port, ATMEL_US_CSR);
810 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
814 * Transmit characters (called from tasklet with TXRDY interrupt
817 static void atmel_tx_chars(struct uart_port *port)
819 struct circ_buf *xmit = &port->state->xmit;
820 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
823 (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY)) {
824 atmel_uart_write_char(port, port->x_char);
828 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
831 while (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY) {
832 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
833 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
835 if (uart_circ_empty(xmit))
839 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
840 uart_write_wakeup(port);
842 if (!uart_circ_empty(xmit)) {
843 /* we still have characters to transmit, so we should continue
844 * transmitting them when TX is ready, regardless of
847 atmel_port->tx_done_mask |= ATMEL_US_TXRDY;
849 /* Enable interrupts */
850 atmel_uart_writel(port, ATMEL_US_IER,
851 atmel_port->tx_done_mask);
853 if (atmel_uart_is_half_duplex(port))
854 atmel_port->tx_done_mask &= ~ATMEL_US_TXRDY;
858 static void atmel_complete_tx_dma(void *arg)
860 struct atmel_uart_port *atmel_port = arg;
861 struct uart_port *port = &atmel_port->uart;
862 struct circ_buf *xmit = &port->state->xmit;
863 struct dma_chan *chan = atmel_port->chan_tx;
866 spin_lock_irqsave(&port->lock, flags);
869 dmaengine_terminate_all(chan);
870 xmit->tail += atmel_port->tx_len;
871 xmit->tail &= UART_XMIT_SIZE - 1;
873 port->icount.tx += atmel_port->tx_len;
875 spin_lock_irq(&atmel_port->lock_tx);
876 async_tx_ack(atmel_port->desc_tx);
877 atmel_port->cookie_tx = -EINVAL;
878 atmel_port->desc_tx = NULL;
879 spin_unlock_irq(&atmel_port->lock_tx);
881 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
882 uart_write_wakeup(port);
885 * xmit is a circular buffer so, if we have just send data from
886 * xmit->tail to the end of xmit->buf, now we have to transmit the
887 * remaining data from the beginning of xmit->buf to xmit->head.
889 if (!uart_circ_empty(xmit))
890 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
891 else if (atmel_uart_is_half_duplex(port)) {
893 * DMA done, re-enable TXEMPTY and signal that we can stop
894 * TX and start RX for RS485
896 atmel_port->hd_start_rx = true;
897 atmel_uart_writel(port, ATMEL_US_IER,
898 atmel_port->tx_done_mask);
901 spin_unlock_irqrestore(&port->lock, flags);
904 static void atmel_release_tx_dma(struct uart_port *port)
906 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
907 struct dma_chan *chan = atmel_port->chan_tx;
910 dmaengine_terminate_all(chan);
911 dma_release_channel(chan);
912 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
916 atmel_port->desc_tx = NULL;
917 atmel_port->chan_tx = NULL;
918 atmel_port->cookie_tx = -EINVAL;
922 * Called from tasklet with TXRDY interrupt is disabled.
924 static void atmel_tx_dma(struct uart_port *port)
926 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
927 struct circ_buf *xmit = &port->state->xmit;
928 struct dma_chan *chan = atmel_port->chan_tx;
929 struct dma_async_tx_descriptor *desc;
930 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
931 unsigned int tx_len, part1_len, part2_len, sg_len;
932 dma_addr_t phys_addr;
934 /* Make sure we have an idle channel */
935 if (atmel_port->desc_tx != NULL)
938 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
941 * Port xmit buffer is already mapped,
942 * and it is one page... Just adjust
943 * offsets and lengths. Since it is a circular buffer,
944 * we have to transmit till the end, and then the rest.
945 * Take the port lock to get a
946 * consistent xmit buffer state.
948 tx_len = CIRC_CNT_TO_END(xmit->head,
952 if (atmel_port->fifo_size) {
953 /* multi data mode */
954 part1_len = (tx_len & ~0x3); /* DWORD access */
955 part2_len = (tx_len & 0x3); /* BYTE access */
957 /* single data (legacy) mode */
959 part2_len = tx_len; /* BYTE access only */
962 sg_init_table(sgl, 2);
964 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
967 sg_dma_address(sg) = phys_addr;
968 sg_dma_len(sg) = part1_len;
970 phys_addr += part1_len;
975 sg_dma_address(sg) = phys_addr;
976 sg_dma_len(sg) = part2_len;
980 * save tx_len so atmel_complete_tx_dma() will increase
981 * xmit->tail correctly
983 atmel_port->tx_len = tx_len;
985 desc = dmaengine_prep_slave_sg(chan,
992 dev_err(port->dev, "Failed to send via dma!\n");
996 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
998 atmel_port->desc_tx = desc;
999 desc->callback = atmel_complete_tx_dma;
1000 desc->callback_param = atmel_port;
1001 atmel_port->cookie_tx = dmaengine_submit(desc);
1002 if (dma_submit_error(atmel_port->cookie_tx)) {
1003 dev_err(port->dev, "dma_submit_error %d\n",
1004 atmel_port->cookie_tx);
1008 dma_async_issue_pending(chan);
1011 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1012 uart_write_wakeup(port);
1015 static int atmel_prepare_tx_dma(struct uart_port *port)
1017 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1018 struct device *mfd_dev = port->dev->parent;
1019 dma_cap_mask_t mask;
1020 struct dma_slave_config config;
1024 dma_cap_set(DMA_SLAVE, mask);
1026 atmel_port->chan_tx = dma_request_slave_channel(mfd_dev, "tx");
1027 if (atmel_port->chan_tx == NULL)
1029 dev_info(port->dev, "using %s for tx DMA transfers\n",
1030 dma_chan_name(atmel_port->chan_tx));
1032 spin_lock_init(&atmel_port->lock_tx);
1033 sg_init_table(&atmel_port->sg_tx, 1);
1034 /* UART circular tx buffer is an aligned page. */
1035 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
1036 sg_set_page(&atmel_port->sg_tx,
1037 virt_to_page(port->state->xmit.buf),
1039 offset_in_page(port->state->xmit.buf));
1040 nent = dma_map_sg(port->dev,
1046 dev_dbg(port->dev, "need to release resource of dma\n");
1049 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1050 sg_dma_len(&atmel_port->sg_tx),
1051 port->state->xmit.buf,
1052 &sg_dma_address(&atmel_port->sg_tx));
1055 /* Configure the slave DMA */
1056 memset(&config, 0, sizeof(config));
1057 config.direction = DMA_MEM_TO_DEV;
1058 config.dst_addr_width = (atmel_port->fifo_size) ?
1059 DMA_SLAVE_BUSWIDTH_4_BYTES :
1060 DMA_SLAVE_BUSWIDTH_1_BYTE;
1061 config.dst_addr = port->mapbase + ATMEL_US_THR;
1062 config.dst_maxburst = 1;
1064 ret = dmaengine_slave_config(atmel_port->chan_tx,
1067 dev_err(port->dev, "DMA tx slave configuration failed\n");
1074 dev_err(port->dev, "TX channel not available, switch to pio\n");
1075 atmel_port->use_dma_tx = false;
1076 if (atmel_port->chan_tx)
1077 atmel_release_tx_dma(port);
1081 static void atmel_complete_rx_dma(void *arg)
1083 struct uart_port *port = arg;
1084 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1086 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1089 static void atmel_release_rx_dma(struct uart_port *port)
1091 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1092 struct dma_chan *chan = atmel_port->chan_rx;
1095 dmaengine_terminate_all(chan);
1096 dma_release_channel(chan);
1097 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1101 atmel_port->desc_rx = NULL;
1102 atmel_port->chan_rx = NULL;
1103 atmel_port->cookie_rx = -EINVAL;
1106 static void atmel_rx_from_dma(struct uart_port *port)
1108 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1109 struct tty_port *tport = &port->state->port;
1110 struct circ_buf *ring = &atmel_port->rx_ring;
1111 struct dma_chan *chan = atmel_port->chan_rx;
1112 struct dma_tx_state state;
1113 enum dma_status dmastat;
1117 /* Reset the UART timeout early so that we don't miss one */
1118 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1119 dmastat = dmaengine_tx_status(chan,
1120 atmel_port->cookie_rx,
1122 /* Restart a new tasklet if DMA status is error */
1123 if (dmastat == DMA_ERROR) {
1124 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1125 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1126 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1130 /* CPU claims ownership of RX DMA buffer */
1131 dma_sync_sg_for_cpu(port->dev,
1137 * ring->head points to the end of data already written by the DMA.
1138 * ring->tail points to the beginning of data to be read by the
1140 * The current transfer size should not be larger than the dma buffer
1143 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1144 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1146 * At this point ring->head may point to the first byte right after the
1147 * last byte of the dma buffer:
1148 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1150 * However ring->tail must always points inside the dma buffer:
1151 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1153 * Since we use a ring buffer, we have to handle the case
1154 * where head is lower than tail. In such a case, we first read from
1155 * tail to the end of the buffer then reset tail.
1157 if (ring->head < ring->tail) {
1158 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1160 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1162 port->icount.rx += count;
1165 /* Finally we read data from tail to head */
1166 if (ring->tail < ring->head) {
1167 count = ring->head - ring->tail;
1169 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1170 /* Wrap ring->head if needed */
1171 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1173 ring->tail = ring->head;
1174 port->icount.rx += count;
1177 /* USART retreives ownership of RX DMA buffer */
1178 dma_sync_sg_for_device(port->dev,
1183 tty_flip_buffer_push(tport);
1185 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1188 static int atmel_prepare_rx_dma(struct uart_port *port)
1190 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1191 struct device *mfd_dev = port->dev->parent;
1192 struct dma_async_tx_descriptor *desc;
1193 dma_cap_mask_t mask;
1194 struct dma_slave_config config;
1195 struct circ_buf *ring;
1198 ring = &atmel_port->rx_ring;
1201 dma_cap_set(DMA_CYCLIC, mask);
1203 atmel_port->chan_rx = dma_request_slave_channel(mfd_dev, "rx");
1204 if (atmel_port->chan_rx == NULL)
1206 dev_info(port->dev, "using %s for rx DMA transfers\n",
1207 dma_chan_name(atmel_port->chan_rx));
1209 spin_lock_init(&atmel_port->lock_rx);
1210 sg_init_table(&atmel_port->sg_rx, 1);
1211 /* UART circular rx buffer is an aligned page. */
1212 BUG_ON(!PAGE_ALIGNED(ring->buf));
1213 sg_set_page(&atmel_port->sg_rx,
1214 virt_to_page(ring->buf),
1215 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1216 offset_in_page(ring->buf));
1217 nent = dma_map_sg(port->dev,
1223 dev_dbg(port->dev, "need to release resource of dma\n");
1226 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1227 sg_dma_len(&atmel_port->sg_rx),
1229 &sg_dma_address(&atmel_port->sg_rx));
1232 /* Configure the slave DMA */
1233 memset(&config, 0, sizeof(config));
1234 config.direction = DMA_DEV_TO_MEM;
1235 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1236 config.src_addr = port->mapbase + ATMEL_US_RHR;
1237 config.src_maxburst = 1;
1239 ret = dmaengine_slave_config(atmel_port->chan_rx,
1242 dev_err(port->dev, "DMA rx slave configuration failed\n");
1246 * Prepare a cyclic dma transfer, assign 2 descriptors,
1247 * each one is half ring buffer size
1249 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1250 sg_dma_address(&atmel_port->sg_rx),
1251 sg_dma_len(&atmel_port->sg_rx),
1252 sg_dma_len(&atmel_port->sg_rx)/2,
1254 DMA_PREP_INTERRUPT);
1256 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1259 desc->callback = atmel_complete_rx_dma;
1260 desc->callback_param = port;
1261 atmel_port->desc_rx = desc;
1262 atmel_port->cookie_rx = dmaengine_submit(desc);
1263 if (dma_submit_error(atmel_port->cookie_rx)) {
1264 dev_err(port->dev, "dma_submit_error %d\n",
1265 atmel_port->cookie_rx);
1269 dma_async_issue_pending(atmel_port->chan_rx);
1274 dev_err(port->dev, "RX channel not available, switch to pio\n");
1275 atmel_port->use_dma_rx = false;
1276 if (atmel_port->chan_rx)
1277 atmel_release_rx_dma(port);
1281 static void atmel_uart_timer_callback(struct timer_list *t)
1283 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1285 struct uart_port *port = &atmel_port->uart;
1287 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1288 tasklet_schedule(&atmel_port->tasklet_rx);
1289 mod_timer(&atmel_port->uart_timer,
1290 jiffies + uart_poll_timeout(port));
1295 * receive interrupt handler.
1298 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1300 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1302 if (atmel_use_pdc_rx(port)) {
1304 * PDC receive. Just schedule the tasklet and let it
1305 * figure out the details.
1307 * TODO: We're not handling error flags correctly at
1310 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1311 atmel_uart_writel(port, ATMEL_US_IDR,
1312 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1313 atmel_tasklet_schedule(atmel_port,
1314 &atmel_port->tasklet_rx);
1317 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1318 ATMEL_US_FRAME | ATMEL_US_PARE))
1319 atmel_pdc_rxerr(port, pending);
1322 if (atmel_use_dma_rx(port)) {
1323 if (pending & ATMEL_US_TIMEOUT) {
1324 atmel_uart_writel(port, ATMEL_US_IDR,
1326 atmel_tasklet_schedule(atmel_port,
1327 &atmel_port->tasklet_rx);
1331 /* Interrupt receive */
1332 if (pending & ATMEL_US_RXRDY)
1333 atmel_rx_chars(port);
1334 else if (pending & ATMEL_US_RXBRK) {
1336 * End of break detected. If it came along with a
1337 * character, atmel_rx_chars will handle it.
1339 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1340 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1341 atmel_port->break_active = 0;
1346 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1349 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1351 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1353 if (pending & atmel_port->tx_done_mask) {
1354 atmel_uart_writel(port, ATMEL_US_IDR,
1355 atmel_port->tx_done_mask);
1357 /* Start RX if flag was set and FIFO is empty */
1358 if (atmel_port->hd_start_rx) {
1359 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1360 & ATMEL_US_TXEMPTY))
1361 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1363 atmel_port->hd_start_rx = false;
1364 atmel_start_rx(port);
1367 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1372 * status flags interrupt handler.
1375 atmel_handle_status(struct uart_port *port, unsigned int pending,
1376 unsigned int status)
1378 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1379 unsigned int status_change;
1381 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1382 | ATMEL_US_CTSIC)) {
1383 status_change = status ^ atmel_port->irq_status_prev;
1384 atmel_port->irq_status_prev = status;
1386 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1387 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1388 /* TODO: All reads to CSR will clear these interrupts! */
1389 if (status_change & ATMEL_US_RI)
1391 if (status_change & ATMEL_US_DSR)
1393 if (status_change & ATMEL_US_DCD)
1394 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1395 if (status_change & ATMEL_US_CTS)
1396 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1398 wake_up_interruptible(&port->state->port.delta_msr_wait);
1402 if (pending & (ATMEL_US_NACK | ATMEL_US_ITERATION))
1403 dev_dbg(port->dev, "ISO7816 ERROR (0x%08x)\n", pending);
1409 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1411 struct uart_port *port = dev_id;
1412 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1413 unsigned int status, pending, mask, pass_counter = 0;
1415 spin_lock(&atmel_port->lock_suspended);
1418 status = atmel_uart_readl(port, ATMEL_US_CSR);
1419 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1420 pending = status & mask;
1424 if (atmel_port->suspended) {
1425 atmel_port->pending |= pending;
1426 atmel_port->pending_status = status;
1427 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1432 atmel_handle_receive(port, pending);
1433 atmel_handle_status(port, pending, status);
1434 atmel_handle_transmit(port, pending);
1435 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1437 spin_unlock(&atmel_port->lock_suspended);
1439 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1442 static void atmel_release_tx_pdc(struct uart_port *port)
1444 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1445 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1447 dma_unmap_single(port->dev,
1454 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1456 static void atmel_tx_pdc(struct uart_port *port)
1458 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1459 struct circ_buf *xmit = &port->state->xmit;
1460 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1463 /* nothing left to transmit? */
1464 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1467 xmit->tail += pdc->ofs;
1468 xmit->tail &= UART_XMIT_SIZE - 1;
1470 port->icount.tx += pdc->ofs;
1473 /* more to transmit - setup next transfer */
1475 /* disable PDC transmit */
1476 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1478 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1479 dma_sync_single_for_device(port->dev,
1484 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1487 atmel_uart_writel(port, ATMEL_PDC_TPR,
1488 pdc->dma_addr + xmit->tail);
1489 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1490 /* re-enable PDC transmit */
1491 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1492 /* Enable interrupts */
1493 atmel_uart_writel(port, ATMEL_US_IER,
1494 atmel_port->tx_done_mask);
1496 if (atmel_uart_is_half_duplex(port)) {
1497 /* DMA done, stop TX, start RX for RS485 */
1498 atmel_start_rx(port);
1502 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1503 uart_write_wakeup(port);
1506 static int atmel_prepare_tx_pdc(struct uart_port *port)
1508 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1509 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1510 struct circ_buf *xmit = &port->state->xmit;
1512 pdc->buf = xmit->buf;
1513 pdc->dma_addr = dma_map_single(port->dev,
1517 pdc->dma_size = UART_XMIT_SIZE;
1523 static void atmel_rx_from_ring(struct uart_port *port)
1525 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1526 struct circ_buf *ring = &atmel_port->rx_ring;
1528 unsigned int status;
1530 while (ring->head != ring->tail) {
1531 struct atmel_uart_char c;
1533 /* Make sure c is loaded after head. */
1536 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1538 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1545 * note that the error handling code is
1546 * out of the main execution path
1548 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1549 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1550 if (status & ATMEL_US_RXBRK) {
1551 /* ignore side-effect */
1552 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1555 if (uart_handle_break(port))
1558 if (status & ATMEL_US_PARE)
1559 port->icount.parity++;
1560 if (status & ATMEL_US_FRAME)
1561 port->icount.frame++;
1562 if (status & ATMEL_US_OVRE)
1563 port->icount.overrun++;
1565 status &= port->read_status_mask;
1567 if (status & ATMEL_US_RXBRK)
1569 else if (status & ATMEL_US_PARE)
1571 else if (status & ATMEL_US_FRAME)
1576 if (uart_handle_sysrq_char(port, c.ch))
1579 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1582 tty_flip_buffer_push(&port->state->port);
1585 static void atmel_release_rx_pdc(struct uart_port *port)
1587 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1590 for (i = 0; i < 2; i++) {
1591 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1593 dma_unmap_single(port->dev,
1601 static void atmel_rx_from_pdc(struct uart_port *port)
1603 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1604 struct tty_port *tport = &port->state->port;
1605 struct atmel_dma_buffer *pdc;
1606 int rx_idx = atmel_port->pdc_rx_idx;
1612 /* Reset the UART timeout early so that we don't miss one */
1613 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1615 pdc = &atmel_port->pdc_rx[rx_idx];
1616 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1619 /* If the PDC has switched buffers, RPR won't contain
1620 * any address within the current buffer. Since head
1621 * is unsigned, we just need a one-way comparison to
1624 * In this case, we just need to consume the entire
1625 * buffer and resubmit it for DMA. This will clear the
1626 * ENDRX bit as well, so that we can safely re-enable
1627 * all interrupts below.
1629 head = min(head, pdc->dma_size);
1631 if (likely(head != tail)) {
1632 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1633 pdc->dma_size, DMA_FROM_DEVICE);
1636 * head will only wrap around when we recycle
1637 * the DMA buffer, and when that happens, we
1638 * explicitly set tail to 0. So head will
1639 * always be greater than tail.
1641 count = head - tail;
1643 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1646 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1647 pdc->dma_size, DMA_FROM_DEVICE);
1649 port->icount.rx += count;
1654 * If the current buffer is full, we need to check if
1655 * the next one contains any additional data.
1657 if (head >= pdc->dma_size) {
1659 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1660 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1663 atmel_port->pdc_rx_idx = rx_idx;
1665 } while (head >= pdc->dma_size);
1667 tty_flip_buffer_push(tport);
1669 atmel_uart_writel(port, ATMEL_US_IER,
1670 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1673 static int atmel_prepare_rx_pdc(struct uart_port *port)
1675 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1678 for (i = 0; i < 2; i++) {
1679 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1681 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1682 if (pdc->buf == NULL) {
1684 dma_unmap_single(port->dev,
1685 atmel_port->pdc_rx[0].dma_addr,
1688 kfree(atmel_port->pdc_rx[0].buf);
1690 atmel_port->use_pdc_rx = false;
1693 pdc->dma_addr = dma_map_single(port->dev,
1697 pdc->dma_size = PDC_BUFFER_SIZE;
1701 atmel_port->pdc_rx_idx = 0;
1703 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1704 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1706 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1707 atmel_port->pdc_rx[1].dma_addr);
1708 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1714 * tasklet handling tty stuff outside the interrupt handler.
1716 static void atmel_tasklet_rx_func(struct tasklet_struct *t)
1718 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1720 struct uart_port *port = &atmel_port->uart;
1722 /* The interrupt handler does not take the lock */
1723 spin_lock(&port->lock);
1724 atmel_port->schedule_rx(port);
1725 spin_unlock(&port->lock);
1728 static void atmel_tasklet_tx_func(struct tasklet_struct *t)
1730 struct atmel_uart_port *atmel_port = from_tasklet(atmel_port, t,
1732 struct uart_port *port = &atmel_port->uart;
1734 /* The interrupt handler does not take the lock */
1735 spin_lock(&port->lock);
1736 atmel_port->schedule_tx(port);
1737 spin_unlock(&port->lock);
1740 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1741 struct platform_device *pdev)
1743 struct device_node *np = pdev->dev.of_node;
1745 /* DMA/PDC usage specification */
1746 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1747 if (of_property_read_bool(np, "dmas")) {
1748 atmel_port->use_dma_rx = true;
1749 atmel_port->use_pdc_rx = false;
1751 atmel_port->use_dma_rx = false;
1752 atmel_port->use_pdc_rx = true;
1755 atmel_port->use_dma_rx = false;
1756 atmel_port->use_pdc_rx = false;
1759 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1760 if (of_property_read_bool(np, "dmas")) {
1761 atmel_port->use_dma_tx = true;
1762 atmel_port->use_pdc_tx = false;
1764 atmel_port->use_dma_tx = false;
1765 atmel_port->use_pdc_tx = true;
1768 atmel_port->use_dma_tx = false;
1769 atmel_port->use_pdc_tx = false;
1773 static void atmel_set_ops(struct uart_port *port)
1775 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1777 if (atmel_use_dma_rx(port)) {
1778 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1779 atmel_port->schedule_rx = &atmel_rx_from_dma;
1780 atmel_port->release_rx = &atmel_release_rx_dma;
1781 } else if (atmel_use_pdc_rx(port)) {
1782 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1783 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1784 atmel_port->release_rx = &atmel_release_rx_pdc;
1786 atmel_port->prepare_rx = NULL;
1787 atmel_port->schedule_rx = &atmel_rx_from_ring;
1788 atmel_port->release_rx = NULL;
1791 if (atmel_use_dma_tx(port)) {
1792 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1793 atmel_port->schedule_tx = &atmel_tx_dma;
1794 atmel_port->release_tx = &atmel_release_tx_dma;
1795 } else if (atmel_use_pdc_tx(port)) {
1796 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1797 atmel_port->schedule_tx = &atmel_tx_pdc;
1798 atmel_port->release_tx = &atmel_release_tx_pdc;
1800 atmel_port->prepare_tx = NULL;
1801 atmel_port->schedule_tx = &atmel_tx_chars;
1802 atmel_port->release_tx = NULL;
1807 * Get ip name usart or uart
1809 static void atmel_get_ip_name(struct uart_port *port)
1811 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1812 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1814 u32 usart, dbgu_uart, new_uart;
1815 /* ASCII decoding for IP version */
1816 usart = 0x55534152; /* USAR(T) */
1817 dbgu_uart = 0x44424755; /* DBGU */
1818 new_uart = 0x55415254; /* UART */
1821 * Only USART devices from at91sam9260 SOC implement fractional
1822 * baudrate. It is available for all asynchronous modes, with the
1823 * following restriction: the sampling clock's duty cycle is not
1826 atmel_port->has_frac_baudrate = false;
1827 atmel_port->has_hw_timer = false;
1829 if (name == new_uart) {
1830 dev_dbg(port->dev, "Uart with hw timer");
1831 atmel_port->has_hw_timer = true;
1832 atmel_port->rtor = ATMEL_UA_RTOR;
1833 } else if (name == usart) {
1834 dev_dbg(port->dev, "Usart\n");
1835 atmel_port->has_frac_baudrate = true;
1836 atmel_port->has_hw_timer = true;
1837 atmel_port->rtor = ATMEL_US_RTOR;
1838 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1840 case 0x814: /* sama5d2 */
1842 case 0x701: /* sama5d4 */
1843 atmel_port->fidi_min = 3;
1844 atmel_port->fidi_max = 65535;
1846 case 0x502: /* sam9x5, sama5d3 */
1847 atmel_port->fidi_min = 3;
1848 atmel_port->fidi_max = 2047;
1851 atmel_port->fidi_min = 1;
1852 atmel_port->fidi_max = 2047;
1854 } else if (name == dbgu_uart) {
1855 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1857 /* fallback for older SoCs: use version field */
1858 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1863 dev_dbg(port->dev, "This version is usart\n");
1864 atmel_port->has_frac_baudrate = true;
1865 atmel_port->has_hw_timer = true;
1866 atmel_port->rtor = ATMEL_US_RTOR;
1870 dev_dbg(port->dev, "This version is uart\n");
1873 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1879 * Perform initialization and enable port for reception
1881 static int atmel_startup(struct uart_port *port)
1883 struct platform_device *pdev = to_platform_device(port->dev);
1884 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1888 * Ensure that no interrupts are enabled otherwise when
1889 * request_irq() is called we could get stuck trying to
1890 * handle an unexpected interrupt
1892 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1893 atmel_port->ms_irq_enabled = false;
1898 retval = request_irq(port->irq, atmel_interrupt,
1899 IRQF_SHARED | IRQF_COND_SUSPEND,
1900 dev_name(&pdev->dev), port);
1902 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1906 atomic_set(&atmel_port->tasklet_shutdown, 0);
1907 tasklet_setup(&atmel_port->tasklet_rx, atmel_tasklet_rx_func);
1908 tasklet_setup(&atmel_port->tasklet_tx, atmel_tasklet_tx_func);
1911 * Initialize DMA (if necessary)
1913 atmel_init_property(atmel_port, pdev);
1914 atmel_set_ops(port);
1916 if (atmel_port->prepare_rx) {
1917 retval = atmel_port->prepare_rx(port);
1919 atmel_set_ops(port);
1922 if (atmel_port->prepare_tx) {
1923 retval = atmel_port->prepare_tx(port);
1925 atmel_set_ops(port);
1929 * Enable FIFO when available
1931 if (atmel_port->fifo_size) {
1932 unsigned int txrdym = ATMEL_US_ONE_DATA;
1933 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1936 atmel_uart_writel(port, ATMEL_US_CR,
1941 if (atmel_use_dma_tx(port))
1942 txrdym = ATMEL_US_FOUR_DATA;
1944 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1945 if (atmel_port->rts_high &&
1946 atmel_port->rts_low)
1947 fmr |= ATMEL_US_FRTSC |
1948 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1949 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1951 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1954 /* Save current CSR for comparison in atmel_tasklet_func() */
1955 atmel_port->irq_status_prev = atmel_uart_readl(port, ATMEL_US_CSR);
1958 * Finally, enable the serial port
1960 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1961 /* enable xmit & rcvr */
1962 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1963 atmel_port->tx_stopped = false;
1965 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1967 if (atmel_use_pdc_rx(port)) {
1968 /* set UART timeout */
1969 if (!atmel_port->has_hw_timer) {
1970 mod_timer(&atmel_port->uart_timer,
1971 jiffies + uart_poll_timeout(port));
1972 /* set USART timeout */
1974 atmel_uart_writel(port, atmel_port->rtor,
1976 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1978 atmel_uart_writel(port, ATMEL_US_IER,
1979 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1981 /* enable PDC controller */
1982 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1983 } else if (atmel_use_dma_rx(port)) {
1984 /* set UART timeout */
1985 if (!atmel_port->has_hw_timer) {
1986 mod_timer(&atmel_port->uart_timer,
1987 jiffies + uart_poll_timeout(port));
1988 /* set USART timeout */
1990 atmel_uart_writel(port, atmel_port->rtor,
1992 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1994 atmel_uart_writel(port, ATMEL_US_IER,
1998 /* enable receive only */
1999 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
2006 * Flush any TX data submitted for DMA. Called when the TX circular
2009 static void atmel_flush_buffer(struct uart_port *port)
2011 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2013 if (atmel_use_pdc_tx(port)) {
2014 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
2015 atmel_port->pdc_tx.ofs = 0;
2018 * in uart_flush_buffer(), the xmit circular buffer has just
2019 * been cleared, so we have to reset tx_len accordingly.
2021 atmel_port->tx_len = 0;
2027 static void atmel_shutdown(struct uart_port *port)
2029 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2031 /* Disable modem control lines interrupts */
2032 atmel_disable_ms(port);
2034 /* Disable interrupts at device level */
2035 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2037 /* Prevent spurious interrupts from scheduling the tasklet */
2038 atomic_inc(&atmel_port->tasklet_shutdown);
2041 * Prevent any tasklets being scheduled during
2044 del_timer_sync(&atmel_port->uart_timer);
2046 /* Make sure that no interrupt is on the fly */
2047 synchronize_irq(port->irq);
2050 * Clear out any scheduled tasklets before
2051 * we destroy the buffers
2053 tasklet_kill(&atmel_port->tasklet_rx);
2054 tasklet_kill(&atmel_port->tasklet_tx);
2057 * Ensure everything is stopped and
2058 * disable port and break condition.
2060 atmel_stop_rx(port);
2061 atmel_stop_tx(port);
2063 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
2066 * Shut-down the DMA.
2068 if (atmel_port->release_rx)
2069 atmel_port->release_rx(port);
2070 if (atmel_port->release_tx)
2071 atmel_port->release_tx(port);
2074 * Reset ring buffer pointers
2076 atmel_port->rx_ring.head = 0;
2077 atmel_port->rx_ring.tail = 0;
2080 * Free the interrupts
2082 free_irq(port->irq, port);
2084 atmel_flush_buffer(port);
2088 * Power / Clock management.
2090 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
2091 unsigned int oldstate)
2093 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2096 case UART_PM_STATE_ON:
2098 * Enable the peripheral clock for this serial port.
2099 * This is called on uart_open() or a resume event.
2101 clk_prepare_enable(atmel_port->clk);
2103 /* re-enable interrupts if we disabled some on suspend */
2104 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2106 case UART_PM_STATE_OFF:
2107 /* Back up the interrupt mask and disable all interrupts */
2108 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2109 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2112 * Disable the peripheral clock for this serial port.
2113 * This is called on uart_close() or a suspend event.
2115 clk_disable_unprepare(atmel_port->clk);
2118 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2123 * Change the port parameters
2125 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2126 struct ktermios *old)
2128 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2129 unsigned long flags;
2130 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2132 /* save the current mode register */
2133 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2135 /* reset the mode, clock divisor, parity, stop bits and data size */
2136 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2137 ATMEL_US_PAR | ATMEL_US_USMODE);
2139 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2142 switch (termios->c_cflag & CSIZE) {
2144 mode |= ATMEL_US_CHRL_5;
2147 mode |= ATMEL_US_CHRL_6;
2150 mode |= ATMEL_US_CHRL_7;
2153 mode |= ATMEL_US_CHRL_8;
2158 if (termios->c_cflag & CSTOPB)
2159 mode |= ATMEL_US_NBSTOP_2;
2162 if (termios->c_cflag & PARENB) {
2163 /* Mark or Space parity */
2164 if (termios->c_cflag & CMSPAR) {
2165 if (termios->c_cflag & PARODD)
2166 mode |= ATMEL_US_PAR_MARK;
2168 mode |= ATMEL_US_PAR_SPACE;
2169 } else if (termios->c_cflag & PARODD)
2170 mode |= ATMEL_US_PAR_ODD;
2172 mode |= ATMEL_US_PAR_EVEN;
2174 mode |= ATMEL_US_PAR_NONE;
2176 spin_lock_irqsave(&port->lock, flags);
2178 port->read_status_mask = ATMEL_US_OVRE;
2179 if (termios->c_iflag & INPCK)
2180 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2181 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2182 port->read_status_mask |= ATMEL_US_RXBRK;
2184 if (atmel_use_pdc_rx(port))
2185 /* need to enable error interrupts */
2186 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2189 * Characters to ignore
2191 port->ignore_status_mask = 0;
2192 if (termios->c_iflag & IGNPAR)
2193 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2194 if (termios->c_iflag & IGNBRK) {
2195 port->ignore_status_mask |= ATMEL_US_RXBRK;
2197 * If we're ignoring parity and break indicators,
2198 * ignore overruns too (for real raw support).
2200 if (termios->c_iflag & IGNPAR)
2201 port->ignore_status_mask |= ATMEL_US_OVRE;
2203 /* TODO: Ignore all characters if CREAD is set.*/
2205 /* update the per-port timeout */
2206 uart_update_timeout(port, termios->c_cflag, baud);
2209 * save/disable interrupts. The tty layer will ensure that the
2210 * transmitter is empty if requested by the caller, so there's
2211 * no need to wait for it here.
2213 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2214 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2216 /* disable receiver and transmitter */
2217 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2218 atmel_port->tx_stopped = true;
2221 if (port->rs485.flags & SER_RS485_ENABLED) {
2222 atmel_uart_writel(port, ATMEL_US_TTGR,
2223 port->rs485.delay_rts_after_send);
2224 mode |= ATMEL_US_USMODE_RS485;
2225 } else if (port->iso7816.flags & SER_ISO7816_ENABLED) {
2226 atmel_uart_writel(port, ATMEL_US_TTGR, port->iso7816.tg);
2227 /* select mck clock, and output */
2228 mode |= ATMEL_US_USCLKS_MCK | ATMEL_US_CLKO;
2229 /* set max iterations */
2230 mode |= ATMEL_US_MAX_ITER(3);
2231 if ((port->iso7816.flags & SER_ISO7816_T_PARAM)
2232 == SER_ISO7816_T(0))
2233 mode |= ATMEL_US_USMODE_ISO7816_T0;
2235 mode |= ATMEL_US_USMODE_ISO7816_T1;
2236 } else if (termios->c_cflag & CRTSCTS) {
2237 /* RS232 with hardware handshake (RTS/CTS) */
2238 if (atmel_use_fifo(port) &&
2239 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2241 * with ATMEL_US_USMODE_HWHS set, the controller will
2242 * be able to drive the RTS pin high/low when the RX
2243 * FIFO is above RXFTHRES/below RXFTHRES2.
2244 * It will also disable the transmitter when the CTS
2246 * This mode is not activated if CTS pin is a GPIO
2247 * because in this case, the transmitter is always
2248 * disabled (there must be an internal pull-up
2249 * responsible for this behaviour).
2250 * If the RTS pin is a GPIO, the controller won't be
2251 * able to drive it according to the FIFO thresholds,
2252 * but it will be handled by the driver.
2254 mode |= ATMEL_US_USMODE_HWHS;
2257 * For platforms without FIFO, the flow control is
2258 * handled by the driver.
2260 mode |= ATMEL_US_USMODE_NORMAL;
2263 /* RS232 without hadware handshake */
2264 mode |= ATMEL_US_USMODE_NORMAL;
2268 * Set the baud rate:
2269 * Fractional baudrate allows to setup output frequency more
2270 * accurately. This feature is enabled only when using normal mode.
2271 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2272 * Currently, OVER is always set to 0 so we get
2273 * baudrate = selected clock / (16 * (CD + FP / 8))
2275 * 8 CD + FP = selected clock / (2 * baudrate)
2277 if (atmel_port->has_frac_baudrate) {
2278 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2280 fp = div & ATMEL_US_FP_MASK;
2282 cd = uart_get_divisor(port, baud);
2285 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2287 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2289 quot = cd | fp << ATMEL_US_FP_OFFSET;
2291 if (!(port->iso7816.flags & SER_ISO7816_ENABLED))
2292 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2294 /* set the mode, clock divisor, parity, stop bits and data size */
2295 atmel_uart_writel(port, ATMEL_US_MR, mode);
2298 * when switching the mode, set the RTS line state according to the
2299 * new mode, otherwise keep the former state
2301 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2302 unsigned int rts_state;
2304 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2305 /* let the hardware control the RTS line */
2306 rts_state = ATMEL_US_RTSDIS;
2308 /* force RTS line to low level */
2309 rts_state = ATMEL_US_RTSEN;
2312 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2315 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2316 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2317 atmel_port->tx_stopped = false;
2319 /* restore interrupts */
2320 atmel_uart_writel(port, ATMEL_US_IER, imr);
2322 /* CTS flow-control and modem-status interrupts */
2323 if (UART_ENABLE_MS(port, termios->c_cflag))
2324 atmel_enable_ms(port);
2326 atmel_disable_ms(port);
2328 spin_unlock_irqrestore(&port->lock, flags);
2331 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2333 if (termios->c_line == N_PPS) {
2334 port->flags |= UPF_HARDPPS_CD;
2335 spin_lock_irq(&port->lock);
2336 atmel_enable_ms(port);
2337 spin_unlock_irq(&port->lock);
2339 port->flags &= ~UPF_HARDPPS_CD;
2340 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2341 spin_lock_irq(&port->lock);
2342 atmel_disable_ms(port);
2343 spin_unlock_irq(&port->lock);
2349 * Return string describing the specified port
2351 static const char *atmel_type(struct uart_port *port)
2353 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2357 * Release the memory region(s) being used by 'port'.
2359 static void atmel_release_port(struct uart_port *port)
2361 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2362 int size = resource_size(mpdev->resource);
2364 release_mem_region(port->mapbase, size);
2366 if (port->flags & UPF_IOREMAP) {
2367 iounmap(port->membase);
2368 port->membase = NULL;
2373 * Request the memory region(s) being used by 'port'.
2375 static int atmel_request_port(struct uart_port *port)
2377 struct platform_device *mpdev = to_platform_device(port->dev->parent);
2378 int size = resource_size(mpdev->resource);
2380 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2383 if (port->flags & UPF_IOREMAP) {
2384 port->membase = ioremap(port->mapbase, size);
2385 if (port->membase == NULL) {
2386 release_mem_region(port->mapbase, size);
2395 * Configure/autoconfigure the port.
2397 static void atmel_config_port(struct uart_port *port, int flags)
2399 if (flags & UART_CONFIG_TYPE) {
2400 port->type = PORT_ATMEL;
2401 atmel_request_port(port);
2406 * Verify the new serial_struct (for TIOCSSERIAL).
2408 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2411 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2413 if (port->irq != ser->irq)
2415 if (ser->io_type != SERIAL_IO_MEM)
2417 if (port->uartclk / 16 != ser->baud_base)
2419 if (port->mapbase != (unsigned long)ser->iomem_base)
2421 if (port->iobase != ser->port)
2428 #ifdef CONFIG_CONSOLE_POLL
2429 static int atmel_poll_get_char(struct uart_port *port)
2431 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2434 return atmel_uart_read_char(port);
2437 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2439 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2442 atmel_uart_write_char(port, ch);
2446 static const struct uart_ops atmel_pops = {
2447 .tx_empty = atmel_tx_empty,
2448 .set_mctrl = atmel_set_mctrl,
2449 .get_mctrl = atmel_get_mctrl,
2450 .stop_tx = atmel_stop_tx,
2451 .start_tx = atmel_start_tx,
2452 .stop_rx = atmel_stop_rx,
2453 .enable_ms = atmel_enable_ms,
2454 .break_ctl = atmel_break_ctl,
2455 .startup = atmel_startup,
2456 .shutdown = atmel_shutdown,
2457 .flush_buffer = atmel_flush_buffer,
2458 .set_termios = atmel_set_termios,
2459 .set_ldisc = atmel_set_ldisc,
2461 .release_port = atmel_release_port,
2462 .request_port = atmel_request_port,
2463 .config_port = atmel_config_port,
2464 .verify_port = atmel_verify_port,
2465 .pm = atmel_serial_pm,
2466 #ifdef CONFIG_CONSOLE_POLL
2467 .poll_get_char = atmel_poll_get_char,
2468 .poll_put_char = atmel_poll_put_char,
2472 static const struct serial_rs485 atmel_rs485_supported = {
2473 .flags = SER_RS485_ENABLED | SER_RS485_RTS_AFTER_SEND | SER_RS485_RX_DURING_TX,
2474 .delay_rts_before_send = 1,
2475 .delay_rts_after_send = 1,
2479 * Configure the port from the platform device resource info.
2481 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2482 struct platform_device *pdev)
2485 struct uart_port *port = &atmel_port->uart;
2486 struct platform_device *mpdev = to_platform_device(pdev->dev.parent);
2488 atmel_init_property(atmel_port, pdev);
2489 atmel_set_ops(port);
2491 port->iotype = UPIO_MEM;
2492 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2493 port->ops = &atmel_pops;
2495 port->dev = &pdev->dev;
2496 port->mapbase = mpdev->resource[0].start;
2497 port->irq = platform_get_irq(mpdev, 0);
2498 port->rs485_config = atmel_config_rs485;
2499 port->rs485_supported = atmel_rs485_supported;
2500 port->iso7816_config = atmel_config_iso7816;
2501 port->membase = NULL;
2503 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2505 ret = uart_get_rs485_mode(port);
2509 port->uartclk = clk_get_rate(atmel_port->clk);
2512 * Use TXEMPTY for interrupt when rs485 or ISO7816 else TXRDY or
2515 if (atmel_uart_is_half_duplex(port))
2516 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2517 else if (atmel_use_pdc_tx(port)) {
2518 port->fifosize = PDC_BUFFER_SIZE;
2519 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2521 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2527 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2528 static void atmel_console_putchar(struct uart_port *port, unsigned char ch)
2530 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2532 atmel_uart_write_char(port, ch);
2536 * Interrupts are disabled on entering
2538 static void atmel_console_write(struct console *co, const char *s, u_int count)
2540 struct uart_port *port = &atmel_ports[co->index].uart;
2541 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2542 unsigned int status, imr;
2543 unsigned int pdc_tx;
2546 * First, save IMR and then disable interrupts
2548 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2549 atmel_uart_writel(port, ATMEL_US_IDR,
2550 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2552 /* Store PDC transmit status and disable it */
2553 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2554 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2556 /* Make sure that tx path is actually able to send characters */
2557 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2558 atmel_port->tx_stopped = false;
2560 uart_console_write(port, s, count, atmel_console_putchar);
2563 * Finally, wait for transmitter to become empty
2567 status = atmel_uart_readl(port, ATMEL_US_CSR);
2568 } while (!(status & ATMEL_US_TXRDY));
2570 /* Restore PDC transmit status */
2572 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2574 /* set interrupts back the way they were */
2575 atmel_uart_writel(port, ATMEL_US_IER, imr);
2579 * If the port was already initialised (eg, by a boot loader),
2580 * try to determine the current setup.
2582 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2583 int *parity, int *bits)
2585 unsigned int mr, quot;
2588 * If the baud rate generator isn't running, the port wasn't
2589 * initialized by the boot loader.
2591 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2595 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2596 if (mr == ATMEL_US_CHRL_8)
2601 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2602 if (mr == ATMEL_US_PAR_EVEN)
2604 else if (mr == ATMEL_US_PAR_ODD)
2608 * The serial core only rounds down when matching this to a
2609 * supported baud rate. Make sure we don't end up slightly
2610 * lower than one of those, as it would make us fall through
2611 * to a much lower baud rate than we really want.
2613 *baud = port->uartclk / (16 * (quot - 1));
2616 static int __init atmel_console_setup(struct console *co, char *options)
2618 struct uart_port *port = &atmel_ports[co->index].uart;
2619 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2625 if (port->membase == NULL) {
2626 /* Port not initialized yet - delay setup */
2630 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2631 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2632 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2633 atmel_port->tx_stopped = false;
2636 uart_parse_options(options, &baud, &parity, &bits, &flow);
2638 atmel_console_get_options(port, &baud, &parity, &bits);
2640 return uart_set_options(port, co, baud, parity, bits, flow);
2643 static struct uart_driver atmel_uart;
2645 static struct console atmel_console = {
2646 .name = ATMEL_DEVICENAME,
2647 .write = atmel_console_write,
2648 .device = uart_console_device,
2649 .setup = atmel_console_setup,
2650 .flags = CON_PRINTBUFFER,
2652 .data = &atmel_uart,
2655 static void atmel_serial_early_write(struct console *con, const char *s,
2658 struct earlycon_device *dev = con->data;
2660 uart_console_write(&dev->port, s, n, atmel_console_putchar);
2663 static int __init atmel_early_console_setup(struct earlycon_device *device,
2664 const char *options)
2666 if (!device->port.membase)
2669 device->con->write = atmel_serial_early_write;
2674 OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91rm9200-usart",
2675 atmel_early_console_setup);
2676 OF_EARLYCON_DECLARE(atmel_serial, "atmel,at91sam9260-usart",
2677 atmel_early_console_setup);
2679 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2682 #define ATMEL_CONSOLE_DEVICE NULL
2685 static struct uart_driver atmel_uart = {
2686 .owner = THIS_MODULE,
2687 .driver_name = "atmel_serial",
2688 .dev_name = ATMEL_DEVICENAME,
2689 .major = SERIAL_ATMEL_MAJOR,
2690 .minor = MINOR_START,
2691 .nr = ATMEL_MAX_UART,
2692 .cons = ATMEL_CONSOLE_DEVICE,
2695 static bool atmel_serial_clk_will_stop(void)
2697 #ifdef CONFIG_ARCH_AT91
2698 return at91_suspend_entering_slow_clock();
2704 static int __maybe_unused atmel_serial_suspend(struct device *dev)
2706 struct uart_port *port = dev_get_drvdata(dev);
2707 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2709 if (uart_console(port) && console_suspend_enabled) {
2710 /* Drain the TX shifter */
2711 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2716 if (uart_console(port) && !console_suspend_enabled) {
2717 /* Cache register values as we won't get a full shutdown/startup
2720 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2721 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2722 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2723 atmel_port->cache.rtor = atmel_uart_readl(port,
2725 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2726 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2727 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2730 /* we can not wake up if we're running on slow clock */
2731 atmel_port->may_wakeup = device_may_wakeup(dev);
2732 if (atmel_serial_clk_will_stop()) {
2733 unsigned long flags;
2735 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2736 atmel_port->suspended = true;
2737 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2738 device_set_wakeup_enable(dev, 0);
2741 uart_suspend_port(&atmel_uart, port);
2746 static int __maybe_unused atmel_serial_resume(struct device *dev)
2748 struct uart_port *port = dev_get_drvdata(dev);
2749 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2750 unsigned long flags;
2752 if (uart_console(port) && !console_suspend_enabled) {
2753 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2754 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2755 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2756 atmel_uart_writel(port, atmel_port->rtor,
2757 atmel_port->cache.rtor);
2758 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2760 if (atmel_port->fifo_size) {
2761 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2762 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2763 atmel_uart_writel(port, ATMEL_US_FMR,
2764 atmel_port->cache.fmr);
2765 atmel_uart_writel(port, ATMEL_US_FIER,
2766 atmel_port->cache.fimr);
2768 atmel_start_rx(port);
2771 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2772 if (atmel_port->pending) {
2773 atmel_handle_receive(port, atmel_port->pending);
2774 atmel_handle_status(port, atmel_port->pending,
2775 atmel_port->pending_status);
2776 atmel_handle_transmit(port, atmel_port->pending);
2777 atmel_port->pending = 0;
2779 atmel_port->suspended = false;
2780 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2782 uart_resume_port(&atmel_uart, port);
2783 device_set_wakeup_enable(dev, atmel_port->may_wakeup);
2788 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2789 struct platform_device *pdev)
2791 atmel_port->fifo_size = 0;
2792 atmel_port->rts_low = 0;
2793 atmel_port->rts_high = 0;
2795 if (of_property_read_u32(pdev->dev.of_node,
2797 &atmel_port->fifo_size))
2800 if (!atmel_port->fifo_size)
2803 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2804 atmel_port->fifo_size = 0;
2805 dev_err(&pdev->dev, "Invalid FIFO size\n");
2810 * 0 <= rts_low <= rts_high <= fifo_size
2811 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2812 * to flush their internal TX FIFO, commonly up to 16 data, before
2813 * actually stopping to send new data. So we try to set the RTS High
2814 * Threshold to a reasonably high value respecting this 16 data
2815 * empirical rule when possible.
2817 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2818 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2819 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2820 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2822 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2823 atmel_port->fifo_size);
2824 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2825 atmel_port->rts_high);
2826 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2827 atmel_port->rts_low);
2830 static int atmel_serial_probe(struct platform_device *pdev)
2832 struct atmel_uart_port *atmel_port;
2833 struct device_node *np = pdev->dev.parent->of_node;
2838 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2841 * In device tree there is no node with "atmel,at91rm9200-usart-serial"
2842 * as compatible string. This driver is probed by at91-usart mfd driver
2843 * which is just a wrapper over the atmel_serial driver and
2844 * spi-at91-usart driver. All attributes needed by this driver are
2845 * found in of_node of parent.
2847 pdev->dev.of_node = np;
2849 ret = of_alias_get_id(np, "serial");
2851 /* port id not found in platform data nor device-tree aliases:
2852 * auto-enumerate it */
2853 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2855 if (ret >= ATMEL_MAX_UART) {
2860 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2861 /* port already in use */
2866 atmel_port = &atmel_ports[ret];
2867 atmel_port->backup_imr = 0;
2868 atmel_port->uart.line = ret;
2869 atmel_port->uart.has_sysrq = IS_ENABLED(CONFIG_SERIAL_ATMEL_CONSOLE);
2870 atmel_serial_probe_fifos(atmel_port, pdev);
2872 atomic_set(&atmel_port->tasklet_shutdown, 0);
2873 spin_lock_init(&atmel_port->lock_suspended);
2875 atmel_port->clk = devm_clk_get(&pdev->dev, "usart");
2876 if (IS_ERR(atmel_port->clk)) {
2877 ret = PTR_ERR(atmel_port->clk);
2880 ret = clk_prepare_enable(atmel_port->clk);
2884 ret = atmel_init_port(atmel_port, pdev);
2886 goto err_clk_disable_unprepare;
2888 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2889 if (IS_ERR(atmel_port->gpios)) {
2890 ret = PTR_ERR(atmel_port->gpios);
2891 goto err_clk_disable_unprepare;
2894 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2896 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2897 sizeof(struct atmel_uart_char),
2900 goto err_clk_disable_unprepare;
2901 atmel_port->rx_ring.buf = data;
2904 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2906 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2910 device_init_wakeup(&pdev->dev, 1);
2911 platform_set_drvdata(pdev, atmel_port);
2913 if (rs485_enabled) {
2914 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2915 ATMEL_US_USMODE_NORMAL);
2916 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2921 * Get port name of usart or uart
2923 atmel_get_ip_name(&atmel_port->uart);
2926 * The peripheral clock can now safely be disabled till the port
2929 clk_disable_unprepare(atmel_port->clk);
2934 kfree(atmel_port->rx_ring.buf);
2935 atmel_port->rx_ring.buf = NULL;
2936 err_clk_disable_unprepare:
2937 clk_disable_unprepare(atmel_port->clk);
2938 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2944 * Even if the driver is not modular, it makes sense to be able to
2945 * unbind a device: there can be many bound devices, and there are
2946 * situations where dynamic binding and unbinding can be useful.
2948 * For example, a connected device can require a specific firmware update
2949 * protocol that needs bitbanging on IO lines, but use the regular serial
2950 * port in the normal case.
2952 static int atmel_serial_remove(struct platform_device *pdev)
2954 struct uart_port *port = platform_get_drvdata(pdev);
2955 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2958 tasklet_kill(&atmel_port->tasklet_rx);
2959 tasklet_kill(&atmel_port->tasklet_tx);
2961 device_init_wakeup(&pdev->dev, 0);
2963 ret = uart_remove_one_port(&atmel_uart, port);
2965 kfree(atmel_port->rx_ring.buf);
2967 /* "port" is allocated statically, so we shouldn't free it */
2969 clear_bit(port->line, atmel_ports_in_use);
2971 pdev->dev.of_node = NULL;
2976 static SIMPLE_DEV_PM_OPS(atmel_serial_pm_ops, atmel_serial_suspend,
2977 atmel_serial_resume);
2979 static struct platform_driver atmel_serial_driver = {
2980 .probe = atmel_serial_probe,
2981 .remove = atmel_serial_remove,
2983 .name = "atmel_usart_serial",
2984 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2985 .pm = pm_ptr(&atmel_serial_pm_ops),
2989 static int __init atmel_serial_init(void)
2993 ret = uart_register_driver(&atmel_uart);
2997 ret = platform_driver_register(&atmel_serial_driver);
2999 uart_unregister_driver(&atmel_uart);
3003 device_initcall(atmel_serial_init);