1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Atmel AT91 Serial ports
4 * Copyright (C) 2003 Rick Bronson
6 * Based on drivers/char/serial_sa1100.c, by Deep Blue Solutions Ltd.
7 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
9 * DMA support added by Chip Coldwell.
11 #include <linux/tty.h>
12 #include <linux/ioport.h>
13 #include <linux/slab.h>
14 #include <linux/init.h>
15 #include <linux/serial.h>
16 #include <linux/clk.h>
17 #include <linux/console.h>
18 #include <linux/sysrq.h>
19 #include <linux/tty_flip.h>
20 #include <linux/platform_device.h>
22 #include <linux/of_device.h>
23 #include <linux/of_gpio.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/dmaengine.h>
26 #include <linux/atmel_pdc.h>
27 #include <linux/uaccess.h>
28 #include <linux/platform_data/atmel.h>
29 #include <linux/timer.h>
30 #include <linux/gpio.h>
31 #include <linux/gpio/consumer.h>
32 #include <linux/err.h>
33 #include <linux/irq.h>
34 #include <linux/suspend.h>
38 #include <asm/ioctls.h>
40 #define PDC_BUFFER_SIZE 512
41 /* Revisit: We should calculate this based on the actual port settings */
42 #define PDC_RX_TIMEOUT (3 * 10) /* 3 bytes */
44 /* The minium number of data FIFOs should be able to contain */
45 #define ATMEL_MIN_FIFO_SIZE 8
47 * These two offsets are substracted from the RX FIFO size to define the RTS
48 * high and low thresholds
50 #define ATMEL_RTS_HIGH_OFFSET 16
51 #define ATMEL_RTS_LOW_OFFSET 20
53 #if defined(CONFIG_SERIAL_ATMEL_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
57 #include <linux/serial_core.h>
59 #include "serial_mctrl_gpio.h"
60 #include "atmel_serial.h"
62 static void atmel_start_rx(struct uart_port *port);
63 static void atmel_stop_rx(struct uart_port *port);
65 #ifdef CONFIG_SERIAL_ATMEL_TTYAT
67 /* Use device name ttyAT, major 204 and minor 154-169. This is necessary if we
68 * should coexist with the 8250 driver, such as if we have an external 16C550
70 #define SERIAL_ATMEL_MAJOR 204
71 #define MINOR_START 154
72 #define ATMEL_DEVICENAME "ttyAT"
76 /* Use device name ttyS, major 4, minor 64-68. This is the usual serial port
77 * name, but it is legally reserved for the 8250 driver. */
78 #define SERIAL_ATMEL_MAJOR TTY_MAJOR
79 #define MINOR_START 64
80 #define ATMEL_DEVICENAME "ttyS"
84 #define ATMEL_ISR_PASS_LIMIT 256
86 struct atmel_dma_buffer {
89 unsigned int dma_size;
93 struct atmel_uart_char {
99 * Be careful, the real size of the ring buffer is
100 * sizeof(atmel_uart_char) * ATMEL_SERIAL_RINGSIZE. It means that ring buffer
101 * can contain up to 1024 characters in PIO mode and up to 4096 characters in
104 #define ATMEL_SERIAL_RINGSIZE 1024
107 * at91: 6 USARTs and one DBGU port (SAM9260)
108 * samx7: 3 USARTs and 5 UARTs
110 #define ATMEL_MAX_UART 8
113 * We wrap our port structure around the generic uart_port.
115 struct atmel_uart_port {
116 struct uart_port uart; /* uart */
117 struct clk *clk; /* uart clock */
118 int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */
119 u32 backup_imr; /* IMR saved during suspend */
120 int break_active; /* break being received */
122 bool use_dma_rx; /* enable DMA receiver */
123 bool use_pdc_rx; /* enable PDC receiver */
124 short pdc_rx_idx; /* current PDC RX buffer */
125 struct atmel_dma_buffer pdc_rx[2]; /* PDC receier */
127 bool use_dma_tx; /* enable DMA transmitter */
128 bool use_pdc_tx; /* enable PDC transmitter */
129 struct atmel_dma_buffer pdc_tx; /* PDC transmitter */
131 spinlock_t lock_tx; /* port lock */
132 spinlock_t lock_rx; /* port lock */
133 struct dma_chan *chan_tx;
134 struct dma_chan *chan_rx;
135 struct dma_async_tx_descriptor *desc_tx;
136 struct dma_async_tx_descriptor *desc_rx;
137 dma_cookie_t cookie_tx;
138 dma_cookie_t cookie_rx;
139 struct scatterlist sg_tx;
140 struct scatterlist sg_rx;
141 struct tasklet_struct tasklet_rx;
142 struct tasklet_struct tasklet_tx;
143 atomic_t tasklet_shutdown;
144 unsigned int irq_status_prev;
147 struct circ_buf rx_ring;
149 struct mctrl_gpios *gpios;
150 unsigned int tx_done_mask;
155 u32 rtor; /* address of receiver timeout register if it exists */
156 bool has_frac_baudrate;
158 struct timer_list uart_timer;
162 unsigned int pending;
163 unsigned int pending_status;
164 spinlock_t lock_suspended;
166 bool hd_start_rx; /* can start RX during half-duplex operation */
181 int (*prepare_rx)(struct uart_port *port);
182 int (*prepare_tx)(struct uart_port *port);
183 void (*schedule_rx)(struct uart_port *port);
184 void (*schedule_tx)(struct uart_port *port);
185 void (*release_rx)(struct uart_port *port);
186 void (*release_tx)(struct uart_port *port);
189 static struct atmel_uart_port atmel_ports[ATMEL_MAX_UART];
190 static DECLARE_BITMAP(atmel_ports_in_use, ATMEL_MAX_UART);
193 static struct console atmel_console;
196 #if defined(CONFIG_OF)
197 static const struct of_device_id atmel_serial_dt_ids[] = {
198 { .compatible = "atmel,at91rm9200-usart" },
199 { .compatible = "atmel,at91sam9260-usart" },
204 static inline struct atmel_uart_port *
205 to_atmel_uart_port(struct uart_port *uart)
207 return container_of(uart, struct atmel_uart_port, uart);
210 static inline u32 atmel_uart_readl(struct uart_port *port, u32 reg)
212 return __raw_readl(port->membase + reg);
215 static inline void atmel_uart_writel(struct uart_port *port, u32 reg, u32 value)
217 __raw_writel(value, port->membase + reg);
220 static inline u8 atmel_uart_read_char(struct uart_port *port)
222 return __raw_readb(port->membase + ATMEL_US_RHR);
225 static inline void atmel_uart_write_char(struct uart_port *port, u8 value)
227 __raw_writeb(value, port->membase + ATMEL_US_THR);
230 static inline int atmel_uart_is_half_duplex(struct uart_port *port)
232 return (port->rs485.flags & SER_RS485_ENABLED) &&
233 !(port->rs485.flags & SER_RS485_RX_DURING_TX);
236 #ifdef CONFIG_SERIAL_ATMEL_PDC
237 static bool atmel_use_pdc_rx(struct uart_port *port)
239 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
241 return atmel_port->use_pdc_rx;
244 static bool atmel_use_pdc_tx(struct uart_port *port)
246 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
248 return atmel_port->use_pdc_tx;
251 static bool atmel_use_pdc_rx(struct uart_port *port)
256 static bool atmel_use_pdc_tx(struct uart_port *port)
262 static bool atmel_use_dma_tx(struct uart_port *port)
264 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
266 return atmel_port->use_dma_tx;
269 static bool atmel_use_dma_rx(struct uart_port *port)
271 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
273 return atmel_port->use_dma_rx;
276 static bool atmel_use_fifo(struct uart_port *port)
278 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
280 return atmel_port->fifo_size;
283 static void atmel_tasklet_schedule(struct atmel_uart_port *atmel_port,
284 struct tasklet_struct *t)
286 if (!atomic_read(&atmel_port->tasklet_shutdown))
290 static unsigned int atmel_get_lines_status(struct uart_port *port)
292 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
293 unsigned int status, ret = 0;
295 status = atmel_uart_readl(port, ATMEL_US_CSR);
297 mctrl_gpio_get(atmel_port->gpios, &ret);
299 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
302 status &= ~ATMEL_US_CTS;
304 status |= ATMEL_US_CTS;
307 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
310 status &= ~ATMEL_US_DSR;
312 status |= ATMEL_US_DSR;
315 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
318 status &= ~ATMEL_US_RI;
320 status |= ATMEL_US_RI;
323 if (!IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(atmel_port->gpios,
326 status &= ~ATMEL_US_DCD;
328 status |= ATMEL_US_DCD;
334 /* Enable or disable the rs485 support */
335 static int atmel_config_rs485(struct uart_port *port,
336 struct serial_rs485 *rs485conf)
338 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
341 /* Disable interrupts */
342 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
344 mode = atmel_uart_readl(port, ATMEL_US_MR);
346 /* Resetting serial mode to RS232 (0x0) */
347 mode &= ~ATMEL_US_USMODE;
349 port->rs485 = *rs485conf;
351 if (rs485conf->flags & SER_RS485_ENABLED) {
352 dev_dbg(port->dev, "Setting UART to RS485\n");
353 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
354 atmel_uart_writel(port, ATMEL_US_TTGR,
355 rs485conf->delay_rts_after_send);
356 mode |= ATMEL_US_USMODE_RS485;
358 dev_dbg(port->dev, "Setting UART to RS232\n");
359 if (atmel_use_pdc_tx(port))
360 atmel_port->tx_done_mask = ATMEL_US_ENDTX |
363 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
365 atmel_uart_writel(port, ATMEL_US_MR, mode);
367 /* Enable interrupts */
368 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
374 * Return TIOCSER_TEMT when transmitter FIFO and Shift register is empty.
376 static u_int atmel_tx_empty(struct uart_port *port)
378 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
380 if (atmel_port->tx_stopped)
382 return (atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXEMPTY) ?
388 * Set state of the modem control output lines
390 static void atmel_set_mctrl(struct uart_port *port, u_int mctrl)
392 unsigned int control = 0;
393 unsigned int mode = atmel_uart_readl(port, ATMEL_US_MR);
394 unsigned int rts_paused, rts_ready;
395 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
397 /* override mode to RS485 if needed, otherwise keep the current mode */
398 if (port->rs485.flags & SER_RS485_ENABLED) {
399 atmel_uart_writel(port, ATMEL_US_TTGR,
400 port->rs485.delay_rts_after_send);
401 mode &= ~ATMEL_US_USMODE;
402 mode |= ATMEL_US_USMODE_RS485;
405 /* set the RTS line state according to the mode */
406 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
407 /* force RTS line to high level */
408 rts_paused = ATMEL_US_RTSEN;
410 /* give the control of the RTS line back to the hardware */
411 rts_ready = ATMEL_US_RTSDIS;
413 /* force RTS line to high level */
414 rts_paused = ATMEL_US_RTSDIS;
416 /* force RTS line to low level */
417 rts_ready = ATMEL_US_RTSEN;
420 if (mctrl & TIOCM_RTS)
421 control |= rts_ready;
423 control |= rts_paused;
425 if (mctrl & TIOCM_DTR)
426 control |= ATMEL_US_DTREN;
428 control |= ATMEL_US_DTRDIS;
430 atmel_uart_writel(port, ATMEL_US_CR, control);
432 mctrl_gpio_set(atmel_port->gpios, mctrl);
434 /* Local loopback mode? */
435 mode &= ~ATMEL_US_CHMODE;
436 if (mctrl & TIOCM_LOOP)
437 mode |= ATMEL_US_CHMODE_LOC_LOOP;
439 mode |= ATMEL_US_CHMODE_NORMAL;
441 atmel_uart_writel(port, ATMEL_US_MR, mode);
445 * Get state of the modem control input lines
447 static u_int atmel_get_mctrl(struct uart_port *port)
449 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
450 unsigned int ret = 0, status;
452 status = atmel_uart_readl(port, ATMEL_US_CSR);
455 * The control signals are active low.
457 if (!(status & ATMEL_US_DCD))
459 if (!(status & ATMEL_US_CTS))
461 if (!(status & ATMEL_US_DSR))
463 if (!(status & ATMEL_US_RI))
466 return mctrl_gpio_get(atmel_port->gpios, &ret);
472 static void atmel_stop_tx(struct uart_port *port)
474 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
476 if (atmel_use_pdc_tx(port)) {
477 /* disable PDC transmit */
478 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
482 * Disable the transmitter.
483 * This is mandatory when DMA is used, otherwise the DMA buffer
484 * is fully transmitted.
486 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS);
487 atmel_port->tx_stopped = true;
489 /* Disable interrupts */
490 atmel_uart_writel(port, ATMEL_US_IDR, atmel_port->tx_done_mask);
492 if (atmel_uart_is_half_duplex(port))
493 atmel_start_rx(port);
498 * Start transmitting.
500 static void atmel_start_tx(struct uart_port *port)
502 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
504 if (atmel_use_pdc_tx(port) && (atmel_uart_readl(port, ATMEL_PDC_PTSR)
506 /* The transmitter is already running. Yes, we
510 if (atmel_use_pdc_tx(port) || atmel_use_dma_tx(port))
511 if (atmel_uart_is_half_duplex(port))
514 if (atmel_use_pdc_tx(port))
515 /* re-enable PDC transmit */
516 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
518 /* Enable interrupts */
519 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->tx_done_mask);
521 /* re-enable the transmitter */
522 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
523 atmel_port->tx_stopped = false;
527 * start receiving - port is in process of being opened.
529 static void atmel_start_rx(struct uart_port *port)
531 /* reset status and receiver */
532 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
534 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXEN);
536 if (atmel_use_pdc_rx(port)) {
537 /* enable PDC controller */
538 atmel_uart_writel(port, ATMEL_US_IER,
539 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
540 port->read_status_mask);
541 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
543 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
548 * Stop receiving - port is in process of being closed.
550 static void atmel_stop_rx(struct uart_port *port)
552 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RXDIS);
554 if (atmel_use_pdc_rx(port)) {
555 /* disable PDC receive */
556 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS);
557 atmel_uart_writel(port, ATMEL_US_IDR,
558 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT |
559 port->read_status_mask);
561 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXRDY);
566 * Enable modem status interrupts
568 static void atmel_enable_ms(struct uart_port *port)
570 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
574 * Interrupt should not be enabled twice
576 if (atmel_port->ms_irq_enabled)
579 atmel_port->ms_irq_enabled = true;
581 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
582 ier |= ATMEL_US_CTSIC;
584 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
585 ier |= ATMEL_US_DSRIC;
587 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
588 ier |= ATMEL_US_RIIC;
590 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
591 ier |= ATMEL_US_DCDIC;
593 atmel_uart_writel(port, ATMEL_US_IER, ier);
595 mctrl_gpio_enable_ms(atmel_port->gpios);
599 * Disable modem status interrupts
601 static void atmel_disable_ms(struct uart_port *port)
603 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
607 * Interrupt should not be disabled twice
609 if (!atmel_port->ms_irq_enabled)
612 atmel_port->ms_irq_enabled = false;
614 mctrl_gpio_disable_ms(atmel_port->gpios);
616 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS))
617 idr |= ATMEL_US_CTSIC;
619 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DSR))
620 idr |= ATMEL_US_DSRIC;
622 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_RI))
623 idr |= ATMEL_US_RIIC;
625 if (!mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_DCD))
626 idr |= ATMEL_US_DCDIC;
628 atmel_uart_writel(port, ATMEL_US_IDR, idr);
632 * Control the transmission of a break signal
634 static void atmel_break_ctl(struct uart_port *port, int break_state)
636 if (break_state != 0)
638 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTBRK);
641 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STPBRK);
645 * Stores the incoming character in the ring buffer
648 atmel_buffer_rx_char(struct uart_port *port, unsigned int status,
651 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
652 struct circ_buf *ring = &atmel_port->rx_ring;
653 struct atmel_uart_char *c;
655 if (!CIRC_SPACE(ring->head, ring->tail, ATMEL_SERIAL_RINGSIZE))
656 /* Buffer overflow, ignore char */
659 c = &((struct atmel_uart_char *)ring->buf)[ring->head];
663 /* Make sure the character is stored before we update head. */
666 ring->head = (ring->head + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
670 * Deal with parity, framing and overrun errors.
672 static void atmel_pdc_rxerr(struct uart_port *port, unsigned int status)
675 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
677 if (status & ATMEL_US_RXBRK) {
678 /* ignore side-effect */
679 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
682 if (status & ATMEL_US_PARE)
683 port->icount.parity++;
684 if (status & ATMEL_US_FRAME)
685 port->icount.frame++;
686 if (status & ATMEL_US_OVRE)
687 port->icount.overrun++;
691 * Characters received (called from interrupt handler)
693 static void atmel_rx_chars(struct uart_port *port)
695 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
696 unsigned int status, ch;
698 status = atmel_uart_readl(port, ATMEL_US_CSR);
699 while (status & ATMEL_US_RXRDY) {
700 ch = atmel_uart_read_char(port);
703 * note that the error handling code is
704 * out of the main execution path
706 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
707 | ATMEL_US_OVRE | ATMEL_US_RXBRK)
708 || atmel_port->break_active)) {
711 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
713 if (status & ATMEL_US_RXBRK
714 && !atmel_port->break_active) {
715 atmel_port->break_active = 1;
716 atmel_uart_writel(port, ATMEL_US_IER,
720 * This is either the end-of-break
721 * condition or we've received at
722 * least one character without RXBRK
723 * being set. In both cases, the next
724 * RXBRK will indicate start-of-break.
726 atmel_uart_writel(port, ATMEL_US_IDR,
728 status &= ~ATMEL_US_RXBRK;
729 atmel_port->break_active = 0;
733 atmel_buffer_rx_char(port, status, ch);
734 status = atmel_uart_readl(port, ATMEL_US_CSR);
737 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
741 * Transmit characters (called from tasklet with TXRDY interrupt
744 static void atmel_tx_chars(struct uart_port *port)
746 struct circ_buf *xmit = &port->state->xmit;
747 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
750 (atmel_uart_readl(port, ATMEL_US_CSR) & atmel_port->tx_done_mask)) {
751 atmel_uart_write_char(port, port->x_char);
755 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
758 while (atmel_uart_readl(port, ATMEL_US_CSR) &
759 atmel_port->tx_done_mask) {
760 atmel_uart_write_char(port, xmit->buf[xmit->tail]);
761 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
763 if (uart_circ_empty(xmit))
767 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
768 uart_write_wakeup(port);
770 if (!uart_circ_empty(xmit))
771 /* Enable interrupts */
772 atmel_uart_writel(port, ATMEL_US_IER,
773 atmel_port->tx_done_mask);
776 static void atmel_complete_tx_dma(void *arg)
778 struct atmel_uart_port *atmel_port = arg;
779 struct uart_port *port = &atmel_port->uart;
780 struct circ_buf *xmit = &port->state->xmit;
781 struct dma_chan *chan = atmel_port->chan_tx;
784 spin_lock_irqsave(&port->lock, flags);
787 dmaengine_terminate_all(chan);
788 xmit->tail += atmel_port->tx_len;
789 xmit->tail &= UART_XMIT_SIZE - 1;
791 port->icount.tx += atmel_port->tx_len;
793 spin_lock_irq(&atmel_port->lock_tx);
794 async_tx_ack(atmel_port->desc_tx);
795 atmel_port->cookie_tx = -EINVAL;
796 atmel_port->desc_tx = NULL;
797 spin_unlock_irq(&atmel_port->lock_tx);
799 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
800 uart_write_wakeup(port);
803 * xmit is a circular buffer so, if we have just send data from
804 * xmit->tail to the end of xmit->buf, now we have to transmit the
805 * remaining data from the beginning of xmit->buf to xmit->head.
807 if (!uart_circ_empty(xmit))
808 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
809 else if (atmel_uart_is_half_duplex(port)) {
811 * DMA done, re-enable TXEMPTY and signal that we can stop
812 * TX and start RX for RS485
814 atmel_port->hd_start_rx = true;
815 atmel_uart_writel(port, ATMEL_US_IER,
816 atmel_port->tx_done_mask);
819 spin_unlock_irqrestore(&port->lock, flags);
822 static void atmel_release_tx_dma(struct uart_port *port)
824 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
825 struct dma_chan *chan = atmel_port->chan_tx;
828 dmaengine_terminate_all(chan);
829 dma_release_channel(chan);
830 dma_unmap_sg(port->dev, &atmel_port->sg_tx, 1,
834 atmel_port->desc_tx = NULL;
835 atmel_port->chan_tx = NULL;
836 atmel_port->cookie_tx = -EINVAL;
840 * Called from tasklet with TXRDY interrupt is disabled.
842 static void atmel_tx_dma(struct uart_port *port)
844 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
845 struct circ_buf *xmit = &port->state->xmit;
846 struct dma_chan *chan = atmel_port->chan_tx;
847 struct dma_async_tx_descriptor *desc;
848 struct scatterlist sgl[2], *sg, *sg_tx = &atmel_port->sg_tx;
849 unsigned int tx_len, part1_len, part2_len, sg_len;
850 dma_addr_t phys_addr;
852 /* Make sure we have an idle channel */
853 if (atmel_port->desc_tx != NULL)
856 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
859 * Port xmit buffer is already mapped,
860 * and it is one page... Just adjust
861 * offsets and lengths. Since it is a circular buffer,
862 * we have to transmit till the end, and then the rest.
863 * Take the port lock to get a
864 * consistent xmit buffer state.
866 tx_len = CIRC_CNT_TO_END(xmit->head,
870 if (atmel_port->fifo_size) {
871 /* multi data mode */
872 part1_len = (tx_len & ~0x3); /* DWORD access */
873 part2_len = (tx_len & 0x3); /* BYTE access */
875 /* single data (legacy) mode */
877 part2_len = tx_len; /* BYTE access only */
880 sg_init_table(sgl, 2);
882 phys_addr = sg_dma_address(sg_tx) + xmit->tail;
885 sg_dma_address(sg) = phys_addr;
886 sg_dma_len(sg) = part1_len;
888 phys_addr += part1_len;
893 sg_dma_address(sg) = phys_addr;
894 sg_dma_len(sg) = part2_len;
898 * save tx_len so atmel_complete_tx_dma() will increase
899 * xmit->tail correctly
901 atmel_port->tx_len = tx_len;
903 desc = dmaengine_prep_slave_sg(chan,
910 dev_err(port->dev, "Failed to send via dma!\n");
914 dma_sync_sg_for_device(port->dev, sg_tx, 1, DMA_TO_DEVICE);
916 atmel_port->desc_tx = desc;
917 desc->callback = atmel_complete_tx_dma;
918 desc->callback_param = atmel_port;
919 atmel_port->cookie_tx = dmaengine_submit(desc);
922 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
923 uart_write_wakeup(port);
926 static int atmel_prepare_tx_dma(struct uart_port *port)
928 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
930 struct dma_slave_config config;
934 dma_cap_set(DMA_SLAVE, mask);
936 atmel_port->chan_tx = dma_request_slave_channel(port->dev, "tx");
937 if (atmel_port->chan_tx == NULL)
939 dev_info(port->dev, "using %s for tx DMA transfers\n",
940 dma_chan_name(atmel_port->chan_tx));
942 spin_lock_init(&atmel_port->lock_tx);
943 sg_init_table(&atmel_port->sg_tx, 1);
944 /* UART circular tx buffer is an aligned page. */
945 BUG_ON(!PAGE_ALIGNED(port->state->xmit.buf));
946 sg_set_page(&atmel_port->sg_tx,
947 virt_to_page(port->state->xmit.buf),
949 offset_in_page(port->state->xmit.buf));
950 nent = dma_map_sg(port->dev,
956 dev_dbg(port->dev, "need to release resource of dma\n");
959 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
960 sg_dma_len(&atmel_port->sg_tx),
961 port->state->xmit.buf,
962 &sg_dma_address(&atmel_port->sg_tx));
965 /* Configure the slave DMA */
966 memset(&config, 0, sizeof(config));
967 config.direction = DMA_MEM_TO_DEV;
968 config.dst_addr_width = (atmel_port->fifo_size) ?
969 DMA_SLAVE_BUSWIDTH_4_BYTES :
970 DMA_SLAVE_BUSWIDTH_1_BYTE;
971 config.dst_addr = port->mapbase + ATMEL_US_THR;
972 config.dst_maxburst = 1;
974 ret = dmaengine_slave_config(atmel_port->chan_tx,
977 dev_err(port->dev, "DMA tx slave configuration failed\n");
984 dev_err(port->dev, "TX channel not available, switch to pio\n");
985 atmel_port->use_dma_tx = 0;
986 if (atmel_port->chan_tx)
987 atmel_release_tx_dma(port);
991 static void atmel_complete_rx_dma(void *arg)
993 struct uart_port *port = arg;
994 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
996 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
999 static void atmel_release_rx_dma(struct uart_port *port)
1001 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1002 struct dma_chan *chan = atmel_port->chan_rx;
1005 dmaengine_terminate_all(chan);
1006 dma_release_channel(chan);
1007 dma_unmap_sg(port->dev, &atmel_port->sg_rx, 1,
1011 atmel_port->desc_rx = NULL;
1012 atmel_port->chan_rx = NULL;
1013 atmel_port->cookie_rx = -EINVAL;
1016 static void atmel_rx_from_dma(struct uart_port *port)
1018 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1019 struct tty_port *tport = &port->state->port;
1020 struct circ_buf *ring = &atmel_port->rx_ring;
1021 struct dma_chan *chan = atmel_port->chan_rx;
1022 struct dma_tx_state state;
1023 enum dma_status dmastat;
1027 /* Reset the UART timeout early so that we don't miss one */
1028 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1029 dmastat = dmaengine_tx_status(chan,
1030 atmel_port->cookie_rx,
1032 /* Restart a new tasklet if DMA status is error */
1033 if (dmastat == DMA_ERROR) {
1034 dev_dbg(port->dev, "Get residue error, restart tasklet\n");
1035 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1036 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_rx);
1040 /* CPU claims ownership of RX DMA buffer */
1041 dma_sync_sg_for_cpu(port->dev,
1047 * ring->head points to the end of data already written by the DMA.
1048 * ring->tail points to the beginning of data to be read by the
1050 * The current transfer size should not be larger than the dma buffer
1053 ring->head = sg_dma_len(&atmel_port->sg_rx) - state.residue;
1054 BUG_ON(ring->head > sg_dma_len(&atmel_port->sg_rx));
1056 * At this point ring->head may point to the first byte right after the
1057 * last byte of the dma buffer:
1058 * 0 <= ring->head <= sg_dma_len(&atmel_port->sg_rx)
1060 * However ring->tail must always points inside the dma buffer:
1061 * 0 <= ring->tail <= sg_dma_len(&atmel_port->sg_rx) - 1
1063 * Since we use a ring buffer, we have to handle the case
1064 * where head is lower than tail. In such a case, we first read from
1065 * tail to the end of the buffer then reset tail.
1067 if (ring->head < ring->tail) {
1068 count = sg_dma_len(&atmel_port->sg_rx) - ring->tail;
1070 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1072 port->icount.rx += count;
1075 /* Finally we read data from tail to head */
1076 if (ring->tail < ring->head) {
1077 count = ring->head - ring->tail;
1079 tty_insert_flip_string(tport, ring->buf + ring->tail, count);
1080 /* Wrap ring->head if needed */
1081 if (ring->head >= sg_dma_len(&atmel_port->sg_rx))
1083 ring->tail = ring->head;
1084 port->icount.rx += count;
1087 /* USART retreives ownership of RX DMA buffer */
1088 dma_sync_sg_for_device(port->dev,
1094 * Drop the lock here since it might end up calling
1095 * uart_start(), which takes the lock.
1097 spin_unlock(&port->lock);
1098 tty_flip_buffer_push(tport);
1099 spin_lock(&port->lock);
1101 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_TIMEOUT);
1104 static int atmel_prepare_rx_dma(struct uart_port *port)
1106 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1107 struct dma_async_tx_descriptor *desc;
1108 dma_cap_mask_t mask;
1109 struct dma_slave_config config;
1110 struct circ_buf *ring;
1113 ring = &atmel_port->rx_ring;
1116 dma_cap_set(DMA_CYCLIC, mask);
1118 atmel_port->chan_rx = dma_request_slave_channel(port->dev, "rx");
1119 if (atmel_port->chan_rx == NULL)
1121 dev_info(port->dev, "using %s for rx DMA transfers\n",
1122 dma_chan_name(atmel_port->chan_rx));
1124 spin_lock_init(&atmel_port->lock_rx);
1125 sg_init_table(&atmel_port->sg_rx, 1);
1126 /* UART circular rx buffer is an aligned page. */
1127 BUG_ON(!PAGE_ALIGNED(ring->buf));
1128 sg_set_page(&atmel_port->sg_rx,
1129 virt_to_page(ring->buf),
1130 sizeof(struct atmel_uart_char) * ATMEL_SERIAL_RINGSIZE,
1131 offset_in_page(ring->buf));
1132 nent = dma_map_sg(port->dev,
1138 dev_dbg(port->dev, "need to release resource of dma\n");
1141 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n", __func__,
1142 sg_dma_len(&atmel_port->sg_rx),
1144 &sg_dma_address(&atmel_port->sg_rx));
1147 /* Configure the slave DMA */
1148 memset(&config, 0, sizeof(config));
1149 config.direction = DMA_DEV_TO_MEM;
1150 config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1151 config.src_addr = port->mapbase + ATMEL_US_RHR;
1152 config.src_maxburst = 1;
1154 ret = dmaengine_slave_config(atmel_port->chan_rx,
1157 dev_err(port->dev, "DMA rx slave configuration failed\n");
1161 * Prepare a cyclic dma transfer, assign 2 descriptors,
1162 * each one is half ring buffer size
1164 desc = dmaengine_prep_dma_cyclic(atmel_port->chan_rx,
1165 sg_dma_address(&atmel_port->sg_rx),
1166 sg_dma_len(&atmel_port->sg_rx),
1167 sg_dma_len(&atmel_port->sg_rx)/2,
1169 DMA_PREP_INTERRUPT);
1171 dev_err(port->dev, "Preparing DMA cyclic failed\n");
1174 desc->callback = atmel_complete_rx_dma;
1175 desc->callback_param = port;
1176 atmel_port->desc_rx = desc;
1177 atmel_port->cookie_rx = dmaengine_submit(desc);
1182 dev_err(port->dev, "RX channel not available, switch to pio\n");
1183 atmel_port->use_dma_rx = 0;
1184 if (atmel_port->chan_rx)
1185 atmel_release_rx_dma(port);
1189 static void atmel_uart_timer_callback(struct timer_list *t)
1191 struct atmel_uart_port *atmel_port = from_timer(atmel_port, t,
1193 struct uart_port *port = &atmel_port->uart;
1195 if (!atomic_read(&atmel_port->tasklet_shutdown)) {
1196 tasklet_schedule(&atmel_port->tasklet_rx);
1197 mod_timer(&atmel_port->uart_timer,
1198 jiffies + uart_poll_timeout(port));
1203 * receive interrupt handler.
1206 atmel_handle_receive(struct uart_port *port, unsigned int pending)
1208 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1210 if (atmel_use_pdc_rx(port)) {
1212 * PDC receive. Just schedule the tasklet and let it
1213 * figure out the details.
1215 * TODO: We're not handling error flags correctly at
1218 if (pending & (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT)) {
1219 atmel_uart_writel(port, ATMEL_US_IDR,
1220 (ATMEL_US_ENDRX | ATMEL_US_TIMEOUT));
1221 atmel_tasklet_schedule(atmel_port,
1222 &atmel_port->tasklet_rx);
1225 if (pending & (ATMEL_US_RXBRK | ATMEL_US_OVRE |
1226 ATMEL_US_FRAME | ATMEL_US_PARE))
1227 atmel_pdc_rxerr(port, pending);
1230 if (atmel_use_dma_rx(port)) {
1231 if (pending & ATMEL_US_TIMEOUT) {
1232 atmel_uart_writel(port, ATMEL_US_IDR,
1234 atmel_tasklet_schedule(atmel_port,
1235 &atmel_port->tasklet_rx);
1239 /* Interrupt receive */
1240 if (pending & ATMEL_US_RXRDY)
1241 atmel_rx_chars(port);
1242 else if (pending & ATMEL_US_RXBRK) {
1244 * End of break detected. If it came along with a
1245 * character, atmel_rx_chars will handle it.
1247 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1248 atmel_uart_writel(port, ATMEL_US_IDR, ATMEL_US_RXBRK);
1249 atmel_port->break_active = 0;
1254 * transmit interrupt handler. (Transmit is IRQF_NODELAY safe)
1257 atmel_handle_transmit(struct uart_port *port, unsigned int pending)
1259 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1261 if (pending & atmel_port->tx_done_mask) {
1262 atmel_uart_writel(port, ATMEL_US_IDR,
1263 atmel_port->tx_done_mask);
1265 /* Start RX if flag was set and FIFO is empty */
1266 if (atmel_port->hd_start_rx) {
1267 if (!(atmel_uart_readl(port, ATMEL_US_CSR)
1268 & ATMEL_US_TXEMPTY))
1269 dev_warn(port->dev, "Should start RX, but TX fifo is not empty\n");
1271 atmel_port->hd_start_rx = false;
1272 atmel_start_rx(port);
1275 atmel_tasklet_schedule(atmel_port, &atmel_port->tasklet_tx);
1280 * status flags interrupt handler.
1283 atmel_handle_status(struct uart_port *port, unsigned int pending,
1284 unsigned int status)
1286 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1287 unsigned int status_change;
1289 if (pending & (ATMEL_US_RIIC | ATMEL_US_DSRIC | ATMEL_US_DCDIC
1290 | ATMEL_US_CTSIC)) {
1291 status_change = status ^ atmel_port->irq_status_prev;
1292 atmel_port->irq_status_prev = status;
1294 if (status_change & (ATMEL_US_RI | ATMEL_US_DSR
1295 | ATMEL_US_DCD | ATMEL_US_CTS)) {
1296 /* TODO: All reads to CSR will clear these interrupts! */
1297 if (status_change & ATMEL_US_RI)
1299 if (status_change & ATMEL_US_DSR)
1301 if (status_change & ATMEL_US_DCD)
1302 uart_handle_dcd_change(port, !(status & ATMEL_US_DCD));
1303 if (status_change & ATMEL_US_CTS)
1304 uart_handle_cts_change(port, !(status & ATMEL_US_CTS));
1306 wake_up_interruptible(&port->state->port.delta_msr_wait);
1314 static irqreturn_t atmel_interrupt(int irq, void *dev_id)
1316 struct uart_port *port = dev_id;
1317 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1318 unsigned int status, pending, mask, pass_counter = 0;
1320 spin_lock(&atmel_port->lock_suspended);
1323 status = atmel_get_lines_status(port);
1324 mask = atmel_uart_readl(port, ATMEL_US_IMR);
1325 pending = status & mask;
1329 if (atmel_port->suspended) {
1330 atmel_port->pending |= pending;
1331 atmel_port->pending_status = status;
1332 atmel_uart_writel(port, ATMEL_US_IDR, mask);
1337 atmel_handle_receive(port, pending);
1338 atmel_handle_status(port, pending, status);
1339 atmel_handle_transmit(port, pending);
1340 } while (pass_counter++ < ATMEL_ISR_PASS_LIMIT);
1342 spin_unlock(&atmel_port->lock_suspended);
1344 return pass_counter ? IRQ_HANDLED : IRQ_NONE;
1347 static void atmel_release_tx_pdc(struct uart_port *port)
1349 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1350 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1352 dma_unmap_single(port->dev,
1359 * Called from tasklet with ENDTX and TXBUFE interrupts disabled.
1361 static void atmel_tx_pdc(struct uart_port *port)
1363 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1364 struct circ_buf *xmit = &port->state->xmit;
1365 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1368 /* nothing left to transmit? */
1369 if (atmel_uart_readl(port, ATMEL_PDC_TCR))
1372 xmit->tail += pdc->ofs;
1373 xmit->tail &= UART_XMIT_SIZE - 1;
1375 port->icount.tx += pdc->ofs;
1378 /* more to transmit - setup next transfer */
1380 /* disable PDC transmit */
1381 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
1383 if (!uart_circ_empty(xmit) && !uart_tx_stopped(port)) {
1384 dma_sync_single_for_device(port->dev,
1389 count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1392 atmel_uart_writel(port, ATMEL_PDC_TPR,
1393 pdc->dma_addr + xmit->tail);
1394 atmel_uart_writel(port, ATMEL_PDC_TCR, count);
1395 /* re-enable PDC transmit */
1396 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
1397 /* Enable interrupts */
1398 atmel_uart_writel(port, ATMEL_US_IER,
1399 atmel_port->tx_done_mask);
1401 if (atmel_uart_is_half_duplex(port)) {
1402 /* DMA done, stop TX, start RX for RS485 */
1403 atmel_start_rx(port);
1407 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1408 uart_write_wakeup(port);
1411 static int atmel_prepare_tx_pdc(struct uart_port *port)
1413 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1414 struct atmel_dma_buffer *pdc = &atmel_port->pdc_tx;
1415 struct circ_buf *xmit = &port->state->xmit;
1417 pdc->buf = xmit->buf;
1418 pdc->dma_addr = dma_map_single(port->dev,
1422 pdc->dma_size = UART_XMIT_SIZE;
1428 static void atmel_rx_from_ring(struct uart_port *port)
1430 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1431 struct circ_buf *ring = &atmel_port->rx_ring;
1433 unsigned int status;
1435 while (ring->head != ring->tail) {
1436 struct atmel_uart_char c;
1438 /* Make sure c is loaded after head. */
1441 c = ((struct atmel_uart_char *)ring->buf)[ring->tail];
1443 ring->tail = (ring->tail + 1) & (ATMEL_SERIAL_RINGSIZE - 1);
1450 * note that the error handling code is
1451 * out of the main execution path
1453 if (unlikely(status & (ATMEL_US_PARE | ATMEL_US_FRAME
1454 | ATMEL_US_OVRE | ATMEL_US_RXBRK))) {
1455 if (status & ATMEL_US_RXBRK) {
1456 /* ignore side-effect */
1457 status &= ~(ATMEL_US_PARE | ATMEL_US_FRAME);
1460 if (uart_handle_break(port))
1463 if (status & ATMEL_US_PARE)
1464 port->icount.parity++;
1465 if (status & ATMEL_US_FRAME)
1466 port->icount.frame++;
1467 if (status & ATMEL_US_OVRE)
1468 port->icount.overrun++;
1470 status &= port->read_status_mask;
1472 if (status & ATMEL_US_RXBRK)
1474 else if (status & ATMEL_US_PARE)
1476 else if (status & ATMEL_US_FRAME)
1481 if (uart_handle_sysrq_char(port, c.ch))
1484 uart_insert_char(port, status, ATMEL_US_OVRE, c.ch, flg);
1488 * Drop the lock here since it might end up calling
1489 * uart_start(), which takes the lock.
1491 spin_unlock(&port->lock);
1492 tty_flip_buffer_push(&port->state->port);
1493 spin_lock(&port->lock);
1496 static void atmel_release_rx_pdc(struct uart_port *port)
1498 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1501 for (i = 0; i < 2; i++) {
1502 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1504 dma_unmap_single(port->dev,
1512 static void atmel_rx_from_pdc(struct uart_port *port)
1514 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1515 struct tty_port *tport = &port->state->port;
1516 struct atmel_dma_buffer *pdc;
1517 int rx_idx = atmel_port->pdc_rx_idx;
1523 /* Reset the UART timeout early so that we don't miss one */
1524 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1526 pdc = &atmel_port->pdc_rx[rx_idx];
1527 head = atmel_uart_readl(port, ATMEL_PDC_RPR) - pdc->dma_addr;
1530 /* If the PDC has switched buffers, RPR won't contain
1531 * any address within the current buffer. Since head
1532 * is unsigned, we just need a one-way comparison to
1535 * In this case, we just need to consume the entire
1536 * buffer and resubmit it for DMA. This will clear the
1537 * ENDRX bit as well, so that we can safely re-enable
1538 * all interrupts below.
1540 head = min(head, pdc->dma_size);
1542 if (likely(head != tail)) {
1543 dma_sync_single_for_cpu(port->dev, pdc->dma_addr,
1544 pdc->dma_size, DMA_FROM_DEVICE);
1547 * head will only wrap around when we recycle
1548 * the DMA buffer, and when that happens, we
1549 * explicitly set tail to 0. So head will
1550 * always be greater than tail.
1552 count = head - tail;
1554 tty_insert_flip_string(tport, pdc->buf + pdc->ofs,
1557 dma_sync_single_for_device(port->dev, pdc->dma_addr,
1558 pdc->dma_size, DMA_FROM_DEVICE);
1560 port->icount.rx += count;
1565 * If the current buffer is full, we need to check if
1566 * the next one contains any additional data.
1568 if (head >= pdc->dma_size) {
1570 atmel_uart_writel(port, ATMEL_PDC_RNPR, pdc->dma_addr);
1571 atmel_uart_writel(port, ATMEL_PDC_RNCR, pdc->dma_size);
1574 atmel_port->pdc_rx_idx = rx_idx;
1576 } while (head >= pdc->dma_size);
1579 * Drop the lock here since it might end up calling
1580 * uart_start(), which takes the lock.
1582 spin_unlock(&port->lock);
1583 tty_flip_buffer_push(tport);
1584 spin_lock(&port->lock);
1586 atmel_uart_writel(port, ATMEL_US_IER,
1587 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1590 static int atmel_prepare_rx_pdc(struct uart_port *port)
1592 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1595 for (i = 0; i < 2; i++) {
1596 struct atmel_dma_buffer *pdc = &atmel_port->pdc_rx[i];
1598 pdc->buf = kmalloc(PDC_BUFFER_SIZE, GFP_KERNEL);
1599 if (pdc->buf == NULL) {
1601 dma_unmap_single(port->dev,
1602 atmel_port->pdc_rx[0].dma_addr,
1605 kfree(atmel_port->pdc_rx[0].buf);
1607 atmel_port->use_pdc_rx = 0;
1610 pdc->dma_addr = dma_map_single(port->dev,
1614 pdc->dma_size = PDC_BUFFER_SIZE;
1618 atmel_port->pdc_rx_idx = 0;
1620 atmel_uart_writel(port, ATMEL_PDC_RPR, atmel_port->pdc_rx[0].dma_addr);
1621 atmel_uart_writel(port, ATMEL_PDC_RCR, PDC_BUFFER_SIZE);
1623 atmel_uart_writel(port, ATMEL_PDC_RNPR,
1624 atmel_port->pdc_rx[1].dma_addr);
1625 atmel_uart_writel(port, ATMEL_PDC_RNCR, PDC_BUFFER_SIZE);
1631 * tasklet handling tty stuff outside the interrupt handler.
1633 static void atmel_tasklet_rx_func(unsigned long data)
1635 struct uart_port *port = (struct uart_port *)data;
1636 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1638 /* The interrupt handler does not take the lock */
1639 spin_lock(&port->lock);
1640 atmel_port->schedule_rx(port);
1641 spin_unlock(&port->lock);
1644 static void atmel_tasklet_tx_func(unsigned long data)
1646 struct uart_port *port = (struct uart_port *)data;
1647 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1649 /* The interrupt handler does not take the lock */
1650 spin_lock(&port->lock);
1651 atmel_port->schedule_tx(port);
1652 spin_unlock(&port->lock);
1655 static void atmel_init_property(struct atmel_uart_port *atmel_port,
1656 struct platform_device *pdev)
1658 struct device_node *np = pdev->dev.of_node;
1660 /* DMA/PDC usage specification */
1661 if (of_property_read_bool(np, "atmel,use-dma-rx")) {
1662 if (of_property_read_bool(np, "dmas")) {
1663 atmel_port->use_dma_rx = true;
1664 atmel_port->use_pdc_rx = false;
1666 atmel_port->use_dma_rx = false;
1667 atmel_port->use_pdc_rx = true;
1670 atmel_port->use_dma_rx = false;
1671 atmel_port->use_pdc_rx = false;
1674 if (of_property_read_bool(np, "atmel,use-dma-tx")) {
1675 if (of_property_read_bool(np, "dmas")) {
1676 atmel_port->use_dma_tx = true;
1677 atmel_port->use_pdc_tx = false;
1679 atmel_port->use_dma_tx = false;
1680 atmel_port->use_pdc_tx = true;
1683 atmel_port->use_dma_tx = false;
1684 atmel_port->use_pdc_tx = false;
1688 static void atmel_set_ops(struct uart_port *port)
1690 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1692 if (atmel_use_dma_rx(port)) {
1693 atmel_port->prepare_rx = &atmel_prepare_rx_dma;
1694 atmel_port->schedule_rx = &atmel_rx_from_dma;
1695 atmel_port->release_rx = &atmel_release_rx_dma;
1696 } else if (atmel_use_pdc_rx(port)) {
1697 atmel_port->prepare_rx = &atmel_prepare_rx_pdc;
1698 atmel_port->schedule_rx = &atmel_rx_from_pdc;
1699 atmel_port->release_rx = &atmel_release_rx_pdc;
1701 atmel_port->prepare_rx = NULL;
1702 atmel_port->schedule_rx = &atmel_rx_from_ring;
1703 atmel_port->release_rx = NULL;
1706 if (atmel_use_dma_tx(port)) {
1707 atmel_port->prepare_tx = &atmel_prepare_tx_dma;
1708 atmel_port->schedule_tx = &atmel_tx_dma;
1709 atmel_port->release_tx = &atmel_release_tx_dma;
1710 } else if (atmel_use_pdc_tx(port)) {
1711 atmel_port->prepare_tx = &atmel_prepare_tx_pdc;
1712 atmel_port->schedule_tx = &atmel_tx_pdc;
1713 atmel_port->release_tx = &atmel_release_tx_pdc;
1715 atmel_port->prepare_tx = NULL;
1716 atmel_port->schedule_tx = &atmel_tx_chars;
1717 atmel_port->release_tx = NULL;
1722 * Get ip name usart or uart
1724 static void atmel_get_ip_name(struct uart_port *port)
1726 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1727 int name = atmel_uart_readl(port, ATMEL_US_NAME);
1729 u32 usart, dbgu_uart, new_uart;
1730 /* ASCII decoding for IP version */
1731 usart = 0x55534152; /* USAR(T) */
1732 dbgu_uart = 0x44424755; /* DBGU */
1733 new_uart = 0x55415254; /* UART */
1736 * Only USART devices from at91sam9260 SOC implement fractional
1737 * baudrate. It is available for all asynchronous modes, with the
1738 * following restriction: the sampling clock's duty cycle is not
1741 atmel_port->has_frac_baudrate = false;
1742 atmel_port->has_hw_timer = false;
1744 if (name == new_uart) {
1745 dev_dbg(port->dev, "Uart with hw timer");
1746 atmel_port->has_hw_timer = true;
1747 atmel_port->rtor = ATMEL_UA_RTOR;
1748 } else if (name == usart) {
1749 dev_dbg(port->dev, "Usart\n");
1750 atmel_port->has_frac_baudrate = true;
1751 atmel_port->has_hw_timer = true;
1752 atmel_port->rtor = ATMEL_US_RTOR;
1753 } else if (name == dbgu_uart) {
1754 dev_dbg(port->dev, "Dbgu or uart without hw timer\n");
1756 /* fallback for older SoCs: use version field */
1757 version = atmel_uart_readl(port, ATMEL_US_VERSION);
1762 dev_dbg(port->dev, "This version is usart\n");
1763 atmel_port->has_frac_baudrate = true;
1764 atmel_port->has_hw_timer = true;
1765 atmel_port->rtor = ATMEL_US_RTOR;
1769 dev_dbg(port->dev, "This version is uart\n");
1772 dev_err(port->dev, "Not supported ip name nor version, set to uart\n");
1778 * Perform initialization and enable port for reception
1780 static int atmel_startup(struct uart_port *port)
1782 struct platform_device *pdev = to_platform_device(port->dev);
1783 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1787 * Ensure that no interrupts are enabled otherwise when
1788 * request_irq() is called we could get stuck trying to
1789 * handle an unexpected interrupt
1791 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1792 atmel_port->ms_irq_enabled = false;
1797 retval = request_irq(port->irq, atmel_interrupt,
1798 IRQF_SHARED | IRQF_COND_SUSPEND,
1799 dev_name(&pdev->dev), port);
1801 dev_err(port->dev, "atmel_startup - Can't get irq\n");
1805 atomic_set(&atmel_port->tasklet_shutdown, 0);
1806 tasklet_init(&atmel_port->tasklet_rx, atmel_tasklet_rx_func,
1807 (unsigned long)port);
1808 tasklet_init(&atmel_port->tasklet_tx, atmel_tasklet_tx_func,
1809 (unsigned long)port);
1812 * Initialize DMA (if necessary)
1814 atmel_init_property(atmel_port, pdev);
1815 atmel_set_ops(port);
1817 if (atmel_port->prepare_rx) {
1818 retval = atmel_port->prepare_rx(port);
1820 atmel_set_ops(port);
1823 if (atmel_port->prepare_tx) {
1824 retval = atmel_port->prepare_tx(port);
1826 atmel_set_ops(port);
1830 * Enable FIFO when available
1832 if (atmel_port->fifo_size) {
1833 unsigned int txrdym = ATMEL_US_ONE_DATA;
1834 unsigned int rxrdym = ATMEL_US_ONE_DATA;
1837 atmel_uart_writel(port, ATMEL_US_CR,
1842 if (atmel_use_dma_tx(port))
1843 txrdym = ATMEL_US_FOUR_DATA;
1845 fmr = ATMEL_US_TXRDYM(txrdym) | ATMEL_US_RXRDYM(rxrdym);
1846 if (atmel_port->rts_high &&
1847 atmel_port->rts_low)
1848 fmr |= ATMEL_US_FRTSC |
1849 ATMEL_US_RXFTHRES(atmel_port->rts_high) |
1850 ATMEL_US_RXFTHRES2(atmel_port->rts_low);
1852 atmel_uart_writel(port, ATMEL_US_FMR, fmr);
1855 /* Save current CSR for comparison in atmel_tasklet_func() */
1856 atmel_port->irq_status_prev = atmel_get_lines_status(port);
1859 * Finally, enable the serial port
1861 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
1862 /* enable xmit & rcvr */
1863 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
1864 atmel_port->tx_stopped = false;
1866 timer_setup(&atmel_port->uart_timer, atmel_uart_timer_callback, 0);
1868 if (atmel_use_pdc_rx(port)) {
1869 /* set UART timeout */
1870 if (!atmel_port->has_hw_timer) {
1871 mod_timer(&atmel_port->uart_timer,
1872 jiffies + uart_poll_timeout(port));
1873 /* set USART timeout */
1875 atmel_uart_writel(port, atmel_port->rtor,
1877 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1879 atmel_uart_writel(port, ATMEL_US_IER,
1880 ATMEL_US_ENDRX | ATMEL_US_TIMEOUT);
1882 /* enable PDC controller */
1883 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
1884 } else if (atmel_use_dma_rx(port)) {
1885 /* set UART timeout */
1886 if (!atmel_port->has_hw_timer) {
1887 mod_timer(&atmel_port->uart_timer,
1888 jiffies + uart_poll_timeout(port));
1889 /* set USART timeout */
1891 atmel_uart_writel(port, atmel_port->rtor,
1893 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_STTTO);
1895 atmel_uart_writel(port, ATMEL_US_IER,
1899 /* enable receive only */
1900 atmel_uart_writel(port, ATMEL_US_IER, ATMEL_US_RXRDY);
1907 * Flush any TX data submitted for DMA. Called when the TX circular
1910 static void atmel_flush_buffer(struct uart_port *port)
1912 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1914 if (atmel_use_pdc_tx(port)) {
1915 atmel_uart_writel(port, ATMEL_PDC_TCR, 0);
1916 atmel_port->pdc_tx.ofs = 0;
1919 * in uart_flush_buffer(), the xmit circular buffer has just
1920 * been cleared, so we have to reset tx_len accordingly.
1922 atmel_port->tx_len = 0;
1928 static void atmel_shutdown(struct uart_port *port)
1930 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1932 /* Disable modem control lines interrupts */
1933 atmel_disable_ms(port);
1935 /* Disable interrupts at device level */
1936 atmel_uart_writel(port, ATMEL_US_IDR, -1);
1938 /* Prevent spurious interrupts from scheduling the tasklet */
1939 atomic_inc(&atmel_port->tasklet_shutdown);
1942 * Prevent any tasklets being scheduled during
1945 del_timer_sync(&atmel_port->uart_timer);
1947 /* Make sure that no interrupt is on the fly */
1948 synchronize_irq(port->irq);
1951 * Clear out any scheduled tasklets before
1952 * we destroy the buffers
1954 tasklet_kill(&atmel_port->tasklet_rx);
1955 tasklet_kill(&atmel_port->tasklet_tx);
1958 * Ensure everything is stopped and
1959 * disable port and break condition.
1961 atmel_stop_rx(port);
1962 atmel_stop_tx(port);
1964 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA);
1967 * Shut-down the DMA.
1969 if (atmel_port->release_rx)
1970 atmel_port->release_rx(port);
1971 if (atmel_port->release_tx)
1972 atmel_port->release_tx(port);
1975 * Reset ring buffer pointers
1977 atmel_port->rx_ring.head = 0;
1978 atmel_port->rx_ring.tail = 0;
1981 * Free the interrupts
1983 free_irq(port->irq, port);
1985 atmel_flush_buffer(port);
1989 * Power / Clock management.
1991 static void atmel_serial_pm(struct uart_port *port, unsigned int state,
1992 unsigned int oldstate)
1994 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
1999 * Enable the peripheral clock for this serial port.
2000 * This is called on uart_open() or a resume event.
2002 clk_prepare_enable(atmel_port->clk);
2004 /* re-enable interrupts if we disabled some on suspend */
2005 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->backup_imr);
2008 /* Back up the interrupt mask and disable all interrupts */
2009 atmel_port->backup_imr = atmel_uart_readl(port, ATMEL_US_IMR);
2010 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2013 * Disable the peripheral clock for this serial port.
2014 * This is called on uart_close() or a suspend event.
2016 clk_disable_unprepare(atmel_port->clk);
2019 dev_err(port->dev, "atmel_serial: unknown pm %d\n", state);
2024 * Change the port parameters
2026 static void atmel_set_termios(struct uart_port *port, struct ktermios *termios,
2027 struct ktermios *old)
2029 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2030 unsigned long flags;
2031 unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0;
2033 /* save the current mode register */
2034 mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR);
2036 /* reset the mode, clock divisor, parity, stop bits and data size */
2037 mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP |
2038 ATMEL_US_PAR | ATMEL_US_USMODE);
2040 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
2043 switch (termios->c_cflag & CSIZE) {
2045 mode |= ATMEL_US_CHRL_5;
2048 mode |= ATMEL_US_CHRL_6;
2051 mode |= ATMEL_US_CHRL_7;
2054 mode |= ATMEL_US_CHRL_8;
2059 if (termios->c_cflag & CSTOPB)
2060 mode |= ATMEL_US_NBSTOP_2;
2063 if (termios->c_cflag & PARENB) {
2064 /* Mark or Space parity */
2065 if (termios->c_cflag & CMSPAR) {
2066 if (termios->c_cflag & PARODD)
2067 mode |= ATMEL_US_PAR_MARK;
2069 mode |= ATMEL_US_PAR_SPACE;
2070 } else if (termios->c_cflag & PARODD)
2071 mode |= ATMEL_US_PAR_ODD;
2073 mode |= ATMEL_US_PAR_EVEN;
2075 mode |= ATMEL_US_PAR_NONE;
2077 spin_lock_irqsave(&port->lock, flags);
2079 port->read_status_mask = ATMEL_US_OVRE;
2080 if (termios->c_iflag & INPCK)
2081 port->read_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2082 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2083 port->read_status_mask |= ATMEL_US_RXBRK;
2085 if (atmel_use_pdc_rx(port))
2086 /* need to enable error interrupts */
2087 atmel_uart_writel(port, ATMEL_US_IER, port->read_status_mask);
2090 * Characters to ignore
2092 port->ignore_status_mask = 0;
2093 if (termios->c_iflag & IGNPAR)
2094 port->ignore_status_mask |= (ATMEL_US_FRAME | ATMEL_US_PARE);
2095 if (termios->c_iflag & IGNBRK) {
2096 port->ignore_status_mask |= ATMEL_US_RXBRK;
2098 * If we're ignoring parity and break indicators,
2099 * ignore overruns too (for real raw support).
2101 if (termios->c_iflag & IGNPAR)
2102 port->ignore_status_mask |= ATMEL_US_OVRE;
2104 /* TODO: Ignore all characters if CREAD is set.*/
2106 /* update the per-port timeout */
2107 uart_update_timeout(port, termios->c_cflag, baud);
2110 * save/disable interrupts. The tty layer will ensure that the
2111 * transmitter is empty if requested by the caller, so there's
2112 * no need to wait for it here.
2114 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2115 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2117 /* disable receiver and transmitter */
2118 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXDIS | ATMEL_US_RXDIS);
2119 atmel_port->tx_stopped = true;
2122 if (port->rs485.flags & SER_RS485_ENABLED) {
2123 atmel_uart_writel(port, ATMEL_US_TTGR,
2124 port->rs485.delay_rts_after_send);
2125 mode |= ATMEL_US_USMODE_RS485;
2126 } else if (termios->c_cflag & CRTSCTS) {
2127 /* RS232 with hardware handshake (RTS/CTS) */
2128 if (atmel_use_fifo(port) &&
2129 !mctrl_gpio_to_gpiod(atmel_port->gpios, UART_GPIO_CTS)) {
2131 * with ATMEL_US_USMODE_HWHS set, the controller will
2132 * be able to drive the RTS pin high/low when the RX
2133 * FIFO is above RXFTHRES/below RXFTHRES2.
2134 * It will also disable the transmitter when the CTS
2136 * This mode is not activated if CTS pin is a GPIO
2137 * because in this case, the transmitter is always
2138 * disabled (there must be an internal pull-up
2139 * responsible for this behaviour).
2140 * If the RTS pin is a GPIO, the controller won't be
2141 * able to drive it according to the FIFO thresholds,
2142 * but it will be handled by the driver.
2144 mode |= ATMEL_US_USMODE_HWHS;
2147 * For platforms without FIFO, the flow control is
2148 * handled by the driver.
2150 mode |= ATMEL_US_USMODE_NORMAL;
2153 /* RS232 without hadware handshake */
2154 mode |= ATMEL_US_USMODE_NORMAL;
2157 /* set the mode, clock divisor, parity, stop bits and data size */
2158 atmel_uart_writel(port, ATMEL_US_MR, mode);
2161 * when switching the mode, set the RTS line state according to the
2162 * new mode, otherwise keep the former state
2164 if ((old_mode & ATMEL_US_USMODE) != (mode & ATMEL_US_USMODE)) {
2165 unsigned int rts_state;
2167 if ((mode & ATMEL_US_USMODE) == ATMEL_US_USMODE_HWHS) {
2168 /* let the hardware control the RTS line */
2169 rts_state = ATMEL_US_RTSDIS;
2171 /* force RTS line to low level */
2172 rts_state = ATMEL_US_RTSEN;
2175 atmel_uart_writel(port, ATMEL_US_CR, rts_state);
2179 * Set the baud rate:
2180 * Fractional baudrate allows to setup output frequency more
2181 * accurately. This feature is enabled only when using normal mode.
2182 * baudrate = selected clock / (8 * (2 - OVER) * (CD + FP / 8))
2183 * Currently, OVER is always set to 0 so we get
2184 * baudrate = selected clock / (16 * (CD + FP / 8))
2186 * 8 CD + FP = selected clock / (2 * baudrate)
2188 if (atmel_port->has_frac_baudrate) {
2189 div = DIV_ROUND_CLOSEST(port->uartclk, baud * 2);
2191 fp = div & ATMEL_US_FP_MASK;
2193 cd = uart_get_divisor(port, baud);
2196 if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */
2198 mode |= ATMEL_US_USCLKS_MCK_DIV8;
2200 quot = cd | fp << ATMEL_US_FP_OFFSET;
2202 atmel_uart_writel(port, ATMEL_US_BRGR, quot);
2203 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2204 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2205 atmel_port->tx_stopped = false;
2207 /* restore interrupts */
2208 atmel_uart_writel(port, ATMEL_US_IER, imr);
2210 /* CTS flow-control and modem-status interrupts */
2211 if (UART_ENABLE_MS(port, termios->c_cflag))
2212 atmel_enable_ms(port);
2214 atmel_disable_ms(port);
2216 spin_unlock_irqrestore(&port->lock, flags);
2219 static void atmel_set_ldisc(struct uart_port *port, struct ktermios *termios)
2221 if (termios->c_line == N_PPS) {
2222 port->flags |= UPF_HARDPPS_CD;
2223 spin_lock_irq(&port->lock);
2224 atmel_enable_ms(port);
2225 spin_unlock_irq(&port->lock);
2227 port->flags &= ~UPF_HARDPPS_CD;
2228 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2229 spin_lock_irq(&port->lock);
2230 atmel_disable_ms(port);
2231 spin_unlock_irq(&port->lock);
2237 * Return string describing the specified port
2239 static const char *atmel_type(struct uart_port *port)
2241 return (port->type == PORT_ATMEL) ? "ATMEL_SERIAL" : NULL;
2245 * Release the memory region(s) being used by 'port'.
2247 static void atmel_release_port(struct uart_port *port)
2249 struct platform_device *pdev = to_platform_device(port->dev);
2250 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2252 release_mem_region(port->mapbase, size);
2254 if (port->flags & UPF_IOREMAP) {
2255 iounmap(port->membase);
2256 port->membase = NULL;
2261 * Request the memory region(s) being used by 'port'.
2263 static int atmel_request_port(struct uart_port *port)
2265 struct platform_device *pdev = to_platform_device(port->dev);
2266 int size = pdev->resource[0].end - pdev->resource[0].start + 1;
2268 if (!request_mem_region(port->mapbase, size, "atmel_serial"))
2271 if (port->flags & UPF_IOREMAP) {
2272 port->membase = ioremap(port->mapbase, size);
2273 if (port->membase == NULL) {
2274 release_mem_region(port->mapbase, size);
2283 * Configure/autoconfigure the port.
2285 static void atmel_config_port(struct uart_port *port, int flags)
2287 if (flags & UART_CONFIG_TYPE) {
2288 port->type = PORT_ATMEL;
2289 atmel_request_port(port);
2294 * Verify the new serial_struct (for TIOCSSERIAL).
2296 static int atmel_verify_port(struct uart_port *port, struct serial_struct *ser)
2299 if (ser->type != PORT_UNKNOWN && ser->type != PORT_ATMEL)
2301 if (port->irq != ser->irq)
2303 if (ser->io_type != SERIAL_IO_MEM)
2305 if (port->uartclk / 16 != ser->baud_base)
2307 if (port->mapbase != (unsigned long)ser->iomem_base)
2309 if (port->iobase != ser->port)
2316 #ifdef CONFIG_CONSOLE_POLL
2317 static int atmel_poll_get_char(struct uart_port *port)
2319 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_RXRDY))
2322 return atmel_uart_read_char(port);
2325 static void atmel_poll_put_char(struct uart_port *port, unsigned char ch)
2327 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2330 atmel_uart_write_char(port, ch);
2334 static const struct uart_ops atmel_pops = {
2335 .tx_empty = atmel_tx_empty,
2336 .set_mctrl = atmel_set_mctrl,
2337 .get_mctrl = atmel_get_mctrl,
2338 .stop_tx = atmel_stop_tx,
2339 .start_tx = atmel_start_tx,
2340 .stop_rx = atmel_stop_rx,
2341 .enable_ms = atmel_enable_ms,
2342 .break_ctl = atmel_break_ctl,
2343 .startup = atmel_startup,
2344 .shutdown = atmel_shutdown,
2345 .flush_buffer = atmel_flush_buffer,
2346 .set_termios = atmel_set_termios,
2347 .set_ldisc = atmel_set_ldisc,
2349 .release_port = atmel_release_port,
2350 .request_port = atmel_request_port,
2351 .config_port = atmel_config_port,
2352 .verify_port = atmel_verify_port,
2353 .pm = atmel_serial_pm,
2354 #ifdef CONFIG_CONSOLE_POLL
2355 .poll_get_char = atmel_poll_get_char,
2356 .poll_put_char = atmel_poll_put_char,
2361 * Configure the port from the platform device resource info.
2363 static int atmel_init_port(struct atmel_uart_port *atmel_port,
2364 struct platform_device *pdev)
2367 struct uart_port *port = &atmel_port->uart;
2369 atmel_init_property(atmel_port, pdev);
2370 atmel_set_ops(port);
2372 uart_get_rs485_mode(&pdev->dev, &port->rs485);
2374 port->iotype = UPIO_MEM;
2375 port->flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
2376 port->ops = &atmel_pops;
2378 port->dev = &pdev->dev;
2379 port->mapbase = pdev->resource[0].start;
2380 port->irq = pdev->resource[1].start;
2381 port->rs485_config = atmel_config_rs485;
2382 port->membase = NULL;
2384 memset(&atmel_port->rx_ring, 0, sizeof(atmel_port->rx_ring));
2386 /* for console, the clock could already be configured */
2387 if (!atmel_port->clk) {
2388 atmel_port->clk = clk_get(&pdev->dev, "usart");
2389 if (IS_ERR(atmel_port->clk)) {
2390 ret = PTR_ERR(atmel_port->clk);
2391 atmel_port->clk = NULL;
2394 ret = clk_prepare_enable(atmel_port->clk);
2396 clk_put(atmel_port->clk);
2397 atmel_port->clk = NULL;
2400 port->uartclk = clk_get_rate(atmel_port->clk);
2401 clk_disable_unprepare(atmel_port->clk);
2402 /* only enable clock when USART is in use */
2405 /* Use TXEMPTY for interrupt when rs485 else TXRDY or ENDTX|TXBUFE */
2406 if (port->rs485.flags & SER_RS485_ENABLED)
2407 atmel_port->tx_done_mask = ATMEL_US_TXEMPTY;
2408 else if (atmel_use_pdc_tx(port)) {
2409 port->fifosize = PDC_BUFFER_SIZE;
2410 atmel_port->tx_done_mask = ATMEL_US_ENDTX | ATMEL_US_TXBUFE;
2412 atmel_port->tx_done_mask = ATMEL_US_TXRDY;
2418 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2419 static void atmel_console_putchar(struct uart_port *port, int ch)
2421 while (!(atmel_uart_readl(port, ATMEL_US_CSR) & ATMEL_US_TXRDY))
2423 atmel_uart_write_char(port, ch);
2427 * Interrupts are disabled on entering
2429 static void atmel_console_write(struct console *co, const char *s, u_int count)
2431 struct uart_port *port = &atmel_ports[co->index].uart;
2432 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2433 unsigned int status, imr;
2434 unsigned int pdc_tx;
2437 * First, save IMR and then disable interrupts
2439 imr = atmel_uart_readl(port, ATMEL_US_IMR);
2440 atmel_uart_writel(port, ATMEL_US_IDR,
2441 ATMEL_US_RXRDY | atmel_port->tx_done_mask);
2443 /* Store PDC transmit status and disable it */
2444 pdc_tx = atmel_uart_readl(port, ATMEL_PDC_PTSR) & ATMEL_PDC_TXTEN;
2445 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTDIS);
2447 /* Make sure that tx path is actually able to send characters */
2448 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN);
2449 atmel_port->tx_stopped = false;
2451 uart_console_write(port, s, count, atmel_console_putchar);
2454 * Finally, wait for transmitter to become empty
2458 status = atmel_uart_readl(port, ATMEL_US_CSR);
2459 } while (!(status & ATMEL_US_TXRDY));
2461 /* Restore PDC transmit status */
2463 atmel_uart_writel(port, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
2465 /* set interrupts back the way they were */
2466 atmel_uart_writel(port, ATMEL_US_IER, imr);
2470 * If the port was already initialised (eg, by a boot loader),
2471 * try to determine the current setup.
2473 static void __init atmel_console_get_options(struct uart_port *port, int *baud,
2474 int *parity, int *bits)
2476 unsigned int mr, quot;
2479 * If the baud rate generator isn't running, the port wasn't
2480 * initialized by the boot loader.
2482 quot = atmel_uart_readl(port, ATMEL_US_BRGR) & ATMEL_US_CD;
2486 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_CHRL;
2487 if (mr == ATMEL_US_CHRL_8)
2492 mr = atmel_uart_readl(port, ATMEL_US_MR) & ATMEL_US_PAR;
2493 if (mr == ATMEL_US_PAR_EVEN)
2495 else if (mr == ATMEL_US_PAR_ODD)
2499 * The serial core only rounds down when matching this to a
2500 * supported baud rate. Make sure we don't end up slightly
2501 * lower than one of those, as it would make us fall through
2502 * to a much lower baud rate than we really want.
2504 *baud = port->uartclk / (16 * (quot - 1));
2507 static int __init atmel_console_setup(struct console *co, char *options)
2510 struct uart_port *port = &atmel_ports[co->index].uart;
2511 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2517 if (port->membase == NULL) {
2518 /* Port not initialized yet - delay setup */
2522 ret = clk_prepare_enable(atmel_ports[co->index].clk);
2526 atmel_uart_writel(port, ATMEL_US_IDR, -1);
2527 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_RSTSTA | ATMEL_US_RSTRX);
2528 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_TXEN | ATMEL_US_RXEN);
2529 atmel_port->tx_stopped = false;
2532 uart_parse_options(options, &baud, &parity, &bits, &flow);
2534 atmel_console_get_options(port, &baud, &parity, &bits);
2536 return uart_set_options(port, co, baud, parity, bits, flow);
2539 static struct uart_driver atmel_uart;
2541 static struct console atmel_console = {
2542 .name = ATMEL_DEVICENAME,
2543 .write = atmel_console_write,
2544 .device = uart_console_device,
2545 .setup = atmel_console_setup,
2546 .flags = CON_PRINTBUFFER,
2548 .data = &atmel_uart,
2551 #define ATMEL_CONSOLE_DEVICE (&atmel_console)
2553 static inline bool atmel_is_console_port(struct uart_port *port)
2555 return port->cons && port->cons->index == port->line;
2559 #define ATMEL_CONSOLE_DEVICE NULL
2561 static inline bool atmel_is_console_port(struct uart_port *port)
2567 static struct uart_driver atmel_uart = {
2568 .owner = THIS_MODULE,
2569 .driver_name = "atmel_serial",
2570 .dev_name = ATMEL_DEVICENAME,
2571 .major = SERIAL_ATMEL_MAJOR,
2572 .minor = MINOR_START,
2573 .nr = ATMEL_MAX_UART,
2574 .cons = ATMEL_CONSOLE_DEVICE,
2578 static bool atmel_serial_clk_will_stop(void)
2580 #ifdef CONFIG_ARCH_AT91
2581 return at91_suspend_entering_slow_clock();
2587 static int atmel_serial_suspend(struct platform_device *pdev,
2590 struct uart_port *port = platform_get_drvdata(pdev);
2591 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2593 if (atmel_is_console_port(port) && console_suspend_enabled) {
2594 /* Drain the TX shifter */
2595 while (!(atmel_uart_readl(port, ATMEL_US_CSR) &
2600 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2601 /* Cache register values as we won't get a full shutdown/startup
2604 atmel_port->cache.mr = atmel_uart_readl(port, ATMEL_US_MR);
2605 atmel_port->cache.imr = atmel_uart_readl(port, ATMEL_US_IMR);
2606 atmel_port->cache.brgr = atmel_uart_readl(port, ATMEL_US_BRGR);
2607 atmel_port->cache.rtor = atmel_uart_readl(port,
2609 atmel_port->cache.ttgr = atmel_uart_readl(port, ATMEL_US_TTGR);
2610 atmel_port->cache.fmr = atmel_uart_readl(port, ATMEL_US_FMR);
2611 atmel_port->cache.fimr = atmel_uart_readl(port, ATMEL_US_FIMR);
2614 /* we can not wake up if we're running on slow clock */
2615 atmel_port->may_wakeup = device_may_wakeup(&pdev->dev);
2616 if (atmel_serial_clk_will_stop()) {
2617 unsigned long flags;
2619 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2620 atmel_port->suspended = true;
2621 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2622 device_set_wakeup_enable(&pdev->dev, 0);
2625 uart_suspend_port(&atmel_uart, port);
2630 static int atmel_serial_resume(struct platform_device *pdev)
2632 struct uart_port *port = platform_get_drvdata(pdev);
2633 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2634 unsigned long flags;
2636 if (atmel_is_console_port(port) && !console_suspend_enabled) {
2637 atmel_uart_writel(port, ATMEL_US_MR, atmel_port->cache.mr);
2638 atmel_uart_writel(port, ATMEL_US_IER, atmel_port->cache.imr);
2639 atmel_uart_writel(port, ATMEL_US_BRGR, atmel_port->cache.brgr);
2640 atmel_uart_writel(port, atmel_port->rtor,
2641 atmel_port->cache.rtor);
2642 atmel_uart_writel(port, ATMEL_US_TTGR, atmel_port->cache.ttgr);
2644 if (atmel_port->fifo_size) {
2645 atmel_uart_writel(port, ATMEL_US_CR, ATMEL_US_FIFOEN |
2646 ATMEL_US_RXFCLR | ATMEL_US_TXFLCLR);
2647 atmel_uart_writel(port, ATMEL_US_FMR,
2648 atmel_port->cache.fmr);
2649 atmel_uart_writel(port, ATMEL_US_FIER,
2650 atmel_port->cache.fimr);
2652 atmel_start_rx(port);
2655 spin_lock_irqsave(&atmel_port->lock_suspended, flags);
2656 if (atmel_port->pending) {
2657 atmel_handle_receive(port, atmel_port->pending);
2658 atmel_handle_status(port, atmel_port->pending,
2659 atmel_port->pending_status);
2660 atmel_handle_transmit(port, atmel_port->pending);
2661 atmel_port->pending = 0;
2663 atmel_port->suspended = false;
2664 spin_unlock_irqrestore(&atmel_port->lock_suspended, flags);
2666 uart_resume_port(&atmel_uart, port);
2667 device_set_wakeup_enable(&pdev->dev, atmel_port->may_wakeup);
2672 #define atmel_serial_suspend NULL
2673 #define atmel_serial_resume NULL
2676 static void atmel_serial_probe_fifos(struct atmel_uart_port *atmel_port,
2677 struct platform_device *pdev)
2679 atmel_port->fifo_size = 0;
2680 atmel_port->rts_low = 0;
2681 atmel_port->rts_high = 0;
2683 if (of_property_read_u32(pdev->dev.of_node,
2685 &atmel_port->fifo_size))
2688 if (!atmel_port->fifo_size)
2691 if (atmel_port->fifo_size < ATMEL_MIN_FIFO_SIZE) {
2692 atmel_port->fifo_size = 0;
2693 dev_err(&pdev->dev, "Invalid FIFO size\n");
2698 * 0 <= rts_low <= rts_high <= fifo_size
2699 * Once their CTS line asserted by the remote peer, some x86 UARTs tend
2700 * to flush their internal TX FIFO, commonly up to 16 data, before
2701 * actually stopping to send new data. So we try to set the RTS High
2702 * Threshold to a reasonably high value respecting this 16 data
2703 * empirical rule when possible.
2705 atmel_port->rts_high = max_t(int, atmel_port->fifo_size >> 1,
2706 atmel_port->fifo_size - ATMEL_RTS_HIGH_OFFSET);
2707 atmel_port->rts_low = max_t(int, atmel_port->fifo_size >> 2,
2708 atmel_port->fifo_size - ATMEL_RTS_LOW_OFFSET);
2710 dev_info(&pdev->dev, "Using FIFO (%u data)\n",
2711 atmel_port->fifo_size);
2712 dev_dbg(&pdev->dev, "RTS High Threshold : %2u data\n",
2713 atmel_port->rts_high);
2714 dev_dbg(&pdev->dev, "RTS Low Threshold : %2u data\n",
2715 atmel_port->rts_low);
2718 static int atmel_serial_probe(struct platform_device *pdev)
2720 struct atmel_uart_port *atmel_port;
2721 struct device_node *np = pdev->dev.of_node;
2726 BUILD_BUG_ON(ATMEL_SERIAL_RINGSIZE & (ATMEL_SERIAL_RINGSIZE - 1));
2728 ret = of_alias_get_id(np, "serial");
2730 /* port id not found in platform data nor device-tree aliases:
2731 * auto-enumerate it */
2732 ret = find_first_zero_bit(atmel_ports_in_use, ATMEL_MAX_UART);
2734 if (ret >= ATMEL_MAX_UART) {
2739 if (test_and_set_bit(ret, atmel_ports_in_use)) {
2740 /* port already in use */
2745 atmel_port = &atmel_ports[ret];
2746 atmel_port->backup_imr = 0;
2747 atmel_port->uart.line = ret;
2748 atmel_serial_probe_fifos(atmel_port, pdev);
2750 atomic_set(&atmel_port->tasklet_shutdown, 0);
2751 spin_lock_init(&atmel_port->lock_suspended);
2753 ret = atmel_init_port(atmel_port, pdev);
2757 atmel_port->gpios = mctrl_gpio_init(&atmel_port->uart, 0);
2758 if (IS_ERR(atmel_port->gpios)) {
2759 ret = PTR_ERR(atmel_port->gpios);
2763 if (!atmel_use_pdc_rx(&atmel_port->uart)) {
2765 data = kmalloc_array(ATMEL_SERIAL_RINGSIZE,
2766 sizeof(struct atmel_uart_char),
2769 goto err_alloc_ring;
2770 atmel_port->rx_ring.buf = data;
2773 rs485_enabled = atmel_port->uart.rs485.flags & SER_RS485_ENABLED;
2775 ret = uart_add_one_port(&atmel_uart, &atmel_port->uart);
2779 #ifdef CONFIG_SERIAL_ATMEL_CONSOLE
2780 if (atmel_is_console_port(&atmel_port->uart)
2781 && ATMEL_CONSOLE_DEVICE->flags & CON_ENABLED) {
2783 * The serial core enabled the clock for us, so undo
2784 * the clk_prepare_enable() in atmel_console_setup()
2786 clk_disable_unprepare(atmel_port->clk);
2790 device_init_wakeup(&pdev->dev, 1);
2791 platform_set_drvdata(pdev, atmel_port);
2794 * The peripheral clock has been disabled by atmel_init_port():
2795 * enable it before accessing I/O registers
2797 clk_prepare_enable(atmel_port->clk);
2799 if (rs485_enabled) {
2800 atmel_uart_writel(&atmel_port->uart, ATMEL_US_MR,
2801 ATMEL_US_USMODE_NORMAL);
2802 atmel_uart_writel(&atmel_port->uart, ATMEL_US_CR,
2807 * Get port name of usart or uart
2809 atmel_get_ip_name(&atmel_port->uart);
2812 * The peripheral clock can now safely be disabled till the port
2815 clk_disable_unprepare(atmel_port->clk);
2820 kfree(atmel_port->rx_ring.buf);
2821 atmel_port->rx_ring.buf = NULL;
2823 if (!atmel_is_console_port(&atmel_port->uart)) {
2824 clk_put(atmel_port->clk);
2825 atmel_port->clk = NULL;
2828 clear_bit(atmel_port->uart.line, atmel_ports_in_use);
2834 * Even if the driver is not modular, it makes sense to be able to
2835 * unbind a device: there can be many bound devices, and there are
2836 * situations where dynamic binding and unbinding can be useful.
2838 * For example, a connected device can require a specific firmware update
2839 * protocol that needs bitbanging on IO lines, but use the regular serial
2840 * port in the normal case.
2842 static int atmel_serial_remove(struct platform_device *pdev)
2844 struct uart_port *port = platform_get_drvdata(pdev);
2845 struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
2848 tasklet_kill(&atmel_port->tasklet_rx);
2849 tasklet_kill(&atmel_port->tasklet_tx);
2851 device_init_wakeup(&pdev->dev, 0);
2853 ret = uart_remove_one_port(&atmel_uart, port);
2855 kfree(atmel_port->rx_ring.buf);
2857 /* "port" is allocated statically, so we shouldn't free it */
2859 clear_bit(port->line, atmel_ports_in_use);
2861 clk_put(atmel_port->clk);
2862 atmel_port->clk = NULL;
2867 static struct platform_driver atmel_serial_driver = {
2868 .probe = atmel_serial_probe,
2869 .remove = atmel_serial_remove,
2870 .suspend = atmel_serial_suspend,
2871 .resume = atmel_serial_resume,
2873 .name = "atmel_usart",
2874 .of_match_table = of_match_ptr(atmel_serial_dt_ids),
2878 static int __init atmel_serial_init(void)
2882 ret = uart_register_driver(&atmel_uart);
2886 ret = platform_driver_register(&atmel_serial_driver);
2888 uart_unregister_driver(&atmel_uart);
2892 device_initcall(atmel_serial_init);