1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/sysrq.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/tty.h>
24 #include <linux/ratelimit.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_8250.h>
28 #include <linux/nmi.h>
29 #include <linux/mutex.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/ktime.h>
40 /* Nuvoton NPCM timeout register */
41 #define UART_NPCM_TOR 7
42 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
48 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
50 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
54 * Here we define the default xmit fifo size used for each type of UART.
56 static const struct serial8250_config uart_config[] = {
81 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
82 .rxtrig_bytes = {1, 4, 8, 14},
83 .flags = UART_CAP_FIFO,
94 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
100 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
102 .rxtrig_bytes = {8, 16, 24, 28},
103 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
109 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
111 .rxtrig_bytes = {1, 16, 32, 56},
112 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
120 .name = "16C950/954",
123 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
124 .rxtrig_bytes = {16, 32, 112, 120},
125 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
126 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
132 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
134 .rxtrig_bytes = {8, 16, 56, 60},
135 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
141 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
142 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
148 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
149 .flags = UART_CAP_FIFO,
155 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
156 .flags = UART_CAP_FIFO | UART_NATSEMI,
162 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
163 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
169 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
170 .flags = UART_CAP_FIFO,
176 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
177 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
183 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
184 .flags = UART_CAP_FIFO | UART_CAP_AFE,
190 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
192 .rxtrig_bytes = {1, 4, 8, 14},
193 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
199 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
200 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
207 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
209 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
216 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
217 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
218 .flags = UART_CAP_FIFO,
220 [PORT_BRCM_TRUMANAGE] = {
224 .flags = UART_CAP_HFIFO,
229 [PORT_ALTR_16550_F32] = {
230 .name = "Altera 16550 FIFO32",
233 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
234 .rxtrig_bytes = {1, 8, 16, 30},
235 .flags = UART_CAP_FIFO | UART_CAP_AFE,
237 [PORT_ALTR_16550_F64] = {
238 .name = "Altera 16550 FIFO64",
241 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
242 .rxtrig_bytes = {1, 16, 32, 62},
243 .flags = UART_CAP_FIFO | UART_CAP_AFE,
245 [PORT_ALTR_16550_F128] = {
246 .name = "Altera 16550 FIFO128",
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
250 .rxtrig_bytes = {1, 32, 64, 126},
251 .flags = UART_CAP_FIFO | UART_CAP_AFE,
254 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
255 * workaround of errata A-008006 which states that tx_loadsz should
256 * be configured less than Maximum supported fifo bytes.
258 [PORT_16550A_FSL64] = {
259 .name = "16550A_FSL64",
262 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
264 .flags = UART_CAP_FIFO | UART_CAP_NOTEMT,
267 .name = "Palmchip BK-3103",
270 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
271 .rxtrig_bytes = {1, 4, 8, 14},
272 .flags = UART_CAP_FIFO,
275 .name = "TI DA8xx/66AK2x",
278 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
280 .rxtrig_bytes = {1, 4, 8, 14},
281 .flags = UART_CAP_FIFO | UART_CAP_AFE,
284 .name = "MediaTek BTIF",
287 .fcr = UART_FCR_ENABLE_FIFO |
288 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
289 .flags = UART_CAP_FIFO,
292 .name = "Nuvoton 16550",
295 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
296 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
297 .rxtrig_bytes = {1, 4, 8, 14},
298 .flags = UART_CAP_FIFO,
304 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
305 .rxtrig_bytes = {1, 32, 64, 112},
306 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
308 [PORT_ASPEED_VUART] = {
309 .name = "ASPEED VUART",
312 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
313 .rxtrig_bytes = {1, 4, 8, 14},
314 .flags = UART_CAP_FIFO,
318 /* Uart divisor latch read */
319 static int default_serial_dl_read(struct uart_8250_port *up)
321 /* Assign these in pieces to truncate any bits above 7. */
322 unsigned char dll = serial_in(up, UART_DLL);
323 unsigned char dlm = serial_in(up, UART_DLM);
325 return dll | dlm << 8;
328 /* Uart divisor latch write */
329 static void default_serial_dl_write(struct uart_8250_port *up, int value)
331 serial_out(up, UART_DLL, value & 0xff);
332 serial_out(up, UART_DLM, value >> 8 & 0xff);
335 #ifdef CONFIG_SERIAL_8250_RT288X
337 #define UART_REG_UNMAPPED -1
339 /* Au1x00/RT288x UART hardware has a weird register layout */
340 static const s8 au_io_in_map[8] = {
348 [UART_SCR] = UART_REG_UNMAPPED,
351 static const s8 au_io_out_map[8] = {
357 [UART_LSR] = UART_REG_UNMAPPED,
358 [UART_MSR] = UART_REG_UNMAPPED,
359 [UART_SCR] = UART_REG_UNMAPPED,
362 unsigned int au_serial_in(struct uart_port *p, int offset)
364 if (offset >= ARRAY_SIZE(au_io_in_map))
366 offset = au_io_in_map[offset];
367 if (offset == UART_REG_UNMAPPED)
369 return __raw_readl(p->membase + (offset << p->regshift));
372 void au_serial_out(struct uart_port *p, int offset, int value)
374 if (offset >= ARRAY_SIZE(au_io_out_map))
376 offset = au_io_out_map[offset];
377 if (offset == UART_REG_UNMAPPED)
379 __raw_writel(value, p->membase + (offset << p->regshift));
382 /* Au1x00 haven't got a standard divisor latch */
383 static int au_serial_dl_read(struct uart_8250_port *up)
385 return __raw_readl(up->port.membase + 0x28);
388 static void au_serial_dl_write(struct uart_8250_port *up, int value)
390 __raw_writel(value, up->port.membase + 0x28);
395 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
397 offset = offset << p->regshift;
398 outb(p->hub6 - 1 + offset, p->iobase);
399 return inb(p->iobase + 1);
402 static void hub6_serial_out(struct uart_port *p, int offset, int value)
404 offset = offset << p->regshift;
405 outb(p->hub6 - 1 + offset, p->iobase);
406 outb(value, p->iobase + 1);
409 static unsigned int mem_serial_in(struct uart_port *p, int offset)
411 offset = offset << p->regshift;
412 return readb(p->membase + offset);
415 static void mem_serial_out(struct uart_port *p, int offset, int value)
417 offset = offset << p->regshift;
418 writeb(value, p->membase + offset);
421 static void mem16_serial_out(struct uart_port *p, int offset, int value)
423 offset = offset << p->regshift;
424 writew(value, p->membase + offset);
427 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
429 offset = offset << p->regshift;
430 return readw(p->membase + offset);
433 static void mem32_serial_out(struct uart_port *p, int offset, int value)
435 offset = offset << p->regshift;
436 writel(value, p->membase + offset);
439 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
441 offset = offset << p->regshift;
442 return readl(p->membase + offset);
445 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
447 offset = offset << p->regshift;
448 iowrite32be(value, p->membase + offset);
451 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
453 offset = offset << p->regshift;
454 return ioread32be(p->membase + offset);
457 static unsigned int io_serial_in(struct uart_port *p, int offset)
459 offset = offset << p->regshift;
460 return inb(p->iobase + offset);
463 static void io_serial_out(struct uart_port *p, int offset, int value)
465 offset = offset << p->regshift;
466 outb(value, p->iobase + offset);
469 static int serial8250_default_handle_irq(struct uart_port *port);
471 static void set_io_from_upio(struct uart_port *p)
473 struct uart_8250_port *up = up_to_u8250p(p);
475 up->dl_read = default_serial_dl_read;
476 up->dl_write = default_serial_dl_write;
480 p->serial_in = hub6_serial_in;
481 p->serial_out = hub6_serial_out;
485 p->serial_in = mem_serial_in;
486 p->serial_out = mem_serial_out;
490 p->serial_in = mem16_serial_in;
491 p->serial_out = mem16_serial_out;
495 p->serial_in = mem32_serial_in;
496 p->serial_out = mem32_serial_out;
500 p->serial_in = mem32be_serial_in;
501 p->serial_out = mem32be_serial_out;
504 #ifdef CONFIG_SERIAL_8250_RT288X
506 p->serial_in = au_serial_in;
507 p->serial_out = au_serial_out;
508 up->dl_read = au_serial_dl_read;
509 up->dl_write = au_serial_dl_write;
514 p->serial_in = io_serial_in;
515 p->serial_out = io_serial_out;
518 /* Remember loaded iotype */
519 up->cur_iotype = p->iotype;
520 p->handle_irq = serial8250_default_handle_irq;
524 serial_port_out_sync(struct uart_port *p, int offset, int value)
532 p->serial_out(p, offset, value);
533 p->serial_in(p, UART_LCR); /* safe, no side-effects */
536 p->serial_out(p, offset, value);
543 static void serial8250_clear_fifos(struct uart_8250_port *p)
545 if (p->capabilities & UART_CAP_FIFO) {
546 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
547 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
548 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
549 serial_out(p, UART_FCR, 0);
553 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
554 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
556 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
558 serial8250_clear_fifos(p);
559 serial_out(p, UART_FCR, p->fcr);
561 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
563 void serial8250_rpm_get(struct uart_8250_port *p)
565 if (!(p->capabilities & UART_CAP_RPM))
567 pm_runtime_get_sync(p->port.dev);
569 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
571 void serial8250_rpm_put(struct uart_8250_port *p)
573 if (!(p->capabilities & UART_CAP_RPM))
575 pm_runtime_mark_last_busy(p->port.dev);
576 pm_runtime_put_autosuspend(p->port.dev);
578 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
581 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
582 * @p: uart_8250_port port instance
584 * The function is used to start rs485 software emulating on the
585 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
586 * transmission. The function is idempotent, so it is safe to call it
589 * The caller MUST enable interrupt on empty shift register before
590 * calling serial8250_em485_init(). This interrupt is not a part of
591 * 8250 standard, but implementation defined.
593 * The function is supposed to be called from .rs485_config callback
594 * or from any other callback protected with p->port.lock spinlock.
596 * See also serial8250_em485_destroy()
598 * Return 0 - success, -errno - otherwise
600 static int serial8250_em485_init(struct uart_8250_port *p)
605 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
609 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
611 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
613 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
614 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
616 p->em485->active_timer = NULL;
617 p->em485->tx_stopped = true;
620 if (p->em485->tx_stopped)
627 * serial8250_em485_destroy() - put uart_8250_port into normal state
628 * @p: uart_8250_port port instance
630 * The function is used to stop rs485 software emulating on the
631 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
632 * call it multiple times.
634 * The function is supposed to be called from .rs485_config callback
635 * or from any other callback protected with p->port.lock spinlock.
637 * See also serial8250_em485_init()
639 void serial8250_em485_destroy(struct uart_8250_port *p)
644 hrtimer_cancel(&p->em485->start_tx_timer);
645 hrtimer_cancel(&p->em485->stop_tx_timer);
650 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
652 struct serial_rs485 serial8250_em485_supported = {
653 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
654 SER_RS485_TERMINATE_BUS | SER_RS485_RX_DURING_TX,
655 .delay_rts_before_send = 1,
656 .delay_rts_after_send = 1,
658 EXPORT_SYMBOL_GPL(serial8250_em485_supported);
661 * serial8250_em485_config() - generic ->rs485_config() callback
663 * @rs485: rs485 settings
665 * Generic callback usable by 8250 uart drivers to activate rs485 settings
666 * if the uart is incapable of driving RTS as a Transmit Enable signal in
667 * hardware, relying on software emulation instead.
669 int serial8250_em485_config(struct uart_port *port, struct ktermios *termios,
670 struct serial_rs485 *rs485)
672 struct uart_8250_port *up = up_to_u8250p(port);
674 /* pick sane settings if the user hasn't */
675 if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
676 !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
677 rs485->flags |= SER_RS485_RTS_ON_SEND;
678 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
682 * Both serial8250_em485_init() and serial8250_em485_destroy()
685 if (rs485->flags & SER_RS485_ENABLED)
686 return serial8250_em485_init(up);
688 serial8250_em485_destroy(up);
691 EXPORT_SYMBOL_GPL(serial8250_em485_config);
694 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
695 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
696 * empty and the HW can idle again.
698 void serial8250_rpm_get_tx(struct uart_8250_port *p)
700 unsigned char rpm_active;
702 if (!(p->capabilities & UART_CAP_RPM))
705 rpm_active = xchg(&p->rpm_tx_active, 1);
708 pm_runtime_get_sync(p->port.dev);
710 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
712 void serial8250_rpm_put_tx(struct uart_8250_port *p)
714 unsigned char rpm_active;
716 if (!(p->capabilities & UART_CAP_RPM))
719 rpm_active = xchg(&p->rpm_tx_active, 0);
722 pm_runtime_mark_last_busy(p->port.dev);
723 pm_runtime_put_autosuspend(p->port.dev);
725 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
728 * IER sleep support. UARTs which have EFRs need the "extended
729 * capability" bit enabled. Note that on XR16C850s, we need to
730 * reset LCR to write to IER.
732 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
734 unsigned char lcr = 0, efr = 0;
736 serial8250_rpm_get(p);
738 if (p->capabilities & UART_CAP_SLEEP) {
739 if (p->capabilities & UART_CAP_EFR) {
740 lcr = serial_in(p, UART_LCR);
741 efr = serial_in(p, UART_EFR);
742 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
743 serial_out(p, UART_EFR, UART_EFR_ECB);
744 serial_out(p, UART_LCR, 0);
746 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
747 if (p->capabilities & UART_CAP_EFR) {
748 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
749 serial_out(p, UART_EFR, efr);
750 serial_out(p, UART_LCR, lcr);
754 serial8250_rpm_put(p);
757 static void serial8250_clear_IER(struct uart_8250_port *up)
759 if (up->capabilities & UART_CAP_UUE)
760 serial_out(up, UART_IER, UART_IER_UUE);
762 serial_out(up, UART_IER, 0);
765 #ifdef CONFIG_SERIAL_8250_RSA
767 * Attempts to turn on the RSA FIFO. Returns zero on failure.
768 * We set the port uart clock rate if we succeed.
770 static int __enable_rsa(struct uart_8250_port *up)
775 mode = serial_in(up, UART_RSA_MSR);
776 result = mode & UART_RSA_MSR_FIFO;
779 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
780 mode = serial_in(up, UART_RSA_MSR);
781 result = mode & UART_RSA_MSR_FIFO;
785 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
790 static void enable_rsa(struct uart_8250_port *up)
792 if (up->port.type == PORT_RSA) {
793 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
794 spin_lock_irq(&up->port.lock);
796 spin_unlock_irq(&up->port.lock);
798 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
799 serial_out(up, UART_RSA_FRR, 0);
804 * Attempts to turn off the RSA FIFO. Returns zero on failure.
805 * It is unknown why interrupts were disabled in here. However,
806 * the caller is expected to preserve this behaviour by grabbing
807 * the spinlock before calling this function.
809 static void disable_rsa(struct uart_8250_port *up)
814 if (up->port.type == PORT_RSA &&
815 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
816 spin_lock_irq(&up->port.lock);
818 mode = serial_in(up, UART_RSA_MSR);
819 result = !(mode & UART_RSA_MSR_FIFO);
822 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
823 mode = serial_in(up, UART_RSA_MSR);
824 result = !(mode & UART_RSA_MSR_FIFO);
828 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
829 spin_unlock_irq(&up->port.lock);
832 #endif /* CONFIG_SERIAL_8250_RSA */
835 * This is a quickie test to see how big the FIFO is.
836 * It doesn't work at all the time, more's the pity.
838 static int size_fifo(struct uart_8250_port *up)
840 unsigned char old_fcr, old_mcr, old_lcr;
841 unsigned short old_dl;
844 old_lcr = serial_in(up, UART_LCR);
845 serial_out(up, UART_LCR, 0);
846 old_fcr = serial_in(up, UART_FCR);
847 old_mcr = serial8250_in_MCR(up);
848 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
849 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
850 serial8250_out_MCR(up, UART_MCR_LOOP);
851 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
852 old_dl = serial_dl_read(up);
853 serial_dl_write(up, 0x0001);
854 serial_out(up, UART_LCR, UART_LCR_WLEN8);
855 for (count = 0; count < 256; count++)
856 serial_out(up, UART_TX, count);
857 mdelay(20);/* FIXME - schedule_timeout */
858 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
859 (count < 256); count++)
860 serial_in(up, UART_RX);
861 serial_out(up, UART_FCR, old_fcr);
862 serial8250_out_MCR(up, old_mcr);
863 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
864 serial_dl_write(up, old_dl);
865 serial_out(up, UART_LCR, old_lcr);
871 * Read UART ID using the divisor method - set DLL and DLM to zero
872 * and the revision will be in DLL and device type in DLM. We
873 * preserve the device state across this.
875 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
877 unsigned char old_lcr;
878 unsigned int id, old_dl;
880 old_lcr = serial_in(p, UART_LCR);
881 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
882 old_dl = serial_dl_read(p);
883 serial_dl_write(p, 0);
884 id = serial_dl_read(p);
885 serial_dl_write(p, old_dl);
887 serial_out(p, UART_LCR, old_lcr);
893 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
894 * When this function is called we know it is at least a StarTech
895 * 16650 V2, but it might be one of several StarTech UARTs, or one of
896 * its clones. (We treat the broken original StarTech 16650 V1 as a
897 * 16550, and why not? Startech doesn't seem to even acknowledge its
900 * What evil have men's minds wrought...
902 static void autoconfig_has_efr(struct uart_8250_port *up)
904 unsigned int id1, id2, id3, rev;
907 * Everything with an EFR has SLEEP
909 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
912 * First we check to see if it's an Oxford Semiconductor UART.
914 * If we have to do this here because some non-National
915 * Semiconductor clone chips lock up if you try writing to the
916 * LSR register (which serial_icr_read does)
920 * Check for Oxford Semiconductor 16C950.
922 * EFR [4] must be set else this test fails.
924 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
925 * claims that it's needed for 952 dual UART's (which are not
926 * recommended for new designs).
929 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
930 serial_out(up, UART_EFR, UART_EFR_ECB);
931 serial_out(up, UART_LCR, 0x00);
932 id1 = serial_icr_read(up, UART_ID1);
933 id2 = serial_icr_read(up, UART_ID2);
934 id3 = serial_icr_read(up, UART_ID3);
935 rev = serial_icr_read(up, UART_REV);
937 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
939 if (id1 == 0x16 && id2 == 0xC9 &&
940 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
941 up->port.type = PORT_16C950;
944 * Enable work around for the Oxford Semiconductor 952 rev B
945 * chip which causes it to seriously miscalculate baud rates
948 if (id3 == 0x52 && rev == 0x01)
949 up->bugs |= UART_BUG_QUOT;
954 * We check for a XR16C850 by setting DLL and DLM to 0, and then
955 * reading back DLL and DLM. The chip type depends on the DLM
957 * 0x10 - XR16C850 and the DLL contains the chip revision.
961 id1 = autoconfig_read_divisor_id(up);
962 DEBUG_AUTOCONF("850id=%04x ", id1);
965 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
966 up->port.type = PORT_16850;
971 * It wasn't an XR16C850.
973 * We distinguish between the '654 and the '650 by counting
974 * how many bytes are in the FIFO. I'm using this for now,
975 * since that's the technique that was sent to me in the
976 * serial driver update, but I'm not convinced this works.
977 * I've had problems doing this in the past. -TYT
979 if (size_fifo(up) == 64)
980 up->port.type = PORT_16654;
982 up->port.type = PORT_16650V2;
986 * We detected a chip without a FIFO. Only two fall into
987 * this category - the original 8250 and the 16450. The
988 * 16450 has a scratch register (accessible with LCR=0)
990 static void autoconfig_8250(struct uart_8250_port *up)
992 unsigned char scratch, status1, status2;
994 up->port.type = PORT_8250;
996 scratch = serial_in(up, UART_SCR);
997 serial_out(up, UART_SCR, 0xa5);
998 status1 = serial_in(up, UART_SCR);
999 serial_out(up, UART_SCR, 0x5a);
1000 status2 = serial_in(up, UART_SCR);
1001 serial_out(up, UART_SCR, scratch);
1003 if (status1 == 0xa5 && status2 == 0x5a)
1004 up->port.type = PORT_16450;
1007 static int broken_efr(struct uart_8250_port *up)
1010 * Exar ST16C2550 "A2" devices incorrectly detect as
1011 * having an EFR, and report an ID of 0x0201. See
1012 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1014 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1021 * We know that the chip has FIFOs. Does it have an EFR? The
1022 * EFR is located in the same register position as the IIR and
1023 * we know the top two bits of the IIR are currently set. The
1024 * EFR should contain zero. Try to read the EFR.
1026 static void autoconfig_16550a(struct uart_8250_port *up)
1028 unsigned char status1, status2;
1029 unsigned int iersave;
1031 up->port.type = PORT_16550A;
1032 up->capabilities |= UART_CAP_FIFO;
1034 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) &&
1035 !(up->port.flags & UPF_FULL_PROBE))
1039 * Check for presence of the EFR when DLAB is set.
1040 * Only ST16C650V1 UARTs pass this test.
1042 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1043 if (serial_in(up, UART_EFR) == 0) {
1044 serial_out(up, UART_EFR, 0xA8);
1045 if (serial_in(up, UART_EFR) != 0) {
1046 DEBUG_AUTOCONF("EFRv1 ");
1047 up->port.type = PORT_16650;
1048 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1050 serial_out(up, UART_LCR, 0);
1051 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1053 status1 = serial_in(up, UART_IIR) >> 5;
1054 serial_out(up, UART_FCR, 0);
1055 serial_out(up, UART_LCR, 0);
1058 up->port.type = PORT_16550A_FSL64;
1060 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1062 serial_out(up, UART_EFR, 0);
1067 * Maybe it requires 0xbf to be written to the LCR.
1068 * (other ST16C650V2 UARTs, TI16C752A, etc)
1070 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1071 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1072 DEBUG_AUTOCONF("EFRv2 ");
1073 autoconfig_has_efr(up);
1078 * Check for a National Semiconductor SuperIO chip.
1079 * Attempt to switch to bank 2, read the value of the LOOP bit
1080 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1081 * switch back to bank 2, read it from EXCR1 again and check
1082 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1084 serial_out(up, UART_LCR, 0);
1085 status1 = serial8250_in_MCR(up);
1086 serial_out(up, UART_LCR, 0xE0);
1087 status2 = serial_in(up, 0x02); /* EXCR1 */
1089 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1090 serial_out(up, UART_LCR, 0);
1091 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1092 serial_out(up, UART_LCR, 0xE0);
1093 status2 = serial_in(up, 0x02); /* EXCR1 */
1094 serial_out(up, UART_LCR, 0);
1095 serial8250_out_MCR(up, status1);
1097 if ((status2 ^ status1) & UART_MCR_LOOP) {
1098 unsigned short quot;
1100 serial_out(up, UART_LCR, 0xE0);
1102 quot = serial_dl_read(up);
1105 if (ns16550a_goto_highspeed(up))
1106 serial_dl_write(up, quot);
1108 serial_out(up, UART_LCR, 0);
1110 up->port.uartclk = 921600*16;
1111 up->port.type = PORT_NS16550A;
1112 up->capabilities |= UART_NATSEMI;
1118 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1119 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1120 * Try setting it with and without DLAB set. Cheap clones
1121 * set bit 5 without DLAB set.
1123 serial_out(up, UART_LCR, 0);
1124 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1125 status1 = serial_in(up, UART_IIR) >> 5;
1126 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1127 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1128 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1129 status2 = serial_in(up, UART_IIR) >> 5;
1130 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1131 serial_out(up, UART_LCR, 0);
1133 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1135 if (status1 == 6 && status2 == 7) {
1136 up->port.type = PORT_16750;
1137 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1142 * Try writing and reading the UART_IER_UUE bit (b6).
1143 * If it works, this is probably one of the Xscale platform's
1145 * We're going to explicitly set the UUE bit to 0 before
1146 * trying to write and read a 1 just to make sure it's not
1147 * already a 1 and maybe locked there before we even start.
1149 iersave = serial_in(up, UART_IER);
1150 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1151 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1153 * OK it's in a known zero state, try writing and reading
1154 * without disturbing the current state of the other bits.
1156 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1157 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1160 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1162 DEBUG_AUTOCONF("Xscale ");
1163 up->port.type = PORT_XSCALE;
1164 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1169 * If we got here we couldn't force the IER_UUE bit to 0.
1170 * Log it and continue.
1172 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1174 serial_out(up, UART_IER, iersave);
1177 * We distinguish between 16550A and U6 16550A by counting
1178 * how many bytes are in the FIFO.
1180 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1181 up->port.type = PORT_U6_16550A;
1182 up->capabilities |= UART_CAP_AFE;
1187 * This routine is called by rs_init() to initialize a specific serial
1188 * port. It determines what type of UART chip this serial port is
1189 * using: 8250, 16450, 16550, 16550A. The important question is
1190 * whether or not this UART is a 16550A or not, since this will
1191 * determine whether or not we can use its FIFO features or not.
1193 static void autoconfig(struct uart_8250_port *up)
1195 unsigned char status1, scratch, scratch2, scratch3;
1196 unsigned char save_lcr, save_mcr;
1197 struct uart_port *port = &up->port;
1198 unsigned long flags;
1199 unsigned int old_capabilities;
1201 if (!port->iobase && !port->mapbase && !port->membase)
1204 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1205 port->name, port->iobase, port->membase);
1208 * We really do need global IRQs disabled here - we're going to
1209 * be frobbing the chips IRQ enable register to see if it exists.
1211 spin_lock_irqsave(&port->lock, flags);
1213 up->capabilities = 0;
1216 if (!(port->flags & UPF_BUGGY_UART)) {
1218 * Do a simple existence test first; if we fail this,
1219 * there's no point trying anything else.
1221 * 0x80 is used as a nonsense port to prevent against
1222 * false positives due to ISA bus float. The
1223 * assumption is that 0x80 is a non-existent port;
1224 * which should be safe since include/asm/io.h also
1225 * makes this assumption.
1227 * Note: this is safe as long as MCR bit 4 is clear
1228 * and the device is in "PC" mode.
1230 scratch = serial_in(up, UART_IER);
1231 serial_out(up, UART_IER, 0);
1236 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1237 * 16C754B) allow only to modify them if an EFR bit is set.
1239 scratch2 = serial_in(up, UART_IER) & 0x0f;
1240 serial_out(up, UART_IER, 0x0F);
1244 scratch3 = serial_in(up, UART_IER) & 0x0f;
1245 serial_out(up, UART_IER, scratch);
1246 if (scratch2 != 0 || scratch3 != 0x0F) {
1248 * We failed; there's nothing here
1250 spin_unlock_irqrestore(&port->lock, flags);
1251 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1252 scratch2, scratch3);
1257 save_mcr = serial8250_in_MCR(up);
1258 save_lcr = serial_in(up, UART_LCR);
1261 * Check to see if a UART is really there. Certain broken
1262 * internal modems based on the Rockwell chipset fail this
1263 * test, because they apparently don't implement the loopback
1264 * test mode. So this test is skipped on the COM 1 through
1265 * COM 4 ports. This *should* be safe, since no board
1266 * manufacturer would be stupid enough to design a board
1267 * that conflicts with COM 1-4 --- we hope!
1269 if (!(port->flags & UPF_SKIP_TEST)) {
1270 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1271 status1 = serial_in(up, UART_MSR) & 0xF0;
1272 serial8250_out_MCR(up, save_mcr);
1273 if (status1 != 0x90) {
1274 spin_unlock_irqrestore(&port->lock, flags);
1275 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1282 * We're pretty sure there's a port here. Lets find out what
1283 * type of port it is. The IIR top two bits allows us to find
1284 * out if it's 8250 or 16450, 16550, 16550A or later. This
1285 * determines what we test for next.
1287 * We also initialise the EFR (if any) to zero for later. The
1288 * EFR occupies the same register location as the FCR and IIR.
1290 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1291 serial_out(up, UART_EFR, 0);
1292 serial_out(up, UART_LCR, 0);
1294 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1296 /* Assign this as it is to truncate any bits above 7. */
1297 scratch = serial_in(up, UART_IIR);
1299 switch (scratch >> 6) {
1301 autoconfig_8250(up);
1304 port->type = PORT_UNKNOWN;
1307 port->type = PORT_16550;
1310 autoconfig_16550a(up);
1314 #ifdef CONFIG_SERIAL_8250_RSA
1316 * Only probe for RSA ports if we got the region.
1318 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1320 port->type = PORT_RSA;
1323 serial_out(up, UART_LCR, save_lcr);
1325 port->fifosize = uart_config[up->port.type].fifo_size;
1326 old_capabilities = up->capabilities;
1327 up->capabilities = uart_config[port->type].flags;
1328 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1330 if (port->type == PORT_UNKNOWN)
1336 #ifdef CONFIG_SERIAL_8250_RSA
1337 if (port->type == PORT_RSA)
1338 serial_out(up, UART_RSA_FRR, 0);
1340 serial8250_out_MCR(up, save_mcr);
1341 serial8250_clear_fifos(up);
1342 serial_in(up, UART_RX);
1343 serial8250_clear_IER(up);
1346 spin_unlock_irqrestore(&port->lock, flags);
1349 * Check if the device is a Fintek F81216A
1351 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1352 fintek_8250_probe(up);
1354 if (up->capabilities != old_capabilities) {
1355 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1356 old_capabilities, up->capabilities);
1359 DEBUG_AUTOCONF("iir=%d ", scratch);
1360 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1363 static void autoconfig_irq(struct uart_8250_port *up)
1365 struct uart_port *port = &up->port;
1366 unsigned char save_mcr, save_ier;
1367 unsigned char save_ICP = 0;
1368 unsigned int ICP = 0;
1372 if (port->flags & UPF_FOURPORT) {
1373 ICP = (port->iobase & 0xfe0) | 0x1f;
1374 save_ICP = inb_p(ICP);
1379 if (uart_console(port))
1382 /* forget possible initially masked and pending IRQ */
1383 probe_irq_off(probe_irq_on());
1384 save_mcr = serial8250_in_MCR(up);
1385 save_ier = serial_in(up, UART_IER);
1386 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1388 irqs = probe_irq_on();
1389 serial8250_out_MCR(up, 0);
1391 if (port->flags & UPF_FOURPORT) {
1392 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1394 serial8250_out_MCR(up,
1395 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1397 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1398 serial_in(up, UART_LSR);
1399 serial_in(up, UART_RX);
1400 serial_in(up, UART_IIR);
1401 serial_in(up, UART_MSR);
1402 serial_out(up, UART_TX, 0xFF);
1404 irq = probe_irq_off(irqs);
1406 serial8250_out_MCR(up, save_mcr);
1407 serial_out(up, UART_IER, save_ier);
1409 if (port->flags & UPF_FOURPORT)
1410 outb_p(save_ICP, ICP);
1412 if (uart_console(port))
1415 port->irq = (irq > 0) ? irq : 0;
1418 static void serial8250_stop_rx(struct uart_port *port)
1420 struct uart_8250_port *up = up_to_u8250p(port);
1422 serial8250_rpm_get(up);
1424 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1425 up->port.read_status_mask &= ~UART_LSR_DR;
1426 serial_port_out(port, UART_IER, up->ier);
1428 serial8250_rpm_put(up);
1432 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1433 * @p: uart 8250 port
1435 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1437 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1439 unsigned char mcr = serial8250_in_MCR(p);
1441 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1442 mcr |= UART_MCR_RTS;
1444 mcr &= ~UART_MCR_RTS;
1445 serial8250_out_MCR(p, mcr);
1448 * Empty the RX FIFO, we are not interested in anything
1449 * received during the half-duplex transmission.
1450 * Enable previously disabled RX interrupts.
1452 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1453 serial8250_clear_and_reinit_fifos(p);
1455 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1456 serial_port_out(&p->port, UART_IER, p->ier);
1459 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1461 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1463 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1465 struct uart_8250_port *p = em485->port;
1466 unsigned long flags;
1468 serial8250_rpm_get(p);
1469 spin_lock_irqsave(&p->port.lock, flags);
1470 if (em485->active_timer == &em485->stop_tx_timer) {
1471 p->rs485_stop_tx(p);
1472 em485->active_timer = NULL;
1473 em485->tx_stopped = true;
1475 spin_unlock_irqrestore(&p->port.lock, flags);
1476 serial8250_rpm_put(p);
1478 return HRTIMER_NORESTART;
1481 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1483 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1486 static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
1488 struct uart_8250_em485 *em485 = p->em485;
1490 stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
1493 * rs485_stop_tx() is going to set RTS according to config
1494 * AND flush RX FIFO if required.
1496 if (stop_delay > 0) {
1497 em485->active_timer = &em485->stop_tx_timer;
1498 hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL);
1500 p->rs485_stop_tx(p);
1501 em485->active_timer = NULL;
1502 em485->tx_stopped = true;
1506 static inline void __stop_tx(struct uart_8250_port *p)
1508 struct uart_8250_em485 *em485 = p->em485;
1511 u16 lsr = serial_lsr_in(p);
1514 p->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1516 if (!(lsr & UART_LSR_THRE))
1519 * To provide required timing and allow FIFO transfer,
1520 * __stop_tx_rs485() must be called only when both FIFO and
1521 * shift register are empty. The device driver should either
1522 * enable interrupt on TEMT or set UART_CAP_NOTEMT that will
1523 * enlarge stop_tx_timer by the tx time of one frame to cover
1524 * for emptying of the shift register.
1526 if (!(lsr & UART_LSR_TEMT)) {
1527 if (!(p->capabilities & UART_CAP_NOTEMT))
1530 * RTS might get deasserted too early with the normal
1531 * frame timing formula. It seems to suggest THRE might
1532 * get asserted already during tx of the stop bit
1533 * rather than after it is fully sent.
1534 * Roughly estimate 1 extra bit here with / 7.
1536 stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
1539 __stop_tx_rs485(p, stop_delay);
1542 if (serial8250_clear_THRI(p))
1543 serial8250_rpm_put_tx(p);
1546 static void serial8250_stop_tx(struct uart_port *port)
1548 struct uart_8250_port *up = up_to_u8250p(port);
1550 serial8250_rpm_get(up);
1554 * We really want to stop the transmitter from sending.
1556 if (port->type == PORT_16C950) {
1557 up->acr |= UART_ACR_TXDIS;
1558 serial_icr_write(up, UART_ACR, up->acr);
1560 serial8250_rpm_put(up);
1563 static inline void __start_tx(struct uart_port *port)
1565 struct uart_8250_port *up = up_to_u8250p(port);
1567 if (up->dma && !up->dma->tx_dma(up))
1570 if (serial8250_set_THRI(up)) {
1571 if (up->bugs & UART_BUG_TXEN) {
1572 u16 lsr = serial_lsr_in(up);
1574 if (lsr & UART_LSR_THRE)
1575 serial8250_tx_chars(up);
1580 * Re-enable the transmitter if we disabled it.
1582 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1583 up->acr &= ~UART_ACR_TXDIS;
1584 serial_icr_write(up, UART_ACR, up->acr);
1589 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1590 * @up: uart 8250 port
1592 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1593 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1594 * (Some chips use inverse semantics.) Further assumes that reception is
1595 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1596 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1598 void serial8250_em485_start_tx(struct uart_8250_port *up)
1600 unsigned char mcr = serial8250_in_MCR(up);
1602 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1603 serial8250_stop_rx(&up->port);
1605 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1606 mcr |= UART_MCR_RTS;
1608 mcr &= ~UART_MCR_RTS;
1609 serial8250_out_MCR(up, mcr);
1611 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1613 /* Returns false, if start_tx_timer was setup to defer TX start */
1614 static bool start_tx_rs485(struct uart_port *port)
1616 struct uart_8250_port *up = up_to_u8250p(port);
1617 struct uart_8250_em485 *em485 = up->em485;
1620 * While serial8250_em485_handle_stop_tx() is a noop if
1621 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1622 * the timer is still armed and triggers only after the current bunch of
1623 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1624 * So cancel the timer. There is still a theoretical race condition if
1625 * the timer is already running and only comes around to check for
1626 * em485->active_timer when &em485->stop_tx_timer is armed again.
1628 if (em485->active_timer == &em485->stop_tx_timer)
1629 hrtimer_try_to_cancel(&em485->stop_tx_timer);
1631 em485->active_timer = NULL;
1633 if (em485->tx_stopped) {
1634 em485->tx_stopped = false;
1636 up->rs485_start_tx(up);
1638 if (up->port.rs485.delay_rts_before_send > 0) {
1639 em485->active_timer = &em485->start_tx_timer;
1640 start_hrtimer_ms(&em485->start_tx_timer,
1641 up->port.rs485.delay_rts_before_send);
1649 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1651 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1653 struct uart_8250_port *p = em485->port;
1654 unsigned long flags;
1656 spin_lock_irqsave(&p->port.lock, flags);
1657 if (em485->active_timer == &em485->start_tx_timer) {
1658 __start_tx(&p->port);
1659 em485->active_timer = NULL;
1661 spin_unlock_irqrestore(&p->port.lock, flags);
1663 return HRTIMER_NORESTART;
1666 static void serial8250_start_tx(struct uart_port *port)
1668 struct uart_8250_port *up = up_to_u8250p(port);
1669 struct uart_8250_em485 *em485 = up->em485;
1671 if (!port->x_char && uart_circ_empty(&port->state->xmit))
1674 serial8250_rpm_get_tx(up);
1677 if ((em485->active_timer == &em485->start_tx_timer) ||
1678 !start_tx_rs485(port))
1684 static void serial8250_throttle(struct uart_port *port)
1686 port->throttle(port);
1689 static void serial8250_unthrottle(struct uart_port *port)
1691 port->unthrottle(port);
1694 static void serial8250_disable_ms(struct uart_port *port)
1696 struct uart_8250_port *up = up_to_u8250p(port);
1698 /* no MSR capabilities */
1699 if (up->bugs & UART_BUG_NOMSR)
1702 mctrl_gpio_disable_ms(up->gpios);
1704 up->ier &= ~UART_IER_MSI;
1705 serial_port_out(port, UART_IER, up->ier);
1708 static void serial8250_enable_ms(struct uart_port *port)
1710 struct uart_8250_port *up = up_to_u8250p(port);
1712 /* no MSR capabilities */
1713 if (up->bugs & UART_BUG_NOMSR)
1716 mctrl_gpio_enable_ms(up->gpios);
1718 up->ier |= UART_IER_MSI;
1720 serial8250_rpm_get(up);
1721 serial_port_out(port, UART_IER, up->ier);
1722 serial8250_rpm_put(up);
1725 void serial8250_read_char(struct uart_8250_port *up, u16 lsr)
1727 struct uart_port *port = &up->port;
1729 char flag = TTY_NORMAL;
1731 if (likely(lsr & UART_LSR_DR))
1732 ch = serial_in(up, UART_RX);
1735 * Intel 82571 has a Serial Over Lan device that will
1736 * set UART_LSR_BI without setting UART_LSR_DR when
1737 * it receives a break. To avoid reading from the
1738 * receive buffer without UART_LSR_DR bit set, we
1739 * just force the read character to be 0
1745 lsr |= up->lsr_saved_flags;
1746 up->lsr_saved_flags = 0;
1748 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1749 if (lsr & UART_LSR_BI) {
1750 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1753 * We do the SysRQ and SAK checking
1754 * here because otherwise the break
1755 * may get masked by ignore_status_mask
1756 * or read_status_mask.
1758 if (uart_handle_break(port))
1760 } else if (lsr & UART_LSR_PE)
1761 port->icount.parity++;
1762 else if (lsr & UART_LSR_FE)
1763 port->icount.frame++;
1764 if (lsr & UART_LSR_OE)
1765 port->icount.overrun++;
1768 * Mask off conditions which should be ignored.
1770 lsr &= port->read_status_mask;
1772 if (lsr & UART_LSR_BI) {
1773 dev_dbg(port->dev, "handling break\n");
1775 } else if (lsr & UART_LSR_PE)
1777 else if (lsr & UART_LSR_FE)
1780 if (uart_prepare_sysrq_char(port, ch))
1783 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1785 EXPORT_SYMBOL_GPL(serial8250_read_char);
1788 * serial8250_rx_chars - Read characters. The first LSR value must be passed in.
1790 * Returns LSR bits. The caller should rely only on non-Rx related LSR bits
1791 * (such as THRE) because the LSR value might come from an already consumed
1794 u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr)
1796 struct uart_port *port = &up->port;
1797 int max_count = 256;
1800 serial8250_read_char(up, lsr);
1801 if (--max_count == 0)
1803 lsr = serial_in(up, UART_LSR);
1804 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1806 tty_flip_buffer_push(&port->state->port);
1809 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1811 void serial8250_tx_chars(struct uart_8250_port *up)
1813 struct uart_port *port = &up->port;
1814 struct circ_buf *xmit = &port->state->xmit;
1818 uart_xchar_out(port, UART_TX);
1821 if (uart_tx_stopped(port)) {
1822 serial8250_stop_tx(port);
1825 if (uart_circ_empty(xmit)) {
1830 count = up->tx_loadsz;
1832 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1833 if (up->bugs & UART_BUG_TXRACE) {
1835 * The Aspeed BMC virtual UARTs have a bug where data
1836 * may get stuck in the BMC's Tx FIFO from bursts of
1837 * writes on the APB interface.
1839 * Delay back-to-back writes by a read cycle to avoid
1840 * stalling the VUART. Read a register that won't have
1841 * side-effects and discard the result.
1843 serial_in(up, UART_SCR);
1845 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1847 if (uart_circ_empty(xmit))
1849 if ((up->capabilities & UART_CAP_HFIFO) &&
1850 !uart_lsr_tx_empty(serial_in(up, UART_LSR)))
1852 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1853 if ((up->capabilities & UART_CAP_MINI) &&
1854 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1856 } while (--count > 0);
1858 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1859 uart_write_wakeup(port);
1862 * With RPM enabled, we have to wait until the FIFO is empty before the
1863 * HW can go idle. So we get here once again with empty FIFO and disable
1864 * the interrupt and RPM in __stop_tx()
1866 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1869 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1871 /* Caller holds uart port lock */
1872 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1874 struct uart_port *port = &up->port;
1875 unsigned int status = serial_in(up, UART_MSR);
1877 status |= up->msr_saved_flags;
1878 up->msr_saved_flags = 0;
1879 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1880 port->state != NULL) {
1881 if (status & UART_MSR_TERI)
1883 if (status & UART_MSR_DDSR)
1885 if (status & UART_MSR_DDCD)
1886 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1887 if (status & UART_MSR_DCTS)
1888 uart_handle_cts_change(port, status & UART_MSR_CTS);
1890 wake_up_interruptible(&port->state->port.delta_msr_wait);
1895 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1897 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1899 switch (iir & 0x3f) {
1900 case UART_IIR_RX_TIMEOUT:
1901 serial8250_rx_dma_flush(up);
1906 return up->dma->rx_dma(up);
1910 * This handles the interrupt from one port.
1912 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1914 struct uart_8250_port *up = up_to_u8250p(port);
1915 bool skip_rx = false;
1916 unsigned long flags;
1919 if (iir & UART_IIR_NO_INT)
1922 spin_lock_irqsave(&port->lock, flags);
1924 status = serial_lsr_in(up);
1927 * If port is stopped and there are no error conditions in the
1928 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1929 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1930 * control when FIFO occupancy reaches preset threshold, thus
1931 * halting RX. This only works when auto HW flow control is
1934 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1935 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1936 !(port->read_status_mask & UART_LSR_DR))
1939 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1940 if (!up->dma || handle_rx_dma(up, iir))
1941 status = serial8250_rx_chars(up, status);
1943 serial8250_modem_status(up);
1944 if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
1945 if (!up->dma || up->dma->tx_err)
1946 serial8250_tx_chars(up);
1947 else if (!up->dma->tx_running)
1951 uart_unlock_and_check_sysrq_irqrestore(port, flags);
1955 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1957 static int serial8250_default_handle_irq(struct uart_port *port)
1959 struct uart_8250_port *up = up_to_u8250p(port);
1963 serial8250_rpm_get(up);
1965 iir = serial_port_in(port, UART_IIR);
1966 ret = serial8250_handle_irq(port, iir);
1968 serial8250_rpm_put(up);
1973 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1974 * have a programmable TX threshold that triggers the THRE interrupt in
1975 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1976 * has space available. Load it up with tx_loadsz bytes.
1978 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1980 unsigned long flags;
1981 unsigned int iir = serial_port_in(port, UART_IIR);
1983 /* TX Threshold IRQ triggered so load up FIFO */
1984 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1985 struct uart_8250_port *up = up_to_u8250p(port);
1987 spin_lock_irqsave(&port->lock, flags);
1988 serial8250_tx_chars(up);
1989 spin_unlock_irqrestore(&port->lock, flags);
1992 iir = serial_port_in(port, UART_IIR);
1993 return serial8250_handle_irq(port, iir);
1996 static unsigned int serial8250_tx_empty(struct uart_port *port)
1998 struct uart_8250_port *up = up_to_u8250p(port);
1999 unsigned long flags;
2002 serial8250_rpm_get(up);
2004 spin_lock_irqsave(&port->lock, flags);
2005 lsr = serial_lsr_in(up);
2006 spin_unlock_irqrestore(&port->lock, flags);
2008 serial8250_rpm_put(up);
2010 return uart_lsr_tx_empty(lsr) ? TIOCSER_TEMT : 0;
2013 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
2015 struct uart_8250_port *up = up_to_u8250p(port);
2016 unsigned int status;
2019 serial8250_rpm_get(up);
2020 status = serial8250_modem_status(up);
2021 serial8250_rpm_put(up);
2023 val = serial8250_MSR_to_TIOCM(status);
2025 return mctrl_gpio_get(up->gpios, &val);
2029 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2031 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2033 if (port->get_mctrl)
2034 return port->get_mctrl(port);
2035 return serial8250_do_get_mctrl(port);
2038 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2040 struct uart_8250_port *up = up_to_u8250p(port);
2043 mcr = serial8250_TIOCM_to_MCR(mctrl);
2047 serial8250_out_MCR(up, mcr);
2049 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2051 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2053 if (port->rs485.flags & SER_RS485_ENABLED)
2056 if (port->set_mctrl)
2057 port->set_mctrl(port, mctrl);
2059 serial8250_do_set_mctrl(port, mctrl);
2062 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2064 struct uart_8250_port *up = up_to_u8250p(port);
2065 unsigned long flags;
2067 serial8250_rpm_get(up);
2068 spin_lock_irqsave(&port->lock, flags);
2069 if (break_state == -1)
2070 up->lcr |= UART_LCR_SBC;
2072 up->lcr &= ~UART_LCR_SBC;
2073 serial_port_out(port, UART_LCR, up->lcr);
2074 spin_unlock_irqrestore(&port->lock, flags);
2075 serial8250_rpm_put(up);
2078 static void wait_for_lsr(struct uart_8250_port *up, int bits)
2080 unsigned int status, tmout = 10000;
2082 /* Wait up to 10ms for the character(s) to be sent. */
2084 status = serial_lsr_in(up);
2086 if ((status & bits) == bits)
2091 touch_nmi_watchdog();
2096 * Wait for transmitter & holding register to empty
2098 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2102 wait_for_lsr(up, bits);
2104 /* Wait up to 1s for flow control if necessary */
2105 if (up->port.flags & UPF_CONS_FLOW) {
2106 for (tmout = 1000000; tmout; tmout--) {
2107 unsigned int msr = serial_in(up, UART_MSR);
2108 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2109 if (msr & UART_MSR_CTS)
2112 touch_nmi_watchdog();
2117 #ifdef CONFIG_CONSOLE_POLL
2119 * Console polling routines for writing and reading from the uart while
2120 * in an interrupt or debug context.
2123 static int serial8250_get_poll_char(struct uart_port *port)
2125 struct uart_8250_port *up = up_to_u8250p(port);
2129 serial8250_rpm_get(up);
2131 lsr = serial_port_in(port, UART_LSR);
2133 if (!(lsr & UART_LSR_DR)) {
2134 status = NO_POLL_CHAR;
2138 status = serial_port_in(port, UART_RX);
2140 serial8250_rpm_put(up);
2145 static void serial8250_put_poll_char(struct uart_port *port,
2149 struct uart_8250_port *up = up_to_u8250p(port);
2151 serial8250_rpm_get(up);
2153 * First save the IER then disable the interrupts
2155 ier = serial_port_in(port, UART_IER);
2156 serial8250_clear_IER(up);
2158 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2160 * Send the character out.
2162 serial_port_out(port, UART_TX, c);
2165 * Finally, wait for transmitter to become empty
2166 * and restore the IER
2168 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2169 serial_port_out(port, UART_IER, ier);
2170 serial8250_rpm_put(up);
2173 #endif /* CONFIG_CONSOLE_POLL */
2175 int serial8250_do_startup(struct uart_port *port)
2177 struct uart_8250_port *up = up_to_u8250p(port);
2178 unsigned long flags;
2183 if (!port->fifosize)
2184 port->fifosize = uart_config[port->type].fifo_size;
2186 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2187 if (!up->capabilities)
2188 up->capabilities = uart_config[port->type].flags;
2191 if (port->iotype != up->cur_iotype)
2192 set_io_from_upio(port);
2194 serial8250_rpm_get(up);
2195 if (port->type == PORT_16C950) {
2196 /* Wake up and initialize UART */
2198 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2199 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2200 serial_port_out(port, UART_IER, 0);
2201 serial_port_out(port, UART_LCR, 0);
2202 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2203 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2204 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2205 serial_port_out(port, UART_LCR, 0);
2208 if (port->type == PORT_DA830) {
2209 /* Reset the port */
2210 serial_port_out(port, UART_IER, 0);
2211 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2214 /* Enable Tx, Rx and free run mode */
2215 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2216 UART_DA830_PWREMU_MGMT_UTRST |
2217 UART_DA830_PWREMU_MGMT_URRST |
2218 UART_DA830_PWREMU_MGMT_FREE);
2221 if (port->type == PORT_NPCM) {
2223 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2224 * register). Enable it, and set TIOC (timeout interrupt
2225 * comparator) to be 0x20 for correct operation.
2227 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2230 #ifdef CONFIG_SERIAL_8250_RSA
2232 * If this is an RSA port, see if we can kick it up to the
2233 * higher speed clock.
2239 * Clear the FIFO buffers and disable them.
2240 * (they will be reenabled in set_termios())
2242 serial8250_clear_fifos(up);
2245 * Clear the interrupt registers.
2247 serial_port_in(port, UART_LSR);
2248 serial_port_in(port, UART_RX);
2249 serial_port_in(port, UART_IIR);
2250 serial_port_in(port, UART_MSR);
2253 * At this point, there's no way the LSR could still be 0xff;
2254 * if it is, then bail out, because there's likely no UART
2257 if (!(port->flags & UPF_BUGGY_UART) &&
2258 (serial_port_in(port, UART_LSR) == 0xff)) {
2259 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2265 * For a XR16C850, we need to set the trigger levels
2267 if (port->type == PORT_16850) {
2270 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2272 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2273 serial_port_out(port, UART_FCTR,
2274 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2275 serial_port_out(port, UART_TRG, UART_TRG_96);
2276 serial_port_out(port, UART_FCTR,
2277 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2278 serial_port_out(port, UART_TRG, UART_TRG_96);
2280 serial_port_out(port, UART_LCR, 0);
2284 * For the Altera 16550 variants, set TX threshold trigger level.
2286 if (((port->type == PORT_ALTR_16550_F32) ||
2287 (port->type == PORT_ALTR_16550_F64) ||
2288 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2289 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2290 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2291 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2293 serial_port_out(port, UART_ALTR_AFR,
2294 UART_ALTR_EN_TXFIFO_LW);
2295 serial_port_out(port, UART_ALTR_TX_LOW,
2296 port->fifosize - up->tx_loadsz);
2297 port->handle_irq = serial8250_tx_threshold_handle_irq;
2301 /* Check if we need to have shared IRQs */
2302 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2303 up->port.irqflags |= IRQF_SHARED;
2305 retval = up->ops->setup_irq(up);
2309 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2312 if (port->irqflags & IRQF_SHARED)
2313 disable_irq_nosync(port->irq);
2316 * Test for UARTs that do not reassert THRE when the
2317 * transmitter is idle and the interrupt has already
2318 * been cleared. Real 16550s should always reassert
2319 * this interrupt whenever the transmitter is idle and
2320 * the interrupt is enabled. Delays are necessary to
2321 * allow register changes to become visible.
2323 spin_lock_irqsave(&port->lock, flags);
2325 wait_for_xmitr(up, UART_LSR_THRE);
2326 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2327 udelay(1); /* allow THRE to set */
2328 iir1 = serial_port_in(port, UART_IIR);
2329 serial_port_out(port, UART_IER, 0);
2330 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2331 udelay(1); /* allow a working UART time to re-assert THRE */
2332 iir = serial_port_in(port, UART_IIR);
2333 serial_port_out(port, UART_IER, 0);
2335 spin_unlock_irqrestore(&port->lock, flags);
2337 if (port->irqflags & IRQF_SHARED)
2338 enable_irq(port->irq);
2341 * If the interrupt is not reasserted, or we otherwise
2342 * don't trust the iir, setup a timer to kick the UART
2343 * on a regular basis.
2345 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2346 up->port.flags & UPF_BUG_THRE) {
2347 up->bugs |= UART_BUG_THRE;
2351 up->ops->setup_timer(up);
2354 * Now, initialize the UART
2356 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2358 spin_lock_irqsave(&port->lock, flags);
2359 if (up->port.flags & UPF_FOURPORT) {
2361 up->port.mctrl |= TIOCM_OUT1;
2364 * Most PC uarts need OUT2 raised to enable interrupts.
2367 up->port.mctrl |= TIOCM_OUT2;
2369 serial8250_set_mctrl(port, port->mctrl);
2372 * Serial over Lan (SoL) hack:
2373 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2374 * used for Serial Over Lan. Those chips take a longer time than a
2375 * normal serial device to signalize that a transmission data was
2376 * queued. Due to that, the above test generally fails. One solution
2377 * would be to delay the reading of iir. However, this is not
2378 * reliable, since the timeout is variable. So, let's just don't
2379 * test if we receive TX irq. This way, we'll never enable
2382 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2383 goto dont_test_tx_en;
2386 * Do a quick test to see if we receive an interrupt when we enable
2389 serial_port_out(port, UART_IER, UART_IER_THRI);
2390 lsr = serial_port_in(port, UART_LSR);
2391 iir = serial_port_in(port, UART_IIR);
2392 serial_port_out(port, UART_IER, 0);
2394 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2395 if (!(up->bugs & UART_BUG_TXEN)) {
2396 up->bugs |= UART_BUG_TXEN;
2397 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2400 up->bugs &= ~UART_BUG_TXEN;
2404 spin_unlock_irqrestore(&port->lock, flags);
2407 * Clear the interrupt registers again for luck, and clear the
2408 * saved flags to avoid getting false values from polling
2409 * routines or the previous session.
2411 serial_port_in(port, UART_LSR);
2412 serial_port_in(port, UART_RX);
2413 serial_port_in(port, UART_IIR);
2414 serial_port_in(port, UART_MSR);
2415 up->lsr_saved_flags = 0;
2416 up->msr_saved_flags = 0;
2419 * Request DMA channels for both RX and TX.
2422 const char *msg = NULL;
2424 if (uart_console(port))
2425 msg = "forbid DMA for kernel console";
2426 else if (serial8250_request_dma(up))
2427 msg = "failed to request DMA";
2429 dev_warn_ratelimited(port->dev, "%s\n", msg);
2435 * Set the IER shadow for rx interrupts but defer actual interrupt
2436 * enable until after the FIFOs are enabled; otherwise, an already-
2437 * active sender can swamp the interrupt handler with "too much work".
2439 up->ier = UART_IER_RLSI | UART_IER_RDI;
2441 if (port->flags & UPF_FOURPORT) {
2444 * Enable interrupts on the AST Fourport board
2446 icp = (port->iobase & 0xfe0) | 0x01f;
2452 serial8250_rpm_put(up);
2455 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2457 static int serial8250_startup(struct uart_port *port)
2460 return port->startup(port);
2461 return serial8250_do_startup(port);
2464 void serial8250_do_shutdown(struct uart_port *port)
2466 struct uart_8250_port *up = up_to_u8250p(port);
2467 unsigned long flags;
2469 serial8250_rpm_get(up);
2471 * Disable interrupts from this port
2473 spin_lock_irqsave(&port->lock, flags);
2475 serial_port_out(port, UART_IER, 0);
2476 spin_unlock_irqrestore(&port->lock, flags);
2478 synchronize_irq(port->irq);
2481 serial8250_release_dma(up);
2483 spin_lock_irqsave(&port->lock, flags);
2484 if (port->flags & UPF_FOURPORT) {
2485 /* reset interrupts on the AST Fourport board */
2486 inb((port->iobase & 0xfe0) | 0x1f);
2487 port->mctrl |= TIOCM_OUT1;
2489 port->mctrl &= ~TIOCM_OUT2;
2491 serial8250_set_mctrl(port, port->mctrl);
2492 spin_unlock_irqrestore(&port->lock, flags);
2495 * Disable break condition and FIFOs
2497 serial_port_out(port, UART_LCR,
2498 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2499 serial8250_clear_fifos(up);
2501 #ifdef CONFIG_SERIAL_8250_RSA
2503 * Reset the RSA board back to 115kbps compat mode.
2509 * Read data port to reset things, and then unlink from
2512 serial_port_in(port, UART_RX);
2513 serial8250_rpm_put(up);
2515 up->ops->release_irq(up);
2517 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2519 static void serial8250_shutdown(struct uart_port *port)
2522 port->shutdown(port);
2524 serial8250_do_shutdown(port);
2527 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2528 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2531 struct uart_port *port = &up->port;
2533 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2536 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2540 upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2541 struct uart_8250_port *up = up_to_u8250p(port);
2545 * Handle magic divisors for baud rates above baud_base on SMSC
2546 * Super I/O chips. We clamp custom rates from clk/6 and clk/12
2547 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
2548 * magic divisors actually reprogram the baud rate generator's
2549 * reference clock derived from chips's 14.318MHz clock input.
2551 * Documentation claims that with these magic divisors the base
2552 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2553 * for the extra baud rates of 460800bps and 230400bps rather
2554 * than the usual base frequency of 1.8462MHz. However empirical
2555 * evidence contradicts that.
2557 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2558 * effectively used as a clock prescaler selection bit for the
2559 * base frequency of 7.3728MHz, always used. If set to 0, then
2560 * the base frequency is divided by 4 for use by the Baud Rate
2561 * Generator, for the usual arrangement where the value of 1 of
2562 * the divisor produces the baud rate of 115200bps. Conversely,
2563 * if set to 1 and high-speed operation has been enabled with the
2564 * Serial Port Mode Register in the Device Configuration Space,
2565 * then the base frequency is supplied directly to the Baud Rate
2566 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2567 * 0x8004, etc. the respective baud rates produced are 460800bps,
2568 * 230400bps, 153600bps, 115200bps, etc.
2570 * In all cases only low 15 bits of the divisor are used to divide
2571 * the baud base and therefore 32767 is the maximum divisor value
2572 * possible, even though documentation says that the programmable
2573 * Baud Rate Generator is capable of dividing the internal PLL
2574 * clock by any divisor from 1 to 65535.
2576 if (magic_multiplier && baud >= port->uartclk / 6)
2578 else if (magic_multiplier && baud >= port->uartclk / 12)
2580 else if (up->port.type == PORT_NPCM)
2581 quot = npcm_get_divisor(up, baud);
2583 quot = uart_get_divisor(port, baud);
2586 * Oxford Semi 952 rev B workaround
2588 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2594 static unsigned int serial8250_get_divisor(struct uart_port *port,
2598 if (port->get_divisor)
2599 return port->get_divisor(port, baud, frac);
2601 return serial8250_do_get_divisor(port, baud, frac);
2604 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2609 cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2611 if (c_cflag & CSTOPB)
2612 cval |= UART_LCR_STOP;
2613 if (c_cflag & PARENB) {
2614 cval |= UART_LCR_PARITY;
2615 if (up->bugs & UART_BUG_PARITY)
2616 up->fifo_bug = true;
2618 if (!(c_cflag & PARODD))
2619 cval |= UART_LCR_EPAR;
2620 if (c_cflag & CMSPAR)
2621 cval |= UART_LCR_SPAR;
2626 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2627 unsigned int quot, unsigned int quot_frac)
2629 struct uart_8250_port *up = up_to_u8250p(port);
2631 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2632 if (is_omap1510_8250(up)) {
2633 if (baud == 115200) {
2635 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2637 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2641 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2642 * otherwise just set DLAB
2644 if (up->capabilities & UART_NATSEMI)
2645 serial_port_out(port, UART_LCR, 0xe0);
2647 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2649 serial_dl_write(up, quot);
2651 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2653 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2654 unsigned int quot, unsigned int quot_frac)
2656 if (port->set_divisor)
2657 port->set_divisor(port, baud, quot, quot_frac);
2659 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2662 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2663 struct ktermios *termios,
2664 const struct ktermios *old)
2666 unsigned int tolerance = port->uartclk / 100;
2671 * Handle magic divisors for baud rates above baud_base on SMSC
2672 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2673 * disable divisor values beyond 32767, which are unavailable.
2675 if (port->flags & UPF_MAGIC_MULTIPLIER) {
2676 min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2677 max = (port->uartclk + tolerance) / 4;
2679 min = port->uartclk / 16 / UART_DIV_MAX;
2680 max = (port->uartclk + tolerance) / 16;
2684 * Ask the core to calculate the divisor for us.
2685 * Allow 1% tolerance at the upper limit so uart clks marginally
2686 * slower than nominal still match standard baud rates without
2687 * causing transmission errors.
2689 return uart_get_baud_rate(port, termios, old, min, max);
2693 * Note in order to avoid the tty port mutex deadlock don't use the next method
2694 * within the uart port callbacks. Primarily it's supposed to be utilized to
2695 * handle a sudden reference clock rate change.
2697 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2699 struct uart_8250_port *up = up_to_u8250p(port);
2700 struct tty_port *tport = &port->state->port;
2701 unsigned int baud, quot, frac = 0;
2702 struct ktermios *termios;
2703 struct tty_struct *tty;
2704 unsigned long flags;
2706 tty = tty_port_tty_get(tport);
2708 mutex_lock(&tport->mutex);
2709 port->uartclk = uartclk;
2710 mutex_unlock(&tport->mutex);
2714 down_write(&tty->termios_rwsem);
2715 mutex_lock(&tport->mutex);
2717 if (port->uartclk == uartclk)
2720 port->uartclk = uartclk;
2722 if (!tty_port_initialized(tport))
2725 termios = &tty->termios;
2727 baud = serial8250_get_baud_rate(port, termios, NULL);
2728 quot = serial8250_get_divisor(port, baud, &frac);
2730 serial8250_rpm_get(up);
2731 spin_lock_irqsave(&port->lock, flags);
2733 uart_update_timeout(port, termios->c_cflag, baud);
2735 serial8250_set_divisor(port, baud, quot, frac);
2736 serial_port_out(port, UART_LCR, up->lcr);
2738 spin_unlock_irqrestore(&port->lock, flags);
2739 serial8250_rpm_put(up);
2742 mutex_unlock(&tport->mutex);
2743 up_write(&tty->termios_rwsem);
2746 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2749 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2750 const struct ktermios *old)
2752 struct uart_8250_port *up = up_to_u8250p(port);
2754 unsigned long flags;
2755 unsigned int baud, quot, frac = 0;
2757 if (up->capabilities & UART_CAP_MINI) {
2758 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2759 if ((termios->c_cflag & CSIZE) == CS5 ||
2760 (termios->c_cflag & CSIZE) == CS6)
2761 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2763 cval = serial8250_compute_lcr(up, termios->c_cflag);
2765 baud = serial8250_get_baud_rate(port, termios, old);
2766 quot = serial8250_get_divisor(port, baud, &frac);
2769 * Ok, we're now changing the port state. Do it with
2770 * interrupts disabled.
2772 serial8250_rpm_get(up);
2773 spin_lock_irqsave(&port->lock, flags);
2775 up->lcr = cval; /* Save computed LCR */
2777 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2778 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2779 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2780 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2781 up->fcr |= UART_FCR_TRIGGER_1;
2786 * MCR-based auto flow control. When AFE is enabled, RTS will be
2787 * deasserted when the receive FIFO contains more characters than
2788 * the trigger, or the MCR RTS bit is cleared.
2790 if (up->capabilities & UART_CAP_AFE) {
2791 up->mcr &= ~UART_MCR_AFE;
2792 if (termios->c_cflag & CRTSCTS)
2793 up->mcr |= UART_MCR_AFE;
2797 * Update the per-port timeout.
2799 uart_update_timeout(port, termios->c_cflag, baud);
2801 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2802 if (termios->c_iflag & INPCK)
2803 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2804 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2805 port->read_status_mask |= UART_LSR_BI;
2808 * Characters to ignore
2810 port->ignore_status_mask = 0;
2811 if (termios->c_iflag & IGNPAR)
2812 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2813 if (termios->c_iflag & IGNBRK) {
2814 port->ignore_status_mask |= UART_LSR_BI;
2816 * If we're ignoring parity and break indicators,
2817 * ignore overruns too (for real raw support).
2819 if (termios->c_iflag & IGNPAR)
2820 port->ignore_status_mask |= UART_LSR_OE;
2824 * ignore all characters if CREAD is not set
2826 if ((termios->c_cflag & CREAD) == 0)
2827 port->ignore_status_mask |= UART_LSR_DR;
2830 * CTS flow control flag and modem status interrupts
2832 up->ier &= ~UART_IER_MSI;
2833 if (!(up->bugs & UART_BUG_NOMSR) &&
2834 UART_ENABLE_MS(&up->port, termios->c_cflag))
2835 up->ier |= UART_IER_MSI;
2836 if (up->capabilities & UART_CAP_UUE)
2837 up->ier |= UART_IER_UUE;
2838 if (up->capabilities & UART_CAP_RTOIE)
2839 up->ier |= UART_IER_RTOIE;
2841 serial_port_out(port, UART_IER, up->ier);
2843 if (up->capabilities & UART_CAP_EFR) {
2844 unsigned char efr = 0;
2846 * TI16C752/Startech hardware flow control. FIXME:
2847 * - TI16C752 requires control thresholds to be set.
2848 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2850 if (termios->c_cflag & CRTSCTS)
2851 efr |= UART_EFR_CTS;
2853 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2854 if (port->flags & UPF_EXAR_EFR)
2855 serial_port_out(port, UART_XR_EFR, efr);
2857 serial_port_out(port, UART_EFR, efr);
2860 serial8250_set_divisor(port, baud, quot, frac);
2863 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2864 * is written without DLAB set, this mode will be disabled.
2866 if (port->type == PORT_16750)
2867 serial_port_out(port, UART_FCR, up->fcr);
2869 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2870 if (port->type != PORT_16750) {
2871 /* emulated UARTs (Lucent Venus 167x) need two steps */
2872 if (up->fcr & UART_FCR_ENABLE_FIFO)
2873 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2874 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2876 serial8250_set_mctrl(port, port->mctrl);
2877 spin_unlock_irqrestore(&port->lock, flags);
2878 serial8250_rpm_put(up);
2880 /* Don't rewrite B0 */
2881 if (tty_termios_baud_rate(termios))
2882 tty_termios_encode_baud_rate(termios, baud, baud);
2884 EXPORT_SYMBOL(serial8250_do_set_termios);
2887 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2888 const struct ktermios *old)
2890 if (port->set_termios)
2891 port->set_termios(port, termios, old);
2893 serial8250_do_set_termios(port, termios, old);
2896 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2898 if (termios->c_line == N_PPS) {
2899 port->flags |= UPF_HARDPPS_CD;
2900 spin_lock_irq(&port->lock);
2901 serial8250_enable_ms(port);
2902 spin_unlock_irq(&port->lock);
2904 port->flags &= ~UPF_HARDPPS_CD;
2905 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2906 spin_lock_irq(&port->lock);
2907 serial8250_disable_ms(port);
2908 spin_unlock_irq(&port->lock);
2912 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2915 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2917 if (port->set_ldisc)
2918 port->set_ldisc(port, termios);
2920 serial8250_do_set_ldisc(port, termios);
2923 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2924 unsigned int oldstate)
2926 struct uart_8250_port *p = up_to_u8250p(port);
2928 serial8250_set_sleep(p, state != 0);
2930 EXPORT_SYMBOL(serial8250_do_pm);
2933 serial8250_pm(struct uart_port *port, unsigned int state,
2934 unsigned int oldstate)
2937 port->pm(port, state, oldstate);
2939 serial8250_do_pm(port, state, oldstate);
2942 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2944 if (pt->port.mapsize)
2945 return pt->port.mapsize;
2946 if (pt->port.iotype == UPIO_AU) {
2947 if (pt->port.type == PORT_RT2880)
2951 if (is_omap1_8250(pt))
2952 return 0x16 << pt->port.regshift;
2954 return 8 << pt->port.regshift;
2958 * Resource handling.
2960 static int serial8250_request_std_resource(struct uart_8250_port *up)
2962 unsigned int size = serial8250_port_size(up);
2963 struct uart_port *port = &up->port;
2966 switch (port->iotype) {
2973 if (!port->mapbase) {
2978 if (!request_mem_region(port->mapbase, size, "serial")) {
2983 if (port->flags & UPF_IOREMAP) {
2984 port->membase = ioremap(port->mapbase, size);
2985 if (!port->membase) {
2986 release_mem_region(port->mapbase, size);
2994 if (!request_region(port->iobase, size, "serial"))
3001 static void serial8250_release_std_resource(struct uart_8250_port *up)
3003 unsigned int size = serial8250_port_size(up);
3004 struct uart_port *port = &up->port;
3006 switch (port->iotype) {
3016 if (port->flags & UPF_IOREMAP) {
3017 iounmap(port->membase);
3018 port->membase = NULL;
3021 release_mem_region(port->mapbase, size);
3026 release_region(port->iobase, size);
3031 static void serial8250_release_port(struct uart_port *port)
3033 struct uart_8250_port *up = up_to_u8250p(port);
3035 serial8250_release_std_resource(up);
3038 static int serial8250_request_port(struct uart_port *port)
3040 struct uart_8250_port *up = up_to_u8250p(port);
3042 return serial8250_request_std_resource(up);
3045 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3047 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3048 unsigned char bytes;
3050 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3052 return bytes ? bytes : -EOPNOTSUPP;
3055 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3057 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3060 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3063 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3064 if (bytes < conf_type->rxtrig_bytes[i])
3065 /* Use the nearest lower value */
3066 return (--i) << UART_FCR_R_TRIG_SHIFT;
3069 return UART_FCR_R_TRIG_11;
3072 static int do_get_rxtrig(struct tty_port *port)
3074 struct uart_state *state = container_of(port, struct uart_state, port);
3075 struct uart_port *uport = state->uart_port;
3076 struct uart_8250_port *up = up_to_u8250p(uport);
3078 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3081 return fcr_get_rxtrig_bytes(up);
3084 static int do_serial8250_get_rxtrig(struct tty_port *port)
3088 mutex_lock(&port->mutex);
3089 rxtrig_bytes = do_get_rxtrig(port);
3090 mutex_unlock(&port->mutex);
3092 return rxtrig_bytes;
3095 static ssize_t rx_trig_bytes_show(struct device *dev,
3096 struct device_attribute *attr, char *buf)
3098 struct tty_port *port = dev_get_drvdata(dev);
3101 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3102 if (rxtrig_bytes < 0)
3103 return rxtrig_bytes;
3105 return sysfs_emit(buf, "%d\n", rxtrig_bytes);
3108 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3110 struct uart_state *state = container_of(port, struct uart_state, port);
3111 struct uart_port *uport = state->uart_port;
3112 struct uart_8250_port *up = up_to_u8250p(uport);
3115 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3119 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3123 serial8250_clear_fifos(up);
3124 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3125 up->fcr |= (unsigned char)rxtrig;
3126 serial_out(up, UART_FCR, up->fcr);
3130 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3134 mutex_lock(&port->mutex);
3135 ret = do_set_rxtrig(port, bytes);
3136 mutex_unlock(&port->mutex);
3141 static ssize_t rx_trig_bytes_store(struct device *dev,
3142 struct device_attribute *attr, const char *buf, size_t count)
3144 struct tty_port *port = dev_get_drvdata(dev);
3145 unsigned char bytes;
3151 ret = kstrtou8(buf, 10, &bytes);
3155 ret = do_serial8250_set_rxtrig(port, bytes);
3162 static DEVICE_ATTR_RW(rx_trig_bytes);
3164 static struct attribute *serial8250_dev_attrs[] = {
3165 &dev_attr_rx_trig_bytes.attr,
3169 static struct attribute_group serial8250_dev_attr_group = {
3170 .attrs = serial8250_dev_attrs,
3173 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3175 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3177 if (conf_type->rxtrig_bytes[0])
3178 up->port.attr_group = &serial8250_dev_attr_group;
3181 static void serial8250_config_port(struct uart_port *port, int flags)
3183 struct uart_8250_port *up = up_to_u8250p(port);
3187 * Find the region that we can probe for. This in turn
3188 * tells us whether we can probe for the type of port.
3190 ret = serial8250_request_std_resource(up);
3194 if (port->iotype != up->cur_iotype)
3195 set_io_from_upio(port);
3197 if (flags & UART_CONFIG_TYPE)
3200 /* if access method is AU, it is a 16550 with a quirk */
3201 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3202 up->bugs |= UART_BUG_NOMSR;
3204 /* HW bugs may trigger IRQ while IIR == NO_INT */
3205 if (port->type == PORT_TEGRA)
3206 up->bugs |= UART_BUG_NOMSR;
3208 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3211 if (port->type == PORT_UNKNOWN)
3212 serial8250_release_std_resource(up);
3214 register_dev_spec_attr_grp(up);
3215 up->fcr = uart_config[up->port.type].fcr;
3219 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3221 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3222 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3223 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3224 ser->type == PORT_STARTECH)
3229 static const char *serial8250_type(struct uart_port *port)
3231 int type = port->type;
3233 if (type >= ARRAY_SIZE(uart_config))
3235 return uart_config[type].name;
3238 static const struct uart_ops serial8250_pops = {
3239 .tx_empty = serial8250_tx_empty,
3240 .set_mctrl = serial8250_set_mctrl,
3241 .get_mctrl = serial8250_get_mctrl,
3242 .stop_tx = serial8250_stop_tx,
3243 .start_tx = serial8250_start_tx,
3244 .throttle = serial8250_throttle,
3245 .unthrottle = serial8250_unthrottle,
3246 .stop_rx = serial8250_stop_rx,
3247 .enable_ms = serial8250_enable_ms,
3248 .break_ctl = serial8250_break_ctl,
3249 .startup = serial8250_startup,
3250 .shutdown = serial8250_shutdown,
3251 .set_termios = serial8250_set_termios,
3252 .set_ldisc = serial8250_set_ldisc,
3253 .pm = serial8250_pm,
3254 .type = serial8250_type,
3255 .release_port = serial8250_release_port,
3256 .request_port = serial8250_request_port,
3257 .config_port = serial8250_config_port,
3258 .verify_port = serial8250_verify_port,
3259 #ifdef CONFIG_CONSOLE_POLL
3260 .poll_get_char = serial8250_get_poll_char,
3261 .poll_put_char = serial8250_put_poll_char,
3265 void serial8250_init_port(struct uart_8250_port *up)
3267 struct uart_port *port = &up->port;
3269 spin_lock_init(&port->lock);
3270 port->ops = &serial8250_pops;
3271 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3273 up->cur_iotype = 0xFF;
3275 EXPORT_SYMBOL_GPL(serial8250_init_port);
3277 void serial8250_set_defaults(struct uart_8250_port *up)
3279 struct uart_port *port = &up->port;
3281 if (up->port.flags & UPF_FIXED_TYPE) {
3282 unsigned int type = up->port.type;
3284 if (!up->port.fifosize)
3285 up->port.fifosize = uart_config[type].fifo_size;
3287 up->tx_loadsz = uart_config[type].tx_loadsz;
3288 if (!up->capabilities)
3289 up->capabilities = uart_config[type].flags;
3292 set_io_from_upio(port);
3294 /* default dma handlers */
3296 if (!up->dma->tx_dma)
3297 up->dma->tx_dma = serial8250_tx_dma;
3298 if (!up->dma->rx_dma)
3299 up->dma->rx_dma = serial8250_rx_dma;
3302 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3304 #ifdef CONFIG_SERIAL_8250_CONSOLE
3306 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3308 struct uart_8250_port *up = up_to_u8250p(port);
3310 wait_for_xmitr(up, UART_LSR_THRE);
3311 serial_port_out(port, UART_TX, ch);
3315 * Restore serial console when h/w power-off detected
3317 static void serial8250_console_restore(struct uart_8250_port *up)
3319 struct uart_port *port = &up->port;
3320 struct ktermios termios;
3321 unsigned int baud, quot, frac = 0;
3323 termios.c_cflag = port->cons->cflag;
3324 termios.c_ispeed = port->cons->ispeed;
3325 termios.c_ospeed = port->cons->ospeed;
3326 if (port->state->port.tty && termios.c_cflag == 0) {
3327 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3328 termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3329 termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3332 baud = serial8250_get_baud_rate(port, &termios, NULL);
3333 quot = serial8250_get_divisor(port, baud, &frac);
3335 serial8250_set_divisor(port, baud, quot, frac);
3336 serial_port_out(port, UART_LCR, up->lcr);
3337 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3341 * Print a string to the serial port using the device FIFO
3343 * It sends fifosize bytes and then waits for the fifo
3346 static void serial8250_console_fifo_write(struct uart_8250_port *up,
3347 const char *s, unsigned int count)
3350 const char *end = s + count;
3351 unsigned int fifosize = up->tx_loadsz;
3352 bool cr_sent = false;
3355 wait_for_lsr(up, UART_LSR_THRE);
3357 for (i = 0; i < fifosize && s != end; ++i) {
3358 if (*s == '\n' && !cr_sent) {
3359 serial_out(up, UART_TX, '\r');
3362 serial_out(up, UART_TX, *s++);
3370 * Print a string to the serial port trying not to disturb
3371 * any possible real use of the port...
3373 * The console_lock must be held when we get here.
3375 * Doing runtime PM is really a bad idea for the kernel console.
3376 * Thus, we assume the function is called when device is powered up.
3378 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3381 struct uart_8250_em485 *em485 = up->em485;
3382 struct uart_port *port = &up->port;
3383 unsigned long flags;
3384 unsigned int ier, use_fifo;
3387 touch_nmi_watchdog();
3389 if (oops_in_progress)
3390 locked = spin_trylock_irqsave(&port->lock, flags);
3392 spin_lock_irqsave(&port->lock, flags);
3395 * First save the IER then disable the interrupts
3397 ier = serial_port_in(port, UART_IER);
3398 serial8250_clear_IER(up);
3400 /* check scratch reg to see if port powered off during system sleep */
3401 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3402 serial8250_console_restore(up);
3407 if (em485->tx_stopped)
3408 up->rs485_start_tx(up);
3409 mdelay(port->rs485.delay_rts_before_send);
3412 use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3414 * BCM283x requires to check the fifo
3417 !(up->capabilities & UART_CAP_MINI) &&
3419 * tx_loadsz contains the transmit fifo size
3421 up->tx_loadsz > 1 &&
3422 (up->fcr & UART_FCR_ENABLE_FIFO) &&
3424 test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
3426 * After we put a data in the fifo, the controller will send
3427 * it regardless of the CTS state. Therefore, only use fifo
3428 * if we don't use control flow.
3430 !(up->port.flags & UPF_CONS_FLOW);
3432 if (likely(use_fifo))
3433 serial8250_console_fifo_write(up, s, count);
3435 uart_console_write(port, s, count, serial8250_console_putchar);
3438 * Finally, wait for transmitter to become empty
3439 * and restore the IER
3441 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
3444 mdelay(port->rs485.delay_rts_after_send);
3445 if (em485->tx_stopped)
3446 up->rs485_stop_tx(up);
3449 serial_port_out(port, UART_IER, ier);
3452 * The receive handling will happen properly because the
3453 * receive ready bit will still be set; it is not cleared
3454 * on read. However, modem control will not, we must
3455 * call it if we have saved something in the saved flags
3456 * while processing with interrupts off.
3458 if (up->msr_saved_flags)
3459 serial8250_modem_status(up);
3462 spin_unlock_irqrestore(&port->lock, flags);
3465 static unsigned int probe_baud(struct uart_port *port)
3467 unsigned char lcr, dll, dlm;
3470 lcr = serial_port_in(port, UART_LCR);
3471 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3472 dll = serial_port_in(port, UART_DLL);
3473 dlm = serial_port_in(port, UART_DLM);
3474 serial_port_out(port, UART_LCR, lcr);
3476 quot = (dlm << 8) | dll;
3477 return (port->uartclk / 16) / quot;
3480 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3488 if (!port->iobase && !port->membase)
3492 uart_parse_options(options, &baud, &parity, &bits, &flow);
3494 baud = probe_baud(port);
3496 ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3501 pm_runtime_get_sync(port->dev);
3506 int serial8250_console_exit(struct uart_port *port)
3509 pm_runtime_put_sync(port->dev);
3514 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3516 MODULE_LICENSE("GPL");