1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/sysrq.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/tty.h>
24 #include <linux/ratelimit.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_8250.h>
28 #include <linux/nmi.h>
29 #include <linux/mutex.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/ktime.h>
40 /* Nuvoton NPCM timeout register */
41 #define UART_NPCM_TOR 7
42 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
48 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
50 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
54 * Here we define the default xmit fifo size used for each type of UART.
56 static const struct serial8250_config uart_config[] = {
74 #ifdef CONFIG_SOC_STARFIVE
77 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
78 .rxtrig_bytes = {1, 4, 8, 14},
79 .flags = UART_CAP_FIFO,
89 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
90 .rxtrig_bytes = {1, 4, 8, 14},
91 .flags = UART_CAP_FIFO,
102 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
108 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
110 .rxtrig_bytes = {8, 16, 24, 28},
111 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
117 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
119 .rxtrig_bytes = {1, 16, 32, 56},
120 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
128 .name = "16C950/954",
131 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
132 .rxtrig_bytes = {16, 32, 112, 120},
133 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
134 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
140 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
142 .rxtrig_bytes = {8, 16, 56, 60},
143 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
149 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
150 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
156 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
157 .flags = UART_CAP_FIFO,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO | UART_NATSEMI,
170 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
171 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
177 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
178 .flags = UART_CAP_FIFO,
184 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
185 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
191 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
192 .flags = UART_CAP_FIFO | UART_CAP_AFE,
198 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
200 .rxtrig_bytes = {1, 4, 8, 14},
201 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
207 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
208 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
215 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
217 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
224 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
225 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
226 .flags = UART_CAP_FIFO,
228 [PORT_BRCM_TRUMANAGE] = {
232 .flags = UART_CAP_HFIFO,
237 [PORT_ALTR_16550_F32] = {
238 .name = "Altera 16550 FIFO32",
241 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
242 .rxtrig_bytes = {1, 8, 16, 30},
243 .flags = UART_CAP_FIFO | UART_CAP_AFE,
245 [PORT_ALTR_16550_F64] = {
246 .name = "Altera 16550 FIFO64",
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
250 .rxtrig_bytes = {1, 16, 32, 62},
251 .flags = UART_CAP_FIFO | UART_CAP_AFE,
253 [PORT_ALTR_16550_F128] = {
254 .name = "Altera 16550 FIFO128",
257 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
258 .rxtrig_bytes = {1, 32, 64, 126},
259 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
263 * workaround of errata A-008006 which states that tx_loadsz should
264 * be configured less than Maximum supported fifo bytes.
266 [PORT_16550A_FSL64] = {
267 .name = "16550A_FSL64",
270 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
272 .flags = UART_CAP_FIFO | UART_CAP_NOTEMT,
275 .name = "Palmchip BK-3103",
278 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
279 .rxtrig_bytes = {1, 4, 8, 14},
280 .flags = UART_CAP_FIFO,
283 .name = "TI DA8xx/66AK2x",
286 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
288 .rxtrig_bytes = {1, 4, 8, 14},
289 .flags = UART_CAP_FIFO | UART_CAP_AFE,
292 .name = "MediaTek BTIF",
295 .fcr = UART_FCR_ENABLE_FIFO |
296 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
297 .flags = UART_CAP_FIFO,
300 .name = "Nuvoton 16550",
303 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
304 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
305 .rxtrig_bytes = {1, 4, 8, 14},
306 .flags = UART_CAP_FIFO,
312 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
313 .rxtrig_bytes = {1, 32, 64, 112},
314 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
316 [PORT_ASPEED_VUART] = {
317 .name = "ASPEED VUART",
320 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
321 .rxtrig_bytes = {1, 4, 8, 14},
322 .flags = UART_CAP_FIFO,
326 /* Uart divisor latch read */
327 static int default_serial_dl_read(struct uart_8250_port *up)
329 /* Assign these in pieces to truncate any bits above 7. */
330 unsigned char dll = serial_in(up, UART_DLL);
331 unsigned char dlm = serial_in(up, UART_DLM);
333 return dll | dlm << 8;
336 /* Uart divisor latch write */
337 static void default_serial_dl_write(struct uart_8250_port *up, int value)
339 serial_out(up, UART_DLL, value & 0xff);
340 serial_out(up, UART_DLM, value >> 8 & 0xff);
343 #ifdef CONFIG_SERIAL_8250_RT288X
345 #define UART_REG_UNMAPPED -1
347 /* Au1x00/RT288x UART hardware has a weird register layout */
348 static const s8 au_io_in_map[8] = {
356 [UART_SCR] = UART_REG_UNMAPPED,
359 static const s8 au_io_out_map[8] = {
365 [UART_LSR] = UART_REG_UNMAPPED,
366 [UART_MSR] = UART_REG_UNMAPPED,
367 [UART_SCR] = UART_REG_UNMAPPED,
370 unsigned int au_serial_in(struct uart_port *p, int offset)
372 if (offset >= ARRAY_SIZE(au_io_in_map))
374 offset = au_io_in_map[offset];
375 if (offset == UART_REG_UNMAPPED)
377 return __raw_readl(p->membase + (offset << p->regshift));
380 void au_serial_out(struct uart_port *p, int offset, int value)
382 if (offset >= ARRAY_SIZE(au_io_out_map))
384 offset = au_io_out_map[offset];
385 if (offset == UART_REG_UNMAPPED)
387 __raw_writel(value, p->membase + (offset << p->regshift));
390 /* Au1x00 haven't got a standard divisor latch */
391 static int au_serial_dl_read(struct uart_8250_port *up)
393 return __raw_readl(up->port.membase + 0x28);
396 static void au_serial_dl_write(struct uart_8250_port *up, int value)
398 __raw_writel(value, up->port.membase + 0x28);
403 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
405 offset = offset << p->regshift;
406 outb(p->hub6 - 1 + offset, p->iobase);
407 return inb(p->iobase + 1);
410 static void hub6_serial_out(struct uart_port *p, int offset, int value)
412 offset = offset << p->regshift;
413 outb(p->hub6 - 1 + offset, p->iobase);
414 outb(value, p->iobase + 1);
417 static unsigned int mem_serial_in(struct uart_port *p, int offset)
419 offset = offset << p->regshift;
420 return readb(p->membase + offset);
423 static void mem_serial_out(struct uart_port *p, int offset, int value)
425 offset = offset << p->regshift;
426 writeb(value, p->membase + offset);
429 static void mem16_serial_out(struct uart_port *p, int offset, int value)
431 offset = offset << p->regshift;
432 writew(value, p->membase + offset);
435 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
437 offset = offset << p->regshift;
438 return readw(p->membase + offset);
441 static void mem32_serial_out(struct uart_port *p, int offset, int value)
443 offset = offset << p->regshift;
444 writel(value, p->membase + offset);
447 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
449 offset = offset << p->regshift;
450 return readl(p->membase + offset);
453 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
455 offset = offset << p->regshift;
456 iowrite32be(value, p->membase + offset);
459 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
461 offset = offset << p->regshift;
462 return ioread32be(p->membase + offset);
465 static unsigned int io_serial_in(struct uart_port *p, int offset)
467 offset = offset << p->regshift;
468 return inb(p->iobase + offset);
471 static void io_serial_out(struct uart_port *p, int offset, int value)
473 offset = offset << p->regshift;
474 outb(value, p->iobase + offset);
477 static int serial8250_default_handle_irq(struct uart_port *port);
479 static void set_io_from_upio(struct uart_port *p)
481 struct uart_8250_port *up = up_to_u8250p(p);
483 up->dl_read = default_serial_dl_read;
484 up->dl_write = default_serial_dl_write;
488 p->serial_in = hub6_serial_in;
489 p->serial_out = hub6_serial_out;
493 p->serial_in = mem_serial_in;
494 p->serial_out = mem_serial_out;
498 p->serial_in = mem16_serial_in;
499 p->serial_out = mem16_serial_out;
503 p->serial_in = mem32_serial_in;
504 p->serial_out = mem32_serial_out;
508 p->serial_in = mem32be_serial_in;
509 p->serial_out = mem32be_serial_out;
512 #ifdef CONFIG_SERIAL_8250_RT288X
514 p->serial_in = au_serial_in;
515 p->serial_out = au_serial_out;
516 up->dl_read = au_serial_dl_read;
517 up->dl_write = au_serial_dl_write;
522 p->serial_in = io_serial_in;
523 p->serial_out = io_serial_out;
526 /* Remember loaded iotype */
527 up->cur_iotype = p->iotype;
528 p->handle_irq = serial8250_default_handle_irq;
532 serial_port_out_sync(struct uart_port *p, int offset, int value)
540 p->serial_out(p, offset, value);
541 p->serial_in(p, UART_LCR); /* safe, no side-effects */
544 p->serial_out(p, offset, value);
551 static void serial8250_clear_fifos(struct uart_8250_port *p)
553 if (p->capabilities & UART_CAP_FIFO) {
554 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
555 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
556 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
557 serial_out(p, UART_FCR, 0);
561 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
562 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
564 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
566 serial8250_clear_fifos(p);
567 serial_out(p, UART_FCR, p->fcr);
569 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
571 void serial8250_rpm_get(struct uart_8250_port *p)
573 if (!(p->capabilities & UART_CAP_RPM))
575 pm_runtime_get_sync(p->port.dev);
577 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
579 void serial8250_rpm_put(struct uart_8250_port *p)
581 if (!(p->capabilities & UART_CAP_RPM))
583 pm_runtime_mark_last_busy(p->port.dev);
584 pm_runtime_put_autosuspend(p->port.dev);
586 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
589 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
590 * @p: uart_8250_port port instance
592 * The function is used to start rs485 software emulating on the
593 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
594 * transmission. The function is idempotent, so it is safe to call it
597 * The caller MUST enable interrupt on empty shift register before
598 * calling serial8250_em485_init(). This interrupt is not a part of
599 * 8250 standard, but implementation defined.
601 * The function is supposed to be called from .rs485_config callback
602 * or from any other callback protected with p->port.lock spinlock.
604 * See also serial8250_em485_destroy()
606 * Return 0 - success, -errno - otherwise
608 static int serial8250_em485_init(struct uart_8250_port *p)
613 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
617 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
619 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
621 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
622 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
624 p->em485->active_timer = NULL;
625 p->em485->tx_stopped = true;
628 if (p->em485->tx_stopped)
635 * serial8250_em485_destroy() - put uart_8250_port into normal state
636 * @p: uart_8250_port port instance
638 * The function is used to stop rs485 software emulating on the
639 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
640 * call it multiple times.
642 * The function is supposed to be called from .rs485_config callback
643 * or from any other callback protected with p->port.lock spinlock.
645 * See also serial8250_em485_init()
647 void serial8250_em485_destroy(struct uart_8250_port *p)
652 hrtimer_cancel(&p->em485->start_tx_timer);
653 hrtimer_cancel(&p->em485->stop_tx_timer);
658 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
660 struct serial_rs485 serial8250_em485_supported = {
661 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
662 SER_RS485_TERMINATE_BUS | SER_RS485_RX_DURING_TX,
663 .delay_rts_before_send = 1,
664 .delay_rts_after_send = 1,
666 EXPORT_SYMBOL_GPL(serial8250_em485_supported);
669 * serial8250_em485_config() - generic ->rs485_config() callback
671 * @rs485: rs485 settings
673 * Generic callback usable by 8250 uart drivers to activate rs485 settings
674 * if the uart is incapable of driving RTS as a Transmit Enable signal in
675 * hardware, relying on software emulation instead.
677 int serial8250_em485_config(struct uart_port *port, struct ktermios *termios,
678 struct serial_rs485 *rs485)
680 struct uart_8250_port *up = up_to_u8250p(port);
682 /* pick sane settings if the user hasn't */
683 if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
684 !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
685 rs485->flags |= SER_RS485_RTS_ON_SEND;
686 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
690 * Both serial8250_em485_init() and serial8250_em485_destroy()
693 if (rs485->flags & SER_RS485_ENABLED)
694 return serial8250_em485_init(up);
696 serial8250_em485_destroy(up);
699 EXPORT_SYMBOL_GPL(serial8250_em485_config);
702 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
703 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
704 * empty and the HW can idle again.
706 void serial8250_rpm_get_tx(struct uart_8250_port *p)
708 unsigned char rpm_active;
710 if (!(p->capabilities & UART_CAP_RPM))
713 rpm_active = xchg(&p->rpm_tx_active, 1);
716 pm_runtime_get_sync(p->port.dev);
718 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
720 void serial8250_rpm_put_tx(struct uart_8250_port *p)
722 unsigned char rpm_active;
724 if (!(p->capabilities & UART_CAP_RPM))
727 rpm_active = xchg(&p->rpm_tx_active, 0);
730 pm_runtime_mark_last_busy(p->port.dev);
731 pm_runtime_put_autosuspend(p->port.dev);
733 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
736 * IER sleep support. UARTs which have EFRs need the "extended
737 * capability" bit enabled. Note that on XR16C850s, we need to
738 * reset LCR to write to IER.
740 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
742 unsigned char lcr = 0, efr = 0;
744 serial8250_rpm_get(p);
746 if (p->capabilities & UART_CAP_SLEEP) {
747 if (p->capabilities & UART_CAP_EFR) {
748 lcr = serial_in(p, UART_LCR);
749 efr = serial_in(p, UART_EFR);
750 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
751 serial_out(p, UART_EFR, UART_EFR_ECB);
752 serial_out(p, UART_LCR, 0);
754 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
755 if (p->capabilities & UART_CAP_EFR) {
756 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
757 serial_out(p, UART_EFR, efr);
758 serial_out(p, UART_LCR, lcr);
762 serial8250_rpm_put(p);
765 static void serial8250_clear_IER(struct uart_8250_port *up)
767 if (up->capabilities & UART_CAP_UUE)
768 serial_out(up, UART_IER, UART_IER_UUE);
770 serial_out(up, UART_IER, 0);
773 #ifdef CONFIG_SERIAL_8250_RSA
775 * Attempts to turn on the RSA FIFO. Returns zero on failure.
776 * We set the port uart clock rate if we succeed.
778 static int __enable_rsa(struct uart_8250_port *up)
783 mode = serial_in(up, UART_RSA_MSR);
784 result = mode & UART_RSA_MSR_FIFO;
787 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
788 mode = serial_in(up, UART_RSA_MSR);
789 result = mode & UART_RSA_MSR_FIFO;
793 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
798 static void enable_rsa(struct uart_8250_port *up)
800 if (up->port.type == PORT_RSA) {
801 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
802 spin_lock_irq(&up->port.lock);
804 spin_unlock_irq(&up->port.lock);
806 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
807 serial_out(up, UART_RSA_FRR, 0);
812 * Attempts to turn off the RSA FIFO. Returns zero on failure.
813 * It is unknown why interrupts were disabled in here. However,
814 * the caller is expected to preserve this behaviour by grabbing
815 * the spinlock before calling this function.
817 static void disable_rsa(struct uart_8250_port *up)
822 if (up->port.type == PORT_RSA &&
823 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
824 spin_lock_irq(&up->port.lock);
826 mode = serial_in(up, UART_RSA_MSR);
827 result = !(mode & UART_RSA_MSR_FIFO);
830 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
831 mode = serial_in(up, UART_RSA_MSR);
832 result = !(mode & UART_RSA_MSR_FIFO);
836 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
837 spin_unlock_irq(&up->port.lock);
840 #endif /* CONFIG_SERIAL_8250_RSA */
843 * This is a quickie test to see how big the FIFO is.
844 * It doesn't work at all the time, more's the pity.
846 static int size_fifo(struct uart_8250_port *up)
848 unsigned char old_fcr, old_mcr, old_lcr;
849 unsigned short old_dl;
852 old_lcr = serial_in(up, UART_LCR);
853 serial_out(up, UART_LCR, 0);
854 old_fcr = serial_in(up, UART_FCR);
855 old_mcr = serial8250_in_MCR(up);
856 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
857 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
858 serial8250_out_MCR(up, UART_MCR_LOOP);
859 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
860 old_dl = serial_dl_read(up);
861 serial_dl_write(up, 0x0001);
862 serial_out(up, UART_LCR, UART_LCR_WLEN8);
863 for (count = 0; count < 256; count++)
864 serial_out(up, UART_TX, count);
865 mdelay(20);/* FIXME - schedule_timeout */
866 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
867 (count < 256); count++)
868 serial_in(up, UART_RX);
869 serial_out(up, UART_FCR, old_fcr);
870 serial8250_out_MCR(up, old_mcr);
871 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
872 serial_dl_write(up, old_dl);
873 serial_out(up, UART_LCR, old_lcr);
879 * Read UART ID using the divisor method - set DLL and DLM to zero
880 * and the revision will be in DLL and device type in DLM. We
881 * preserve the device state across this.
883 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
885 unsigned char old_lcr;
886 unsigned int id, old_dl;
888 old_lcr = serial_in(p, UART_LCR);
889 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
890 old_dl = serial_dl_read(p);
891 serial_dl_write(p, 0);
892 id = serial_dl_read(p);
893 serial_dl_write(p, old_dl);
895 serial_out(p, UART_LCR, old_lcr);
901 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
902 * When this function is called we know it is at least a StarTech
903 * 16650 V2, but it might be one of several StarTech UARTs, or one of
904 * its clones. (We treat the broken original StarTech 16650 V1 as a
905 * 16550, and why not? Startech doesn't seem to even acknowledge its
908 * What evil have men's minds wrought...
910 static void autoconfig_has_efr(struct uart_8250_port *up)
912 unsigned int id1, id2, id3, rev;
915 * Everything with an EFR has SLEEP
917 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
920 * First we check to see if it's an Oxford Semiconductor UART.
922 * If we have to do this here because some non-National
923 * Semiconductor clone chips lock up if you try writing to the
924 * LSR register (which serial_icr_read does)
928 * Check for Oxford Semiconductor 16C950.
930 * EFR [4] must be set else this test fails.
932 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
933 * claims that it's needed for 952 dual UART's (which are not
934 * recommended for new designs).
937 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
938 serial_out(up, UART_EFR, UART_EFR_ECB);
939 serial_out(up, UART_LCR, 0x00);
940 id1 = serial_icr_read(up, UART_ID1);
941 id2 = serial_icr_read(up, UART_ID2);
942 id3 = serial_icr_read(up, UART_ID3);
943 rev = serial_icr_read(up, UART_REV);
945 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
947 if (id1 == 0x16 && id2 == 0xC9 &&
948 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
949 up->port.type = PORT_16C950;
952 * Enable work around for the Oxford Semiconductor 952 rev B
953 * chip which causes it to seriously miscalculate baud rates
956 if (id3 == 0x52 && rev == 0x01)
957 up->bugs |= UART_BUG_QUOT;
962 * We check for a XR16C850 by setting DLL and DLM to 0, and then
963 * reading back DLL and DLM. The chip type depends on the DLM
965 * 0x10 - XR16C850 and the DLL contains the chip revision.
969 id1 = autoconfig_read_divisor_id(up);
970 DEBUG_AUTOCONF("850id=%04x ", id1);
973 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
974 up->port.type = PORT_16850;
979 * It wasn't an XR16C850.
981 * We distinguish between the '654 and the '650 by counting
982 * how many bytes are in the FIFO. I'm using this for now,
983 * since that's the technique that was sent to me in the
984 * serial driver update, but I'm not convinced this works.
985 * I've had problems doing this in the past. -TYT
987 if (size_fifo(up) == 64)
988 up->port.type = PORT_16654;
990 up->port.type = PORT_16650V2;
994 * We detected a chip without a FIFO. Only two fall into
995 * this category - the original 8250 and the 16450. The
996 * 16450 has a scratch register (accessible with LCR=0)
998 static void autoconfig_8250(struct uart_8250_port *up)
1000 unsigned char scratch, status1, status2;
1002 up->port.type = PORT_8250;
1004 scratch = serial_in(up, UART_SCR);
1005 serial_out(up, UART_SCR, 0xa5);
1006 status1 = serial_in(up, UART_SCR);
1007 serial_out(up, UART_SCR, 0x5a);
1008 status2 = serial_in(up, UART_SCR);
1009 serial_out(up, UART_SCR, scratch);
1011 if (status1 == 0xa5 && status2 == 0x5a)
1012 up->port.type = PORT_16450;
1015 static int broken_efr(struct uart_8250_port *up)
1018 * Exar ST16C2550 "A2" devices incorrectly detect as
1019 * having an EFR, and report an ID of 0x0201. See
1020 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1022 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1029 * We know that the chip has FIFOs. Does it have an EFR? The
1030 * EFR is located in the same register position as the IIR and
1031 * we know the top two bits of the IIR are currently set. The
1032 * EFR should contain zero. Try to read the EFR.
1034 static void autoconfig_16550a(struct uart_8250_port *up)
1036 unsigned char status1, status2;
1037 unsigned int iersave;
1039 up->port.type = PORT_16550A;
1040 up->capabilities |= UART_CAP_FIFO;
1042 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) &&
1043 !(up->port.flags & UPF_FULL_PROBE))
1047 * Check for presence of the EFR when DLAB is set.
1048 * Only ST16C650V1 UARTs pass this test.
1050 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1051 if (serial_in(up, UART_EFR) == 0) {
1052 serial_out(up, UART_EFR, 0xA8);
1053 if (serial_in(up, UART_EFR) != 0) {
1054 DEBUG_AUTOCONF("EFRv1 ");
1055 up->port.type = PORT_16650;
1056 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1058 serial_out(up, UART_LCR, 0);
1059 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1061 status1 = serial_in(up, UART_IIR) >> 5;
1062 serial_out(up, UART_FCR, 0);
1063 serial_out(up, UART_LCR, 0);
1066 up->port.type = PORT_16550A_FSL64;
1068 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1070 serial_out(up, UART_EFR, 0);
1075 * Maybe it requires 0xbf to be written to the LCR.
1076 * (other ST16C650V2 UARTs, TI16C752A, etc)
1078 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1079 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1080 DEBUG_AUTOCONF("EFRv2 ");
1081 autoconfig_has_efr(up);
1086 * Check for a National Semiconductor SuperIO chip.
1087 * Attempt to switch to bank 2, read the value of the LOOP bit
1088 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1089 * switch back to bank 2, read it from EXCR1 again and check
1090 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1092 serial_out(up, UART_LCR, 0);
1093 status1 = serial8250_in_MCR(up);
1094 serial_out(up, UART_LCR, 0xE0);
1095 status2 = serial_in(up, 0x02); /* EXCR1 */
1097 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1098 serial_out(up, UART_LCR, 0);
1099 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1100 serial_out(up, UART_LCR, 0xE0);
1101 status2 = serial_in(up, 0x02); /* EXCR1 */
1102 serial_out(up, UART_LCR, 0);
1103 serial8250_out_MCR(up, status1);
1105 if ((status2 ^ status1) & UART_MCR_LOOP) {
1106 unsigned short quot;
1108 serial_out(up, UART_LCR, 0xE0);
1110 quot = serial_dl_read(up);
1113 if (ns16550a_goto_highspeed(up))
1114 serial_dl_write(up, quot);
1116 serial_out(up, UART_LCR, 0);
1118 up->port.uartclk = 921600*16;
1119 up->port.type = PORT_NS16550A;
1120 up->capabilities |= UART_NATSEMI;
1126 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1127 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1128 * Try setting it with and without DLAB set. Cheap clones
1129 * set bit 5 without DLAB set.
1131 serial_out(up, UART_LCR, 0);
1132 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1133 status1 = serial_in(up, UART_IIR) >> 5;
1134 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1135 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1136 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1137 status2 = serial_in(up, UART_IIR) >> 5;
1138 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1139 serial_out(up, UART_LCR, 0);
1141 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1143 if (status1 == 6 && status2 == 7) {
1144 up->port.type = PORT_16750;
1145 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1150 * Try writing and reading the UART_IER_UUE bit (b6).
1151 * If it works, this is probably one of the Xscale platform's
1153 * We're going to explicitly set the UUE bit to 0 before
1154 * trying to write and read a 1 just to make sure it's not
1155 * already a 1 and maybe locked there before we even start.
1157 iersave = serial_in(up, UART_IER);
1158 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1159 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1161 * OK it's in a known zero state, try writing and reading
1162 * without disturbing the current state of the other bits.
1164 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1165 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1168 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1170 DEBUG_AUTOCONF("Xscale ");
1171 up->port.type = PORT_XSCALE;
1172 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1177 * If we got here we couldn't force the IER_UUE bit to 0.
1178 * Log it and continue.
1180 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1182 serial_out(up, UART_IER, iersave);
1185 * We distinguish between 16550A and U6 16550A by counting
1186 * how many bytes are in the FIFO.
1188 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1189 up->port.type = PORT_U6_16550A;
1190 up->capabilities |= UART_CAP_AFE;
1195 * This routine is called by rs_init() to initialize a specific serial
1196 * port. It determines what type of UART chip this serial port is
1197 * using: 8250, 16450, 16550, 16550A. The important question is
1198 * whether or not this UART is a 16550A or not, since this will
1199 * determine whether or not we can use its FIFO features or not.
1201 static void autoconfig(struct uart_8250_port *up)
1203 unsigned char status1, scratch, scratch2, scratch3;
1204 unsigned char save_lcr, save_mcr;
1205 struct uart_port *port = &up->port;
1206 unsigned long flags;
1207 unsigned int old_capabilities;
1209 if (!port->iobase && !port->mapbase && !port->membase)
1212 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1213 port->name, port->iobase, port->membase);
1216 * We really do need global IRQs disabled here - we're going to
1217 * be frobbing the chips IRQ enable register to see if it exists.
1219 spin_lock_irqsave(&port->lock, flags);
1221 up->capabilities = 0;
1224 if (!(port->flags & UPF_BUGGY_UART)) {
1226 * Do a simple existence test first; if we fail this,
1227 * there's no point trying anything else.
1229 * 0x80 is used as a nonsense port to prevent against
1230 * false positives due to ISA bus float. The
1231 * assumption is that 0x80 is a non-existent port;
1232 * which should be safe since include/asm/io.h also
1233 * makes this assumption.
1235 * Note: this is safe as long as MCR bit 4 is clear
1236 * and the device is in "PC" mode.
1238 scratch = serial_in(up, UART_IER);
1239 serial_out(up, UART_IER, 0);
1244 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1245 * 16C754B) allow only to modify them if an EFR bit is set.
1247 scratch2 = serial_in(up, UART_IER) & 0x0f;
1248 serial_out(up, UART_IER, 0x0F);
1252 scratch3 = serial_in(up, UART_IER) & 0x0f;
1253 serial_out(up, UART_IER, scratch);
1254 if (scratch2 != 0 || scratch3 != 0x0F) {
1256 * We failed; there's nothing here
1258 spin_unlock_irqrestore(&port->lock, flags);
1259 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1260 scratch2, scratch3);
1265 save_mcr = serial8250_in_MCR(up);
1266 save_lcr = serial_in(up, UART_LCR);
1269 * Check to see if a UART is really there. Certain broken
1270 * internal modems based on the Rockwell chipset fail this
1271 * test, because they apparently don't implement the loopback
1272 * test mode. So this test is skipped on the COM 1 through
1273 * COM 4 ports. This *should* be safe, since no board
1274 * manufacturer would be stupid enough to design a board
1275 * that conflicts with COM 1-4 --- we hope!
1277 if (!(port->flags & UPF_SKIP_TEST)) {
1278 serial8250_out_MCR(up, UART_MCR_LOOP | 0x0A);
1279 status1 = serial_in(up, UART_MSR) & 0xF0;
1280 serial8250_out_MCR(up, save_mcr);
1281 if (status1 != 0x90) {
1282 spin_unlock_irqrestore(&port->lock, flags);
1283 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1290 * We're pretty sure there's a port here. Lets find out what
1291 * type of port it is. The IIR top two bits allows us to find
1292 * out if it's 8250 or 16450, 16550, 16550A or later. This
1293 * determines what we test for next.
1295 * We also initialise the EFR (if any) to zero for later. The
1296 * EFR occupies the same register location as the FCR and IIR.
1298 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1299 serial_out(up, UART_EFR, 0);
1300 serial_out(up, UART_LCR, 0);
1302 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1304 /* Assign this as it is to truncate any bits above 7. */
1305 scratch = serial_in(up, UART_IIR);
1307 switch (scratch >> 6) {
1309 autoconfig_8250(up);
1312 port->type = PORT_UNKNOWN;
1315 port->type = PORT_16550;
1318 autoconfig_16550a(up);
1322 #ifdef CONFIG_SERIAL_8250_RSA
1324 * Only probe for RSA ports if we got the region.
1326 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1328 port->type = PORT_RSA;
1331 serial_out(up, UART_LCR, save_lcr);
1333 port->fifosize = uart_config[up->port.type].fifo_size;
1334 old_capabilities = up->capabilities;
1335 up->capabilities = uart_config[port->type].flags;
1336 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1338 if (port->type == PORT_UNKNOWN)
1344 #ifdef CONFIG_SERIAL_8250_RSA
1345 if (port->type == PORT_RSA)
1346 serial_out(up, UART_RSA_FRR, 0);
1348 serial8250_out_MCR(up, save_mcr);
1349 serial8250_clear_fifos(up);
1350 serial_in(up, UART_RX);
1351 serial8250_clear_IER(up);
1354 spin_unlock_irqrestore(&port->lock, flags);
1357 * Check if the device is a Fintek F81216A
1359 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1360 fintek_8250_probe(up);
1362 if (up->capabilities != old_capabilities) {
1363 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1364 old_capabilities, up->capabilities);
1367 DEBUG_AUTOCONF("iir=%d ", scratch);
1368 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1371 static void autoconfig_irq(struct uart_8250_port *up)
1373 struct uart_port *port = &up->port;
1374 unsigned char save_mcr, save_ier;
1375 unsigned char save_ICP = 0;
1376 unsigned int ICP = 0;
1380 if (port->flags & UPF_FOURPORT) {
1381 ICP = (port->iobase & 0xfe0) | 0x1f;
1382 save_ICP = inb_p(ICP);
1387 if (uart_console(port))
1390 /* forget possible initially masked and pending IRQ */
1391 probe_irq_off(probe_irq_on());
1392 save_mcr = serial8250_in_MCR(up);
1393 save_ier = serial_in(up, UART_IER);
1394 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1396 irqs = probe_irq_on();
1397 serial8250_out_MCR(up, 0);
1399 if (port->flags & UPF_FOURPORT) {
1400 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1402 serial8250_out_MCR(up,
1403 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1405 serial_out(up, UART_IER, 0x0f); /* enable all intrs */
1406 serial_in(up, UART_LSR);
1407 serial_in(up, UART_RX);
1408 serial_in(up, UART_IIR);
1409 serial_in(up, UART_MSR);
1410 serial_out(up, UART_TX, 0xFF);
1412 irq = probe_irq_off(irqs);
1414 serial8250_out_MCR(up, save_mcr);
1415 serial_out(up, UART_IER, save_ier);
1417 if (port->flags & UPF_FOURPORT)
1418 outb_p(save_ICP, ICP);
1420 if (uart_console(port))
1423 port->irq = (irq > 0) ? irq : 0;
1426 static void serial8250_stop_rx(struct uart_port *port)
1428 struct uart_8250_port *up = up_to_u8250p(port);
1430 serial8250_rpm_get(up);
1432 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1433 up->port.read_status_mask &= ~UART_LSR_DR;
1434 serial_port_out(port, UART_IER, up->ier);
1436 serial8250_rpm_put(up);
1440 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1441 * @p: uart 8250 port
1443 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1445 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1447 unsigned char mcr = serial8250_in_MCR(p);
1449 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1450 mcr |= UART_MCR_RTS;
1452 mcr &= ~UART_MCR_RTS;
1453 serial8250_out_MCR(p, mcr);
1456 * Empty the RX FIFO, we are not interested in anything
1457 * received during the half-duplex transmission.
1458 * Enable previously disabled RX interrupts.
1460 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1461 serial8250_clear_and_reinit_fifos(p);
1463 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1464 serial_port_out(&p->port, UART_IER, p->ier);
1467 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1469 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1471 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1473 struct uart_8250_port *p = em485->port;
1474 unsigned long flags;
1476 serial8250_rpm_get(p);
1477 spin_lock_irqsave(&p->port.lock, flags);
1478 if (em485->active_timer == &em485->stop_tx_timer) {
1479 p->rs485_stop_tx(p);
1480 em485->active_timer = NULL;
1481 em485->tx_stopped = true;
1483 spin_unlock_irqrestore(&p->port.lock, flags);
1484 serial8250_rpm_put(p);
1486 return HRTIMER_NORESTART;
1489 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1491 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1494 static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
1496 struct uart_8250_em485 *em485 = p->em485;
1498 stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
1501 * rs485_stop_tx() is going to set RTS according to config
1502 * AND flush RX FIFO if required.
1504 if (stop_delay > 0) {
1505 em485->active_timer = &em485->stop_tx_timer;
1506 hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL);
1508 p->rs485_stop_tx(p);
1509 em485->active_timer = NULL;
1510 em485->tx_stopped = true;
1514 static inline void __stop_tx(struct uart_8250_port *p)
1516 struct uart_8250_em485 *em485 = p->em485;
1519 u16 lsr = serial_lsr_in(p);
1522 p->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1524 if (!(lsr & UART_LSR_THRE))
1527 * To provide required timing and allow FIFO transfer,
1528 * __stop_tx_rs485() must be called only when both FIFO and
1529 * shift register are empty. The device driver should either
1530 * enable interrupt on TEMT or set UART_CAP_NOTEMT that will
1531 * enlarge stop_tx_timer by the tx time of one frame to cover
1532 * for emptying of the shift register.
1534 if (!(lsr & UART_LSR_TEMT)) {
1535 if (!(p->capabilities & UART_CAP_NOTEMT))
1538 * RTS might get deasserted too early with the normal
1539 * frame timing formula. It seems to suggest THRE might
1540 * get asserted already during tx of the stop bit
1541 * rather than after it is fully sent.
1542 * Roughly estimate 1 extra bit here with / 7.
1544 stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
1547 __stop_tx_rs485(p, stop_delay);
1550 if (serial8250_clear_THRI(p))
1551 serial8250_rpm_put_tx(p);
1554 static void serial8250_stop_tx(struct uart_port *port)
1556 struct uart_8250_port *up = up_to_u8250p(port);
1558 serial8250_rpm_get(up);
1562 * We really want to stop the transmitter from sending.
1564 if (port->type == PORT_16C950) {
1565 up->acr |= UART_ACR_TXDIS;
1566 serial_icr_write(up, UART_ACR, up->acr);
1568 serial8250_rpm_put(up);
1571 static inline void __start_tx(struct uart_port *port)
1573 struct uart_8250_port *up = up_to_u8250p(port);
1575 if (up->dma && !up->dma->tx_dma(up))
1578 if (serial8250_set_THRI(up)) {
1579 if (up->bugs & UART_BUG_TXEN) {
1580 u16 lsr = serial_lsr_in(up);
1582 if (lsr & UART_LSR_THRE)
1583 serial8250_tx_chars(up);
1588 * Re-enable the transmitter if we disabled it.
1590 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1591 up->acr &= ~UART_ACR_TXDIS;
1592 serial_icr_write(up, UART_ACR, up->acr);
1597 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1598 * @up: uart 8250 port
1600 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1601 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1602 * (Some chips use inverse semantics.) Further assumes that reception is
1603 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1604 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1606 void serial8250_em485_start_tx(struct uart_8250_port *up)
1608 unsigned char mcr = serial8250_in_MCR(up);
1610 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1611 serial8250_stop_rx(&up->port);
1613 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1614 mcr |= UART_MCR_RTS;
1616 mcr &= ~UART_MCR_RTS;
1617 serial8250_out_MCR(up, mcr);
1619 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1621 /* Returns false, if start_tx_timer was setup to defer TX start */
1622 static bool start_tx_rs485(struct uart_port *port)
1624 struct uart_8250_port *up = up_to_u8250p(port);
1625 struct uart_8250_em485 *em485 = up->em485;
1628 * While serial8250_em485_handle_stop_tx() is a noop if
1629 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1630 * the timer is still armed and triggers only after the current bunch of
1631 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1632 * So cancel the timer. There is still a theoretical race condition if
1633 * the timer is already running and only comes around to check for
1634 * em485->active_timer when &em485->stop_tx_timer is armed again.
1636 if (em485->active_timer == &em485->stop_tx_timer)
1637 hrtimer_try_to_cancel(&em485->stop_tx_timer);
1639 em485->active_timer = NULL;
1641 if (em485->tx_stopped) {
1642 em485->tx_stopped = false;
1644 up->rs485_start_tx(up);
1646 if (up->port.rs485.delay_rts_before_send > 0) {
1647 em485->active_timer = &em485->start_tx_timer;
1648 start_hrtimer_ms(&em485->start_tx_timer,
1649 up->port.rs485.delay_rts_before_send);
1657 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1659 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1661 struct uart_8250_port *p = em485->port;
1662 unsigned long flags;
1664 spin_lock_irqsave(&p->port.lock, flags);
1665 if (em485->active_timer == &em485->start_tx_timer) {
1666 __start_tx(&p->port);
1667 em485->active_timer = NULL;
1669 spin_unlock_irqrestore(&p->port.lock, flags);
1671 return HRTIMER_NORESTART;
1674 static void serial8250_start_tx(struct uart_port *port)
1676 struct uart_8250_port *up = up_to_u8250p(port);
1677 struct uart_8250_em485 *em485 = up->em485;
1679 if (!port->x_char && uart_circ_empty(&port->state->xmit))
1682 serial8250_rpm_get_tx(up);
1685 if ((em485->active_timer == &em485->start_tx_timer) ||
1686 !start_tx_rs485(port))
1692 static void serial8250_throttle(struct uart_port *port)
1694 port->throttle(port);
1697 static void serial8250_unthrottle(struct uart_port *port)
1699 port->unthrottle(port);
1702 static void serial8250_disable_ms(struct uart_port *port)
1704 struct uart_8250_port *up = up_to_u8250p(port);
1706 /* no MSR capabilities */
1707 if (up->bugs & UART_BUG_NOMSR)
1710 mctrl_gpio_disable_ms(up->gpios);
1712 up->ier &= ~UART_IER_MSI;
1713 serial_port_out(port, UART_IER, up->ier);
1716 static void serial8250_enable_ms(struct uart_port *port)
1718 struct uart_8250_port *up = up_to_u8250p(port);
1720 /* no MSR capabilities */
1721 if (up->bugs & UART_BUG_NOMSR)
1724 mctrl_gpio_enable_ms(up->gpios);
1726 up->ier |= UART_IER_MSI;
1728 serial8250_rpm_get(up);
1729 serial_port_out(port, UART_IER, up->ier);
1730 serial8250_rpm_put(up);
1733 void serial8250_read_char(struct uart_8250_port *up, u16 lsr)
1735 struct uart_port *port = &up->port;
1737 char flag = TTY_NORMAL;
1739 if (likely(lsr & UART_LSR_DR))
1740 ch = serial_in(up, UART_RX);
1743 * Intel 82571 has a Serial Over Lan device that will
1744 * set UART_LSR_BI without setting UART_LSR_DR when
1745 * it receives a break. To avoid reading from the
1746 * receive buffer without UART_LSR_DR bit set, we
1747 * just force the read character to be 0
1753 lsr |= up->lsr_saved_flags;
1754 up->lsr_saved_flags = 0;
1756 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1757 if (lsr & UART_LSR_BI) {
1758 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1761 * We do the SysRQ and SAK checking
1762 * here because otherwise the break
1763 * may get masked by ignore_status_mask
1764 * or read_status_mask.
1766 if (uart_handle_break(port))
1768 } else if (lsr & UART_LSR_PE)
1769 port->icount.parity++;
1770 else if (lsr & UART_LSR_FE)
1771 port->icount.frame++;
1772 if (lsr & UART_LSR_OE)
1773 port->icount.overrun++;
1776 * Mask off conditions which should be ignored.
1778 lsr &= port->read_status_mask;
1780 if (lsr & UART_LSR_BI) {
1781 dev_dbg(port->dev, "handling break\n");
1783 } else if (lsr & UART_LSR_PE)
1785 else if (lsr & UART_LSR_FE)
1788 if (uart_prepare_sysrq_char(port, ch))
1791 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1793 EXPORT_SYMBOL_GPL(serial8250_read_char);
1796 * serial8250_rx_chars - Read characters. The first LSR value must be passed in.
1798 * Returns LSR bits. The caller should rely only on non-Rx related LSR bits
1799 * (such as THRE) because the LSR value might come from an already consumed
1802 u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr)
1804 struct uart_port *port = &up->port;
1805 int max_count = 256;
1808 serial8250_read_char(up, lsr);
1809 if (--max_count == 0)
1811 lsr = serial_in(up, UART_LSR);
1812 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1814 tty_flip_buffer_push(&port->state->port);
1817 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1819 void serial8250_tx_chars(struct uart_8250_port *up)
1821 struct uart_port *port = &up->port;
1822 struct circ_buf *xmit = &port->state->xmit;
1826 uart_xchar_out(port, UART_TX);
1829 if (uart_tx_stopped(port)) {
1830 serial8250_stop_tx(port);
1833 if (uart_circ_empty(xmit)) {
1838 count = up->tx_loadsz;
1840 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1841 if (up->bugs & UART_BUG_TXRACE) {
1843 * The Aspeed BMC virtual UARTs have a bug where data
1844 * may get stuck in the BMC's Tx FIFO from bursts of
1845 * writes on the APB interface.
1847 * Delay back-to-back writes by a read cycle to avoid
1848 * stalling the VUART. Read a register that won't have
1849 * side-effects and discard the result.
1851 serial_in(up, UART_SCR);
1853 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1855 if (uart_circ_empty(xmit))
1857 if ((up->capabilities & UART_CAP_HFIFO) &&
1858 !uart_lsr_tx_empty(serial_in(up, UART_LSR)))
1860 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1861 if ((up->capabilities & UART_CAP_MINI) &&
1862 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1864 } while (--count > 0);
1866 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1867 uart_write_wakeup(port);
1870 * With RPM enabled, we have to wait until the FIFO is empty before the
1871 * HW can go idle. So we get here once again with empty FIFO and disable
1872 * the interrupt and RPM in __stop_tx()
1874 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1877 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1879 /* Caller holds uart port lock */
1880 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1882 struct uart_port *port = &up->port;
1883 unsigned int status = serial_in(up, UART_MSR);
1885 status |= up->msr_saved_flags;
1886 up->msr_saved_flags = 0;
1887 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1888 port->state != NULL) {
1889 if (status & UART_MSR_TERI)
1891 if (status & UART_MSR_DDSR)
1893 if (status & UART_MSR_DDCD)
1894 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1895 if (status & UART_MSR_DCTS)
1896 uart_handle_cts_change(port, status & UART_MSR_CTS);
1898 wake_up_interruptible(&port->state->port.delta_msr_wait);
1903 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1905 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1907 switch (iir & 0x3f) {
1909 if (!up->dma->rx_running)
1913 case UART_IIR_RX_TIMEOUT:
1914 serial8250_rx_dma_flush(up);
1917 return up->dma->rx_dma(up);
1921 * This handles the interrupt from one port.
1923 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1925 struct uart_8250_port *up = up_to_u8250p(port);
1926 bool skip_rx = false;
1927 unsigned long flags;
1930 if (iir & UART_IIR_NO_INT)
1933 spin_lock_irqsave(&port->lock, flags);
1935 status = serial_lsr_in(up);
1938 * If port is stopped and there are no error conditions in the
1939 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1940 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1941 * control when FIFO occupancy reaches preset threshold, thus
1942 * halting RX. This only works when auto HW flow control is
1945 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1946 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1947 !(port->read_status_mask & UART_LSR_DR))
1950 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1951 if (!up->dma || handle_rx_dma(up, iir))
1952 status = serial8250_rx_chars(up, status);
1954 serial8250_modem_status(up);
1955 if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
1956 if (!up->dma || up->dma->tx_err)
1957 serial8250_tx_chars(up);
1958 else if (!up->dma->tx_running)
1962 uart_unlock_and_check_sysrq_irqrestore(port, flags);
1966 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1968 static int serial8250_default_handle_irq(struct uart_port *port)
1970 struct uart_8250_port *up = up_to_u8250p(port);
1974 serial8250_rpm_get(up);
1976 iir = serial_port_in(port, UART_IIR);
1977 ret = serial8250_handle_irq(port, iir);
1979 serial8250_rpm_put(up);
1984 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1985 * have a programmable TX threshold that triggers the THRE interrupt in
1986 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1987 * has space available. Load it up with tx_loadsz bytes.
1989 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1991 unsigned long flags;
1992 unsigned int iir = serial_port_in(port, UART_IIR);
1994 /* TX Threshold IRQ triggered so load up FIFO */
1995 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1996 struct uart_8250_port *up = up_to_u8250p(port);
1998 spin_lock_irqsave(&port->lock, flags);
1999 serial8250_tx_chars(up);
2000 spin_unlock_irqrestore(&port->lock, flags);
2003 iir = serial_port_in(port, UART_IIR);
2004 return serial8250_handle_irq(port, iir);
2007 static unsigned int serial8250_tx_empty(struct uart_port *port)
2009 struct uart_8250_port *up = up_to_u8250p(port);
2010 unsigned long flags;
2013 serial8250_rpm_get(up);
2015 spin_lock_irqsave(&port->lock, flags);
2016 lsr = serial_lsr_in(up);
2017 spin_unlock_irqrestore(&port->lock, flags);
2019 serial8250_rpm_put(up);
2021 return uart_lsr_tx_empty(lsr) ? TIOCSER_TEMT : 0;
2024 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
2026 struct uart_8250_port *up = up_to_u8250p(port);
2027 unsigned int status;
2030 serial8250_rpm_get(up);
2031 status = serial8250_modem_status(up);
2032 serial8250_rpm_put(up);
2034 val = serial8250_MSR_to_TIOCM(status);
2036 return mctrl_gpio_get(up->gpios, &val);
2040 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2042 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2044 if (port->get_mctrl)
2045 return port->get_mctrl(port);
2046 return serial8250_do_get_mctrl(port);
2049 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2051 struct uart_8250_port *up = up_to_u8250p(port);
2054 mcr = serial8250_TIOCM_to_MCR(mctrl);
2058 serial8250_out_MCR(up, mcr);
2060 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2062 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2064 if (port->rs485.flags & SER_RS485_ENABLED)
2067 if (port->set_mctrl)
2068 port->set_mctrl(port, mctrl);
2070 serial8250_do_set_mctrl(port, mctrl);
2073 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2075 struct uart_8250_port *up = up_to_u8250p(port);
2076 unsigned long flags;
2078 serial8250_rpm_get(up);
2079 spin_lock_irqsave(&port->lock, flags);
2080 if (break_state == -1)
2081 up->lcr |= UART_LCR_SBC;
2083 up->lcr &= ~UART_LCR_SBC;
2084 serial_port_out(port, UART_LCR, up->lcr);
2085 spin_unlock_irqrestore(&port->lock, flags);
2086 serial8250_rpm_put(up);
2089 static void wait_for_lsr(struct uart_8250_port *up, int bits)
2091 unsigned int status, tmout = 10000;
2093 /* Wait up to 10ms for the character(s) to be sent. */
2095 status = serial_lsr_in(up);
2097 if ((status & bits) == bits)
2102 touch_nmi_watchdog();
2107 * Wait for transmitter & holding register to empty
2109 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2113 wait_for_lsr(up, bits);
2115 /* Wait up to 1s for flow control if necessary */
2116 if (up->port.flags & UPF_CONS_FLOW) {
2117 for (tmout = 1000000; tmout; tmout--) {
2118 unsigned int msr = serial_in(up, UART_MSR);
2119 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2120 if (msr & UART_MSR_CTS)
2123 touch_nmi_watchdog();
2128 #ifdef CONFIG_CONSOLE_POLL
2130 * Console polling routines for writing and reading from the uart while
2131 * in an interrupt or debug context.
2134 static int serial8250_get_poll_char(struct uart_port *port)
2136 struct uart_8250_port *up = up_to_u8250p(port);
2140 serial8250_rpm_get(up);
2142 lsr = serial_port_in(port, UART_LSR);
2144 if (!(lsr & UART_LSR_DR)) {
2145 status = NO_POLL_CHAR;
2149 status = serial_port_in(port, UART_RX);
2151 serial8250_rpm_put(up);
2156 static void serial8250_put_poll_char(struct uart_port *port,
2160 struct uart_8250_port *up = up_to_u8250p(port);
2162 serial8250_rpm_get(up);
2164 * First save the IER then disable the interrupts
2166 ier = serial_port_in(port, UART_IER);
2167 serial8250_clear_IER(up);
2169 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2171 * Send the character out.
2173 serial_port_out(port, UART_TX, c);
2176 * Finally, wait for transmitter to become empty
2177 * and restore the IER
2179 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2180 serial_port_out(port, UART_IER, ier);
2181 serial8250_rpm_put(up);
2184 #endif /* CONFIG_CONSOLE_POLL */
2186 int serial8250_do_startup(struct uart_port *port)
2188 struct uart_8250_port *up = up_to_u8250p(port);
2189 unsigned long flags;
2194 if (!port->fifosize)
2195 port->fifosize = uart_config[port->type].fifo_size;
2197 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2198 if (!up->capabilities)
2199 up->capabilities = uart_config[port->type].flags;
2202 if (port->iotype != up->cur_iotype)
2203 set_io_from_upio(port);
2205 serial8250_rpm_get(up);
2206 if (port->type == PORT_16C950) {
2207 /* Wake up and initialize UART */
2209 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2210 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2211 serial_port_out(port, UART_IER, 0);
2212 serial_port_out(port, UART_LCR, 0);
2213 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2214 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2215 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2216 serial_port_out(port, UART_LCR, 0);
2219 if (port->type == PORT_DA830) {
2220 /* Reset the port */
2221 serial_port_out(port, UART_IER, 0);
2222 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2225 /* Enable Tx, Rx and free run mode */
2226 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2227 UART_DA830_PWREMU_MGMT_UTRST |
2228 UART_DA830_PWREMU_MGMT_URRST |
2229 UART_DA830_PWREMU_MGMT_FREE);
2232 if (port->type == PORT_NPCM) {
2234 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2235 * register). Enable it, and set TIOC (timeout interrupt
2236 * comparator) to be 0x20 for correct operation.
2238 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2241 #ifdef CONFIG_SERIAL_8250_RSA
2243 * If this is an RSA port, see if we can kick it up to the
2244 * higher speed clock.
2250 * Clear the FIFO buffers and disable them.
2251 * (they will be reenabled in set_termios())
2253 serial8250_clear_fifos(up);
2256 * Clear the interrupt registers.
2258 serial_port_in(port, UART_LSR);
2259 serial_port_in(port, UART_RX);
2260 serial_port_in(port, UART_IIR);
2261 serial_port_in(port, UART_MSR);
2264 * At this point, there's no way the LSR could still be 0xff;
2265 * if it is, then bail out, because there's likely no UART
2268 if (!(port->flags & UPF_BUGGY_UART) &&
2269 (serial_port_in(port, UART_LSR) == 0xff)) {
2270 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2276 * For a XR16C850, we need to set the trigger levels
2278 if (port->type == PORT_16850) {
2281 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2283 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2284 serial_port_out(port, UART_FCTR,
2285 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2286 serial_port_out(port, UART_TRG, UART_TRG_96);
2287 serial_port_out(port, UART_FCTR,
2288 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2289 serial_port_out(port, UART_TRG, UART_TRG_96);
2291 serial_port_out(port, UART_LCR, 0);
2295 * For the Altera 16550 variants, set TX threshold trigger level.
2297 if (((port->type == PORT_ALTR_16550_F32) ||
2298 (port->type == PORT_ALTR_16550_F64) ||
2299 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2300 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2301 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2302 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2304 serial_port_out(port, UART_ALTR_AFR,
2305 UART_ALTR_EN_TXFIFO_LW);
2306 serial_port_out(port, UART_ALTR_TX_LOW,
2307 port->fifosize - up->tx_loadsz);
2308 port->handle_irq = serial8250_tx_threshold_handle_irq;
2312 /* Check if we need to have shared IRQs */
2313 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2314 up->port.irqflags |= IRQF_SHARED;
2316 retval = up->ops->setup_irq(up);
2320 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2323 if (port->irqflags & IRQF_SHARED)
2324 disable_irq_nosync(port->irq);
2327 * Test for UARTs that do not reassert THRE when the
2328 * transmitter is idle and the interrupt has already
2329 * been cleared. Real 16550s should always reassert
2330 * this interrupt whenever the transmitter is idle and
2331 * the interrupt is enabled. Delays are necessary to
2332 * allow register changes to become visible.
2334 spin_lock_irqsave(&port->lock, flags);
2336 wait_for_xmitr(up, UART_LSR_THRE);
2337 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2338 udelay(1); /* allow THRE to set */
2339 iir1 = serial_port_in(port, UART_IIR);
2340 serial_port_out(port, UART_IER, 0);
2341 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2342 udelay(1); /* allow a working UART time to re-assert THRE */
2343 iir = serial_port_in(port, UART_IIR);
2344 serial_port_out(port, UART_IER, 0);
2346 spin_unlock_irqrestore(&port->lock, flags);
2348 if (port->irqflags & IRQF_SHARED)
2349 enable_irq(port->irq);
2352 * If the interrupt is not reasserted, or we otherwise
2353 * don't trust the iir, setup a timer to kick the UART
2354 * on a regular basis.
2356 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2357 up->port.flags & UPF_BUG_THRE) {
2358 up->bugs |= UART_BUG_THRE;
2362 up->ops->setup_timer(up);
2365 * Now, initialize the UART
2367 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2369 spin_lock_irqsave(&port->lock, flags);
2370 if (up->port.flags & UPF_FOURPORT) {
2372 up->port.mctrl |= TIOCM_OUT1;
2375 * Most PC uarts need OUT2 raised to enable interrupts.
2378 up->port.mctrl |= TIOCM_OUT2;
2380 serial8250_set_mctrl(port, port->mctrl);
2383 * Serial over Lan (SoL) hack:
2384 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2385 * used for Serial Over Lan. Those chips take a longer time than a
2386 * normal serial device to signalize that a transmission data was
2387 * queued. Due to that, the above test generally fails. One solution
2388 * would be to delay the reading of iir. However, this is not
2389 * reliable, since the timeout is variable. So, let's just don't
2390 * test if we receive TX irq. This way, we'll never enable
2393 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2394 goto dont_test_tx_en;
2397 * Do a quick test to see if we receive an interrupt when we enable
2400 serial_port_out(port, UART_IER, UART_IER_THRI);
2401 lsr = serial_port_in(port, UART_LSR);
2402 iir = serial_port_in(port, UART_IIR);
2403 serial_port_out(port, UART_IER, 0);
2405 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2406 if (!(up->bugs & UART_BUG_TXEN)) {
2407 up->bugs |= UART_BUG_TXEN;
2408 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2411 up->bugs &= ~UART_BUG_TXEN;
2415 spin_unlock_irqrestore(&port->lock, flags);
2418 * Clear the interrupt registers again for luck, and clear the
2419 * saved flags to avoid getting false values from polling
2420 * routines or the previous session.
2422 serial_port_in(port, UART_LSR);
2423 serial_port_in(port, UART_RX);
2424 serial_port_in(port, UART_IIR);
2425 serial_port_in(port, UART_MSR);
2426 up->lsr_saved_flags = 0;
2427 up->msr_saved_flags = 0;
2430 * Request DMA channels for both RX and TX.
2433 const char *msg = NULL;
2435 if (uart_console(port))
2436 msg = "forbid DMA for kernel console";
2437 else if (serial8250_request_dma(up))
2438 msg = "failed to request DMA";
2440 dev_warn_ratelimited(port->dev, "%s\n", msg);
2446 * Set the IER shadow for rx interrupts but defer actual interrupt
2447 * enable until after the FIFOs are enabled; otherwise, an already-
2448 * active sender can swamp the interrupt handler with "too much work".
2450 up->ier = UART_IER_RLSI | UART_IER_RDI;
2452 if (port->flags & UPF_FOURPORT) {
2455 * Enable interrupts on the AST Fourport board
2457 icp = (port->iobase & 0xfe0) | 0x01f;
2463 serial8250_rpm_put(up);
2466 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2468 static int serial8250_startup(struct uart_port *port)
2471 return port->startup(port);
2472 return serial8250_do_startup(port);
2475 void serial8250_do_shutdown(struct uart_port *port)
2477 struct uart_8250_port *up = up_to_u8250p(port);
2478 unsigned long flags;
2480 serial8250_rpm_get(up);
2482 * Disable interrupts from this port
2484 spin_lock_irqsave(&port->lock, flags);
2486 serial_port_out(port, UART_IER, 0);
2487 spin_unlock_irqrestore(&port->lock, flags);
2489 synchronize_irq(port->irq);
2492 serial8250_release_dma(up);
2494 spin_lock_irqsave(&port->lock, flags);
2495 if (port->flags & UPF_FOURPORT) {
2496 /* reset interrupts on the AST Fourport board */
2497 inb((port->iobase & 0xfe0) | 0x1f);
2498 port->mctrl |= TIOCM_OUT1;
2500 port->mctrl &= ~TIOCM_OUT2;
2502 serial8250_set_mctrl(port, port->mctrl);
2503 spin_unlock_irqrestore(&port->lock, flags);
2506 * Disable break condition and FIFOs
2508 serial_port_out(port, UART_LCR,
2509 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2510 serial8250_clear_fifos(up);
2512 #ifdef CONFIG_SERIAL_8250_RSA
2514 * Reset the RSA board back to 115kbps compat mode.
2520 * Read data port to reset things, and then unlink from
2523 serial_port_in(port, UART_RX);
2524 serial8250_rpm_put(up);
2526 up->ops->release_irq(up);
2528 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2530 static void serial8250_shutdown(struct uart_port *port)
2533 port->shutdown(port);
2535 serial8250_do_shutdown(port);
2538 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2539 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2542 struct uart_port *port = &up->port;
2544 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2547 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2551 upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2552 struct uart_8250_port *up = up_to_u8250p(port);
2556 * Handle magic divisors for baud rates above baud_base on SMSC
2557 * Super I/O chips. We clamp custom rates from clk/6 and clk/12
2558 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
2559 * magic divisors actually reprogram the baud rate generator's
2560 * reference clock derived from chips's 14.318MHz clock input.
2562 * Documentation claims that with these magic divisors the base
2563 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2564 * for the extra baud rates of 460800bps and 230400bps rather
2565 * than the usual base frequency of 1.8462MHz. However empirical
2566 * evidence contradicts that.
2568 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2569 * effectively used as a clock prescaler selection bit for the
2570 * base frequency of 7.3728MHz, always used. If set to 0, then
2571 * the base frequency is divided by 4 for use by the Baud Rate
2572 * Generator, for the usual arrangement where the value of 1 of
2573 * the divisor produces the baud rate of 115200bps. Conversely,
2574 * if set to 1 and high-speed operation has been enabled with the
2575 * Serial Port Mode Register in the Device Configuration Space,
2576 * then the base frequency is supplied directly to the Baud Rate
2577 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2578 * 0x8004, etc. the respective baud rates produced are 460800bps,
2579 * 230400bps, 153600bps, 115200bps, etc.
2581 * In all cases only low 15 bits of the divisor are used to divide
2582 * the baud base and therefore 32767 is the maximum divisor value
2583 * possible, even though documentation says that the programmable
2584 * Baud Rate Generator is capable of dividing the internal PLL
2585 * clock by any divisor from 1 to 65535.
2587 if (magic_multiplier && baud >= port->uartclk / 6)
2589 else if (magic_multiplier && baud >= port->uartclk / 12)
2591 else if (up->port.type == PORT_NPCM)
2592 quot = npcm_get_divisor(up, baud);
2594 quot = uart_get_divisor(port, baud);
2597 * Oxford Semi 952 rev B workaround
2599 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2605 static unsigned int serial8250_get_divisor(struct uart_port *port,
2609 if (port->get_divisor)
2610 return port->get_divisor(port, baud, frac);
2612 return serial8250_do_get_divisor(port, baud, frac);
2615 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2620 cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2622 if (c_cflag & CSTOPB)
2623 cval |= UART_LCR_STOP;
2624 if (c_cflag & PARENB) {
2625 cval |= UART_LCR_PARITY;
2626 if (up->bugs & UART_BUG_PARITY)
2627 up->fifo_bug = true;
2629 if (!(c_cflag & PARODD))
2630 cval |= UART_LCR_EPAR;
2631 if (c_cflag & CMSPAR)
2632 cval |= UART_LCR_SPAR;
2637 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2638 unsigned int quot, unsigned int quot_frac)
2640 struct uart_8250_port *up = up_to_u8250p(port);
2642 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2643 if (is_omap1510_8250(up)) {
2644 if (baud == 115200) {
2646 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2648 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2652 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2653 * otherwise just set DLAB
2655 if (up->capabilities & UART_NATSEMI)
2656 serial_port_out(port, UART_LCR, 0xe0);
2658 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2660 serial_dl_write(up, quot);
2662 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2664 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2665 unsigned int quot, unsigned int quot_frac)
2667 if (port->set_divisor)
2668 port->set_divisor(port, baud, quot, quot_frac);
2670 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2673 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2674 struct ktermios *termios,
2675 const struct ktermios *old)
2677 unsigned int tolerance = port->uartclk / 100;
2682 * Handle magic divisors for baud rates above baud_base on SMSC
2683 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2684 * disable divisor values beyond 32767, which are unavailable.
2686 if (port->flags & UPF_MAGIC_MULTIPLIER) {
2687 min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2688 max = (port->uartclk + tolerance) / 4;
2690 min = port->uartclk / 16 / UART_DIV_MAX;
2691 max = (port->uartclk + tolerance) / 16;
2695 * Ask the core to calculate the divisor for us.
2696 * Allow 1% tolerance at the upper limit so uart clks marginally
2697 * slower than nominal still match standard baud rates without
2698 * causing transmission errors.
2700 return uart_get_baud_rate(port, termios, old, min, max);
2704 * Note in order to avoid the tty port mutex deadlock don't use the next method
2705 * within the uart port callbacks. Primarily it's supposed to be utilized to
2706 * handle a sudden reference clock rate change.
2708 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2710 struct uart_8250_port *up = up_to_u8250p(port);
2711 struct tty_port *tport = &port->state->port;
2712 unsigned int baud, quot, frac = 0;
2713 struct ktermios *termios;
2714 struct tty_struct *tty;
2715 unsigned long flags;
2717 tty = tty_port_tty_get(tport);
2719 mutex_lock(&tport->mutex);
2720 port->uartclk = uartclk;
2721 mutex_unlock(&tport->mutex);
2725 down_write(&tty->termios_rwsem);
2726 mutex_lock(&tport->mutex);
2728 if (port->uartclk == uartclk)
2731 port->uartclk = uartclk;
2733 if (!tty_port_initialized(tport))
2736 termios = &tty->termios;
2738 baud = serial8250_get_baud_rate(port, termios, NULL);
2739 quot = serial8250_get_divisor(port, baud, &frac);
2741 serial8250_rpm_get(up);
2742 spin_lock_irqsave(&port->lock, flags);
2744 uart_update_timeout(port, termios->c_cflag, baud);
2746 serial8250_set_divisor(port, baud, quot, frac);
2747 serial_port_out(port, UART_LCR, up->lcr);
2749 spin_unlock_irqrestore(&port->lock, flags);
2750 serial8250_rpm_put(up);
2753 mutex_unlock(&tport->mutex);
2754 up_write(&tty->termios_rwsem);
2757 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2760 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2761 const struct ktermios *old)
2763 struct uart_8250_port *up = up_to_u8250p(port);
2765 unsigned long flags;
2766 unsigned int baud, quot, frac = 0;
2768 if (up->capabilities & UART_CAP_MINI) {
2769 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2770 if ((termios->c_cflag & CSIZE) == CS5 ||
2771 (termios->c_cflag & CSIZE) == CS6)
2772 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2774 cval = serial8250_compute_lcr(up, termios->c_cflag);
2776 baud = serial8250_get_baud_rate(port, termios, old);
2777 quot = serial8250_get_divisor(port, baud, &frac);
2780 * Ok, we're now changing the port state. Do it with
2781 * interrupts disabled.
2783 serial8250_rpm_get(up);
2784 spin_lock_irqsave(&port->lock, flags);
2786 up->lcr = cval; /* Save computed LCR */
2788 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2789 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2790 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2791 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2792 up->fcr |= UART_FCR_TRIGGER_1;
2797 * MCR-based auto flow control. When AFE is enabled, RTS will be
2798 * deasserted when the receive FIFO contains more characters than
2799 * the trigger, or the MCR RTS bit is cleared.
2801 if (up->capabilities & UART_CAP_AFE) {
2802 up->mcr &= ~UART_MCR_AFE;
2803 if (termios->c_cflag & CRTSCTS)
2804 up->mcr |= UART_MCR_AFE;
2808 * Update the per-port timeout.
2810 uart_update_timeout(port, termios->c_cflag, baud);
2812 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2813 if (termios->c_iflag & INPCK)
2814 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2815 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2816 port->read_status_mask |= UART_LSR_BI;
2819 * Characters to ignore
2821 port->ignore_status_mask = 0;
2822 if (termios->c_iflag & IGNPAR)
2823 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2824 if (termios->c_iflag & IGNBRK) {
2825 port->ignore_status_mask |= UART_LSR_BI;
2827 * If we're ignoring parity and break indicators,
2828 * ignore overruns too (for real raw support).
2830 if (termios->c_iflag & IGNPAR)
2831 port->ignore_status_mask |= UART_LSR_OE;
2835 * ignore all characters if CREAD is not set
2837 if ((termios->c_cflag & CREAD) == 0)
2838 port->ignore_status_mask |= UART_LSR_DR;
2841 * CTS flow control flag and modem status interrupts
2843 up->ier &= ~UART_IER_MSI;
2844 if (!(up->bugs & UART_BUG_NOMSR) &&
2845 UART_ENABLE_MS(&up->port, termios->c_cflag))
2846 up->ier |= UART_IER_MSI;
2847 if (up->capabilities & UART_CAP_UUE)
2848 up->ier |= UART_IER_UUE;
2849 if (up->capabilities & UART_CAP_RTOIE)
2850 up->ier |= UART_IER_RTOIE;
2852 serial_port_out(port, UART_IER, up->ier);
2854 if (up->capabilities & UART_CAP_EFR) {
2855 unsigned char efr = 0;
2857 * TI16C752/Startech hardware flow control. FIXME:
2858 * - TI16C752 requires control thresholds to be set.
2859 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2861 if (termios->c_cflag & CRTSCTS)
2862 efr |= UART_EFR_CTS;
2864 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2865 if (port->flags & UPF_EXAR_EFR)
2866 serial_port_out(port, UART_XR_EFR, efr);
2868 serial_port_out(port, UART_EFR, efr);
2871 serial8250_set_divisor(port, baud, quot, frac);
2874 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2875 * is written without DLAB set, this mode will be disabled.
2877 if (port->type == PORT_16750)
2878 serial_port_out(port, UART_FCR, up->fcr);
2880 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2881 if (port->type != PORT_16750) {
2882 /* emulated UARTs (Lucent Venus 167x) need two steps */
2883 if (up->fcr & UART_FCR_ENABLE_FIFO)
2884 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2885 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2887 serial8250_set_mctrl(port, port->mctrl);
2888 spin_unlock_irqrestore(&port->lock, flags);
2889 serial8250_rpm_put(up);
2891 /* Don't rewrite B0 */
2892 if (tty_termios_baud_rate(termios))
2893 tty_termios_encode_baud_rate(termios, baud, baud);
2895 EXPORT_SYMBOL(serial8250_do_set_termios);
2898 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2899 const struct ktermios *old)
2901 if (port->set_termios)
2902 port->set_termios(port, termios, old);
2904 serial8250_do_set_termios(port, termios, old);
2907 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2909 if (termios->c_line == N_PPS) {
2910 port->flags |= UPF_HARDPPS_CD;
2911 spin_lock_irq(&port->lock);
2912 serial8250_enable_ms(port);
2913 spin_unlock_irq(&port->lock);
2915 port->flags &= ~UPF_HARDPPS_CD;
2916 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2917 spin_lock_irq(&port->lock);
2918 serial8250_disable_ms(port);
2919 spin_unlock_irq(&port->lock);
2923 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2926 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2928 if (port->set_ldisc)
2929 port->set_ldisc(port, termios);
2931 serial8250_do_set_ldisc(port, termios);
2934 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2935 unsigned int oldstate)
2937 struct uart_8250_port *p = up_to_u8250p(port);
2939 serial8250_set_sleep(p, state != 0);
2941 EXPORT_SYMBOL(serial8250_do_pm);
2944 serial8250_pm(struct uart_port *port, unsigned int state,
2945 unsigned int oldstate)
2948 port->pm(port, state, oldstate);
2950 serial8250_do_pm(port, state, oldstate);
2953 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2955 if (pt->port.mapsize)
2956 return pt->port.mapsize;
2957 if (pt->port.iotype == UPIO_AU) {
2958 if (pt->port.type == PORT_RT2880)
2962 if (is_omap1_8250(pt))
2963 return 0x16 << pt->port.regshift;
2965 return 8 << pt->port.regshift;
2969 * Resource handling.
2971 static int serial8250_request_std_resource(struct uart_8250_port *up)
2973 unsigned int size = serial8250_port_size(up);
2974 struct uart_port *port = &up->port;
2977 switch (port->iotype) {
2984 if (!port->mapbase) {
2989 if (!request_mem_region(port->mapbase, size, "serial")) {
2994 if (port->flags & UPF_IOREMAP) {
2995 port->membase = ioremap(port->mapbase, size);
2996 if (!port->membase) {
2997 release_mem_region(port->mapbase, size);
3005 if (!request_region(port->iobase, size, "serial"))
3012 static void serial8250_release_std_resource(struct uart_8250_port *up)
3014 unsigned int size = serial8250_port_size(up);
3015 struct uart_port *port = &up->port;
3017 switch (port->iotype) {
3027 if (port->flags & UPF_IOREMAP) {
3028 iounmap(port->membase);
3029 port->membase = NULL;
3032 release_mem_region(port->mapbase, size);
3037 release_region(port->iobase, size);
3042 static void serial8250_release_port(struct uart_port *port)
3044 struct uart_8250_port *up = up_to_u8250p(port);
3046 serial8250_release_std_resource(up);
3049 static int serial8250_request_port(struct uart_port *port)
3051 struct uart_8250_port *up = up_to_u8250p(port);
3053 return serial8250_request_std_resource(up);
3056 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3058 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3059 unsigned char bytes;
3061 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3063 return bytes ? bytes : -EOPNOTSUPP;
3066 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3068 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3071 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3074 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3075 if (bytes < conf_type->rxtrig_bytes[i])
3076 /* Use the nearest lower value */
3077 return (--i) << UART_FCR_R_TRIG_SHIFT;
3080 return UART_FCR_R_TRIG_11;
3083 static int do_get_rxtrig(struct tty_port *port)
3085 struct uart_state *state = container_of(port, struct uart_state, port);
3086 struct uart_port *uport = state->uart_port;
3087 struct uart_8250_port *up = up_to_u8250p(uport);
3089 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3092 return fcr_get_rxtrig_bytes(up);
3095 static int do_serial8250_get_rxtrig(struct tty_port *port)
3099 mutex_lock(&port->mutex);
3100 rxtrig_bytes = do_get_rxtrig(port);
3101 mutex_unlock(&port->mutex);
3103 return rxtrig_bytes;
3106 static ssize_t rx_trig_bytes_show(struct device *dev,
3107 struct device_attribute *attr, char *buf)
3109 struct tty_port *port = dev_get_drvdata(dev);
3112 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3113 if (rxtrig_bytes < 0)
3114 return rxtrig_bytes;
3116 return sysfs_emit(buf, "%d\n", rxtrig_bytes);
3119 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3121 struct uart_state *state = container_of(port, struct uart_state, port);
3122 struct uart_port *uport = state->uart_port;
3123 struct uart_8250_port *up = up_to_u8250p(uport);
3126 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3130 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3134 serial8250_clear_fifos(up);
3135 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3136 up->fcr |= (unsigned char)rxtrig;
3137 serial_out(up, UART_FCR, up->fcr);
3141 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3145 mutex_lock(&port->mutex);
3146 ret = do_set_rxtrig(port, bytes);
3147 mutex_unlock(&port->mutex);
3152 static ssize_t rx_trig_bytes_store(struct device *dev,
3153 struct device_attribute *attr, const char *buf, size_t count)
3155 struct tty_port *port = dev_get_drvdata(dev);
3156 unsigned char bytes;
3162 ret = kstrtou8(buf, 10, &bytes);
3166 ret = do_serial8250_set_rxtrig(port, bytes);
3173 static DEVICE_ATTR_RW(rx_trig_bytes);
3175 static struct attribute *serial8250_dev_attrs[] = {
3176 &dev_attr_rx_trig_bytes.attr,
3180 static struct attribute_group serial8250_dev_attr_group = {
3181 .attrs = serial8250_dev_attrs,
3184 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3186 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3188 if (conf_type->rxtrig_bytes[0])
3189 up->port.attr_group = &serial8250_dev_attr_group;
3192 static void serial8250_config_port(struct uart_port *port, int flags)
3194 struct uart_8250_port *up = up_to_u8250p(port);
3198 * Find the region that we can probe for. This in turn
3199 * tells us whether we can probe for the type of port.
3201 ret = serial8250_request_std_resource(up);
3205 if (port->iotype != up->cur_iotype)
3206 set_io_from_upio(port);
3208 if (flags & UART_CONFIG_TYPE)
3211 /* if access method is AU, it is a 16550 with a quirk */
3212 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3213 up->bugs |= UART_BUG_NOMSR;
3215 /* HW bugs may trigger IRQ while IIR == NO_INT */
3216 if (port->type == PORT_TEGRA)
3217 up->bugs |= UART_BUG_NOMSR;
3219 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3222 if (port->type == PORT_UNKNOWN)
3223 serial8250_release_std_resource(up);
3225 register_dev_spec_attr_grp(up);
3226 up->fcr = uart_config[up->port.type].fcr;
3230 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3232 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3233 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3234 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3235 ser->type == PORT_STARTECH)
3240 static const char *serial8250_type(struct uart_port *port)
3242 int type = port->type;
3244 if (type >= ARRAY_SIZE(uart_config))
3246 return uart_config[type].name;
3249 static const struct uart_ops serial8250_pops = {
3250 .tx_empty = serial8250_tx_empty,
3251 .set_mctrl = serial8250_set_mctrl,
3252 .get_mctrl = serial8250_get_mctrl,
3253 .stop_tx = serial8250_stop_tx,
3254 .start_tx = serial8250_start_tx,
3255 .throttle = serial8250_throttle,
3256 .unthrottle = serial8250_unthrottle,
3257 .stop_rx = serial8250_stop_rx,
3258 .enable_ms = serial8250_enable_ms,
3259 .break_ctl = serial8250_break_ctl,
3260 .startup = serial8250_startup,
3261 .shutdown = serial8250_shutdown,
3262 .set_termios = serial8250_set_termios,
3263 .set_ldisc = serial8250_set_ldisc,
3264 .pm = serial8250_pm,
3265 .type = serial8250_type,
3266 .release_port = serial8250_release_port,
3267 .request_port = serial8250_request_port,
3268 .config_port = serial8250_config_port,
3269 .verify_port = serial8250_verify_port,
3270 #ifdef CONFIG_CONSOLE_POLL
3271 .poll_get_char = serial8250_get_poll_char,
3272 .poll_put_char = serial8250_put_poll_char,
3276 void serial8250_init_port(struct uart_8250_port *up)
3278 struct uart_port *port = &up->port;
3280 spin_lock_init(&port->lock);
3281 port->ops = &serial8250_pops;
3282 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3284 up->cur_iotype = 0xFF;
3286 EXPORT_SYMBOL_GPL(serial8250_init_port);
3288 void serial8250_set_defaults(struct uart_8250_port *up)
3290 struct uart_port *port = &up->port;
3292 if (up->port.flags & UPF_FIXED_TYPE) {
3293 unsigned int type = up->port.type;
3295 if (!up->port.fifosize)
3296 up->port.fifosize = uart_config[type].fifo_size;
3298 up->tx_loadsz = uart_config[type].tx_loadsz;
3299 if (!up->capabilities)
3300 up->capabilities = uart_config[type].flags;
3303 set_io_from_upio(port);
3305 /* default dma handlers */
3307 if (!up->dma->tx_dma)
3308 up->dma->tx_dma = serial8250_tx_dma;
3309 if (!up->dma->rx_dma)
3310 up->dma->rx_dma = serial8250_rx_dma;
3313 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3315 #ifdef CONFIG_SERIAL_8250_CONSOLE
3317 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3319 struct uart_8250_port *up = up_to_u8250p(port);
3321 wait_for_xmitr(up, UART_LSR_THRE);
3322 serial_port_out(port, UART_TX, ch);
3326 * Restore serial console when h/w power-off detected
3328 static void serial8250_console_restore(struct uart_8250_port *up)
3330 struct uart_port *port = &up->port;
3331 struct ktermios termios;
3332 unsigned int baud, quot, frac = 0;
3334 termios.c_cflag = port->cons->cflag;
3335 termios.c_ispeed = port->cons->ispeed;
3336 termios.c_ospeed = port->cons->ospeed;
3337 if (port->state->port.tty && termios.c_cflag == 0) {
3338 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3339 termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3340 termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3343 baud = serial8250_get_baud_rate(port, &termios, NULL);
3344 quot = serial8250_get_divisor(port, baud, &frac);
3346 serial8250_set_divisor(port, baud, quot, frac);
3347 serial_port_out(port, UART_LCR, up->lcr);
3348 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3352 * Print a string to the serial port using the device FIFO
3354 * It sends fifosize bytes and then waits for the fifo
3357 static void serial8250_console_fifo_write(struct uart_8250_port *up,
3358 const char *s, unsigned int count)
3361 const char *end = s + count;
3362 unsigned int fifosize = up->tx_loadsz;
3363 bool cr_sent = false;
3366 wait_for_lsr(up, UART_LSR_THRE);
3368 for (i = 0; i < fifosize && s != end; ++i) {
3369 if (*s == '\n' && !cr_sent) {
3370 serial_out(up, UART_TX, '\r');
3373 serial_out(up, UART_TX, *s++);
3381 * Print a string to the serial port trying not to disturb
3382 * any possible real use of the port...
3384 * The console_lock must be held when we get here.
3386 * Doing runtime PM is really a bad idea for the kernel console.
3387 * Thus, we assume the function is called when device is powered up.
3389 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3392 struct uart_8250_em485 *em485 = up->em485;
3393 struct uart_port *port = &up->port;
3394 unsigned long flags;
3395 unsigned int ier, use_fifo;
3398 touch_nmi_watchdog();
3400 if (oops_in_progress)
3401 locked = spin_trylock_irqsave(&port->lock, flags);
3403 spin_lock_irqsave(&port->lock, flags);
3406 * First save the IER then disable the interrupts
3408 ier = serial_port_in(port, UART_IER);
3409 serial8250_clear_IER(up);
3411 /* check scratch reg to see if port powered off during system sleep */
3412 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3413 serial8250_console_restore(up);
3418 if (em485->tx_stopped)
3419 up->rs485_start_tx(up);
3420 mdelay(port->rs485.delay_rts_before_send);
3423 use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3425 * BCM283x requires to check the fifo
3428 !(up->capabilities & UART_CAP_MINI) &&
3430 * tx_loadsz contains the transmit fifo size
3432 up->tx_loadsz > 1 &&
3433 (up->fcr & UART_FCR_ENABLE_FIFO) &&
3435 test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
3437 * After we put a data in the fifo, the controller will send
3438 * it regardless of the CTS state. Therefore, only use fifo
3439 * if we don't use control flow.
3441 !(up->port.flags & UPF_CONS_FLOW);
3443 if (likely(use_fifo))
3444 serial8250_console_fifo_write(up, s, count);
3446 uart_console_write(port, s, count, serial8250_console_putchar);
3449 * Finally, wait for transmitter to become empty
3450 * and restore the IER
3452 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
3455 mdelay(port->rs485.delay_rts_after_send);
3456 if (em485->tx_stopped)
3457 up->rs485_stop_tx(up);
3460 serial_port_out(port, UART_IER, ier);
3463 * The receive handling will happen properly because the
3464 * receive ready bit will still be set; it is not cleared
3465 * on read. However, modem control will not, we must
3466 * call it if we have saved something in the saved flags
3467 * while processing with interrupts off.
3469 if (up->msr_saved_flags)
3470 serial8250_modem_status(up);
3473 spin_unlock_irqrestore(&port->lock, flags);
3476 static unsigned int probe_baud(struct uart_port *port)
3478 unsigned char lcr, dll, dlm;
3481 lcr = serial_port_in(port, UART_LCR);
3482 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3483 dll = serial_port_in(port, UART_DLL);
3484 dlm = serial_port_in(port, UART_DLM);
3485 serial_port_out(port, UART_LCR, lcr);
3487 quot = (dlm << 8) | dll;
3488 return (port->uartclk / 16) / quot;
3491 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3499 if (!port->iobase && !port->membase)
3503 uart_parse_options(options, &baud, &parity, &bits, &flow);
3505 baud = probe_baud(port);
3507 ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3512 pm_runtime_get_sync(port->dev);
3517 int serial8250_console_exit(struct uart_port *port)
3520 pm_runtime_put_sync(port->dev);
3525 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3527 MODULE_LICENSE("GPL");