1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/console.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/sysrq.h>
21 #include <linux/delay.h>
22 #include <linux/platform_device.h>
23 #include <linux/tty.h>
24 #include <linux/ratelimit.h>
25 #include <linux/tty_flip.h>
26 #include <linux/serial.h>
27 #include <linux/serial_8250.h>
28 #include <linux/nmi.h>
29 #include <linux/mutex.h>
30 #include <linux/slab.h>
31 #include <linux/uaccess.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/ktime.h>
40 /* Nuvoton NPCM timeout register */
41 #define UART_NPCM_TOR 7
42 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
48 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
50 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
54 * Here we define the default xmit fifo size used for each type of UART.
56 static const struct serial8250_config uart_config[] = {
81 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
82 .rxtrig_bytes = {1, 4, 8, 14},
83 .flags = UART_CAP_FIFO,
94 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
100 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
102 .rxtrig_bytes = {8, 16, 24, 28},
103 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
109 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
111 .rxtrig_bytes = {1, 16, 32, 56},
112 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
120 .name = "16C950/954",
123 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
124 .rxtrig_bytes = {16, 32, 112, 120},
125 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
126 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
132 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
134 .rxtrig_bytes = {8, 16, 56, 60},
135 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
141 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
142 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
148 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
149 .flags = UART_CAP_FIFO,
155 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
156 .flags = UART_CAP_FIFO | UART_NATSEMI,
162 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
163 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
169 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
170 .flags = UART_CAP_FIFO,
176 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
177 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
183 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
184 .flags = UART_CAP_FIFO | UART_CAP_AFE,
190 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
192 .rxtrig_bytes = {1, 4, 8, 14},
193 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
199 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
200 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
207 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
209 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
216 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
217 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
218 .flags = UART_CAP_FIFO,
220 [PORT_BRCM_TRUMANAGE] = {
224 .flags = UART_CAP_HFIFO,
229 [PORT_ALTR_16550_F32] = {
230 .name = "Altera 16550 FIFO32",
233 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
234 .rxtrig_bytes = {1, 8, 16, 30},
235 .flags = UART_CAP_FIFO | UART_CAP_AFE,
237 [PORT_ALTR_16550_F64] = {
238 .name = "Altera 16550 FIFO64",
241 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
242 .rxtrig_bytes = {1, 16, 32, 62},
243 .flags = UART_CAP_FIFO | UART_CAP_AFE,
245 [PORT_ALTR_16550_F128] = {
246 .name = "Altera 16550 FIFO128",
249 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
250 .rxtrig_bytes = {1, 32, 64, 126},
251 .flags = UART_CAP_FIFO | UART_CAP_AFE,
254 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
255 * workaround of errata A-008006 which states that tx_loadsz should
256 * be configured less than Maximum supported fifo bytes.
258 [PORT_16550A_FSL64] = {
259 .name = "16550A_FSL64",
262 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
264 .flags = UART_CAP_FIFO | UART_CAP_NOTEMT,
267 .name = "Palmchip BK-3103",
270 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
271 .rxtrig_bytes = {1, 4, 8, 14},
272 .flags = UART_CAP_FIFO,
275 .name = "TI DA8xx/66AK2x",
278 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
280 .rxtrig_bytes = {1, 4, 8, 14},
281 .flags = UART_CAP_FIFO | UART_CAP_AFE,
284 .name = "MediaTek BTIF",
287 .fcr = UART_FCR_ENABLE_FIFO |
288 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
289 .flags = UART_CAP_FIFO,
292 .name = "Nuvoton 16550",
295 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
296 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
297 .rxtrig_bytes = {1, 4, 8, 14},
298 .flags = UART_CAP_FIFO,
304 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
305 .rxtrig_bytes = {1, 32, 64, 112},
306 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
308 [PORT_ASPEED_VUART] = {
309 .name = "ASPEED VUART",
312 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
313 .rxtrig_bytes = {1, 4, 8, 14},
314 .flags = UART_CAP_FIFO,
316 [PORT_MCHP16550A] = {
317 .name = "MCHP16550A",
320 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
321 .rxtrig_bytes = {2, 66, 130, 194},
322 .flags = UART_CAP_FIFO,
326 /* Uart divisor latch read */
327 static int default_serial_dl_read(struct uart_8250_port *up)
329 /* Assign these in pieces to truncate any bits above 7. */
330 unsigned char dll = serial_in(up, UART_DLL);
331 unsigned char dlm = serial_in(up, UART_DLM);
333 return dll | dlm << 8;
336 /* Uart divisor latch write */
337 static void default_serial_dl_write(struct uart_8250_port *up, int value)
339 serial_out(up, UART_DLL, value & 0xff);
340 serial_out(up, UART_DLM, value >> 8 & 0xff);
343 #ifdef CONFIG_SERIAL_8250_RT288X
345 #define UART_REG_UNMAPPED -1
347 /* Au1x00/RT288x UART hardware has a weird register layout */
348 static const s8 au_io_in_map[8] = {
356 [UART_SCR] = UART_REG_UNMAPPED,
359 static const s8 au_io_out_map[8] = {
365 [UART_LSR] = UART_REG_UNMAPPED,
366 [UART_MSR] = UART_REG_UNMAPPED,
367 [UART_SCR] = UART_REG_UNMAPPED,
370 unsigned int au_serial_in(struct uart_port *p, int offset)
372 if (offset >= ARRAY_SIZE(au_io_in_map))
374 offset = au_io_in_map[offset];
375 if (offset == UART_REG_UNMAPPED)
377 return __raw_readl(p->membase + (offset << p->regshift));
380 void au_serial_out(struct uart_port *p, int offset, int value)
382 if (offset >= ARRAY_SIZE(au_io_out_map))
384 offset = au_io_out_map[offset];
385 if (offset == UART_REG_UNMAPPED)
387 __raw_writel(value, p->membase + (offset << p->regshift));
390 /* Au1x00 haven't got a standard divisor latch */
391 static int au_serial_dl_read(struct uart_8250_port *up)
393 return __raw_readl(up->port.membase + 0x28);
396 static void au_serial_dl_write(struct uart_8250_port *up, int value)
398 __raw_writel(value, up->port.membase + 0x28);
403 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
405 offset = offset << p->regshift;
406 outb(p->hub6 - 1 + offset, p->iobase);
407 return inb(p->iobase + 1);
410 static void hub6_serial_out(struct uart_port *p, int offset, int value)
412 offset = offset << p->regshift;
413 outb(p->hub6 - 1 + offset, p->iobase);
414 outb(value, p->iobase + 1);
417 static unsigned int mem_serial_in(struct uart_port *p, int offset)
419 offset = offset << p->regshift;
420 return readb(p->membase + offset);
423 static void mem_serial_out(struct uart_port *p, int offset, int value)
425 offset = offset << p->regshift;
426 writeb(value, p->membase + offset);
429 static void mem16_serial_out(struct uart_port *p, int offset, int value)
431 offset = offset << p->regshift;
432 writew(value, p->membase + offset);
435 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
437 offset = offset << p->regshift;
438 return readw(p->membase + offset);
441 static void mem32_serial_out(struct uart_port *p, int offset, int value)
443 offset = offset << p->regshift;
444 writel(value, p->membase + offset);
447 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
449 offset = offset << p->regshift;
450 return readl(p->membase + offset);
453 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
455 offset = offset << p->regshift;
456 iowrite32be(value, p->membase + offset);
459 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
461 offset = offset << p->regshift;
462 return ioread32be(p->membase + offset);
465 static unsigned int io_serial_in(struct uart_port *p, int offset)
467 offset = offset << p->regshift;
468 return inb(p->iobase + offset);
471 static void io_serial_out(struct uart_port *p, int offset, int value)
473 offset = offset << p->regshift;
474 outb(value, p->iobase + offset);
477 static int serial8250_default_handle_irq(struct uart_port *port);
479 static void set_io_from_upio(struct uart_port *p)
481 struct uart_8250_port *up = up_to_u8250p(p);
483 up->dl_read = default_serial_dl_read;
484 up->dl_write = default_serial_dl_write;
488 p->serial_in = hub6_serial_in;
489 p->serial_out = hub6_serial_out;
493 p->serial_in = mem_serial_in;
494 p->serial_out = mem_serial_out;
498 p->serial_in = mem16_serial_in;
499 p->serial_out = mem16_serial_out;
503 p->serial_in = mem32_serial_in;
504 p->serial_out = mem32_serial_out;
508 p->serial_in = mem32be_serial_in;
509 p->serial_out = mem32be_serial_out;
512 #ifdef CONFIG_SERIAL_8250_RT288X
514 p->serial_in = au_serial_in;
515 p->serial_out = au_serial_out;
516 up->dl_read = au_serial_dl_read;
517 up->dl_write = au_serial_dl_write;
522 p->serial_in = io_serial_in;
523 p->serial_out = io_serial_out;
526 /* Remember loaded iotype */
527 up->cur_iotype = p->iotype;
528 p->handle_irq = serial8250_default_handle_irq;
532 serial_port_out_sync(struct uart_port *p, int offset, int value)
540 p->serial_out(p, offset, value);
541 p->serial_in(p, UART_LCR); /* safe, no side-effects */
544 p->serial_out(p, offset, value);
551 static void serial8250_clear_fifos(struct uart_8250_port *p)
553 if (p->capabilities & UART_CAP_FIFO) {
554 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
555 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
556 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
557 serial_out(p, UART_FCR, 0);
561 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
562 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
564 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
566 serial8250_clear_fifos(p);
567 serial_out(p, UART_FCR, p->fcr);
569 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
571 void serial8250_rpm_get(struct uart_8250_port *p)
573 if (!(p->capabilities & UART_CAP_RPM))
575 pm_runtime_get_sync(p->port.dev);
577 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
579 void serial8250_rpm_put(struct uart_8250_port *p)
581 if (!(p->capabilities & UART_CAP_RPM))
583 pm_runtime_mark_last_busy(p->port.dev);
584 pm_runtime_put_autosuspend(p->port.dev);
586 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
589 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
590 * @p: uart_8250_port port instance
592 * The function is used to start rs485 software emulating on the
593 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
594 * transmission. The function is idempotent, so it is safe to call it
597 * The caller MUST enable interrupt on empty shift register before
598 * calling serial8250_em485_init(). This interrupt is not a part of
599 * 8250 standard, but implementation defined.
601 * The function is supposed to be called from .rs485_config callback
602 * or from any other callback protected with p->port.lock spinlock.
604 * See also serial8250_em485_destroy()
606 * Return 0 - success, -errno - otherwise
608 static int serial8250_em485_init(struct uart_8250_port *p)
613 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
617 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
619 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
621 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
622 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
624 p->em485->active_timer = NULL;
625 p->em485->tx_stopped = true;
628 if (p->em485->tx_stopped)
635 * serial8250_em485_destroy() - put uart_8250_port into normal state
636 * @p: uart_8250_port port instance
638 * The function is used to stop rs485 software emulating on the
639 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
640 * call it multiple times.
642 * The function is supposed to be called from .rs485_config callback
643 * or from any other callback protected with p->port.lock spinlock.
645 * See also serial8250_em485_init()
647 void serial8250_em485_destroy(struct uart_8250_port *p)
652 hrtimer_cancel(&p->em485->start_tx_timer);
653 hrtimer_cancel(&p->em485->stop_tx_timer);
658 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
660 struct serial_rs485 serial8250_em485_supported = {
661 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
662 SER_RS485_TERMINATE_BUS | SER_RS485_RX_DURING_TX,
663 .delay_rts_before_send = 1,
664 .delay_rts_after_send = 1,
666 EXPORT_SYMBOL_GPL(serial8250_em485_supported);
669 * serial8250_em485_config() - generic ->rs485_config() callback
671 * @rs485: rs485 settings
673 * Generic callback usable by 8250 uart drivers to activate rs485 settings
674 * if the uart is incapable of driving RTS as a Transmit Enable signal in
675 * hardware, relying on software emulation instead.
677 int serial8250_em485_config(struct uart_port *port, struct ktermios *termios,
678 struct serial_rs485 *rs485)
680 struct uart_8250_port *up = up_to_u8250p(port);
682 /* pick sane settings if the user hasn't */
683 if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
684 !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
685 rs485->flags |= SER_RS485_RTS_ON_SEND;
686 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
690 * Both serial8250_em485_init() and serial8250_em485_destroy()
693 if (rs485->flags & SER_RS485_ENABLED)
694 return serial8250_em485_init(up);
696 serial8250_em485_destroy(up);
699 EXPORT_SYMBOL_GPL(serial8250_em485_config);
702 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
703 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
704 * empty and the HW can idle again.
706 void serial8250_rpm_get_tx(struct uart_8250_port *p)
708 unsigned char rpm_active;
710 if (!(p->capabilities & UART_CAP_RPM))
713 rpm_active = xchg(&p->rpm_tx_active, 1);
716 pm_runtime_get_sync(p->port.dev);
718 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
720 void serial8250_rpm_put_tx(struct uart_8250_port *p)
722 unsigned char rpm_active;
724 if (!(p->capabilities & UART_CAP_RPM))
727 rpm_active = xchg(&p->rpm_tx_active, 0);
730 pm_runtime_mark_last_busy(p->port.dev);
731 pm_runtime_put_autosuspend(p->port.dev);
733 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
736 * IER sleep support. UARTs which have EFRs need the "extended
737 * capability" bit enabled. Note that on XR16C850s, we need to
738 * reset LCR to write to IER.
740 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
742 unsigned char lcr = 0, efr = 0;
744 serial8250_rpm_get(p);
746 if (p->capabilities & UART_CAP_SLEEP) {
747 if (p->capabilities & UART_CAP_EFR) {
748 lcr = serial_in(p, UART_LCR);
749 efr = serial_in(p, UART_EFR);
750 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
751 serial_out(p, UART_EFR, UART_EFR_ECB);
752 serial_out(p, UART_LCR, 0);
754 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
755 if (p->capabilities & UART_CAP_EFR) {
756 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
757 serial_out(p, UART_EFR, efr);
758 serial_out(p, UART_LCR, lcr);
762 serial8250_rpm_put(p);
765 static void serial8250_clear_IER(struct uart_8250_port *up)
767 if (up->capabilities & UART_CAP_UUE)
768 serial_out(up, UART_IER, UART_IER_UUE);
770 serial_out(up, UART_IER, 0);
773 #ifdef CONFIG_SERIAL_8250_RSA
775 * Attempts to turn on the RSA FIFO. Returns zero on failure.
776 * We set the port uart clock rate if we succeed.
778 static int __enable_rsa(struct uart_8250_port *up)
783 mode = serial_in(up, UART_RSA_MSR);
784 result = mode & UART_RSA_MSR_FIFO;
787 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
788 mode = serial_in(up, UART_RSA_MSR);
789 result = mode & UART_RSA_MSR_FIFO;
793 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
798 static void enable_rsa(struct uart_8250_port *up)
800 if (up->port.type == PORT_RSA) {
801 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
802 spin_lock_irq(&up->port.lock);
804 spin_unlock_irq(&up->port.lock);
806 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
807 serial_out(up, UART_RSA_FRR, 0);
812 * Attempts to turn off the RSA FIFO. Returns zero on failure.
813 * It is unknown why interrupts were disabled in here. However,
814 * the caller is expected to preserve this behaviour by grabbing
815 * the spinlock before calling this function.
817 static void disable_rsa(struct uart_8250_port *up)
822 if (up->port.type == PORT_RSA &&
823 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
824 spin_lock_irq(&up->port.lock);
826 mode = serial_in(up, UART_RSA_MSR);
827 result = !(mode & UART_RSA_MSR_FIFO);
830 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
831 mode = serial_in(up, UART_RSA_MSR);
832 result = !(mode & UART_RSA_MSR_FIFO);
836 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
837 spin_unlock_irq(&up->port.lock);
840 #endif /* CONFIG_SERIAL_8250_RSA */
843 * This is a quickie test to see how big the FIFO is.
844 * It doesn't work at all the time, more's the pity.
846 static int size_fifo(struct uart_8250_port *up)
848 unsigned char old_fcr, old_mcr, old_lcr;
849 unsigned short old_dl;
852 old_lcr = serial_in(up, UART_LCR);
853 serial_out(up, UART_LCR, 0);
854 old_fcr = serial_in(up, UART_FCR);
855 old_mcr = serial8250_in_MCR(up);
856 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
857 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
858 serial8250_out_MCR(up, UART_MCR_LOOP);
859 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
860 old_dl = serial_dl_read(up);
861 serial_dl_write(up, 0x0001);
862 serial_out(up, UART_LCR, UART_LCR_WLEN8);
863 for (count = 0; count < 256; count++)
864 serial_out(up, UART_TX, count);
865 mdelay(20);/* FIXME - schedule_timeout */
866 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
867 (count < 256); count++)
868 serial_in(up, UART_RX);
869 serial_out(up, UART_FCR, old_fcr);
870 serial8250_out_MCR(up, old_mcr);
871 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
872 serial_dl_write(up, old_dl);
873 serial_out(up, UART_LCR, old_lcr);
879 * Read UART ID using the divisor method - set DLL and DLM to zero
880 * and the revision will be in DLL and device type in DLM. We
881 * preserve the device state across this.
883 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
885 unsigned char old_lcr;
886 unsigned int id, old_dl;
888 old_lcr = serial_in(p, UART_LCR);
889 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
890 old_dl = serial_dl_read(p);
891 serial_dl_write(p, 0);
892 id = serial_dl_read(p);
893 serial_dl_write(p, old_dl);
895 serial_out(p, UART_LCR, old_lcr);
901 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
902 * When this function is called we know it is at least a StarTech
903 * 16650 V2, but it might be one of several StarTech UARTs, or one of
904 * its clones. (We treat the broken original StarTech 16650 V1 as a
905 * 16550, and why not? Startech doesn't seem to even acknowledge its
908 * What evil have men's minds wrought...
910 static void autoconfig_has_efr(struct uart_8250_port *up)
912 unsigned int id1, id2, id3, rev;
915 * Everything with an EFR has SLEEP
917 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
920 * First we check to see if it's an Oxford Semiconductor UART.
922 * If we have to do this here because some non-National
923 * Semiconductor clone chips lock up if you try writing to the
924 * LSR register (which serial_icr_read does)
928 * Check for Oxford Semiconductor 16C950.
930 * EFR [4] must be set else this test fails.
932 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
933 * claims that it's needed for 952 dual UART's (which are not
934 * recommended for new designs).
937 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
938 serial_out(up, UART_EFR, UART_EFR_ECB);
939 serial_out(up, UART_LCR, 0x00);
940 id1 = serial_icr_read(up, UART_ID1);
941 id2 = serial_icr_read(up, UART_ID2);
942 id3 = serial_icr_read(up, UART_ID3);
943 rev = serial_icr_read(up, UART_REV);
945 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
947 if (id1 == 0x16 && id2 == 0xC9 &&
948 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
949 up->port.type = PORT_16C950;
952 * Enable work around for the Oxford Semiconductor 952 rev B
953 * chip which causes it to seriously miscalculate baud rates
956 if (id3 == 0x52 && rev == 0x01)
957 up->bugs |= UART_BUG_QUOT;
962 * We check for a XR16C850 by setting DLL and DLM to 0, and then
963 * reading back DLL and DLM. The chip type depends on the DLM
965 * 0x10 - XR16C850 and the DLL contains the chip revision.
969 id1 = autoconfig_read_divisor_id(up);
970 DEBUG_AUTOCONF("850id=%04x ", id1);
973 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
974 up->port.type = PORT_16850;
979 * It wasn't an XR16C850.
981 * We distinguish between the '654 and the '650 by counting
982 * how many bytes are in the FIFO. I'm using this for now,
983 * since that's the technique that was sent to me in the
984 * serial driver update, but I'm not convinced this works.
985 * I've had problems doing this in the past. -TYT
987 if (size_fifo(up) == 64)
988 up->port.type = PORT_16654;
990 up->port.type = PORT_16650V2;
994 * We detected a chip without a FIFO. Only two fall into
995 * this category - the original 8250 and the 16450. The
996 * 16450 has a scratch register (accessible with LCR=0)
998 static void autoconfig_8250(struct uart_8250_port *up)
1000 unsigned char scratch, status1, status2;
1002 up->port.type = PORT_8250;
1004 scratch = serial_in(up, UART_SCR);
1005 serial_out(up, UART_SCR, 0xa5);
1006 status1 = serial_in(up, UART_SCR);
1007 serial_out(up, UART_SCR, 0x5a);
1008 status2 = serial_in(up, UART_SCR);
1009 serial_out(up, UART_SCR, scratch);
1011 if (status1 == 0xa5 && status2 == 0x5a)
1012 up->port.type = PORT_16450;
1015 static int broken_efr(struct uart_8250_port *up)
1018 * Exar ST16C2550 "A2" devices incorrectly detect as
1019 * having an EFR, and report an ID of 0x0201. See
1020 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
1022 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
1029 * We know that the chip has FIFOs. Does it have an EFR? The
1030 * EFR is located in the same register position as the IIR and
1031 * we know the top two bits of the IIR are currently set. The
1032 * EFR should contain zero. Try to read the EFR.
1034 static void autoconfig_16550a(struct uart_8250_port *up)
1036 unsigned char status1, status2;
1037 unsigned int iersave;
1039 up->port.type = PORT_16550A;
1040 up->capabilities |= UART_CAP_FIFO;
1042 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) &&
1043 !(up->port.flags & UPF_FULL_PROBE))
1047 * Check for presence of the EFR when DLAB is set.
1048 * Only ST16C650V1 UARTs pass this test.
1050 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1051 if (serial_in(up, UART_EFR) == 0) {
1052 serial_out(up, UART_EFR, 0xA8);
1053 if (serial_in(up, UART_EFR) != 0) {
1054 DEBUG_AUTOCONF("EFRv1 ");
1055 up->port.type = PORT_16650;
1056 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
1058 serial_out(up, UART_LCR, 0);
1059 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
1061 status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO |
1062 UART_IIR_FIFO_ENABLED);
1063 serial_out(up, UART_FCR, 0);
1064 serial_out(up, UART_LCR, 0);
1066 if (status1 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED))
1067 up->port.type = PORT_16550A_FSL64;
1069 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1071 serial_out(up, UART_EFR, 0);
1076 * Maybe it requires 0xbf to be written to the LCR.
1077 * (other ST16C650V2 UARTs, TI16C752A, etc)
1079 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1080 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1081 DEBUG_AUTOCONF("EFRv2 ");
1082 autoconfig_has_efr(up);
1087 * Check for a National Semiconductor SuperIO chip.
1088 * Attempt to switch to bank 2, read the value of the LOOP bit
1089 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1090 * switch back to bank 2, read it from EXCR1 again and check
1091 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1093 serial_out(up, UART_LCR, 0);
1094 status1 = serial8250_in_MCR(up);
1095 serial_out(up, UART_LCR, 0xE0);
1096 status2 = serial_in(up, 0x02); /* EXCR1 */
1098 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1099 serial_out(up, UART_LCR, 0);
1100 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1101 serial_out(up, UART_LCR, 0xE0);
1102 status2 = serial_in(up, 0x02); /* EXCR1 */
1103 serial_out(up, UART_LCR, 0);
1104 serial8250_out_MCR(up, status1);
1106 if ((status2 ^ status1) & UART_MCR_LOOP) {
1107 unsigned short quot;
1109 serial_out(up, UART_LCR, 0xE0);
1111 quot = serial_dl_read(up);
1114 if (ns16550a_goto_highspeed(up))
1115 serial_dl_write(up, quot);
1117 serial_out(up, UART_LCR, 0);
1119 up->port.uartclk = 921600*16;
1120 up->port.type = PORT_NS16550A;
1121 up->capabilities |= UART_NATSEMI;
1127 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1128 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1129 * Try setting it with and without DLAB set. Cheap clones
1130 * set bit 5 without DLAB set.
1132 serial_out(up, UART_LCR, 0);
1133 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1134 status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
1135 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1137 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1138 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1139 status2 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
1140 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1142 serial_out(up, UART_LCR, 0);
1144 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1146 if (status1 == UART_IIR_FIFO_ENABLED_16550A &&
1147 status2 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED_16550A)) {
1148 up->port.type = PORT_16750;
1149 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1154 * Try writing and reading the UART_IER_UUE bit (b6).
1155 * If it works, this is probably one of the Xscale platform's
1157 * We're going to explicitly set the UUE bit to 0 before
1158 * trying to write and read a 1 just to make sure it's not
1159 * already a 1 and maybe locked there before we even start.
1161 iersave = serial_in(up, UART_IER);
1162 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1163 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1165 * OK it's in a known zero state, try writing and reading
1166 * without disturbing the current state of the other bits.
1168 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1169 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1172 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1174 DEBUG_AUTOCONF("Xscale ");
1175 up->port.type = PORT_XSCALE;
1176 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1181 * If we got here we couldn't force the IER_UUE bit to 0.
1182 * Log it and continue.
1184 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1186 serial_out(up, UART_IER, iersave);
1189 * We distinguish between 16550A and U6 16550A by counting
1190 * how many bytes are in the FIFO.
1192 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1193 up->port.type = PORT_U6_16550A;
1194 up->capabilities |= UART_CAP_AFE;
1199 * This routine is called by rs_init() to initialize a specific serial
1200 * port. It determines what type of UART chip this serial port is
1201 * using: 8250, 16450, 16550, 16550A. The important question is
1202 * whether or not this UART is a 16550A or not, since this will
1203 * determine whether or not we can use its FIFO features or not.
1205 static void autoconfig(struct uart_8250_port *up)
1207 unsigned char status1, scratch, scratch2, scratch3;
1208 unsigned char save_lcr, save_mcr;
1209 struct uart_port *port = &up->port;
1210 unsigned long flags;
1211 unsigned int old_capabilities;
1213 if (!port->iobase && !port->mapbase && !port->membase)
1216 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1217 port->name, port->iobase, port->membase);
1220 * We really do need global IRQs disabled here - we're going to
1221 * be frobbing the chips IRQ enable register to see if it exists.
1223 spin_lock_irqsave(&port->lock, flags);
1225 up->capabilities = 0;
1228 if (!(port->flags & UPF_BUGGY_UART)) {
1230 * Do a simple existence test first; if we fail this,
1231 * there's no point trying anything else.
1233 * 0x80 is used as a nonsense port to prevent against
1234 * false positives due to ISA bus float. The
1235 * assumption is that 0x80 is a non-existent port;
1236 * which should be safe since include/asm/io.h also
1237 * makes this assumption.
1239 * Note: this is safe as long as MCR bit 4 is clear
1240 * and the device is in "PC" mode.
1242 scratch = serial_in(up, UART_IER);
1243 serial_out(up, UART_IER, 0);
1248 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1249 * 16C754B) allow only to modify them if an EFR bit is set.
1251 scratch2 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1252 serial_out(up, UART_IER, UART_IER_ALL_INTR);
1256 scratch3 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1257 serial_out(up, UART_IER, scratch);
1258 if (scratch2 != 0 || scratch3 != UART_IER_ALL_INTR) {
1260 * We failed; there's nothing here
1262 spin_unlock_irqrestore(&port->lock, flags);
1263 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1264 scratch2, scratch3);
1269 save_mcr = serial8250_in_MCR(up);
1270 save_lcr = serial_in(up, UART_LCR);
1273 * Check to see if a UART is really there. Certain broken
1274 * internal modems based on the Rockwell chipset fail this
1275 * test, because they apparently don't implement the loopback
1276 * test mode. So this test is skipped on the COM 1 through
1277 * COM 4 ports. This *should* be safe, since no board
1278 * manufacturer would be stupid enough to design a board
1279 * that conflicts with COM 1-4 --- we hope!
1281 if (!(port->flags & UPF_SKIP_TEST)) {
1282 serial8250_out_MCR(up, UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS);
1283 status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS;
1284 serial8250_out_MCR(up, save_mcr);
1285 if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) {
1286 spin_unlock_irqrestore(&port->lock, flags);
1287 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1294 * We're pretty sure there's a port here. Lets find out what
1295 * type of port it is. The IIR top two bits allows us to find
1296 * out if it's 8250 or 16450, 16550, 16550A or later. This
1297 * determines what we test for next.
1299 * We also initialise the EFR (if any) to zero for later. The
1300 * EFR occupies the same register location as the FCR and IIR.
1302 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1303 serial_out(up, UART_EFR, 0);
1304 serial_out(up, UART_LCR, 0);
1306 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1308 switch (serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED) {
1309 case UART_IIR_FIFO_ENABLED_8250:
1310 autoconfig_8250(up);
1312 case UART_IIR_FIFO_ENABLED_16550:
1313 port->type = PORT_16550;
1315 case UART_IIR_FIFO_ENABLED_16550A:
1316 autoconfig_16550a(up);
1319 port->type = PORT_UNKNOWN;
1323 #ifdef CONFIG_SERIAL_8250_RSA
1325 * Only probe for RSA ports if we got the region.
1327 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1329 port->type = PORT_RSA;
1332 serial_out(up, UART_LCR, save_lcr);
1334 port->fifosize = uart_config[up->port.type].fifo_size;
1335 old_capabilities = up->capabilities;
1336 up->capabilities = uart_config[port->type].flags;
1337 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1339 if (port->type == PORT_UNKNOWN)
1345 #ifdef CONFIG_SERIAL_8250_RSA
1346 if (port->type == PORT_RSA)
1347 serial_out(up, UART_RSA_FRR, 0);
1349 serial8250_out_MCR(up, save_mcr);
1350 serial8250_clear_fifos(up);
1351 serial_in(up, UART_RX);
1352 serial8250_clear_IER(up);
1355 spin_unlock_irqrestore(&port->lock, flags);
1358 * Check if the device is a Fintek F81216A
1360 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1361 fintek_8250_probe(up);
1363 if (up->capabilities != old_capabilities) {
1364 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1365 old_capabilities, up->capabilities);
1368 DEBUG_AUTOCONF("iir=%d ", scratch);
1369 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1372 static void autoconfig_irq(struct uart_8250_port *up)
1374 struct uart_port *port = &up->port;
1375 unsigned char save_mcr, save_ier;
1376 unsigned char save_ICP = 0;
1377 unsigned int ICP = 0;
1381 if (port->flags & UPF_FOURPORT) {
1382 ICP = (port->iobase & 0xfe0) | 0x1f;
1383 save_ICP = inb_p(ICP);
1388 if (uart_console(port))
1391 /* forget possible initially masked and pending IRQ */
1392 probe_irq_off(probe_irq_on());
1393 save_mcr = serial8250_in_MCR(up);
1394 save_ier = serial_in(up, UART_IER);
1395 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1397 irqs = probe_irq_on();
1398 serial8250_out_MCR(up, 0);
1400 if (port->flags & UPF_FOURPORT) {
1401 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1403 serial8250_out_MCR(up,
1404 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1406 serial_out(up, UART_IER, UART_IER_ALL_INTR);
1407 serial_in(up, UART_LSR);
1408 serial_in(up, UART_RX);
1409 serial_in(up, UART_IIR);
1410 serial_in(up, UART_MSR);
1411 serial_out(up, UART_TX, 0xFF);
1413 irq = probe_irq_off(irqs);
1415 serial8250_out_MCR(up, save_mcr);
1416 serial_out(up, UART_IER, save_ier);
1418 if (port->flags & UPF_FOURPORT)
1419 outb_p(save_ICP, ICP);
1421 if (uart_console(port))
1424 port->irq = (irq > 0) ? irq : 0;
1427 static void serial8250_stop_rx(struct uart_port *port)
1429 struct uart_8250_port *up = up_to_u8250p(port);
1431 serial8250_rpm_get(up);
1433 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1434 up->port.read_status_mask &= ~UART_LSR_DR;
1435 serial_port_out(port, UART_IER, up->ier);
1437 serial8250_rpm_put(up);
1441 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1442 * @p: uart 8250 port
1444 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1446 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1448 unsigned char mcr = serial8250_in_MCR(p);
1450 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1451 mcr |= UART_MCR_RTS;
1453 mcr &= ~UART_MCR_RTS;
1454 serial8250_out_MCR(p, mcr);
1457 * Empty the RX FIFO, we are not interested in anything
1458 * received during the half-duplex transmission.
1459 * Enable previously disabled RX interrupts.
1461 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1462 serial8250_clear_and_reinit_fifos(p);
1464 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1465 serial_port_out(&p->port, UART_IER, p->ier);
1468 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1470 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1472 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1474 struct uart_8250_port *p = em485->port;
1475 unsigned long flags;
1477 serial8250_rpm_get(p);
1478 spin_lock_irqsave(&p->port.lock, flags);
1479 if (em485->active_timer == &em485->stop_tx_timer) {
1480 p->rs485_stop_tx(p);
1481 em485->active_timer = NULL;
1482 em485->tx_stopped = true;
1484 spin_unlock_irqrestore(&p->port.lock, flags);
1485 serial8250_rpm_put(p);
1487 return HRTIMER_NORESTART;
1490 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1492 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1495 static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
1497 struct uart_8250_em485 *em485 = p->em485;
1499 stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
1502 * rs485_stop_tx() is going to set RTS according to config
1503 * AND flush RX FIFO if required.
1505 if (stop_delay > 0) {
1506 em485->active_timer = &em485->stop_tx_timer;
1507 hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL);
1509 p->rs485_stop_tx(p);
1510 em485->active_timer = NULL;
1511 em485->tx_stopped = true;
1515 static inline void __stop_tx(struct uart_8250_port *p)
1517 struct uart_8250_em485 *em485 = p->em485;
1520 u16 lsr = serial_lsr_in(p);
1523 if (!(lsr & UART_LSR_THRE))
1526 * To provide required timing and allow FIFO transfer,
1527 * __stop_tx_rs485() must be called only when both FIFO and
1528 * shift register are empty. The device driver should either
1529 * enable interrupt on TEMT or set UART_CAP_NOTEMT that will
1530 * enlarge stop_tx_timer by the tx time of one frame to cover
1531 * for emptying of the shift register.
1533 if (!(lsr & UART_LSR_TEMT)) {
1534 if (!(p->capabilities & UART_CAP_NOTEMT))
1537 * RTS might get deasserted too early with the normal
1538 * frame timing formula. It seems to suggest THRE might
1539 * get asserted already during tx of the stop bit
1540 * rather than after it is fully sent.
1541 * Roughly estimate 1 extra bit here with / 7.
1543 stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
1546 __stop_tx_rs485(p, stop_delay);
1549 if (serial8250_clear_THRI(p))
1550 serial8250_rpm_put_tx(p);
1553 static void serial8250_stop_tx(struct uart_port *port)
1555 struct uart_8250_port *up = up_to_u8250p(port);
1557 serial8250_rpm_get(up);
1561 * We really want to stop the transmitter from sending.
1563 if (port->type == PORT_16C950) {
1564 up->acr |= UART_ACR_TXDIS;
1565 serial_icr_write(up, UART_ACR, up->acr);
1567 serial8250_rpm_put(up);
1570 static inline void __start_tx(struct uart_port *port)
1572 struct uart_8250_port *up = up_to_u8250p(port);
1574 if (up->dma && !up->dma->tx_dma(up))
1577 if (serial8250_set_THRI(up)) {
1578 if (up->bugs & UART_BUG_TXEN) {
1579 u16 lsr = serial_lsr_in(up);
1581 if (lsr & UART_LSR_THRE)
1582 serial8250_tx_chars(up);
1587 * Re-enable the transmitter if we disabled it.
1589 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1590 up->acr &= ~UART_ACR_TXDIS;
1591 serial_icr_write(up, UART_ACR, up->acr);
1596 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1597 * @up: uart 8250 port
1599 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1600 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1601 * (Some chips use inverse semantics.) Further assumes that reception is
1602 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1603 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1605 void serial8250_em485_start_tx(struct uart_8250_port *up)
1607 unsigned char mcr = serial8250_in_MCR(up);
1609 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1610 serial8250_stop_rx(&up->port);
1612 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1613 mcr |= UART_MCR_RTS;
1615 mcr &= ~UART_MCR_RTS;
1616 serial8250_out_MCR(up, mcr);
1618 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1620 /* Returns false, if start_tx_timer was setup to defer TX start */
1621 static bool start_tx_rs485(struct uart_port *port)
1623 struct uart_8250_port *up = up_to_u8250p(port);
1624 struct uart_8250_em485 *em485 = up->em485;
1627 * While serial8250_em485_handle_stop_tx() is a noop if
1628 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1629 * the timer is still armed and triggers only after the current bunch of
1630 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1631 * So cancel the timer. There is still a theoretical race condition if
1632 * the timer is already running and only comes around to check for
1633 * em485->active_timer when &em485->stop_tx_timer is armed again.
1635 if (em485->active_timer == &em485->stop_tx_timer)
1636 hrtimer_try_to_cancel(&em485->stop_tx_timer);
1638 em485->active_timer = NULL;
1640 if (em485->tx_stopped) {
1641 em485->tx_stopped = false;
1643 up->rs485_start_tx(up);
1645 if (up->port.rs485.delay_rts_before_send > 0) {
1646 em485->active_timer = &em485->start_tx_timer;
1647 start_hrtimer_ms(&em485->start_tx_timer,
1648 up->port.rs485.delay_rts_before_send);
1656 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1658 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1660 struct uart_8250_port *p = em485->port;
1661 unsigned long flags;
1663 spin_lock_irqsave(&p->port.lock, flags);
1664 if (em485->active_timer == &em485->start_tx_timer) {
1665 __start_tx(&p->port);
1666 em485->active_timer = NULL;
1668 spin_unlock_irqrestore(&p->port.lock, flags);
1670 return HRTIMER_NORESTART;
1673 static void serial8250_start_tx(struct uart_port *port)
1675 struct uart_8250_port *up = up_to_u8250p(port);
1676 struct uart_8250_em485 *em485 = up->em485;
1678 if (!port->x_char && uart_circ_empty(&port->state->xmit))
1681 serial8250_rpm_get_tx(up);
1684 if ((em485->active_timer == &em485->start_tx_timer) ||
1685 !start_tx_rs485(port))
1691 static void serial8250_throttle(struct uart_port *port)
1693 port->throttle(port);
1696 static void serial8250_unthrottle(struct uart_port *port)
1698 port->unthrottle(port);
1701 static void serial8250_disable_ms(struct uart_port *port)
1703 struct uart_8250_port *up = up_to_u8250p(port);
1705 /* no MSR capabilities */
1706 if (up->bugs & UART_BUG_NOMSR)
1709 mctrl_gpio_disable_ms(up->gpios);
1711 up->ier &= ~UART_IER_MSI;
1712 serial_port_out(port, UART_IER, up->ier);
1715 static void serial8250_enable_ms(struct uart_port *port)
1717 struct uart_8250_port *up = up_to_u8250p(port);
1719 /* no MSR capabilities */
1720 if (up->bugs & UART_BUG_NOMSR)
1723 mctrl_gpio_enable_ms(up->gpios);
1725 up->ier |= UART_IER_MSI;
1727 serial8250_rpm_get(up);
1728 serial_port_out(port, UART_IER, up->ier);
1729 serial8250_rpm_put(up);
1732 void serial8250_read_char(struct uart_8250_port *up, u16 lsr)
1734 struct uart_port *port = &up->port;
1736 char flag = TTY_NORMAL;
1738 if (likely(lsr & UART_LSR_DR))
1739 ch = serial_in(up, UART_RX);
1742 * Intel 82571 has a Serial Over Lan device that will
1743 * set UART_LSR_BI without setting UART_LSR_DR when
1744 * it receives a break. To avoid reading from the
1745 * receive buffer without UART_LSR_DR bit set, we
1746 * just force the read character to be 0
1752 lsr |= up->lsr_saved_flags;
1753 up->lsr_saved_flags = 0;
1755 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1756 if (lsr & UART_LSR_BI) {
1757 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1760 * We do the SysRQ and SAK checking
1761 * here because otherwise the break
1762 * may get masked by ignore_status_mask
1763 * or read_status_mask.
1765 if (uart_handle_break(port))
1767 } else if (lsr & UART_LSR_PE)
1768 port->icount.parity++;
1769 else if (lsr & UART_LSR_FE)
1770 port->icount.frame++;
1771 if (lsr & UART_LSR_OE)
1772 port->icount.overrun++;
1775 * Mask off conditions which should be ignored.
1777 lsr &= port->read_status_mask;
1779 if (lsr & UART_LSR_BI) {
1780 dev_dbg(port->dev, "handling break\n");
1782 } else if (lsr & UART_LSR_PE)
1784 else if (lsr & UART_LSR_FE)
1787 if (uart_prepare_sysrq_char(port, ch))
1790 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1792 EXPORT_SYMBOL_GPL(serial8250_read_char);
1795 * serial8250_rx_chars - Read characters. The first LSR value must be passed in.
1797 * Returns LSR bits. The caller should rely only on non-Rx related LSR bits
1798 * (such as THRE) because the LSR value might come from an already consumed
1801 u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr)
1803 struct uart_port *port = &up->port;
1804 int max_count = 256;
1807 serial8250_read_char(up, lsr);
1808 if (--max_count == 0)
1810 lsr = serial_in(up, UART_LSR);
1811 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1813 tty_flip_buffer_push(&port->state->port);
1816 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1818 void serial8250_tx_chars(struct uart_8250_port *up)
1820 struct uart_port *port = &up->port;
1821 struct circ_buf *xmit = &port->state->xmit;
1825 uart_xchar_out(port, UART_TX);
1828 if (uart_tx_stopped(port)) {
1829 serial8250_stop_tx(port);
1832 if (uart_circ_empty(xmit)) {
1837 count = up->tx_loadsz;
1839 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1840 if (up->bugs & UART_BUG_TXRACE) {
1842 * The Aspeed BMC virtual UARTs have a bug where data
1843 * may get stuck in the BMC's Tx FIFO from bursts of
1844 * writes on the APB interface.
1846 * Delay back-to-back writes by a read cycle to avoid
1847 * stalling the VUART. Read a register that won't have
1848 * side-effects and discard the result.
1850 serial_in(up, UART_SCR);
1852 uart_xmit_advance(port, 1);
1853 if (uart_circ_empty(xmit))
1855 if ((up->capabilities & UART_CAP_HFIFO) &&
1856 !uart_lsr_tx_empty(serial_in(up, UART_LSR)))
1858 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1859 if ((up->capabilities & UART_CAP_MINI) &&
1860 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1862 } while (--count > 0);
1864 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1865 uart_write_wakeup(port);
1868 * With RPM enabled, we have to wait until the FIFO is empty before the
1869 * HW can go idle. So we get here once again with empty FIFO and disable
1870 * the interrupt and RPM in __stop_tx()
1872 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1875 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1877 /* Caller holds uart port lock */
1878 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1880 struct uart_port *port = &up->port;
1881 unsigned int status = serial_in(up, UART_MSR);
1883 status |= up->msr_saved_flags;
1884 up->msr_saved_flags = 0;
1885 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1886 port->state != NULL) {
1887 if (status & UART_MSR_TERI)
1889 if (status & UART_MSR_DDSR)
1891 if (status & UART_MSR_DDCD)
1892 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1893 if (status & UART_MSR_DCTS)
1894 uart_handle_cts_change(port, status & UART_MSR_CTS);
1896 wake_up_interruptible(&port->state->port.delta_msr_wait);
1901 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1903 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1905 switch (iir & 0x3f) {
1908 * Postpone DMA or not decision to IIR_RDI or IIR_RX_TIMEOUT
1909 * because it's impossible to do an informed decision about
1910 * that with IIR_THRI.
1912 * This also fixes one known DMA Rx corruption issue where
1913 * DR is asserted but DMA Rx only gets a corrupted zero byte
1918 if (!up->dma->rx_running)
1922 case UART_IIR_RX_TIMEOUT:
1923 serial8250_rx_dma_flush(up);
1926 return up->dma->rx_dma(up);
1930 * This handles the interrupt from one port.
1932 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1934 struct uart_8250_port *up = up_to_u8250p(port);
1935 bool skip_rx = false;
1936 unsigned long flags;
1939 if (iir & UART_IIR_NO_INT)
1942 spin_lock_irqsave(&port->lock, flags);
1944 status = serial_lsr_in(up);
1947 * If port is stopped and there are no error conditions in the
1948 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1949 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1950 * control when FIFO occupancy reaches preset threshold, thus
1951 * halting RX. This only works when auto HW flow control is
1954 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1955 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1956 !(port->read_status_mask & UART_LSR_DR))
1959 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1960 if (!up->dma || handle_rx_dma(up, iir))
1961 status = serial8250_rx_chars(up, status);
1963 serial8250_modem_status(up);
1964 if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
1965 if (!up->dma || up->dma->tx_err)
1966 serial8250_tx_chars(up);
1967 else if (!up->dma->tx_running)
1971 uart_unlock_and_check_sysrq_irqrestore(port, flags);
1975 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1977 static int serial8250_default_handle_irq(struct uart_port *port)
1979 struct uart_8250_port *up = up_to_u8250p(port);
1983 serial8250_rpm_get(up);
1985 iir = serial_port_in(port, UART_IIR);
1986 ret = serial8250_handle_irq(port, iir);
1988 serial8250_rpm_put(up);
1993 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1994 * have a programmable TX threshold that triggers the THRE interrupt in
1995 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1996 * has space available. Load it up with tx_loadsz bytes.
1998 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
2000 unsigned long flags;
2001 unsigned int iir = serial_port_in(port, UART_IIR);
2003 /* TX Threshold IRQ triggered so load up FIFO */
2004 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
2005 struct uart_8250_port *up = up_to_u8250p(port);
2007 spin_lock_irqsave(&port->lock, flags);
2008 serial8250_tx_chars(up);
2009 spin_unlock_irqrestore(&port->lock, flags);
2012 iir = serial_port_in(port, UART_IIR);
2013 return serial8250_handle_irq(port, iir);
2016 static unsigned int serial8250_tx_empty(struct uart_port *port)
2018 struct uart_8250_port *up = up_to_u8250p(port);
2019 unsigned int result = 0;
2020 unsigned long flags;
2022 serial8250_rpm_get(up);
2024 spin_lock_irqsave(&port->lock, flags);
2025 if (!serial8250_tx_dma_running(up) && uart_lsr_tx_empty(serial_lsr_in(up)))
2026 result = TIOCSER_TEMT;
2027 spin_unlock_irqrestore(&port->lock, flags);
2029 serial8250_rpm_put(up);
2034 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
2036 struct uart_8250_port *up = up_to_u8250p(port);
2037 unsigned int status;
2040 serial8250_rpm_get(up);
2041 status = serial8250_modem_status(up);
2042 serial8250_rpm_put(up);
2044 val = serial8250_MSR_to_TIOCM(status);
2046 return mctrl_gpio_get(up->gpios, &val);
2050 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
2052 static unsigned int serial8250_get_mctrl(struct uart_port *port)
2054 if (port->get_mctrl)
2055 return port->get_mctrl(port);
2056 return serial8250_do_get_mctrl(port);
2059 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
2061 struct uart_8250_port *up = up_to_u8250p(port);
2064 mcr = serial8250_TIOCM_to_MCR(mctrl);
2068 serial8250_out_MCR(up, mcr);
2070 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2072 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2074 if (port->rs485.flags & SER_RS485_ENABLED)
2077 if (port->set_mctrl)
2078 port->set_mctrl(port, mctrl);
2080 serial8250_do_set_mctrl(port, mctrl);
2083 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2085 struct uart_8250_port *up = up_to_u8250p(port);
2086 unsigned long flags;
2088 serial8250_rpm_get(up);
2089 spin_lock_irqsave(&port->lock, flags);
2090 if (break_state == -1)
2091 up->lcr |= UART_LCR_SBC;
2093 up->lcr &= ~UART_LCR_SBC;
2094 serial_port_out(port, UART_LCR, up->lcr);
2095 spin_unlock_irqrestore(&port->lock, flags);
2096 serial8250_rpm_put(up);
2099 static void wait_for_lsr(struct uart_8250_port *up, int bits)
2101 unsigned int status, tmout = 10000;
2103 /* Wait up to 10ms for the character(s) to be sent. */
2105 status = serial_lsr_in(up);
2107 if ((status & bits) == bits)
2112 touch_nmi_watchdog();
2117 * Wait for transmitter & holding register to empty
2119 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2123 wait_for_lsr(up, bits);
2125 /* Wait up to 1s for flow control if necessary */
2126 if (up->port.flags & UPF_CONS_FLOW) {
2127 for (tmout = 1000000; tmout; tmout--) {
2128 unsigned int msr = serial_in(up, UART_MSR);
2129 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2130 if (msr & UART_MSR_CTS)
2133 touch_nmi_watchdog();
2138 #ifdef CONFIG_CONSOLE_POLL
2140 * Console polling routines for writing and reading from the uart while
2141 * in an interrupt or debug context.
2144 static int serial8250_get_poll_char(struct uart_port *port)
2146 struct uart_8250_port *up = up_to_u8250p(port);
2150 serial8250_rpm_get(up);
2152 lsr = serial_port_in(port, UART_LSR);
2154 if (!(lsr & UART_LSR_DR)) {
2155 status = NO_POLL_CHAR;
2159 status = serial_port_in(port, UART_RX);
2161 serial8250_rpm_put(up);
2166 static void serial8250_put_poll_char(struct uart_port *port,
2170 struct uart_8250_port *up = up_to_u8250p(port);
2172 serial8250_rpm_get(up);
2174 * First save the IER then disable the interrupts
2176 ier = serial_port_in(port, UART_IER);
2177 serial8250_clear_IER(up);
2179 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2181 * Send the character out.
2183 serial_port_out(port, UART_TX, c);
2186 * Finally, wait for transmitter to become empty
2187 * and restore the IER
2189 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2190 serial_port_out(port, UART_IER, ier);
2191 serial8250_rpm_put(up);
2194 #endif /* CONFIG_CONSOLE_POLL */
2196 int serial8250_do_startup(struct uart_port *port)
2198 struct uart_8250_port *up = up_to_u8250p(port);
2199 unsigned long flags;
2204 if (!port->fifosize)
2205 port->fifosize = uart_config[port->type].fifo_size;
2207 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2208 if (!up->capabilities)
2209 up->capabilities = uart_config[port->type].flags;
2212 if (port->iotype != up->cur_iotype)
2213 set_io_from_upio(port);
2215 serial8250_rpm_get(up);
2216 if (port->type == PORT_16C950) {
2217 /* Wake up and initialize UART */
2219 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2220 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2221 serial_port_out(port, UART_IER, 0);
2222 serial_port_out(port, UART_LCR, 0);
2223 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2224 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2225 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2226 serial_port_out(port, UART_LCR, 0);
2229 if (port->type == PORT_DA830) {
2230 /* Reset the port */
2231 serial_port_out(port, UART_IER, 0);
2232 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2235 /* Enable Tx, Rx and free run mode */
2236 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2237 UART_DA830_PWREMU_MGMT_UTRST |
2238 UART_DA830_PWREMU_MGMT_URRST |
2239 UART_DA830_PWREMU_MGMT_FREE);
2242 if (port->type == PORT_NPCM) {
2244 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2245 * register). Enable it, and set TIOC (timeout interrupt
2246 * comparator) to be 0x20 for correct operation.
2248 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2251 #ifdef CONFIG_SERIAL_8250_RSA
2253 * If this is an RSA port, see if we can kick it up to the
2254 * higher speed clock.
2260 * Clear the FIFO buffers and disable them.
2261 * (they will be reenabled in set_termios())
2263 serial8250_clear_fifos(up);
2266 * Clear the interrupt registers.
2268 serial_port_in(port, UART_LSR);
2269 serial_port_in(port, UART_RX);
2270 serial_port_in(port, UART_IIR);
2271 serial_port_in(port, UART_MSR);
2274 * At this point, there's no way the LSR could still be 0xff;
2275 * if it is, then bail out, because there's likely no UART
2278 if (!(port->flags & UPF_BUGGY_UART) &&
2279 (serial_port_in(port, UART_LSR) == 0xff)) {
2280 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2286 * For a XR16C850, we need to set the trigger levels
2288 if (port->type == PORT_16850) {
2291 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2293 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2294 serial_port_out(port, UART_FCTR,
2295 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2296 serial_port_out(port, UART_TRG, UART_TRG_96);
2297 serial_port_out(port, UART_FCTR,
2298 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2299 serial_port_out(port, UART_TRG, UART_TRG_96);
2301 serial_port_out(port, UART_LCR, 0);
2305 * For the Altera 16550 variants, set TX threshold trigger level.
2307 if (((port->type == PORT_ALTR_16550_F32) ||
2308 (port->type == PORT_ALTR_16550_F64) ||
2309 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2310 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2311 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2312 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2314 serial_port_out(port, UART_ALTR_AFR,
2315 UART_ALTR_EN_TXFIFO_LW);
2316 serial_port_out(port, UART_ALTR_TX_LOW,
2317 port->fifosize - up->tx_loadsz);
2318 port->handle_irq = serial8250_tx_threshold_handle_irq;
2322 /* Check if we need to have shared IRQs */
2323 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2324 up->port.irqflags |= IRQF_SHARED;
2326 retval = up->ops->setup_irq(up);
2330 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2333 if (port->irqflags & IRQF_SHARED)
2334 disable_irq_nosync(port->irq);
2337 * Test for UARTs that do not reassert THRE when the
2338 * transmitter is idle and the interrupt has already
2339 * been cleared. Real 16550s should always reassert
2340 * this interrupt whenever the transmitter is idle and
2341 * the interrupt is enabled. Delays are necessary to
2342 * allow register changes to become visible.
2344 spin_lock_irqsave(&port->lock, flags);
2346 wait_for_xmitr(up, UART_LSR_THRE);
2347 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2348 udelay(1); /* allow THRE to set */
2349 iir1 = serial_port_in(port, UART_IIR);
2350 serial_port_out(port, UART_IER, 0);
2351 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2352 udelay(1); /* allow a working UART time to re-assert THRE */
2353 iir = serial_port_in(port, UART_IIR);
2354 serial_port_out(port, UART_IER, 0);
2356 spin_unlock_irqrestore(&port->lock, flags);
2358 if (port->irqflags & IRQF_SHARED)
2359 enable_irq(port->irq);
2362 * If the interrupt is not reasserted, or we otherwise
2363 * don't trust the iir, setup a timer to kick the UART
2364 * on a regular basis.
2366 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2367 up->port.flags & UPF_BUG_THRE) {
2368 up->bugs |= UART_BUG_THRE;
2372 up->ops->setup_timer(up);
2375 * Now, initialize the UART
2377 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2379 spin_lock_irqsave(&port->lock, flags);
2380 if (up->port.flags & UPF_FOURPORT) {
2382 up->port.mctrl |= TIOCM_OUT1;
2385 * Most PC uarts need OUT2 raised to enable interrupts.
2388 up->port.mctrl |= TIOCM_OUT2;
2390 serial8250_set_mctrl(port, port->mctrl);
2393 * Serial over Lan (SoL) hack:
2394 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2395 * used for Serial Over Lan. Those chips take a longer time than a
2396 * normal serial device to signalize that a transmission data was
2397 * queued. Due to that, the above test generally fails. One solution
2398 * would be to delay the reading of iir. However, this is not
2399 * reliable, since the timeout is variable. So, let's just don't
2400 * test if we receive TX irq. This way, we'll never enable
2403 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2404 goto dont_test_tx_en;
2407 * Do a quick test to see if we receive an interrupt when we enable
2410 serial_port_out(port, UART_IER, UART_IER_THRI);
2411 lsr = serial_port_in(port, UART_LSR);
2412 iir = serial_port_in(port, UART_IIR);
2413 serial_port_out(port, UART_IER, 0);
2415 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2416 if (!(up->bugs & UART_BUG_TXEN)) {
2417 up->bugs |= UART_BUG_TXEN;
2418 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2421 up->bugs &= ~UART_BUG_TXEN;
2425 spin_unlock_irqrestore(&port->lock, flags);
2428 * Clear the interrupt registers again for luck, and clear the
2429 * saved flags to avoid getting false values from polling
2430 * routines or the previous session.
2432 serial_port_in(port, UART_LSR);
2433 serial_port_in(port, UART_RX);
2434 serial_port_in(port, UART_IIR);
2435 serial_port_in(port, UART_MSR);
2436 up->lsr_saved_flags = 0;
2437 up->msr_saved_flags = 0;
2440 * Request DMA channels for both RX and TX.
2443 const char *msg = NULL;
2445 if (uart_console(port))
2446 msg = "forbid DMA for kernel console";
2447 else if (serial8250_request_dma(up))
2448 msg = "failed to request DMA";
2450 dev_warn_ratelimited(port->dev, "%s\n", msg);
2456 * Set the IER shadow for rx interrupts but defer actual interrupt
2457 * enable until after the FIFOs are enabled; otherwise, an already-
2458 * active sender can swamp the interrupt handler with "too much work".
2460 up->ier = UART_IER_RLSI | UART_IER_RDI;
2462 if (port->flags & UPF_FOURPORT) {
2465 * Enable interrupts on the AST Fourport board
2467 icp = (port->iobase & 0xfe0) | 0x01f;
2473 serial8250_rpm_put(up);
2476 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2478 static int serial8250_startup(struct uart_port *port)
2481 return port->startup(port);
2482 return serial8250_do_startup(port);
2485 void serial8250_do_shutdown(struct uart_port *port)
2487 struct uart_8250_port *up = up_to_u8250p(port);
2488 unsigned long flags;
2490 serial8250_rpm_get(up);
2492 * Disable interrupts from this port
2494 spin_lock_irqsave(&port->lock, flags);
2496 serial_port_out(port, UART_IER, 0);
2497 spin_unlock_irqrestore(&port->lock, flags);
2499 synchronize_irq(port->irq);
2502 serial8250_release_dma(up);
2504 spin_lock_irqsave(&port->lock, flags);
2505 if (port->flags & UPF_FOURPORT) {
2506 /* reset interrupts on the AST Fourport board */
2507 inb((port->iobase & 0xfe0) | 0x1f);
2508 port->mctrl |= TIOCM_OUT1;
2510 port->mctrl &= ~TIOCM_OUT2;
2512 serial8250_set_mctrl(port, port->mctrl);
2513 spin_unlock_irqrestore(&port->lock, flags);
2516 * Disable break condition and FIFOs
2518 serial_port_out(port, UART_LCR,
2519 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2520 serial8250_clear_fifos(up);
2522 #ifdef CONFIG_SERIAL_8250_RSA
2524 * Reset the RSA board back to 115kbps compat mode.
2530 * Read data port to reset things, and then unlink from
2533 serial_port_in(port, UART_RX);
2534 serial8250_rpm_put(up);
2536 up->ops->release_irq(up);
2538 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2540 static void serial8250_shutdown(struct uart_port *port)
2543 port->shutdown(port);
2545 serial8250_do_shutdown(port);
2548 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2549 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2552 struct uart_port *port = &up->port;
2554 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2557 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2561 upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2562 struct uart_8250_port *up = up_to_u8250p(port);
2566 * Handle magic divisors for baud rates above baud_base on SMSC
2567 * Super I/O chips. We clamp custom rates from clk/6 and clk/12
2568 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
2569 * magic divisors actually reprogram the baud rate generator's
2570 * reference clock derived from chips's 14.318MHz clock input.
2572 * Documentation claims that with these magic divisors the base
2573 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2574 * for the extra baud rates of 460800bps and 230400bps rather
2575 * than the usual base frequency of 1.8462MHz. However empirical
2576 * evidence contradicts that.
2578 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2579 * effectively used as a clock prescaler selection bit for the
2580 * base frequency of 7.3728MHz, always used. If set to 0, then
2581 * the base frequency is divided by 4 for use by the Baud Rate
2582 * Generator, for the usual arrangement where the value of 1 of
2583 * the divisor produces the baud rate of 115200bps. Conversely,
2584 * if set to 1 and high-speed operation has been enabled with the
2585 * Serial Port Mode Register in the Device Configuration Space,
2586 * then the base frequency is supplied directly to the Baud Rate
2587 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2588 * 0x8004, etc. the respective baud rates produced are 460800bps,
2589 * 230400bps, 153600bps, 115200bps, etc.
2591 * In all cases only low 15 bits of the divisor are used to divide
2592 * the baud base and therefore 32767 is the maximum divisor value
2593 * possible, even though documentation says that the programmable
2594 * Baud Rate Generator is capable of dividing the internal PLL
2595 * clock by any divisor from 1 to 65535.
2597 if (magic_multiplier && baud >= port->uartclk / 6)
2599 else if (magic_multiplier && baud >= port->uartclk / 12)
2601 else if (up->port.type == PORT_NPCM)
2602 quot = npcm_get_divisor(up, baud);
2604 quot = uart_get_divisor(port, baud);
2607 * Oxford Semi 952 rev B workaround
2609 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2615 static unsigned int serial8250_get_divisor(struct uart_port *port,
2619 if (port->get_divisor)
2620 return port->get_divisor(port, baud, frac);
2622 return serial8250_do_get_divisor(port, baud, frac);
2625 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2630 cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2632 if (c_cflag & CSTOPB)
2633 cval |= UART_LCR_STOP;
2634 if (c_cflag & PARENB) {
2635 cval |= UART_LCR_PARITY;
2636 if (up->bugs & UART_BUG_PARITY)
2637 up->fifo_bug = true;
2639 if (!(c_cflag & PARODD))
2640 cval |= UART_LCR_EPAR;
2641 if (c_cflag & CMSPAR)
2642 cval |= UART_LCR_SPAR;
2647 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2648 unsigned int quot, unsigned int quot_frac)
2650 struct uart_8250_port *up = up_to_u8250p(port);
2652 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2653 if (is_omap1510_8250(up)) {
2654 if (baud == 115200) {
2656 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2658 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2662 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2663 * otherwise just set DLAB
2665 if (up->capabilities & UART_NATSEMI)
2666 serial_port_out(port, UART_LCR, 0xe0);
2668 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2670 serial_dl_write(up, quot);
2672 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2674 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2675 unsigned int quot, unsigned int quot_frac)
2677 if (port->set_divisor)
2678 port->set_divisor(port, baud, quot, quot_frac);
2680 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2683 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2684 struct ktermios *termios,
2685 const struct ktermios *old)
2687 unsigned int tolerance = port->uartclk / 100;
2692 * Handle magic divisors for baud rates above baud_base on SMSC
2693 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2694 * disable divisor values beyond 32767, which are unavailable.
2696 if (port->flags & UPF_MAGIC_MULTIPLIER) {
2697 min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2698 max = (port->uartclk + tolerance) / 4;
2700 min = port->uartclk / 16 / UART_DIV_MAX;
2701 max = (port->uartclk + tolerance) / 16;
2705 * Ask the core to calculate the divisor for us.
2706 * Allow 1% tolerance at the upper limit so uart clks marginally
2707 * slower than nominal still match standard baud rates without
2708 * causing transmission errors.
2710 return uart_get_baud_rate(port, termios, old, min, max);
2714 * Note in order to avoid the tty port mutex deadlock don't use the next method
2715 * within the uart port callbacks. Primarily it's supposed to be utilized to
2716 * handle a sudden reference clock rate change.
2718 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2720 struct uart_8250_port *up = up_to_u8250p(port);
2721 struct tty_port *tport = &port->state->port;
2722 unsigned int baud, quot, frac = 0;
2723 struct ktermios *termios;
2724 struct tty_struct *tty;
2725 unsigned long flags;
2727 tty = tty_port_tty_get(tport);
2729 mutex_lock(&tport->mutex);
2730 port->uartclk = uartclk;
2731 mutex_unlock(&tport->mutex);
2735 down_write(&tty->termios_rwsem);
2736 mutex_lock(&tport->mutex);
2738 if (port->uartclk == uartclk)
2741 port->uartclk = uartclk;
2743 if (!tty_port_initialized(tport))
2746 termios = &tty->termios;
2748 baud = serial8250_get_baud_rate(port, termios, NULL);
2749 quot = serial8250_get_divisor(port, baud, &frac);
2751 serial8250_rpm_get(up);
2752 spin_lock_irqsave(&port->lock, flags);
2754 uart_update_timeout(port, termios->c_cflag, baud);
2756 serial8250_set_divisor(port, baud, quot, frac);
2757 serial_port_out(port, UART_LCR, up->lcr);
2759 spin_unlock_irqrestore(&port->lock, flags);
2760 serial8250_rpm_put(up);
2763 mutex_unlock(&tport->mutex);
2764 up_write(&tty->termios_rwsem);
2767 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2770 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2771 const struct ktermios *old)
2773 struct uart_8250_port *up = up_to_u8250p(port);
2775 unsigned long flags;
2776 unsigned int baud, quot, frac = 0;
2778 if (up->capabilities & UART_CAP_MINI) {
2779 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2780 if ((termios->c_cflag & CSIZE) == CS5 ||
2781 (termios->c_cflag & CSIZE) == CS6)
2782 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2784 cval = serial8250_compute_lcr(up, termios->c_cflag);
2786 baud = serial8250_get_baud_rate(port, termios, old);
2787 quot = serial8250_get_divisor(port, baud, &frac);
2790 * Ok, we're now changing the port state. Do it with
2791 * interrupts disabled.
2793 serial8250_rpm_get(up);
2794 spin_lock_irqsave(&port->lock, flags);
2796 up->lcr = cval; /* Save computed LCR */
2798 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2799 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2800 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2801 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2802 up->fcr |= UART_FCR_TRIGGER_1;
2807 * MCR-based auto flow control. When AFE is enabled, RTS will be
2808 * deasserted when the receive FIFO contains more characters than
2809 * the trigger, or the MCR RTS bit is cleared.
2811 if (up->capabilities & UART_CAP_AFE) {
2812 up->mcr &= ~UART_MCR_AFE;
2813 if (termios->c_cflag & CRTSCTS)
2814 up->mcr |= UART_MCR_AFE;
2818 * Update the per-port timeout.
2820 uart_update_timeout(port, termios->c_cflag, baud);
2822 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2823 if (termios->c_iflag & INPCK)
2824 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2825 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2826 port->read_status_mask |= UART_LSR_BI;
2829 * Characters to ignore
2831 port->ignore_status_mask = 0;
2832 if (termios->c_iflag & IGNPAR)
2833 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2834 if (termios->c_iflag & IGNBRK) {
2835 port->ignore_status_mask |= UART_LSR_BI;
2837 * If we're ignoring parity and break indicators,
2838 * ignore overruns too (for real raw support).
2840 if (termios->c_iflag & IGNPAR)
2841 port->ignore_status_mask |= UART_LSR_OE;
2845 * ignore all characters if CREAD is not set
2847 if ((termios->c_cflag & CREAD) == 0)
2848 port->ignore_status_mask |= UART_LSR_DR;
2851 * CTS flow control flag and modem status interrupts
2853 up->ier &= ~UART_IER_MSI;
2854 if (!(up->bugs & UART_BUG_NOMSR) &&
2855 UART_ENABLE_MS(&up->port, termios->c_cflag))
2856 up->ier |= UART_IER_MSI;
2857 if (up->capabilities & UART_CAP_UUE)
2858 up->ier |= UART_IER_UUE;
2859 if (up->capabilities & UART_CAP_RTOIE)
2860 up->ier |= UART_IER_RTOIE;
2862 serial_port_out(port, UART_IER, up->ier);
2864 if (up->capabilities & UART_CAP_EFR) {
2865 unsigned char efr = 0;
2867 * TI16C752/Startech hardware flow control. FIXME:
2868 * - TI16C752 requires control thresholds to be set.
2869 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2871 if (termios->c_cflag & CRTSCTS)
2872 efr |= UART_EFR_CTS;
2874 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2875 if (port->flags & UPF_EXAR_EFR)
2876 serial_port_out(port, UART_XR_EFR, efr);
2878 serial_port_out(port, UART_EFR, efr);
2881 serial8250_set_divisor(port, baud, quot, frac);
2884 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2885 * is written without DLAB set, this mode will be disabled.
2887 if (port->type == PORT_16750)
2888 serial_port_out(port, UART_FCR, up->fcr);
2890 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2891 if (port->type != PORT_16750) {
2892 /* emulated UARTs (Lucent Venus 167x) need two steps */
2893 if (up->fcr & UART_FCR_ENABLE_FIFO)
2894 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2895 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2897 serial8250_set_mctrl(port, port->mctrl);
2898 spin_unlock_irqrestore(&port->lock, flags);
2899 serial8250_rpm_put(up);
2901 /* Don't rewrite B0 */
2902 if (tty_termios_baud_rate(termios))
2903 tty_termios_encode_baud_rate(termios, baud, baud);
2905 EXPORT_SYMBOL(serial8250_do_set_termios);
2908 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2909 const struct ktermios *old)
2911 if (port->set_termios)
2912 port->set_termios(port, termios, old);
2914 serial8250_do_set_termios(port, termios, old);
2917 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2919 if (termios->c_line == N_PPS) {
2920 port->flags |= UPF_HARDPPS_CD;
2921 spin_lock_irq(&port->lock);
2922 serial8250_enable_ms(port);
2923 spin_unlock_irq(&port->lock);
2925 port->flags &= ~UPF_HARDPPS_CD;
2926 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2927 spin_lock_irq(&port->lock);
2928 serial8250_disable_ms(port);
2929 spin_unlock_irq(&port->lock);
2933 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2936 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2938 if (port->set_ldisc)
2939 port->set_ldisc(port, termios);
2941 serial8250_do_set_ldisc(port, termios);
2944 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2945 unsigned int oldstate)
2947 struct uart_8250_port *p = up_to_u8250p(port);
2949 serial8250_set_sleep(p, state != 0);
2951 EXPORT_SYMBOL(serial8250_do_pm);
2954 serial8250_pm(struct uart_port *port, unsigned int state,
2955 unsigned int oldstate)
2958 port->pm(port, state, oldstate);
2960 serial8250_do_pm(port, state, oldstate);
2963 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2965 if (pt->port.mapsize)
2966 return pt->port.mapsize;
2967 if (pt->port.iotype == UPIO_AU) {
2968 if (pt->port.type == PORT_RT2880)
2972 if (is_omap1_8250(pt))
2973 return 0x16 << pt->port.regshift;
2975 return 8 << pt->port.regshift;
2979 * Resource handling.
2981 static int serial8250_request_std_resource(struct uart_8250_port *up)
2983 unsigned int size = serial8250_port_size(up);
2984 struct uart_port *port = &up->port;
2987 switch (port->iotype) {
2994 if (!port->mapbase) {
2999 if (!request_mem_region(port->mapbase, size, "serial")) {
3004 if (port->flags & UPF_IOREMAP) {
3005 port->membase = ioremap(port->mapbase, size);
3006 if (!port->membase) {
3007 release_mem_region(port->mapbase, size);
3015 if (!request_region(port->iobase, size, "serial"))
3022 static void serial8250_release_std_resource(struct uart_8250_port *up)
3024 unsigned int size = serial8250_port_size(up);
3025 struct uart_port *port = &up->port;
3027 switch (port->iotype) {
3037 if (port->flags & UPF_IOREMAP) {
3038 iounmap(port->membase);
3039 port->membase = NULL;
3042 release_mem_region(port->mapbase, size);
3047 release_region(port->iobase, size);
3052 static void serial8250_release_port(struct uart_port *port)
3054 struct uart_8250_port *up = up_to_u8250p(port);
3056 serial8250_release_std_resource(up);
3059 static int serial8250_request_port(struct uart_port *port)
3061 struct uart_8250_port *up = up_to_u8250p(port);
3063 return serial8250_request_std_resource(up);
3066 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
3068 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3069 unsigned char bytes;
3071 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3073 return bytes ? bytes : -EOPNOTSUPP;
3076 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3078 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3081 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3084 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3085 if (bytes < conf_type->rxtrig_bytes[i])
3086 /* Use the nearest lower value */
3087 return (--i) << UART_FCR_R_TRIG_SHIFT;
3090 return UART_FCR_R_TRIG_11;
3093 static int do_get_rxtrig(struct tty_port *port)
3095 struct uart_state *state = container_of(port, struct uart_state, port);
3096 struct uart_port *uport = state->uart_port;
3097 struct uart_8250_port *up = up_to_u8250p(uport);
3099 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3102 return fcr_get_rxtrig_bytes(up);
3105 static int do_serial8250_get_rxtrig(struct tty_port *port)
3109 mutex_lock(&port->mutex);
3110 rxtrig_bytes = do_get_rxtrig(port);
3111 mutex_unlock(&port->mutex);
3113 return rxtrig_bytes;
3116 static ssize_t rx_trig_bytes_show(struct device *dev,
3117 struct device_attribute *attr, char *buf)
3119 struct tty_port *port = dev_get_drvdata(dev);
3122 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3123 if (rxtrig_bytes < 0)
3124 return rxtrig_bytes;
3126 return sysfs_emit(buf, "%d\n", rxtrig_bytes);
3129 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3131 struct uart_state *state = container_of(port, struct uart_state, port);
3132 struct uart_port *uport = state->uart_port;
3133 struct uart_8250_port *up = up_to_u8250p(uport);
3136 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3140 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3144 serial8250_clear_fifos(up);
3145 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3146 up->fcr |= (unsigned char)rxtrig;
3147 serial_out(up, UART_FCR, up->fcr);
3151 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3155 mutex_lock(&port->mutex);
3156 ret = do_set_rxtrig(port, bytes);
3157 mutex_unlock(&port->mutex);
3162 static ssize_t rx_trig_bytes_store(struct device *dev,
3163 struct device_attribute *attr, const char *buf, size_t count)
3165 struct tty_port *port = dev_get_drvdata(dev);
3166 unsigned char bytes;
3172 ret = kstrtou8(buf, 10, &bytes);
3176 ret = do_serial8250_set_rxtrig(port, bytes);
3183 static DEVICE_ATTR_RW(rx_trig_bytes);
3185 static struct attribute *serial8250_dev_attrs[] = {
3186 &dev_attr_rx_trig_bytes.attr,
3190 static struct attribute_group serial8250_dev_attr_group = {
3191 .attrs = serial8250_dev_attrs,
3194 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3196 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3198 if (conf_type->rxtrig_bytes[0])
3199 up->port.attr_group = &serial8250_dev_attr_group;
3202 static void serial8250_config_port(struct uart_port *port, int flags)
3204 struct uart_8250_port *up = up_to_u8250p(port);
3208 * Find the region that we can probe for. This in turn
3209 * tells us whether we can probe for the type of port.
3211 ret = serial8250_request_std_resource(up);
3215 if (port->iotype != up->cur_iotype)
3216 set_io_from_upio(port);
3218 if (flags & UART_CONFIG_TYPE)
3221 /* if access method is AU, it is a 16550 with a quirk */
3222 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
3223 up->bugs |= UART_BUG_NOMSR;
3225 /* HW bugs may trigger IRQ while IIR == NO_INT */
3226 if (port->type == PORT_TEGRA)
3227 up->bugs |= UART_BUG_NOMSR;
3229 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3232 if (port->type == PORT_UNKNOWN)
3233 serial8250_release_std_resource(up);
3235 register_dev_spec_attr_grp(up);
3236 up->fcr = uart_config[up->port.type].fcr;
3240 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3242 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3243 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3244 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3245 ser->type == PORT_STARTECH)
3250 static const char *serial8250_type(struct uart_port *port)
3252 int type = port->type;
3254 if (type >= ARRAY_SIZE(uart_config))
3256 return uart_config[type].name;
3259 static const struct uart_ops serial8250_pops = {
3260 .tx_empty = serial8250_tx_empty,
3261 .set_mctrl = serial8250_set_mctrl,
3262 .get_mctrl = serial8250_get_mctrl,
3263 .stop_tx = serial8250_stop_tx,
3264 .start_tx = serial8250_start_tx,
3265 .throttle = serial8250_throttle,
3266 .unthrottle = serial8250_unthrottle,
3267 .stop_rx = serial8250_stop_rx,
3268 .enable_ms = serial8250_enable_ms,
3269 .break_ctl = serial8250_break_ctl,
3270 .startup = serial8250_startup,
3271 .shutdown = serial8250_shutdown,
3272 .set_termios = serial8250_set_termios,
3273 .set_ldisc = serial8250_set_ldisc,
3274 .pm = serial8250_pm,
3275 .type = serial8250_type,
3276 .release_port = serial8250_release_port,
3277 .request_port = serial8250_request_port,
3278 .config_port = serial8250_config_port,
3279 .verify_port = serial8250_verify_port,
3280 #ifdef CONFIG_CONSOLE_POLL
3281 .poll_get_char = serial8250_get_poll_char,
3282 .poll_put_char = serial8250_put_poll_char,
3286 void serial8250_init_port(struct uart_8250_port *up)
3288 struct uart_port *port = &up->port;
3290 spin_lock_init(&port->lock);
3291 port->ops = &serial8250_pops;
3292 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3294 up->cur_iotype = 0xFF;
3296 EXPORT_SYMBOL_GPL(serial8250_init_port);
3298 void serial8250_set_defaults(struct uart_8250_port *up)
3300 struct uart_port *port = &up->port;
3302 if (up->port.flags & UPF_FIXED_TYPE) {
3303 unsigned int type = up->port.type;
3305 if (!up->port.fifosize)
3306 up->port.fifosize = uart_config[type].fifo_size;
3308 up->tx_loadsz = uart_config[type].tx_loadsz;
3309 if (!up->capabilities)
3310 up->capabilities = uart_config[type].flags;
3313 set_io_from_upio(port);
3315 /* default dma handlers */
3317 if (!up->dma->tx_dma)
3318 up->dma->tx_dma = serial8250_tx_dma;
3319 if (!up->dma->rx_dma)
3320 up->dma->rx_dma = serial8250_rx_dma;
3323 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3325 #ifdef CONFIG_SERIAL_8250_CONSOLE
3327 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3329 struct uart_8250_port *up = up_to_u8250p(port);
3331 wait_for_xmitr(up, UART_LSR_THRE);
3332 serial_port_out(port, UART_TX, ch);
3336 * Restore serial console when h/w power-off detected
3338 static void serial8250_console_restore(struct uart_8250_port *up)
3340 struct uart_port *port = &up->port;
3341 struct ktermios termios;
3342 unsigned int baud, quot, frac = 0;
3344 termios.c_cflag = port->cons->cflag;
3345 termios.c_ispeed = port->cons->ispeed;
3346 termios.c_ospeed = port->cons->ospeed;
3347 if (port->state->port.tty && termios.c_cflag == 0) {
3348 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3349 termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3350 termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3353 baud = serial8250_get_baud_rate(port, &termios, NULL);
3354 quot = serial8250_get_divisor(port, baud, &frac);
3356 serial8250_set_divisor(port, baud, quot, frac);
3357 serial_port_out(port, UART_LCR, up->lcr);
3358 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3362 * Print a string to the serial port using the device FIFO
3364 * It sends fifosize bytes and then waits for the fifo
3367 static void serial8250_console_fifo_write(struct uart_8250_port *up,
3368 const char *s, unsigned int count)
3371 const char *end = s + count;
3372 unsigned int fifosize = up->tx_loadsz;
3373 bool cr_sent = false;
3376 wait_for_lsr(up, UART_LSR_THRE);
3378 for (i = 0; i < fifosize && s != end; ++i) {
3379 if (*s == '\n' && !cr_sent) {
3380 serial_out(up, UART_TX, '\r');
3383 serial_out(up, UART_TX, *s++);
3391 * Print a string to the serial port trying not to disturb
3392 * any possible real use of the port...
3394 * The console_lock must be held when we get here.
3396 * Doing runtime PM is really a bad idea for the kernel console.
3397 * Thus, we assume the function is called when device is powered up.
3399 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3402 struct uart_8250_em485 *em485 = up->em485;
3403 struct uart_port *port = &up->port;
3404 unsigned long flags;
3405 unsigned int ier, use_fifo;
3408 touch_nmi_watchdog();
3410 if (oops_in_progress)
3411 locked = spin_trylock_irqsave(&port->lock, flags);
3413 spin_lock_irqsave(&port->lock, flags);
3416 * First save the IER then disable the interrupts
3418 ier = serial_port_in(port, UART_IER);
3419 serial8250_clear_IER(up);
3421 /* check scratch reg to see if port powered off during system sleep */
3422 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3423 serial8250_console_restore(up);
3428 if (em485->tx_stopped)
3429 up->rs485_start_tx(up);
3430 mdelay(port->rs485.delay_rts_before_send);
3433 use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3435 * BCM283x requires to check the fifo
3438 !(up->capabilities & UART_CAP_MINI) &&
3440 * tx_loadsz contains the transmit fifo size
3442 up->tx_loadsz > 1 &&
3443 (up->fcr & UART_FCR_ENABLE_FIFO) &&
3445 test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
3447 * After we put a data in the fifo, the controller will send
3448 * it regardless of the CTS state. Therefore, only use fifo
3449 * if we don't use control flow.
3451 !(up->port.flags & UPF_CONS_FLOW);
3453 if (likely(use_fifo))
3454 serial8250_console_fifo_write(up, s, count);
3456 uart_console_write(port, s, count, serial8250_console_putchar);
3459 * Finally, wait for transmitter to become empty
3460 * and restore the IER
3462 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
3465 mdelay(port->rs485.delay_rts_after_send);
3466 if (em485->tx_stopped)
3467 up->rs485_stop_tx(up);
3470 serial_port_out(port, UART_IER, ier);
3473 * The receive handling will happen properly because the
3474 * receive ready bit will still be set; it is not cleared
3475 * on read. However, modem control will not, we must
3476 * call it if we have saved something in the saved flags
3477 * while processing with interrupts off.
3479 if (up->msr_saved_flags)
3480 serial8250_modem_status(up);
3483 spin_unlock_irqrestore(&port->lock, flags);
3486 static unsigned int probe_baud(struct uart_port *port)
3488 unsigned char lcr, dll, dlm;
3491 lcr = serial_port_in(port, UART_LCR);
3492 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3493 dll = serial_port_in(port, UART_DLL);
3494 dlm = serial_port_in(port, UART_DLM);
3495 serial_port_out(port, UART_LCR, lcr);
3497 quot = (dlm << 8) | dll;
3498 return (port->uartclk / 16) / quot;
3501 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3509 if (!port->iobase && !port->membase)
3513 uart_parse_options(options, &baud, &parity, &bits, &flow);
3515 baud = probe_baud(port);
3517 ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3522 pm_runtime_get_sync(port->dev);
3527 int serial8250_console_exit(struct uart_port *port)
3530 pm_runtime_put_sync(port->dev);
3535 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3537 MODULE_LICENSE("GPL");