1 // SPDX-License-Identifier: GPL-2.0+
3 * Base port operations for 8250/16550-type serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Split from 8250_core.c, Copyright (C) 2001 Russell King.
8 * A note about mapbase / membase
10 * mapbase is the physical address of the IO port.
11 * membase is an 'ioremapped' cookie.
14 #include <linux/module.h>
15 #include <linux/moduleparam.h>
16 #include <linux/ioport.h>
17 #include <linux/init.h>
18 #include <linux/irq.h>
19 #include <linux/console.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/sysrq.h>
22 #include <linux/delay.h>
23 #include <linux/platform_device.h>
24 #include <linux/tty.h>
25 #include <linux/ratelimit.h>
26 #include <linux/tty_flip.h>
27 #include <linux/serial.h>
28 #include <linux/serial_8250.h>
29 #include <linux/nmi.h>
30 #include <linux/mutex.h>
31 #include <linux/slab.h>
32 #include <linux/uaccess.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/ktime.h>
41 /* Nuvoton NPCM timeout register */
42 #define UART_NPCM_TOR 7
43 #define UART_NPCM_TOIE BIT(7) /* Timeout Interrupt Enable */
49 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
51 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
55 * Here we define the default xmit fifo size used for each type of UART.
57 static const struct serial8250_config uart_config[] = {
82 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
83 .rxtrig_bytes = {1, 4, 8, 14},
84 .flags = UART_CAP_FIFO,
95 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
101 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
103 .rxtrig_bytes = {8, 16, 24, 28},
104 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
110 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
112 .rxtrig_bytes = {1, 16, 32, 56},
113 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
121 .name = "16C950/954",
124 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
125 .rxtrig_bytes = {16, 32, 112, 120},
126 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
127 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
133 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
135 .rxtrig_bytes = {8, 16, 56, 60},
136 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
142 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
143 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
149 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
150 .flags = UART_CAP_FIFO,
156 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
157 .flags = UART_CAP_FIFO | UART_NATSEMI,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
170 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
171 .flags = UART_CAP_FIFO,
177 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
178 .flags = UART_CAP_FIFO /* | UART_CAP_AFE */,
184 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
185 .flags = UART_CAP_FIFO | UART_CAP_AFE,
191 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
193 .rxtrig_bytes = {1, 4, 8, 14},
194 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
200 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
201 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
208 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
210 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
217 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
218 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
219 .flags = UART_CAP_FIFO,
221 [PORT_BRCM_TRUMANAGE] = {
225 .flags = UART_CAP_HFIFO,
230 [PORT_ALTR_16550_F32] = {
231 .name = "Altera 16550 FIFO32",
234 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
235 .rxtrig_bytes = {1, 8, 16, 30},
236 .flags = UART_CAP_FIFO | UART_CAP_AFE,
238 [PORT_ALTR_16550_F64] = {
239 .name = "Altera 16550 FIFO64",
242 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
243 .rxtrig_bytes = {1, 16, 32, 62},
244 .flags = UART_CAP_FIFO | UART_CAP_AFE,
246 [PORT_ALTR_16550_F128] = {
247 .name = "Altera 16550 FIFO128",
250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
251 .rxtrig_bytes = {1, 32, 64, 126},
252 .flags = UART_CAP_FIFO | UART_CAP_AFE,
255 * tx_loadsz is set to 63-bytes instead of 64-bytes to implement
256 * workaround of errata A-008006 which states that tx_loadsz should
257 * be configured less than Maximum supported fifo bytes.
259 [PORT_16550A_FSL64] = {
260 .name = "16550A_FSL64",
263 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
265 .flags = UART_CAP_FIFO | UART_CAP_NOTEMT,
268 .name = "Palmchip BK-3103",
271 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
272 .rxtrig_bytes = {1, 4, 8, 14},
273 .flags = UART_CAP_FIFO,
276 .name = "TI DA8xx/66AK2x",
279 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
281 .rxtrig_bytes = {1, 4, 8, 14},
282 .flags = UART_CAP_FIFO | UART_CAP_AFE,
285 .name = "MediaTek BTIF",
288 .fcr = UART_FCR_ENABLE_FIFO |
289 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
290 .flags = UART_CAP_FIFO,
293 .name = "Nuvoton 16550",
296 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
297 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT,
298 .rxtrig_bytes = {1, 4, 8, 14},
299 .flags = UART_CAP_FIFO,
305 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
306 .rxtrig_bytes = {1, 32, 64, 112},
307 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
309 [PORT_ASPEED_VUART] = {
310 .name = "ASPEED VUART",
313 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
314 .rxtrig_bytes = {1, 4, 8, 14},
315 .flags = UART_CAP_FIFO,
317 [PORT_MCHP16550A] = {
318 .name = "MCHP16550A",
321 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01,
322 .rxtrig_bytes = {2, 66, 130, 194},
323 .flags = UART_CAP_FIFO,
327 /* Uart divisor latch read */
328 static u32 default_serial_dl_read(struct uart_8250_port *up)
330 /* Assign these in pieces to truncate any bits above 7. */
331 unsigned char dll = serial_in(up, UART_DLL);
332 unsigned char dlm = serial_in(up, UART_DLM);
334 return dll | dlm << 8;
337 /* Uart divisor latch write */
338 static void default_serial_dl_write(struct uart_8250_port *up, u32 value)
340 serial_out(up, UART_DLL, value & 0xff);
341 serial_out(up, UART_DLM, value >> 8 & 0xff);
344 static unsigned int hub6_serial_in(struct uart_port *p, int offset)
346 offset = offset << p->regshift;
347 outb(p->hub6 - 1 + offset, p->iobase);
348 return inb(p->iobase + 1);
351 static void hub6_serial_out(struct uart_port *p, int offset, int value)
353 offset = offset << p->regshift;
354 outb(p->hub6 - 1 + offset, p->iobase);
355 outb(value, p->iobase + 1);
358 static unsigned int mem_serial_in(struct uart_port *p, int offset)
360 offset = offset << p->regshift;
361 return readb(p->membase + offset);
364 static void mem_serial_out(struct uart_port *p, int offset, int value)
366 offset = offset << p->regshift;
367 writeb(value, p->membase + offset);
370 static void mem16_serial_out(struct uart_port *p, int offset, int value)
372 offset = offset << p->regshift;
373 writew(value, p->membase + offset);
376 static unsigned int mem16_serial_in(struct uart_port *p, int offset)
378 offset = offset << p->regshift;
379 return readw(p->membase + offset);
382 static void mem32_serial_out(struct uart_port *p, int offset, int value)
384 offset = offset << p->regshift;
385 writel(value, p->membase + offset);
388 static unsigned int mem32_serial_in(struct uart_port *p, int offset)
390 offset = offset << p->regshift;
391 return readl(p->membase + offset);
394 static void mem32be_serial_out(struct uart_port *p, int offset, int value)
396 offset = offset << p->regshift;
397 iowrite32be(value, p->membase + offset);
400 static unsigned int mem32be_serial_in(struct uart_port *p, int offset)
402 offset = offset << p->regshift;
403 return ioread32be(p->membase + offset);
406 static unsigned int io_serial_in(struct uart_port *p, int offset)
408 offset = offset << p->regshift;
409 return inb(p->iobase + offset);
412 static void io_serial_out(struct uart_port *p, int offset, int value)
414 offset = offset << p->regshift;
415 outb(value, p->iobase + offset);
418 static int serial8250_default_handle_irq(struct uart_port *port);
420 static void set_io_from_upio(struct uart_port *p)
422 struct uart_8250_port *up = up_to_u8250p(p);
424 up->dl_read = default_serial_dl_read;
425 up->dl_write = default_serial_dl_write;
429 p->serial_in = hub6_serial_in;
430 p->serial_out = hub6_serial_out;
434 p->serial_in = mem_serial_in;
435 p->serial_out = mem_serial_out;
439 p->serial_in = mem16_serial_in;
440 p->serial_out = mem16_serial_out;
444 p->serial_in = mem32_serial_in;
445 p->serial_out = mem32_serial_out;
449 p->serial_in = mem32be_serial_in;
450 p->serial_out = mem32be_serial_out;
454 p->serial_in = io_serial_in;
455 p->serial_out = io_serial_out;
458 /* Remember loaded iotype */
459 up->cur_iotype = p->iotype;
460 p->handle_irq = serial8250_default_handle_irq;
464 serial_port_out_sync(struct uart_port *p, int offset, int value)
472 p->serial_out(p, offset, value);
473 p->serial_in(p, UART_LCR); /* safe, no side-effects */
476 p->serial_out(p, offset, value);
483 static void serial8250_clear_fifos(struct uart_8250_port *p)
485 if (p->capabilities & UART_CAP_FIFO) {
486 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
487 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
488 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
489 serial_out(p, UART_FCR, 0);
493 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t);
494 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t);
496 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
498 serial8250_clear_fifos(p);
499 serial_out(p, UART_FCR, p->fcr);
501 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
503 void serial8250_rpm_get(struct uart_8250_port *p)
505 if (!(p->capabilities & UART_CAP_RPM))
507 pm_runtime_get_sync(p->port.dev);
509 EXPORT_SYMBOL_GPL(serial8250_rpm_get);
511 void serial8250_rpm_put(struct uart_8250_port *p)
513 if (!(p->capabilities & UART_CAP_RPM))
515 pm_runtime_mark_last_busy(p->port.dev);
516 pm_runtime_put_autosuspend(p->port.dev);
518 EXPORT_SYMBOL_GPL(serial8250_rpm_put);
521 * serial8250_em485_init() - put uart_8250_port into rs485 emulating
522 * @p: uart_8250_port port instance
524 * The function is used to start rs485 software emulating on the
525 * &struct uart_8250_port* @p. Namely, RTS is switched before/after
526 * transmission. The function is idempotent, so it is safe to call it
529 * The caller MUST enable interrupt on empty shift register before
530 * calling serial8250_em485_init(). This interrupt is not a part of
531 * 8250 standard, but implementation defined.
533 * The function is supposed to be called from .rs485_config callback
534 * or from any other callback protected with p->port.lock spinlock.
536 * See also serial8250_em485_destroy()
538 * Return 0 - success, -errno - otherwise
540 static int serial8250_em485_init(struct uart_8250_port *p)
545 p->em485 = kmalloc(sizeof(struct uart_8250_em485), GFP_ATOMIC);
549 hrtimer_init(&p->em485->stop_tx_timer, CLOCK_MONOTONIC,
551 hrtimer_init(&p->em485->start_tx_timer, CLOCK_MONOTONIC,
553 p->em485->stop_tx_timer.function = &serial8250_em485_handle_stop_tx;
554 p->em485->start_tx_timer.function = &serial8250_em485_handle_start_tx;
556 p->em485->active_timer = NULL;
557 p->em485->tx_stopped = true;
560 if (p->em485->tx_stopped)
567 * serial8250_em485_destroy() - put uart_8250_port into normal state
568 * @p: uart_8250_port port instance
570 * The function is used to stop rs485 software emulating on the
571 * &struct uart_8250_port* @p. The function is idempotent, so it is safe to
572 * call it multiple times.
574 * The function is supposed to be called from .rs485_config callback
575 * or from any other callback protected with p->port.lock spinlock.
577 * See also serial8250_em485_init()
579 void serial8250_em485_destroy(struct uart_8250_port *p)
584 hrtimer_cancel(&p->em485->start_tx_timer);
585 hrtimer_cancel(&p->em485->stop_tx_timer);
590 EXPORT_SYMBOL_GPL(serial8250_em485_destroy);
592 struct serial_rs485 serial8250_em485_supported = {
593 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
594 SER_RS485_TERMINATE_BUS | SER_RS485_RX_DURING_TX,
595 .delay_rts_before_send = 1,
596 .delay_rts_after_send = 1,
598 EXPORT_SYMBOL_GPL(serial8250_em485_supported);
601 * serial8250_em485_config() - generic ->rs485_config() callback
603 * @termios: termios structure
604 * @rs485: rs485 settings
606 * Generic callback usable by 8250 uart drivers to activate rs485 settings
607 * if the uart is incapable of driving RTS as a Transmit Enable signal in
608 * hardware, relying on software emulation instead.
610 int serial8250_em485_config(struct uart_port *port, struct ktermios *termios,
611 struct serial_rs485 *rs485)
613 struct uart_8250_port *up = up_to_u8250p(port);
615 /* pick sane settings if the user hasn't */
616 if (!!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
617 !!(rs485->flags & SER_RS485_RTS_AFTER_SEND)) {
618 rs485->flags |= SER_RS485_RTS_ON_SEND;
619 rs485->flags &= ~SER_RS485_RTS_AFTER_SEND;
623 * Both serial8250_em485_init() and serial8250_em485_destroy()
626 if (rs485->flags & SER_RS485_ENABLED)
627 return serial8250_em485_init(up);
629 serial8250_em485_destroy(up);
632 EXPORT_SYMBOL_GPL(serial8250_em485_config);
635 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than
636 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is
637 * empty and the HW can idle again.
639 void serial8250_rpm_get_tx(struct uart_8250_port *p)
641 unsigned char rpm_active;
643 if (!(p->capabilities & UART_CAP_RPM))
646 rpm_active = xchg(&p->rpm_tx_active, 1);
649 pm_runtime_get_sync(p->port.dev);
651 EXPORT_SYMBOL_GPL(serial8250_rpm_get_tx);
653 void serial8250_rpm_put_tx(struct uart_8250_port *p)
655 unsigned char rpm_active;
657 if (!(p->capabilities & UART_CAP_RPM))
660 rpm_active = xchg(&p->rpm_tx_active, 0);
663 pm_runtime_mark_last_busy(p->port.dev);
664 pm_runtime_put_autosuspend(p->port.dev);
666 EXPORT_SYMBOL_GPL(serial8250_rpm_put_tx);
669 * IER sleep support. UARTs which have EFRs need the "extended
670 * capability" bit enabled. Note that on XR16C850s, we need to
671 * reset LCR to write to IER.
673 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
675 unsigned char lcr = 0, efr = 0;
677 serial8250_rpm_get(p);
679 if (p->capabilities & UART_CAP_SLEEP) {
680 if (p->capabilities & UART_CAP_EFR) {
681 lcr = serial_in(p, UART_LCR);
682 efr = serial_in(p, UART_EFR);
683 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
684 serial_out(p, UART_EFR, UART_EFR_ECB);
685 serial_out(p, UART_LCR, 0);
687 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
688 if (p->capabilities & UART_CAP_EFR) {
689 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
690 serial_out(p, UART_EFR, efr);
691 serial_out(p, UART_LCR, lcr);
695 serial8250_rpm_put(p);
698 static void serial8250_clear_IER(struct uart_8250_port *up)
700 if (up->capabilities & UART_CAP_UUE)
701 serial_out(up, UART_IER, UART_IER_UUE);
703 serial_out(up, UART_IER, 0);
706 #ifdef CONFIG_SERIAL_8250_RSA
708 * Attempts to turn on the RSA FIFO. Returns zero on failure.
709 * We set the port uart clock rate if we succeed.
711 static int __enable_rsa(struct uart_8250_port *up)
716 mode = serial_in(up, UART_RSA_MSR);
717 result = mode & UART_RSA_MSR_FIFO;
720 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
721 mode = serial_in(up, UART_RSA_MSR);
722 result = mode & UART_RSA_MSR_FIFO;
726 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
731 static void enable_rsa(struct uart_8250_port *up)
733 if (up->port.type == PORT_RSA) {
734 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
735 spin_lock_irq(&up->port.lock);
737 spin_unlock_irq(&up->port.lock);
739 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
740 serial_out(up, UART_RSA_FRR, 0);
745 * Attempts to turn off the RSA FIFO. Returns zero on failure.
746 * It is unknown why interrupts were disabled in here. However,
747 * the caller is expected to preserve this behaviour by grabbing
748 * the spinlock before calling this function.
750 static void disable_rsa(struct uart_8250_port *up)
755 if (up->port.type == PORT_RSA &&
756 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
757 spin_lock_irq(&up->port.lock);
759 mode = serial_in(up, UART_RSA_MSR);
760 result = !(mode & UART_RSA_MSR_FIFO);
763 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
764 mode = serial_in(up, UART_RSA_MSR);
765 result = !(mode & UART_RSA_MSR_FIFO);
769 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
770 spin_unlock_irq(&up->port.lock);
773 #endif /* CONFIG_SERIAL_8250_RSA */
776 * This is a quickie test to see how big the FIFO is.
777 * It doesn't work at all the time, more's the pity.
779 static int size_fifo(struct uart_8250_port *up)
781 unsigned char old_fcr, old_mcr, old_lcr;
785 old_lcr = serial_in(up, UART_LCR);
786 serial_out(up, UART_LCR, 0);
787 old_fcr = serial_in(up, UART_FCR);
788 old_mcr = serial8250_in_MCR(up);
789 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
790 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
791 serial8250_out_MCR(up, UART_MCR_LOOP);
792 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
793 old_dl = serial_dl_read(up);
794 serial_dl_write(up, 0x0001);
795 serial_out(up, UART_LCR, UART_LCR_WLEN8);
796 for (count = 0; count < 256; count++)
797 serial_out(up, UART_TX, count);
798 mdelay(20);/* FIXME - schedule_timeout */
799 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
800 (count < 256); count++)
801 serial_in(up, UART_RX);
802 serial_out(up, UART_FCR, old_fcr);
803 serial8250_out_MCR(up, old_mcr);
804 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
805 serial_dl_write(up, old_dl);
806 serial_out(up, UART_LCR, old_lcr);
812 * Read UART ID using the divisor method - set DLL and DLM to zero
813 * and the revision will be in DLL and device type in DLM. We
814 * preserve the device state across this.
816 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
818 unsigned char old_lcr;
819 unsigned int id, old_dl;
821 old_lcr = serial_in(p, UART_LCR);
822 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
823 old_dl = serial_dl_read(p);
824 serial_dl_write(p, 0);
825 id = serial_dl_read(p);
826 serial_dl_write(p, old_dl);
828 serial_out(p, UART_LCR, old_lcr);
834 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
835 * When this function is called we know it is at least a StarTech
836 * 16650 V2, but it might be one of several StarTech UARTs, or one of
837 * its clones. (We treat the broken original StarTech 16650 V1 as a
838 * 16550, and why not? Startech doesn't seem to even acknowledge its
841 * What evil have men's minds wrought...
843 static void autoconfig_has_efr(struct uart_8250_port *up)
845 unsigned int id1, id2, id3, rev;
848 * Everything with an EFR has SLEEP
850 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
853 * First we check to see if it's an Oxford Semiconductor UART.
855 * If we have to do this here because some non-National
856 * Semiconductor clone chips lock up if you try writing to the
857 * LSR register (which serial_icr_read does)
861 * Check for Oxford Semiconductor 16C950.
863 * EFR [4] must be set else this test fails.
865 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
866 * claims that it's needed for 952 dual UART's (which are not
867 * recommended for new designs).
870 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
871 serial_out(up, UART_EFR, UART_EFR_ECB);
872 serial_out(up, UART_LCR, 0x00);
873 id1 = serial_icr_read(up, UART_ID1);
874 id2 = serial_icr_read(up, UART_ID2);
875 id3 = serial_icr_read(up, UART_ID3);
876 rev = serial_icr_read(up, UART_REV);
878 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
880 if (id1 == 0x16 && id2 == 0xC9 &&
881 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
882 up->port.type = PORT_16C950;
885 * Enable work around for the Oxford Semiconductor 952 rev B
886 * chip which causes it to seriously miscalculate baud rates
889 if (id3 == 0x52 && rev == 0x01)
890 up->bugs |= UART_BUG_QUOT;
895 * We check for a XR16C850 by setting DLL and DLM to 0, and then
896 * reading back DLL and DLM. The chip type depends on the DLM
898 * 0x10 - XR16C850 and the DLL contains the chip revision.
902 id1 = autoconfig_read_divisor_id(up);
903 DEBUG_AUTOCONF("850id=%04x ", id1);
906 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
907 up->port.type = PORT_16850;
912 * It wasn't an XR16C850.
914 * We distinguish between the '654 and the '650 by counting
915 * how many bytes are in the FIFO. I'm using this for now,
916 * since that's the technique that was sent to me in the
917 * serial driver update, but I'm not convinced this works.
918 * I've had problems doing this in the past. -TYT
920 if (size_fifo(up) == 64)
921 up->port.type = PORT_16654;
923 up->port.type = PORT_16650V2;
927 * We detected a chip without a FIFO. Only two fall into
928 * this category - the original 8250 and the 16450. The
929 * 16450 has a scratch register (accessible with LCR=0)
931 static void autoconfig_8250(struct uart_8250_port *up)
933 unsigned char scratch, status1, status2;
935 up->port.type = PORT_8250;
937 scratch = serial_in(up, UART_SCR);
938 serial_out(up, UART_SCR, 0xa5);
939 status1 = serial_in(up, UART_SCR);
940 serial_out(up, UART_SCR, 0x5a);
941 status2 = serial_in(up, UART_SCR);
942 serial_out(up, UART_SCR, scratch);
944 if (status1 == 0xa5 && status2 == 0x5a)
945 up->port.type = PORT_16450;
948 static int broken_efr(struct uart_8250_port *up)
951 * Exar ST16C2550 "A2" devices incorrectly detect as
952 * having an EFR, and report an ID of 0x0201. See
953 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
955 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
962 * We know that the chip has FIFOs. Does it have an EFR? The
963 * EFR is located in the same register position as the IIR and
964 * we know the top two bits of the IIR are currently set. The
965 * EFR should contain zero. Try to read the EFR.
967 static void autoconfig_16550a(struct uart_8250_port *up)
969 unsigned char status1, status2;
970 unsigned int iersave;
972 up->port.type = PORT_16550A;
973 up->capabilities |= UART_CAP_FIFO;
975 if (!IS_ENABLED(CONFIG_SERIAL_8250_16550A_VARIANTS) &&
976 !(up->port.flags & UPF_FULL_PROBE))
980 * Check for presence of the EFR when DLAB is set.
981 * Only ST16C650V1 UARTs pass this test.
983 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
984 if (serial_in(up, UART_EFR) == 0) {
985 serial_out(up, UART_EFR, 0xA8);
986 if (serial_in(up, UART_EFR) != 0) {
987 DEBUG_AUTOCONF("EFRv1 ");
988 up->port.type = PORT_16650;
989 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
991 serial_out(up, UART_LCR, 0);
992 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
994 status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO |
995 UART_IIR_FIFO_ENABLED);
996 serial_out(up, UART_FCR, 0);
997 serial_out(up, UART_LCR, 0);
999 if (status1 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED))
1000 up->port.type = PORT_16550A_FSL64;
1002 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
1004 serial_out(up, UART_EFR, 0);
1009 * Maybe it requires 0xbf to be written to the LCR.
1010 * (other ST16C650V2 UARTs, TI16C752A, etc)
1012 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1013 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
1014 DEBUG_AUTOCONF("EFRv2 ");
1015 autoconfig_has_efr(up);
1020 * Check for a National Semiconductor SuperIO chip.
1021 * Attempt to switch to bank 2, read the value of the LOOP bit
1022 * from EXCR1. Switch back to bank 0, change it in MCR. Then
1023 * switch back to bank 2, read it from EXCR1 again and check
1024 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
1026 serial_out(up, UART_LCR, 0);
1027 status1 = serial8250_in_MCR(up);
1028 serial_out(up, UART_LCR, 0xE0);
1029 status2 = serial_in(up, 0x02); /* EXCR1 */
1031 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
1032 serial_out(up, UART_LCR, 0);
1033 serial8250_out_MCR(up, status1 ^ UART_MCR_LOOP);
1034 serial_out(up, UART_LCR, 0xE0);
1035 status2 = serial_in(up, 0x02); /* EXCR1 */
1036 serial_out(up, UART_LCR, 0);
1037 serial8250_out_MCR(up, status1);
1039 if ((status2 ^ status1) & UART_MCR_LOOP) {
1040 unsigned short quot;
1042 serial_out(up, UART_LCR, 0xE0);
1044 quot = serial_dl_read(up);
1047 if (ns16550a_goto_highspeed(up))
1048 serial_dl_write(up, quot);
1050 serial_out(up, UART_LCR, 0);
1052 up->port.uartclk = 921600*16;
1053 up->port.type = PORT_NS16550A;
1054 up->capabilities |= UART_NATSEMI;
1060 * No EFR. Try to detect a TI16750, which only sets bit 5 of
1061 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
1062 * Try setting it with and without DLAB set. Cheap clones
1063 * set bit 5 without DLAB set.
1065 serial_out(up, UART_LCR, 0);
1066 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1067 status1 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
1068 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1070 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1071 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
1072 status2 = serial_in(up, UART_IIR) & (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED);
1073 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1075 serial_out(up, UART_LCR, 0);
1077 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
1079 if (status1 == UART_IIR_FIFO_ENABLED_16550A &&
1080 status2 == (UART_IIR_64BYTE_FIFO | UART_IIR_FIFO_ENABLED_16550A)) {
1081 up->port.type = PORT_16750;
1082 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
1087 * Try writing and reading the UART_IER_UUE bit (b6).
1088 * If it works, this is probably one of the Xscale platform's
1090 * We're going to explicitly set the UUE bit to 0 before
1091 * trying to write and read a 1 just to make sure it's not
1092 * already a 1 and maybe locked there before we even start.
1094 iersave = serial_in(up, UART_IER);
1095 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
1096 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1098 * OK it's in a known zero state, try writing and reading
1099 * without disturbing the current state of the other bits.
1101 serial_out(up, UART_IER, iersave | UART_IER_UUE);
1102 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1105 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1107 DEBUG_AUTOCONF("Xscale ");
1108 up->port.type = PORT_XSCALE;
1109 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1114 * If we got here we couldn't force the IER_UUE bit to 0.
1115 * Log it and continue.
1117 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1119 serial_out(up, UART_IER, iersave);
1122 * We distinguish between 16550A and U6 16550A by counting
1123 * how many bytes are in the FIFO.
1125 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1126 up->port.type = PORT_U6_16550A;
1127 up->capabilities |= UART_CAP_AFE;
1132 * This routine is called by rs_init() to initialize a specific serial
1133 * port. It determines what type of UART chip this serial port is
1134 * using: 8250, 16450, 16550, 16550A. The important question is
1135 * whether or not this UART is a 16550A or not, since this will
1136 * determine whether or not we can use its FIFO features or not.
1138 static void autoconfig(struct uart_8250_port *up)
1140 unsigned char status1, scratch, scratch2, scratch3;
1141 unsigned char save_lcr, save_mcr;
1142 struct uart_port *port = &up->port;
1143 unsigned long flags;
1144 unsigned int old_capabilities;
1146 if (!port->iobase && !port->mapbase && !port->membase)
1149 DEBUG_AUTOCONF("%s: autoconf (0x%04lx, 0x%p): ",
1150 port->name, port->iobase, port->membase);
1153 * We really do need global IRQs disabled here - we're going to
1154 * be frobbing the chips IRQ enable register to see if it exists.
1156 spin_lock_irqsave(&port->lock, flags);
1158 up->capabilities = 0;
1161 if (!(port->flags & UPF_BUGGY_UART)) {
1163 * Do a simple existence test first; if we fail this,
1164 * there's no point trying anything else.
1166 * 0x80 is used as a nonsense port to prevent against
1167 * false positives due to ISA bus float. The
1168 * assumption is that 0x80 is a non-existent port;
1169 * which should be safe since include/asm/io.h also
1170 * makes this assumption.
1172 * Note: this is safe as long as MCR bit 4 is clear
1173 * and the device is in "PC" mode.
1175 scratch = serial_in(up, UART_IER);
1176 serial_out(up, UART_IER, 0);
1181 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1182 * 16C754B) allow only to modify them if an EFR bit is set.
1184 scratch2 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1185 serial_out(up, UART_IER, UART_IER_ALL_INTR);
1189 scratch3 = serial_in(up, UART_IER) & UART_IER_ALL_INTR;
1190 serial_out(up, UART_IER, scratch);
1191 if (scratch2 != 0 || scratch3 != UART_IER_ALL_INTR) {
1193 * We failed; there's nothing here
1195 spin_unlock_irqrestore(&port->lock, flags);
1196 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1197 scratch2, scratch3);
1202 save_mcr = serial8250_in_MCR(up);
1203 save_lcr = serial_in(up, UART_LCR);
1206 * Check to see if a UART is really there. Certain broken
1207 * internal modems based on the Rockwell chipset fail this
1208 * test, because they apparently don't implement the loopback
1209 * test mode. So this test is skipped on the COM 1 through
1210 * COM 4 ports. This *should* be safe, since no board
1211 * manufacturer would be stupid enough to design a board
1212 * that conflicts with COM 1-4 --- we hope!
1214 if (!(port->flags & UPF_SKIP_TEST)) {
1215 serial8250_out_MCR(up, UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_RTS);
1216 status1 = serial_in(up, UART_MSR) & UART_MSR_STATUS_BITS;
1217 serial8250_out_MCR(up, save_mcr);
1218 if (status1 != (UART_MSR_DCD | UART_MSR_CTS)) {
1219 spin_unlock_irqrestore(&port->lock, flags);
1220 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1227 * We're pretty sure there's a port here. Lets find out what
1228 * type of port it is. The IIR top two bits allows us to find
1229 * out if it's 8250 or 16450, 16550, 16550A or later. This
1230 * determines what we test for next.
1232 * We also initialise the EFR (if any) to zero for later. The
1233 * EFR occupies the same register location as the FCR and IIR.
1235 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1236 serial_out(up, UART_EFR, 0);
1237 serial_out(up, UART_LCR, 0);
1239 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1241 switch (serial_in(up, UART_IIR) & UART_IIR_FIFO_ENABLED) {
1242 case UART_IIR_FIFO_ENABLED_8250:
1243 autoconfig_8250(up);
1245 case UART_IIR_FIFO_ENABLED_16550:
1246 port->type = PORT_16550;
1248 case UART_IIR_FIFO_ENABLED_16550A:
1249 autoconfig_16550a(up);
1252 port->type = PORT_UNKNOWN;
1256 #ifdef CONFIG_SERIAL_8250_RSA
1258 * Only probe for RSA ports if we got the region.
1260 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA &&
1262 port->type = PORT_RSA;
1265 serial_out(up, UART_LCR, save_lcr);
1267 port->fifosize = uart_config[up->port.type].fifo_size;
1268 old_capabilities = up->capabilities;
1269 up->capabilities = uart_config[port->type].flags;
1270 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1272 if (port->type == PORT_UNKNOWN)
1278 #ifdef CONFIG_SERIAL_8250_RSA
1279 if (port->type == PORT_RSA)
1280 serial_out(up, UART_RSA_FRR, 0);
1282 serial8250_out_MCR(up, save_mcr);
1283 serial8250_clear_fifos(up);
1284 serial_in(up, UART_RX);
1285 serial8250_clear_IER(up);
1288 spin_unlock_irqrestore(&port->lock, flags);
1291 * Check if the device is a Fintek F81216A
1293 if (port->type == PORT_16550A && port->iotype == UPIO_PORT)
1294 fintek_8250_probe(up);
1296 if (up->capabilities != old_capabilities) {
1297 dev_warn(port->dev, "detected caps %08x should be %08x\n",
1298 old_capabilities, up->capabilities);
1301 DEBUG_AUTOCONF("iir=%d ", scratch);
1302 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1305 static void autoconfig_irq(struct uart_8250_port *up)
1307 struct uart_port *port = &up->port;
1308 unsigned char save_mcr, save_ier;
1309 unsigned char save_ICP = 0;
1310 unsigned int ICP = 0;
1314 if (port->flags & UPF_FOURPORT) {
1315 ICP = (port->iobase & 0xfe0) | 0x1f;
1316 save_ICP = inb_p(ICP);
1321 if (uart_console(port))
1324 /* forget possible initially masked and pending IRQ */
1325 probe_irq_off(probe_irq_on());
1326 save_mcr = serial8250_in_MCR(up);
1327 save_ier = serial_in(up, UART_IER);
1328 serial8250_out_MCR(up, UART_MCR_OUT1 | UART_MCR_OUT2);
1330 irqs = probe_irq_on();
1331 serial8250_out_MCR(up, 0);
1333 if (port->flags & UPF_FOURPORT) {
1334 serial8250_out_MCR(up, UART_MCR_DTR | UART_MCR_RTS);
1336 serial8250_out_MCR(up,
1337 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1339 serial_out(up, UART_IER, UART_IER_ALL_INTR);
1340 serial_in(up, UART_LSR);
1341 serial_in(up, UART_RX);
1342 serial_in(up, UART_IIR);
1343 serial_in(up, UART_MSR);
1344 serial_out(up, UART_TX, 0xFF);
1346 irq = probe_irq_off(irqs);
1348 serial8250_out_MCR(up, save_mcr);
1349 serial_out(up, UART_IER, save_ier);
1351 if (port->flags & UPF_FOURPORT)
1352 outb_p(save_ICP, ICP);
1354 if (uart_console(port))
1357 port->irq = (irq > 0) ? irq : 0;
1360 static void serial8250_stop_rx(struct uart_port *port)
1362 struct uart_8250_port *up = up_to_u8250p(port);
1364 serial8250_rpm_get(up);
1366 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1367 up->port.read_status_mask &= ~UART_LSR_DR;
1368 serial_port_out(port, UART_IER, up->ier);
1370 serial8250_rpm_put(up);
1374 * serial8250_em485_stop_tx() - generic ->rs485_stop_tx() callback
1375 * @p: uart 8250 port
1377 * Generic callback usable by 8250 uart drivers to stop rs485 transmission.
1379 void serial8250_em485_stop_tx(struct uart_8250_port *p)
1381 unsigned char mcr = serial8250_in_MCR(p);
1383 if (p->port.rs485.flags & SER_RS485_RTS_AFTER_SEND)
1384 mcr |= UART_MCR_RTS;
1386 mcr &= ~UART_MCR_RTS;
1387 serial8250_out_MCR(p, mcr);
1390 * Empty the RX FIFO, we are not interested in anything
1391 * received during the half-duplex transmission.
1392 * Enable previously disabled RX interrupts.
1394 if (!(p->port.rs485.flags & SER_RS485_RX_DURING_TX)) {
1395 serial8250_clear_and_reinit_fifos(p);
1397 p->ier |= UART_IER_RLSI | UART_IER_RDI;
1398 serial_port_out(&p->port, UART_IER, p->ier);
1401 EXPORT_SYMBOL_GPL(serial8250_em485_stop_tx);
1403 static enum hrtimer_restart serial8250_em485_handle_stop_tx(struct hrtimer *t)
1405 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1407 struct uart_8250_port *p = em485->port;
1408 unsigned long flags;
1410 serial8250_rpm_get(p);
1411 spin_lock_irqsave(&p->port.lock, flags);
1412 if (em485->active_timer == &em485->stop_tx_timer) {
1413 p->rs485_stop_tx(p);
1414 em485->active_timer = NULL;
1415 em485->tx_stopped = true;
1417 spin_unlock_irqrestore(&p->port.lock, flags);
1418 serial8250_rpm_put(p);
1420 return HRTIMER_NORESTART;
1423 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
1425 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
1428 static void __stop_tx_rs485(struct uart_8250_port *p, u64 stop_delay)
1430 struct uart_8250_em485 *em485 = p->em485;
1432 stop_delay += (u64)p->port.rs485.delay_rts_after_send * NSEC_PER_MSEC;
1435 * rs485_stop_tx() is going to set RTS according to config
1436 * AND flush RX FIFO if required.
1438 if (stop_delay > 0) {
1439 em485->active_timer = &em485->stop_tx_timer;
1440 hrtimer_start(&em485->stop_tx_timer, ns_to_ktime(stop_delay), HRTIMER_MODE_REL);
1442 p->rs485_stop_tx(p);
1443 em485->active_timer = NULL;
1444 em485->tx_stopped = true;
1448 static inline void __stop_tx(struct uart_8250_port *p)
1450 struct uart_8250_em485 *em485 = p->em485;
1453 u16 lsr = serial_lsr_in(p);
1456 if (!(lsr & UART_LSR_THRE))
1459 * To provide required timing and allow FIFO transfer,
1460 * __stop_tx_rs485() must be called only when both FIFO and
1461 * shift register are empty. The device driver should either
1462 * enable interrupt on TEMT or set UART_CAP_NOTEMT that will
1463 * enlarge stop_tx_timer by the tx time of one frame to cover
1464 * for emptying of the shift register.
1466 if (!(lsr & UART_LSR_TEMT)) {
1467 if (!(p->capabilities & UART_CAP_NOTEMT))
1470 * RTS might get deasserted too early with the normal
1471 * frame timing formula. It seems to suggest THRE might
1472 * get asserted already during tx of the stop bit
1473 * rather than after it is fully sent.
1474 * Roughly estimate 1 extra bit here with / 7.
1476 stop_delay = p->port.frame_time + DIV_ROUND_UP(p->port.frame_time, 7);
1479 __stop_tx_rs485(p, stop_delay);
1482 if (serial8250_clear_THRI(p))
1483 serial8250_rpm_put_tx(p);
1486 static void serial8250_stop_tx(struct uart_port *port)
1488 struct uart_8250_port *up = up_to_u8250p(port);
1490 serial8250_rpm_get(up);
1494 * We really want to stop the transmitter from sending.
1496 if (port->type == PORT_16C950) {
1497 up->acr |= UART_ACR_TXDIS;
1498 serial_icr_write(up, UART_ACR, up->acr);
1500 serial8250_rpm_put(up);
1503 static inline void __start_tx(struct uart_port *port)
1505 struct uart_8250_port *up = up_to_u8250p(port);
1507 if (up->dma && !up->dma->tx_dma(up))
1510 if (serial8250_set_THRI(up)) {
1511 if (up->bugs & UART_BUG_TXEN) {
1512 u16 lsr = serial_lsr_in(up);
1514 if (lsr & UART_LSR_THRE)
1515 serial8250_tx_chars(up);
1520 * Re-enable the transmitter if we disabled it.
1522 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1523 up->acr &= ~UART_ACR_TXDIS;
1524 serial_icr_write(up, UART_ACR, up->acr);
1529 * serial8250_em485_start_tx() - generic ->rs485_start_tx() callback
1530 * @up: uart 8250 port
1532 * Generic callback usable by 8250 uart drivers to start rs485 transmission.
1533 * Assumes that setting the RTS bit in the MCR register means RTS is high.
1534 * (Some chips use inverse semantics.) Further assumes that reception is
1535 * stoppable by disabling the UART_IER_RDI interrupt. (Some chips set the
1536 * UART_LSR_DR bit even when UART_IER_RDI is disabled, foiling this approach.)
1538 void serial8250_em485_start_tx(struct uart_8250_port *up)
1540 unsigned char mcr = serial8250_in_MCR(up);
1542 if (!(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
1543 serial8250_stop_rx(&up->port);
1545 if (up->port.rs485.flags & SER_RS485_RTS_ON_SEND)
1546 mcr |= UART_MCR_RTS;
1548 mcr &= ~UART_MCR_RTS;
1549 serial8250_out_MCR(up, mcr);
1551 EXPORT_SYMBOL_GPL(serial8250_em485_start_tx);
1553 /* Returns false, if start_tx_timer was setup to defer TX start */
1554 static bool start_tx_rs485(struct uart_port *port)
1556 struct uart_8250_port *up = up_to_u8250p(port);
1557 struct uart_8250_em485 *em485 = up->em485;
1560 * While serial8250_em485_handle_stop_tx() is a noop if
1561 * em485->active_timer != &em485->stop_tx_timer, it might happen that
1562 * the timer is still armed and triggers only after the current bunch of
1563 * chars is send and em485->active_timer == &em485->stop_tx_timer again.
1564 * So cancel the timer. There is still a theoretical race condition if
1565 * the timer is already running and only comes around to check for
1566 * em485->active_timer when &em485->stop_tx_timer is armed again.
1568 if (em485->active_timer == &em485->stop_tx_timer)
1569 hrtimer_try_to_cancel(&em485->stop_tx_timer);
1571 em485->active_timer = NULL;
1573 if (em485->tx_stopped) {
1574 em485->tx_stopped = false;
1576 up->rs485_start_tx(up);
1578 if (up->port.rs485.delay_rts_before_send > 0) {
1579 em485->active_timer = &em485->start_tx_timer;
1580 start_hrtimer_ms(&em485->start_tx_timer,
1581 up->port.rs485.delay_rts_before_send);
1589 static enum hrtimer_restart serial8250_em485_handle_start_tx(struct hrtimer *t)
1591 struct uart_8250_em485 *em485 = container_of(t, struct uart_8250_em485,
1593 struct uart_8250_port *p = em485->port;
1594 unsigned long flags;
1596 spin_lock_irqsave(&p->port.lock, flags);
1597 if (em485->active_timer == &em485->start_tx_timer) {
1598 __start_tx(&p->port);
1599 em485->active_timer = NULL;
1601 spin_unlock_irqrestore(&p->port.lock, flags);
1603 return HRTIMER_NORESTART;
1606 static void serial8250_start_tx(struct uart_port *port)
1608 struct uart_8250_port *up = up_to_u8250p(port);
1609 struct uart_8250_em485 *em485 = up->em485;
1611 if (!port->x_char && uart_circ_empty(&port->state->xmit))
1614 serial8250_rpm_get_tx(up);
1617 if ((em485->active_timer == &em485->start_tx_timer) ||
1618 !start_tx_rs485(port))
1624 static void serial8250_throttle(struct uart_port *port)
1626 port->throttle(port);
1629 static void serial8250_unthrottle(struct uart_port *port)
1631 port->unthrottle(port);
1634 static void serial8250_disable_ms(struct uart_port *port)
1636 struct uart_8250_port *up = up_to_u8250p(port);
1638 /* no MSR capabilities */
1639 if (up->bugs & UART_BUG_NOMSR)
1642 mctrl_gpio_disable_ms(up->gpios);
1644 up->ier &= ~UART_IER_MSI;
1645 serial_port_out(port, UART_IER, up->ier);
1648 static void serial8250_enable_ms(struct uart_port *port)
1650 struct uart_8250_port *up = up_to_u8250p(port);
1652 /* no MSR capabilities */
1653 if (up->bugs & UART_BUG_NOMSR)
1656 mctrl_gpio_enable_ms(up->gpios);
1658 up->ier |= UART_IER_MSI;
1660 serial8250_rpm_get(up);
1661 serial_port_out(port, UART_IER, up->ier);
1662 serial8250_rpm_put(up);
1665 void serial8250_read_char(struct uart_8250_port *up, u16 lsr)
1667 struct uart_port *port = &up->port;
1669 char flag = TTY_NORMAL;
1671 if (likely(lsr & UART_LSR_DR))
1672 ch = serial_in(up, UART_RX);
1675 * Intel 82571 has a Serial Over Lan device that will
1676 * set UART_LSR_BI without setting UART_LSR_DR when
1677 * it receives a break. To avoid reading from the
1678 * receive buffer without UART_LSR_DR bit set, we
1679 * just force the read character to be 0
1685 lsr |= up->lsr_saved_flags;
1686 up->lsr_saved_flags = 0;
1688 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1689 if (lsr & UART_LSR_BI) {
1690 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1693 * We do the SysRQ and SAK checking
1694 * here because otherwise the break
1695 * may get masked by ignore_status_mask
1696 * or read_status_mask.
1698 if (uart_handle_break(port))
1700 } else if (lsr & UART_LSR_PE)
1701 port->icount.parity++;
1702 else if (lsr & UART_LSR_FE)
1703 port->icount.frame++;
1704 if (lsr & UART_LSR_OE)
1705 port->icount.overrun++;
1708 * Mask off conditions which should be ignored.
1710 lsr &= port->read_status_mask;
1712 if (lsr & UART_LSR_BI) {
1713 dev_dbg(port->dev, "handling break\n");
1715 } else if (lsr & UART_LSR_PE)
1717 else if (lsr & UART_LSR_FE)
1720 if (uart_prepare_sysrq_char(port, ch))
1723 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1725 EXPORT_SYMBOL_GPL(serial8250_read_char);
1728 * serial8250_rx_chars - Read characters. The first LSR value must be passed in.
1730 * Returns LSR bits. The caller should rely only on non-Rx related LSR bits
1731 * (such as THRE) because the LSR value might come from an already consumed
1734 u16 serial8250_rx_chars(struct uart_8250_port *up, u16 lsr)
1736 struct uart_port *port = &up->port;
1737 int max_count = 256;
1740 serial8250_read_char(up, lsr);
1741 if (--max_count == 0)
1743 lsr = serial_in(up, UART_LSR);
1744 } while (lsr & (UART_LSR_DR | UART_LSR_BI));
1746 tty_flip_buffer_push(&port->state->port);
1749 EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1751 void serial8250_tx_chars(struct uart_8250_port *up)
1753 struct uart_port *port = &up->port;
1754 struct circ_buf *xmit = &port->state->xmit;
1758 uart_xchar_out(port, UART_TX);
1761 if (uart_tx_stopped(port)) {
1762 serial8250_stop_tx(port);
1765 if (uart_circ_empty(xmit)) {
1770 count = up->tx_loadsz;
1772 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1773 if (up->bugs & UART_BUG_TXRACE) {
1775 * The Aspeed BMC virtual UARTs have a bug where data
1776 * may get stuck in the BMC's Tx FIFO from bursts of
1777 * writes on the APB interface.
1779 * Delay back-to-back writes by a read cycle to avoid
1780 * stalling the VUART. Read a register that won't have
1781 * side-effects and discard the result.
1783 serial_in(up, UART_SCR);
1785 uart_xmit_advance(port, 1);
1786 if (uart_circ_empty(xmit))
1788 if ((up->capabilities & UART_CAP_HFIFO) &&
1789 !uart_lsr_tx_empty(serial_in(up, UART_LSR)))
1791 /* The BCM2835 MINI UART THRE bit is really a not-full bit. */
1792 if ((up->capabilities & UART_CAP_MINI) &&
1793 !(serial_in(up, UART_LSR) & UART_LSR_THRE))
1795 } while (--count > 0);
1797 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1798 uart_write_wakeup(port);
1801 * With RPM enabled, we have to wait until the FIFO is empty before the
1802 * HW can go idle. So we get here once again with empty FIFO and disable
1803 * the interrupt and RPM in __stop_tx()
1805 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM))
1808 EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1810 /* Caller holds uart port lock */
1811 unsigned int serial8250_modem_status(struct uart_8250_port *up)
1813 struct uart_port *port = &up->port;
1814 unsigned int status = serial_in(up, UART_MSR);
1816 status |= up->msr_saved_flags;
1817 up->msr_saved_flags = 0;
1818 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1819 port->state != NULL) {
1820 if (status & UART_MSR_TERI)
1822 if (status & UART_MSR_DDSR)
1824 if (status & UART_MSR_DDCD)
1825 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1826 if (status & UART_MSR_DCTS)
1827 uart_handle_cts_change(port, status & UART_MSR_CTS);
1829 wake_up_interruptible(&port->state->port.delta_msr_wait);
1834 EXPORT_SYMBOL_GPL(serial8250_modem_status);
1836 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1838 switch (iir & 0x3f) {
1841 * Postpone DMA or not decision to IIR_RDI or IIR_RX_TIMEOUT
1842 * because it's impossible to do an informed decision about
1843 * that with IIR_THRI.
1845 * This also fixes one known DMA Rx corruption issue where
1846 * DR is asserted but DMA Rx only gets a corrupted zero byte
1851 if (!up->dma->rx_running)
1855 case UART_IIR_RX_TIMEOUT:
1856 serial8250_rx_dma_flush(up);
1859 return up->dma->rx_dma(up);
1863 * This handles the interrupt from one port.
1865 int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1867 struct uart_8250_port *up = up_to_u8250p(port);
1868 struct tty_port *tport = &port->state->port;
1869 bool skip_rx = false;
1870 unsigned long flags;
1873 if (iir & UART_IIR_NO_INT)
1876 spin_lock_irqsave(&port->lock, flags);
1878 status = serial_lsr_in(up);
1881 * If port is stopped and there are no error conditions in the
1882 * FIFO, then don't drain the FIFO, as this may lead to TTY buffer
1883 * overflow. Not servicing, RX FIFO would trigger auto HW flow
1884 * control when FIFO occupancy reaches preset threshold, thus
1885 * halting RX. This only works when auto HW flow control is
1888 if (!(status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS)) &&
1889 (port->status & (UPSTAT_AUTOCTS | UPSTAT_AUTORTS)) &&
1890 !(port->read_status_mask & UART_LSR_DR))
1893 if (status & (UART_LSR_DR | UART_LSR_BI) && !skip_rx) {
1894 if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
1895 pm_wakeup_event(tport->tty->dev, 0);
1896 if (!up->dma || handle_rx_dma(up, iir))
1897 status = serial8250_rx_chars(up, status);
1899 serial8250_modem_status(up);
1900 if ((status & UART_LSR_THRE) && (up->ier & UART_IER_THRI)) {
1901 if (!up->dma || up->dma->tx_err)
1902 serial8250_tx_chars(up);
1903 else if (!up->dma->tx_running)
1907 uart_unlock_and_check_sysrq_irqrestore(port, flags);
1911 EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1913 static int serial8250_default_handle_irq(struct uart_port *port)
1915 struct uart_8250_port *up = up_to_u8250p(port);
1919 serial8250_rpm_get(up);
1921 iir = serial_port_in(port, UART_IIR);
1922 ret = serial8250_handle_irq(port, iir);
1924 serial8250_rpm_put(up);
1929 * Newer 16550 compatible parts such as the SC16C650 & Altera 16550 Soft IP
1930 * have a programmable TX threshold that triggers the THRE interrupt in
1931 * the IIR register. In this case, the THRE interrupt indicates the FIFO
1932 * has space available. Load it up with tx_loadsz bytes.
1934 static int serial8250_tx_threshold_handle_irq(struct uart_port *port)
1936 unsigned long flags;
1937 unsigned int iir = serial_port_in(port, UART_IIR);
1939 /* TX Threshold IRQ triggered so load up FIFO */
1940 if ((iir & UART_IIR_ID) == UART_IIR_THRI) {
1941 struct uart_8250_port *up = up_to_u8250p(port);
1943 spin_lock_irqsave(&port->lock, flags);
1944 serial8250_tx_chars(up);
1945 spin_unlock_irqrestore(&port->lock, flags);
1948 iir = serial_port_in(port, UART_IIR);
1949 return serial8250_handle_irq(port, iir);
1952 static unsigned int serial8250_tx_empty(struct uart_port *port)
1954 struct uart_8250_port *up = up_to_u8250p(port);
1955 unsigned int result = 0;
1956 unsigned long flags;
1958 serial8250_rpm_get(up);
1960 spin_lock_irqsave(&port->lock, flags);
1961 if (!serial8250_tx_dma_running(up) && uart_lsr_tx_empty(serial_lsr_in(up)))
1962 result = TIOCSER_TEMT;
1963 spin_unlock_irqrestore(&port->lock, flags);
1965 serial8250_rpm_put(up);
1970 unsigned int serial8250_do_get_mctrl(struct uart_port *port)
1972 struct uart_8250_port *up = up_to_u8250p(port);
1973 unsigned int status;
1976 serial8250_rpm_get(up);
1977 status = serial8250_modem_status(up);
1978 serial8250_rpm_put(up);
1980 val = serial8250_MSR_to_TIOCM(status);
1982 return mctrl_gpio_get(up->gpios, &val);
1986 EXPORT_SYMBOL_GPL(serial8250_do_get_mctrl);
1988 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1990 if (port->get_mctrl)
1991 return port->get_mctrl(port);
1992 return serial8250_do_get_mctrl(port);
1995 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl)
1997 struct uart_8250_port *up = up_to_u8250p(port);
2000 mcr = serial8250_TIOCM_to_MCR(mctrl);
2004 serial8250_out_MCR(up, mcr);
2006 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl);
2008 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
2010 if (port->rs485.flags & SER_RS485_ENABLED)
2013 if (port->set_mctrl)
2014 port->set_mctrl(port, mctrl);
2016 serial8250_do_set_mctrl(port, mctrl);
2019 static void serial8250_break_ctl(struct uart_port *port, int break_state)
2021 struct uart_8250_port *up = up_to_u8250p(port);
2022 unsigned long flags;
2024 serial8250_rpm_get(up);
2025 spin_lock_irqsave(&port->lock, flags);
2026 if (break_state == -1)
2027 up->lcr |= UART_LCR_SBC;
2029 up->lcr &= ~UART_LCR_SBC;
2030 serial_port_out(port, UART_LCR, up->lcr);
2031 spin_unlock_irqrestore(&port->lock, flags);
2032 serial8250_rpm_put(up);
2035 static void wait_for_lsr(struct uart_8250_port *up, int bits)
2037 unsigned int status, tmout = 10000;
2039 /* Wait up to 10ms for the character(s) to be sent. */
2041 status = serial_lsr_in(up);
2043 if ((status & bits) == bits)
2048 touch_nmi_watchdog();
2053 * Wait for transmitter & holding register to empty
2055 static void wait_for_xmitr(struct uart_8250_port *up, int bits)
2059 wait_for_lsr(up, bits);
2061 /* Wait up to 1s for flow control if necessary */
2062 if (up->port.flags & UPF_CONS_FLOW) {
2063 for (tmout = 1000000; tmout; tmout--) {
2064 unsigned int msr = serial_in(up, UART_MSR);
2065 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
2066 if (msr & UART_MSR_CTS)
2069 touch_nmi_watchdog();
2074 #ifdef CONFIG_CONSOLE_POLL
2076 * Console polling routines for writing and reading from the uart while
2077 * in an interrupt or debug context.
2080 static int serial8250_get_poll_char(struct uart_port *port)
2082 struct uart_8250_port *up = up_to_u8250p(port);
2086 serial8250_rpm_get(up);
2088 lsr = serial_port_in(port, UART_LSR);
2090 if (!(lsr & UART_LSR_DR)) {
2091 status = NO_POLL_CHAR;
2095 status = serial_port_in(port, UART_RX);
2097 serial8250_rpm_put(up);
2102 static void serial8250_put_poll_char(struct uart_port *port,
2106 struct uart_8250_port *up = up_to_u8250p(port);
2108 serial8250_rpm_get(up);
2110 * First save the IER then disable the interrupts
2112 ier = serial_port_in(port, UART_IER);
2113 serial8250_clear_IER(up);
2115 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2117 * Send the character out.
2119 serial_port_out(port, UART_TX, c);
2122 * Finally, wait for transmitter to become empty
2123 * and restore the IER
2125 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
2126 serial_port_out(port, UART_IER, ier);
2127 serial8250_rpm_put(up);
2130 #endif /* CONFIG_CONSOLE_POLL */
2132 int serial8250_do_startup(struct uart_port *port)
2134 struct uart_8250_port *up = up_to_u8250p(port);
2135 unsigned long flags;
2140 if (!port->fifosize)
2141 port->fifosize = uart_config[port->type].fifo_size;
2143 up->tx_loadsz = uart_config[port->type].tx_loadsz;
2144 if (!up->capabilities)
2145 up->capabilities = uart_config[port->type].flags;
2148 if (port->iotype != up->cur_iotype)
2149 set_io_from_upio(port);
2151 serial8250_rpm_get(up);
2152 if (port->type == PORT_16C950) {
2153 /* Wake up and initialize UART */
2155 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2156 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2157 serial_port_out(port, UART_IER, 0);
2158 serial_port_out(port, UART_LCR, 0);
2159 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
2160 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2161 serial_port_out(port, UART_EFR, UART_EFR_ECB);
2162 serial_port_out(port, UART_LCR, 0);
2165 if (port->type == PORT_DA830) {
2166 /* Reset the port */
2167 serial_port_out(port, UART_IER, 0);
2168 serial_port_out(port, UART_DA830_PWREMU_MGMT, 0);
2171 /* Enable Tx, Rx and free run mode */
2172 serial_port_out(port, UART_DA830_PWREMU_MGMT,
2173 UART_DA830_PWREMU_MGMT_UTRST |
2174 UART_DA830_PWREMU_MGMT_URRST |
2175 UART_DA830_PWREMU_MGMT_FREE);
2178 if (port->type == PORT_NPCM) {
2180 * Nuvoton calls the scratch register 'UART_TOR' (timeout
2181 * register). Enable it, and set TIOC (timeout interrupt
2182 * comparator) to be 0x20 for correct operation.
2184 serial_port_out(port, UART_NPCM_TOR, UART_NPCM_TOIE | 0x20);
2187 #ifdef CONFIG_SERIAL_8250_RSA
2189 * If this is an RSA port, see if we can kick it up to the
2190 * higher speed clock.
2196 * Clear the FIFO buffers and disable them.
2197 * (they will be reenabled in set_termios())
2199 serial8250_clear_fifos(up);
2202 * Clear the interrupt registers.
2204 serial_port_in(port, UART_LSR);
2205 serial_port_in(port, UART_RX);
2206 serial_port_in(port, UART_IIR);
2207 serial_port_in(port, UART_MSR);
2210 * At this point, there's no way the LSR could still be 0xff;
2211 * if it is, then bail out, because there's likely no UART
2214 if (!(port->flags & UPF_BUGGY_UART) &&
2215 (serial_port_in(port, UART_LSR) == 0xff)) {
2216 dev_info_ratelimited(port->dev, "LSR safety check engaged!\n");
2222 * For a XR16C850, we need to set the trigger levels
2224 if (port->type == PORT_16850) {
2227 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2229 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2230 serial_port_out(port, UART_FCTR,
2231 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2232 serial_port_out(port, UART_TRG, UART_TRG_96);
2233 serial_port_out(port, UART_FCTR,
2234 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2235 serial_port_out(port, UART_TRG, UART_TRG_96);
2237 serial_port_out(port, UART_LCR, 0);
2241 * For the Altera 16550 variants, set TX threshold trigger level.
2243 if (((port->type == PORT_ALTR_16550_F32) ||
2244 (port->type == PORT_ALTR_16550_F64) ||
2245 (port->type == PORT_ALTR_16550_F128)) && (port->fifosize > 1)) {
2246 /* Bounds checking of TX threshold (valid 0 to fifosize-2) */
2247 if ((up->tx_loadsz < 2) || (up->tx_loadsz > port->fifosize)) {
2248 dev_err(port->dev, "TX FIFO Threshold errors, skipping\n");
2250 serial_port_out(port, UART_ALTR_AFR,
2251 UART_ALTR_EN_TXFIFO_LW);
2252 serial_port_out(port, UART_ALTR_TX_LOW,
2253 port->fifosize - up->tx_loadsz);
2254 port->handle_irq = serial8250_tx_threshold_handle_irq;
2258 /* Check if we need to have shared IRQs */
2259 if (port->irq && (up->port.flags & UPF_SHARE_IRQ))
2260 up->port.irqflags |= IRQF_SHARED;
2262 retval = up->ops->setup_irq(up);
2266 if (port->irq && !(up->port.flags & UPF_NO_THRE_TEST)) {
2269 if (port->irqflags & IRQF_SHARED)
2270 disable_irq_nosync(port->irq);
2273 * Test for UARTs that do not reassert THRE when the
2274 * transmitter is idle and the interrupt has already
2275 * been cleared. Real 16550s should always reassert
2276 * this interrupt whenever the transmitter is idle and
2277 * the interrupt is enabled. Delays are necessary to
2278 * allow register changes to become visible.
2280 spin_lock_irqsave(&port->lock, flags);
2282 wait_for_xmitr(up, UART_LSR_THRE);
2283 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2284 udelay(1); /* allow THRE to set */
2285 iir1 = serial_port_in(port, UART_IIR);
2286 serial_port_out(port, UART_IER, 0);
2287 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2288 udelay(1); /* allow a working UART time to re-assert THRE */
2289 iir = serial_port_in(port, UART_IIR);
2290 serial_port_out(port, UART_IER, 0);
2292 spin_unlock_irqrestore(&port->lock, flags);
2294 if (port->irqflags & IRQF_SHARED)
2295 enable_irq(port->irq);
2298 * If the interrupt is not reasserted, or we otherwise
2299 * don't trust the iir, setup a timer to kick the UART
2300 * on a regular basis.
2302 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2303 up->port.flags & UPF_BUG_THRE) {
2304 up->bugs |= UART_BUG_THRE;
2308 up->ops->setup_timer(up);
2311 * Now, initialize the UART
2313 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2315 spin_lock_irqsave(&port->lock, flags);
2316 if (up->port.flags & UPF_FOURPORT) {
2318 up->port.mctrl |= TIOCM_OUT1;
2321 * Most PC uarts need OUT2 raised to enable interrupts.
2324 up->port.mctrl |= TIOCM_OUT2;
2326 serial8250_set_mctrl(port, port->mctrl);
2329 * Serial over Lan (SoL) hack:
2330 * Intel 8257x Gigabit ethernet chips have a 16550 emulation, to be
2331 * used for Serial Over Lan. Those chips take a longer time than a
2332 * normal serial device to signalize that a transmission data was
2333 * queued. Due to that, the above test generally fails. One solution
2334 * would be to delay the reading of iir. However, this is not
2335 * reliable, since the timeout is variable. So, let's just don't
2336 * test if we receive TX irq. This way, we'll never enable
2339 if (up->port.quirks & UPQ_NO_TXEN_TEST)
2340 goto dont_test_tx_en;
2343 * Do a quick test to see if we receive an interrupt when we enable
2346 serial_port_out(port, UART_IER, UART_IER_THRI);
2347 lsr = serial_port_in(port, UART_LSR);
2348 iir = serial_port_in(port, UART_IIR);
2349 serial_port_out(port, UART_IER, 0);
2351 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2352 if (!(up->bugs & UART_BUG_TXEN)) {
2353 up->bugs |= UART_BUG_TXEN;
2354 dev_dbg(port->dev, "enabling bad tx status workarounds\n");
2357 up->bugs &= ~UART_BUG_TXEN;
2361 spin_unlock_irqrestore(&port->lock, flags);
2364 * Clear the interrupt registers again for luck, and clear the
2365 * saved flags to avoid getting false values from polling
2366 * routines or the previous session.
2368 serial_port_in(port, UART_LSR);
2369 serial_port_in(port, UART_RX);
2370 serial_port_in(port, UART_IIR);
2371 serial_port_in(port, UART_MSR);
2372 up->lsr_saved_flags = 0;
2373 up->msr_saved_flags = 0;
2376 * Request DMA channels for both RX and TX.
2379 const char *msg = NULL;
2381 if (uart_console(port))
2382 msg = "forbid DMA for kernel console";
2383 else if (serial8250_request_dma(up))
2384 msg = "failed to request DMA";
2386 dev_warn_ratelimited(port->dev, "%s\n", msg);
2392 * Set the IER shadow for rx interrupts but defer actual interrupt
2393 * enable until after the FIFOs are enabled; otherwise, an already-
2394 * active sender can swamp the interrupt handler with "too much work".
2396 up->ier = UART_IER_RLSI | UART_IER_RDI;
2398 if (port->flags & UPF_FOURPORT) {
2401 * Enable interrupts on the AST Fourport board
2403 icp = (port->iobase & 0xfe0) | 0x01f;
2409 serial8250_rpm_put(up);
2412 EXPORT_SYMBOL_GPL(serial8250_do_startup);
2414 static int serial8250_startup(struct uart_port *port)
2417 return port->startup(port);
2418 return serial8250_do_startup(port);
2421 void serial8250_do_shutdown(struct uart_port *port)
2423 struct uart_8250_port *up = up_to_u8250p(port);
2424 unsigned long flags;
2426 serial8250_rpm_get(up);
2428 * Disable interrupts from this port
2430 spin_lock_irqsave(&port->lock, flags);
2432 serial_port_out(port, UART_IER, 0);
2433 spin_unlock_irqrestore(&port->lock, flags);
2435 synchronize_irq(port->irq);
2438 serial8250_release_dma(up);
2440 spin_lock_irqsave(&port->lock, flags);
2441 if (port->flags & UPF_FOURPORT) {
2442 /* reset interrupts on the AST Fourport board */
2443 inb((port->iobase & 0xfe0) | 0x1f);
2444 port->mctrl |= TIOCM_OUT1;
2446 port->mctrl &= ~TIOCM_OUT2;
2448 serial8250_set_mctrl(port, port->mctrl);
2449 spin_unlock_irqrestore(&port->lock, flags);
2452 * Disable break condition and FIFOs
2454 serial_port_out(port, UART_LCR,
2455 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2456 serial8250_clear_fifos(up);
2458 #ifdef CONFIG_SERIAL_8250_RSA
2460 * Reset the RSA board back to 115kbps compat mode.
2466 * Read data port to reset things, and then unlink from
2469 serial_port_in(port, UART_RX);
2470 serial8250_rpm_put(up);
2472 up->ops->release_irq(up);
2474 EXPORT_SYMBOL_GPL(serial8250_do_shutdown);
2476 static void serial8250_shutdown(struct uart_port *port)
2479 port->shutdown(port);
2481 serial8250_do_shutdown(port);
2484 /* Nuvoton NPCM UARTs have a custom divisor calculation */
2485 static unsigned int npcm_get_divisor(struct uart_8250_port *up,
2488 struct uart_port *port = &up->port;
2490 return DIV_ROUND_CLOSEST(port->uartclk, 16 * baud + 2) - 2;
2493 static unsigned int serial8250_do_get_divisor(struct uart_port *port,
2497 upf_t magic_multiplier = port->flags & UPF_MAGIC_MULTIPLIER;
2498 struct uart_8250_port *up = up_to_u8250p(port);
2502 * Handle magic divisors for baud rates above baud_base on SMSC
2503 * Super I/O chips. We clamp custom rates from clk/6 and clk/12
2504 * up to clk/4 (0x8001) and clk/8 (0x8002) respectively. These
2505 * magic divisors actually reprogram the baud rate generator's
2506 * reference clock derived from chips's 14.318MHz clock input.
2508 * Documentation claims that with these magic divisors the base
2509 * frequencies of 7.3728MHz and 3.6864MHz are used respectively
2510 * for the extra baud rates of 460800bps and 230400bps rather
2511 * than the usual base frequency of 1.8462MHz. However empirical
2512 * evidence contradicts that.
2514 * Instead bit 7 of the DLM register (bit 15 of the divisor) is
2515 * effectively used as a clock prescaler selection bit for the
2516 * base frequency of 7.3728MHz, always used. If set to 0, then
2517 * the base frequency is divided by 4 for use by the Baud Rate
2518 * Generator, for the usual arrangement where the value of 1 of
2519 * the divisor produces the baud rate of 115200bps. Conversely,
2520 * if set to 1 and high-speed operation has been enabled with the
2521 * Serial Port Mode Register in the Device Configuration Space,
2522 * then the base frequency is supplied directly to the Baud Rate
2523 * Generator, so for the divisor values of 0x8001, 0x8002, 0x8003,
2524 * 0x8004, etc. the respective baud rates produced are 460800bps,
2525 * 230400bps, 153600bps, 115200bps, etc.
2527 * In all cases only low 15 bits of the divisor are used to divide
2528 * the baud base and therefore 32767 is the maximum divisor value
2529 * possible, even though documentation says that the programmable
2530 * Baud Rate Generator is capable of dividing the internal PLL
2531 * clock by any divisor from 1 to 65535.
2533 if (magic_multiplier && baud >= port->uartclk / 6)
2535 else if (magic_multiplier && baud >= port->uartclk / 12)
2537 else if (up->port.type == PORT_NPCM)
2538 quot = npcm_get_divisor(up, baud);
2540 quot = uart_get_divisor(port, baud);
2543 * Oxford Semi 952 rev B workaround
2545 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2551 static unsigned int serial8250_get_divisor(struct uart_port *port,
2555 if (port->get_divisor)
2556 return port->get_divisor(port, baud, frac);
2558 return serial8250_do_get_divisor(port, baud, frac);
2561 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up,
2566 cval = UART_LCR_WLEN(tty_get_char_size(c_cflag));
2568 if (c_cflag & CSTOPB)
2569 cval |= UART_LCR_STOP;
2570 if (c_cflag & PARENB) {
2571 cval |= UART_LCR_PARITY;
2572 if (up->bugs & UART_BUG_PARITY)
2573 up->fifo_bug = true;
2575 if (!(c_cflag & PARODD))
2576 cval |= UART_LCR_EPAR;
2577 if (c_cflag & CMSPAR)
2578 cval |= UART_LCR_SPAR;
2583 void serial8250_do_set_divisor(struct uart_port *port, unsigned int baud,
2584 unsigned int quot, unsigned int quot_frac)
2586 struct uart_8250_port *up = up_to_u8250p(port);
2588 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2589 if (is_omap1510_8250(up)) {
2590 if (baud == 115200) {
2592 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2594 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2598 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2,
2599 * otherwise just set DLAB
2601 if (up->capabilities & UART_NATSEMI)
2602 serial_port_out(port, UART_LCR, 0xe0);
2604 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB);
2606 serial_dl_write(up, quot);
2608 EXPORT_SYMBOL_GPL(serial8250_do_set_divisor);
2610 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud,
2611 unsigned int quot, unsigned int quot_frac)
2613 if (port->set_divisor)
2614 port->set_divisor(port, baud, quot, quot_frac);
2616 serial8250_do_set_divisor(port, baud, quot, quot_frac);
2619 static unsigned int serial8250_get_baud_rate(struct uart_port *port,
2620 struct ktermios *termios,
2621 const struct ktermios *old)
2623 unsigned int tolerance = port->uartclk / 100;
2628 * Handle magic divisors for baud rates above baud_base on SMSC
2629 * Super I/O chips. Enable custom rates of clk/4 and clk/8, but
2630 * disable divisor values beyond 32767, which are unavailable.
2632 if (port->flags & UPF_MAGIC_MULTIPLIER) {
2633 min = port->uartclk / 16 / UART_DIV_MAX >> 1;
2634 max = (port->uartclk + tolerance) / 4;
2636 min = port->uartclk / 16 / UART_DIV_MAX;
2637 max = (port->uartclk + tolerance) / 16;
2641 * Ask the core to calculate the divisor for us.
2642 * Allow 1% tolerance at the upper limit so uart clks marginally
2643 * slower than nominal still match standard baud rates without
2644 * causing transmission errors.
2646 return uart_get_baud_rate(port, termios, old, min, max);
2650 * Note in order to avoid the tty port mutex deadlock don't use the next method
2651 * within the uart port callbacks. Primarily it's supposed to be utilized to
2652 * handle a sudden reference clock rate change.
2654 void serial8250_update_uartclk(struct uart_port *port, unsigned int uartclk)
2656 struct uart_8250_port *up = up_to_u8250p(port);
2657 struct tty_port *tport = &port->state->port;
2658 unsigned int baud, quot, frac = 0;
2659 struct ktermios *termios;
2660 struct tty_struct *tty;
2661 unsigned long flags;
2663 tty = tty_port_tty_get(tport);
2665 mutex_lock(&tport->mutex);
2666 port->uartclk = uartclk;
2667 mutex_unlock(&tport->mutex);
2671 down_write(&tty->termios_rwsem);
2672 mutex_lock(&tport->mutex);
2674 if (port->uartclk == uartclk)
2677 port->uartclk = uartclk;
2679 if (!tty_port_initialized(tport))
2682 termios = &tty->termios;
2684 baud = serial8250_get_baud_rate(port, termios, NULL);
2685 quot = serial8250_get_divisor(port, baud, &frac);
2687 serial8250_rpm_get(up);
2688 spin_lock_irqsave(&port->lock, flags);
2690 uart_update_timeout(port, termios->c_cflag, baud);
2692 serial8250_set_divisor(port, baud, quot, frac);
2693 serial_port_out(port, UART_LCR, up->lcr);
2695 spin_unlock_irqrestore(&port->lock, flags);
2696 serial8250_rpm_put(up);
2699 mutex_unlock(&tport->mutex);
2700 up_write(&tty->termios_rwsem);
2703 EXPORT_SYMBOL_GPL(serial8250_update_uartclk);
2706 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2707 const struct ktermios *old)
2709 struct uart_8250_port *up = up_to_u8250p(port);
2711 unsigned long flags;
2712 unsigned int baud, quot, frac = 0;
2714 if (up->capabilities & UART_CAP_MINI) {
2715 termios->c_cflag &= ~(CSTOPB | PARENB | PARODD | CMSPAR);
2716 if ((termios->c_cflag & CSIZE) == CS5 ||
2717 (termios->c_cflag & CSIZE) == CS6)
2718 termios->c_cflag = (termios->c_cflag & ~CSIZE) | CS7;
2720 cval = serial8250_compute_lcr(up, termios->c_cflag);
2722 baud = serial8250_get_baud_rate(port, termios, old);
2723 quot = serial8250_get_divisor(port, baud, &frac);
2726 * Ok, we're now changing the port state. Do it with
2727 * interrupts disabled.
2729 serial8250_rpm_get(up);
2730 spin_lock_irqsave(&port->lock, flags);
2732 up->lcr = cval; /* Save computed LCR */
2734 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2735 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */
2736 if ((baud < 2400 && !up->dma) || up->fifo_bug) {
2737 up->fcr &= ~UART_FCR_TRIGGER_MASK;
2738 up->fcr |= UART_FCR_TRIGGER_1;
2743 * MCR-based auto flow control. When AFE is enabled, RTS will be
2744 * deasserted when the receive FIFO contains more characters than
2745 * the trigger, or the MCR RTS bit is cleared.
2747 if (up->capabilities & UART_CAP_AFE) {
2748 up->mcr &= ~UART_MCR_AFE;
2749 if (termios->c_cflag & CRTSCTS)
2750 up->mcr |= UART_MCR_AFE;
2754 * Update the per-port timeout.
2756 uart_update_timeout(port, termios->c_cflag, baud);
2758 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2759 if (termios->c_iflag & INPCK)
2760 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2761 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
2762 port->read_status_mask |= UART_LSR_BI;
2765 * Characters to ignore
2767 port->ignore_status_mask = 0;
2768 if (termios->c_iflag & IGNPAR)
2769 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2770 if (termios->c_iflag & IGNBRK) {
2771 port->ignore_status_mask |= UART_LSR_BI;
2773 * If we're ignoring parity and break indicators,
2774 * ignore overruns too (for real raw support).
2776 if (termios->c_iflag & IGNPAR)
2777 port->ignore_status_mask |= UART_LSR_OE;
2781 * ignore all characters if CREAD is not set
2783 if ((termios->c_cflag & CREAD) == 0)
2784 port->ignore_status_mask |= UART_LSR_DR;
2787 * CTS flow control flag and modem status interrupts
2789 up->ier &= ~UART_IER_MSI;
2790 if (!(up->bugs & UART_BUG_NOMSR) &&
2791 UART_ENABLE_MS(&up->port, termios->c_cflag))
2792 up->ier |= UART_IER_MSI;
2793 if (up->capabilities & UART_CAP_UUE)
2794 up->ier |= UART_IER_UUE;
2795 if (up->capabilities & UART_CAP_RTOIE)
2796 up->ier |= UART_IER_RTOIE;
2798 serial_port_out(port, UART_IER, up->ier);
2800 if (up->capabilities & UART_CAP_EFR) {
2801 unsigned char efr = 0;
2803 * TI16C752/Startech hardware flow control. FIXME:
2804 * - TI16C752 requires control thresholds to be set.
2805 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2807 if (termios->c_cflag & CRTSCTS)
2808 efr |= UART_EFR_CTS;
2810 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2811 if (port->flags & UPF_EXAR_EFR)
2812 serial_port_out(port, UART_XR_EFR, efr);
2814 serial_port_out(port, UART_EFR, efr);
2817 serial8250_set_divisor(port, baud, quot, frac);
2820 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2821 * is written without DLAB set, this mode will be disabled.
2823 if (port->type == PORT_16750)
2824 serial_port_out(port, UART_FCR, up->fcr);
2826 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */
2827 if (port->type != PORT_16750) {
2828 /* emulated UARTs (Lucent Venus 167x) need two steps */
2829 if (up->fcr & UART_FCR_ENABLE_FIFO)
2830 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2831 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */
2833 serial8250_set_mctrl(port, port->mctrl);
2834 spin_unlock_irqrestore(&port->lock, flags);
2835 serial8250_rpm_put(up);
2837 /* Don't rewrite B0 */
2838 if (tty_termios_baud_rate(termios))
2839 tty_termios_encode_baud_rate(termios, baud, baud);
2841 EXPORT_SYMBOL(serial8250_do_set_termios);
2844 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2845 const struct ktermios *old)
2847 if (port->set_termios)
2848 port->set_termios(port, termios, old);
2850 serial8250_do_set_termios(port, termios, old);
2853 void serial8250_do_set_ldisc(struct uart_port *port, struct ktermios *termios)
2855 if (termios->c_line == N_PPS) {
2856 port->flags |= UPF_HARDPPS_CD;
2857 spin_lock_irq(&port->lock);
2858 serial8250_enable_ms(port);
2859 spin_unlock_irq(&port->lock);
2861 port->flags &= ~UPF_HARDPPS_CD;
2862 if (!UART_ENABLE_MS(port, termios->c_cflag)) {
2863 spin_lock_irq(&port->lock);
2864 serial8250_disable_ms(port);
2865 spin_unlock_irq(&port->lock);
2869 EXPORT_SYMBOL_GPL(serial8250_do_set_ldisc);
2872 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios)
2874 if (port->set_ldisc)
2875 port->set_ldisc(port, termios);
2877 serial8250_do_set_ldisc(port, termios);
2880 void serial8250_do_pm(struct uart_port *port, unsigned int state,
2881 unsigned int oldstate)
2883 struct uart_8250_port *p = up_to_u8250p(port);
2885 serial8250_set_sleep(p, state != 0);
2887 EXPORT_SYMBOL(serial8250_do_pm);
2890 serial8250_pm(struct uart_port *port, unsigned int state,
2891 unsigned int oldstate)
2894 port->pm(port, state, oldstate);
2896 serial8250_do_pm(port, state, oldstate);
2899 static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2901 if (pt->port.mapsize)
2902 return pt->port.mapsize;
2903 if (is_omap1_8250(pt))
2904 return 0x16 << pt->port.regshift;
2906 return 8 << pt->port.regshift;
2910 * Resource handling.
2912 static int serial8250_request_std_resource(struct uart_8250_port *up)
2914 unsigned int size = serial8250_port_size(up);
2915 struct uart_port *port = &up->port;
2918 switch (port->iotype) {
2925 if (!port->mapbase) {
2930 if (!request_mem_region(port->mapbase, size, "serial")) {
2935 if (port->flags & UPF_IOREMAP) {
2936 port->membase = ioremap(port->mapbase, size);
2937 if (!port->membase) {
2938 release_mem_region(port->mapbase, size);
2946 if (!request_region(port->iobase, size, "serial"))
2953 static void serial8250_release_std_resource(struct uart_8250_port *up)
2955 unsigned int size = serial8250_port_size(up);
2956 struct uart_port *port = &up->port;
2958 switch (port->iotype) {
2968 if (port->flags & UPF_IOREMAP) {
2969 iounmap(port->membase);
2970 port->membase = NULL;
2973 release_mem_region(port->mapbase, size);
2978 release_region(port->iobase, size);
2983 static void serial8250_release_port(struct uart_port *port)
2985 struct uart_8250_port *up = up_to_u8250p(port);
2987 serial8250_release_std_resource(up);
2990 static int serial8250_request_port(struct uart_port *port)
2992 struct uart_8250_port *up = up_to_u8250p(port);
2994 return serial8250_request_std_resource(up);
2997 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up)
2999 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3000 unsigned char bytes;
3002 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)];
3004 return bytes ? bytes : -EOPNOTSUPP;
3007 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes)
3009 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3012 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)])
3015 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) {
3016 if (bytes < conf_type->rxtrig_bytes[i])
3017 /* Use the nearest lower value */
3018 return (--i) << UART_FCR_R_TRIG_SHIFT;
3021 return UART_FCR_R_TRIG_11;
3024 static int do_get_rxtrig(struct tty_port *port)
3026 struct uart_state *state = container_of(port, struct uart_state, port);
3027 struct uart_port *uport = state->uart_port;
3028 struct uart_8250_port *up = up_to_u8250p(uport);
3030 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1)
3033 return fcr_get_rxtrig_bytes(up);
3036 static int do_serial8250_get_rxtrig(struct tty_port *port)
3040 mutex_lock(&port->mutex);
3041 rxtrig_bytes = do_get_rxtrig(port);
3042 mutex_unlock(&port->mutex);
3044 return rxtrig_bytes;
3047 static ssize_t rx_trig_bytes_show(struct device *dev,
3048 struct device_attribute *attr, char *buf)
3050 struct tty_port *port = dev_get_drvdata(dev);
3053 rxtrig_bytes = do_serial8250_get_rxtrig(port);
3054 if (rxtrig_bytes < 0)
3055 return rxtrig_bytes;
3057 return sysfs_emit(buf, "%d\n", rxtrig_bytes);
3060 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes)
3062 struct uart_state *state = container_of(port, struct uart_state, port);
3063 struct uart_port *uport = state->uart_port;
3064 struct uart_8250_port *up = up_to_u8250p(uport);
3067 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 ||
3071 rxtrig = bytes_to_fcr_rxtrig(up, bytes);
3075 serial8250_clear_fifos(up);
3076 up->fcr &= ~UART_FCR_TRIGGER_MASK;
3077 up->fcr |= (unsigned char)rxtrig;
3078 serial_out(up, UART_FCR, up->fcr);
3082 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes)
3086 mutex_lock(&port->mutex);
3087 ret = do_set_rxtrig(port, bytes);
3088 mutex_unlock(&port->mutex);
3093 static ssize_t rx_trig_bytes_store(struct device *dev,
3094 struct device_attribute *attr, const char *buf, size_t count)
3096 struct tty_port *port = dev_get_drvdata(dev);
3097 unsigned char bytes;
3103 ret = kstrtou8(buf, 10, &bytes);
3107 ret = do_serial8250_set_rxtrig(port, bytes);
3114 static DEVICE_ATTR_RW(rx_trig_bytes);
3116 static struct attribute *serial8250_dev_attrs[] = {
3117 &dev_attr_rx_trig_bytes.attr,
3121 static struct attribute_group serial8250_dev_attr_group = {
3122 .attrs = serial8250_dev_attrs,
3125 static void register_dev_spec_attr_grp(struct uart_8250_port *up)
3127 const struct serial8250_config *conf_type = &uart_config[up->port.type];
3129 if (conf_type->rxtrig_bytes[0])
3130 up->port.attr_group = &serial8250_dev_attr_group;
3133 static void serial8250_config_port(struct uart_port *port, int flags)
3135 struct uart_8250_port *up = up_to_u8250p(port);
3139 * Find the region that we can probe for. This in turn
3140 * tells us whether we can probe for the type of port.
3142 ret = serial8250_request_std_resource(up);
3146 if (port->iotype != up->cur_iotype)
3147 set_io_from_upio(port);
3149 if (flags & UART_CONFIG_TYPE)
3152 /* HW bugs may trigger IRQ while IIR == NO_INT */
3153 if (port->type == PORT_TEGRA)
3154 up->bugs |= UART_BUG_NOMSR;
3156 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
3159 if (port->type == PORT_UNKNOWN)
3160 serial8250_release_std_resource(up);
3162 register_dev_spec_attr_grp(up);
3163 up->fcr = uart_config[up->port.type].fcr;
3167 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
3169 if (ser->irq >= nr_irqs || ser->irq < 0 ||
3170 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
3171 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
3172 ser->type == PORT_STARTECH)
3177 static const char *serial8250_type(struct uart_port *port)
3179 int type = port->type;
3181 if (type >= ARRAY_SIZE(uart_config))
3183 return uart_config[type].name;
3186 static const struct uart_ops serial8250_pops = {
3187 .tx_empty = serial8250_tx_empty,
3188 .set_mctrl = serial8250_set_mctrl,
3189 .get_mctrl = serial8250_get_mctrl,
3190 .stop_tx = serial8250_stop_tx,
3191 .start_tx = serial8250_start_tx,
3192 .throttle = serial8250_throttle,
3193 .unthrottle = serial8250_unthrottle,
3194 .stop_rx = serial8250_stop_rx,
3195 .enable_ms = serial8250_enable_ms,
3196 .break_ctl = serial8250_break_ctl,
3197 .startup = serial8250_startup,
3198 .shutdown = serial8250_shutdown,
3199 .set_termios = serial8250_set_termios,
3200 .set_ldisc = serial8250_set_ldisc,
3201 .pm = serial8250_pm,
3202 .type = serial8250_type,
3203 .release_port = serial8250_release_port,
3204 .request_port = serial8250_request_port,
3205 .config_port = serial8250_config_port,
3206 .verify_port = serial8250_verify_port,
3207 #ifdef CONFIG_CONSOLE_POLL
3208 .poll_get_char = serial8250_get_poll_char,
3209 .poll_put_char = serial8250_put_poll_char,
3213 void serial8250_init_port(struct uart_8250_port *up)
3215 struct uart_port *port = &up->port;
3217 spin_lock_init(&port->lock);
3218 port->ops = &serial8250_pops;
3219 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
3221 up->cur_iotype = 0xFF;
3223 EXPORT_SYMBOL_GPL(serial8250_init_port);
3225 void serial8250_set_defaults(struct uart_8250_port *up)
3227 struct uart_port *port = &up->port;
3229 if (up->port.flags & UPF_FIXED_TYPE) {
3230 unsigned int type = up->port.type;
3232 if (!up->port.fifosize)
3233 up->port.fifosize = uart_config[type].fifo_size;
3235 up->tx_loadsz = uart_config[type].tx_loadsz;
3236 if (!up->capabilities)
3237 up->capabilities = uart_config[type].flags;
3240 set_io_from_upio(port);
3242 /* default dma handlers */
3244 if (!up->dma->tx_dma)
3245 up->dma->tx_dma = serial8250_tx_dma;
3246 if (!up->dma->rx_dma)
3247 up->dma->rx_dma = serial8250_rx_dma;
3250 EXPORT_SYMBOL_GPL(serial8250_set_defaults);
3252 #ifdef CONFIG_SERIAL_8250_CONSOLE
3254 static void serial8250_console_putchar(struct uart_port *port, unsigned char ch)
3256 struct uart_8250_port *up = up_to_u8250p(port);
3258 wait_for_xmitr(up, UART_LSR_THRE);
3259 serial_port_out(port, UART_TX, ch);
3263 * Restore serial console when h/w power-off detected
3265 static void serial8250_console_restore(struct uart_8250_port *up)
3267 struct uart_port *port = &up->port;
3268 struct ktermios termios;
3269 unsigned int baud, quot, frac = 0;
3271 termios.c_cflag = port->cons->cflag;
3272 termios.c_ispeed = port->cons->ispeed;
3273 termios.c_ospeed = port->cons->ospeed;
3274 if (port->state->port.tty && termios.c_cflag == 0) {
3275 termios.c_cflag = port->state->port.tty->termios.c_cflag;
3276 termios.c_ispeed = port->state->port.tty->termios.c_ispeed;
3277 termios.c_ospeed = port->state->port.tty->termios.c_ospeed;
3280 baud = serial8250_get_baud_rate(port, &termios, NULL);
3281 quot = serial8250_get_divisor(port, baud, &frac);
3283 serial8250_set_divisor(port, baud, quot, frac);
3284 serial_port_out(port, UART_LCR, up->lcr);
3285 serial8250_out_MCR(up, up->mcr | UART_MCR_DTR | UART_MCR_RTS);
3289 * Print a string to the serial port using the device FIFO
3291 * It sends fifosize bytes and then waits for the fifo
3294 static void serial8250_console_fifo_write(struct uart_8250_port *up,
3295 const char *s, unsigned int count)
3298 const char *end = s + count;
3299 unsigned int fifosize = up->tx_loadsz;
3300 bool cr_sent = false;
3303 wait_for_lsr(up, UART_LSR_THRE);
3305 for (i = 0; i < fifosize && s != end; ++i) {
3306 if (*s == '\n' && !cr_sent) {
3307 serial_out(up, UART_TX, '\r');
3310 serial_out(up, UART_TX, *s++);
3318 * Print a string to the serial port trying not to disturb
3319 * any possible real use of the port...
3321 * The console_lock must be held when we get here.
3323 * Doing runtime PM is really a bad idea for the kernel console.
3324 * Thus, we assume the function is called when device is powered up.
3326 void serial8250_console_write(struct uart_8250_port *up, const char *s,
3329 struct uart_8250_em485 *em485 = up->em485;
3330 struct uart_port *port = &up->port;
3331 unsigned long flags;
3332 unsigned int ier, use_fifo;
3335 touch_nmi_watchdog();
3337 if (oops_in_progress)
3338 locked = spin_trylock_irqsave(&port->lock, flags);
3340 spin_lock_irqsave(&port->lock, flags);
3343 * First save the IER then disable the interrupts
3345 ier = serial_port_in(port, UART_IER);
3346 serial8250_clear_IER(up);
3348 /* check scratch reg to see if port powered off during system sleep */
3349 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) {
3350 serial8250_console_restore(up);
3355 if (em485->tx_stopped)
3356 up->rs485_start_tx(up);
3357 mdelay(port->rs485.delay_rts_before_send);
3360 use_fifo = (up->capabilities & UART_CAP_FIFO) &&
3362 * BCM283x requires to check the fifo
3365 !(up->capabilities & UART_CAP_MINI) &&
3367 * tx_loadsz contains the transmit fifo size
3369 up->tx_loadsz > 1 &&
3370 (up->fcr & UART_FCR_ENABLE_FIFO) &&
3372 test_bit(TTY_PORT_INITIALIZED, &port->state->port.iflags) &&
3374 * After we put a data in the fifo, the controller will send
3375 * it regardless of the CTS state. Therefore, only use fifo
3376 * if we don't use control flow.
3378 !(up->port.flags & UPF_CONS_FLOW);
3380 if (likely(use_fifo))
3381 serial8250_console_fifo_write(up, s, count);
3383 uart_console_write(port, s, count, serial8250_console_putchar);
3386 * Finally, wait for transmitter to become empty
3387 * and restore the IER
3389 wait_for_xmitr(up, UART_LSR_BOTH_EMPTY);
3392 mdelay(port->rs485.delay_rts_after_send);
3393 if (em485->tx_stopped)
3394 up->rs485_stop_tx(up);
3397 serial_port_out(port, UART_IER, ier);
3400 * The receive handling will happen properly because the
3401 * receive ready bit will still be set; it is not cleared
3402 * on read. However, modem control will not, we must
3403 * call it if we have saved something in the saved flags
3404 * while processing with interrupts off.
3406 if (up->msr_saved_flags)
3407 serial8250_modem_status(up);
3410 spin_unlock_irqrestore(&port->lock, flags);
3413 static unsigned int probe_baud(struct uart_port *port)
3415 unsigned char lcr, dll, dlm;
3418 lcr = serial_port_in(port, UART_LCR);
3419 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB);
3420 dll = serial_port_in(port, UART_DLL);
3421 dlm = serial_port_in(port, UART_DLM);
3422 serial_port_out(port, UART_LCR, lcr);
3424 quot = (dlm << 8) | dll;
3425 return (port->uartclk / 16) / quot;
3428 int serial8250_console_setup(struct uart_port *port, char *options, bool probe)
3436 if (!port->iobase && !port->membase)
3440 uart_parse_options(options, &baud, &parity, &bits, &flow);
3442 baud = probe_baud(port);
3444 ret = uart_set_options(port, port->cons, baud, parity, bits, flow);
3449 pm_runtime_get_sync(port->dev);
3454 int serial8250_console_exit(struct uart_port *port)
3457 pm_runtime_put_sync(port->dev);
3462 #endif /* CONFIG_SERIAL_8250_CONSOLE */
3464 MODULE_LICENSE("GPL");