drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/8250_pci.h>
  23 #include <linux/bitops.h>
  24
  25 #include <asm/byteorder.h>
  26 #include <asm/io.h>
  27
  28 #include "8250.h"
  29
  30 #undef SERIAL_DEBUG_PCI
  31
  32 /*
  33  * init function returns:
  34  *  > 0 - number of ports
  35  *  = 0 - use board->num_ports
  36  *  < 0 - error
  37  */
  38 struct pci_serial_quirk {
  39         u32     vendor;
  40         u32     device;
  41         u32     subvendor;
  42         u32     subdevice;
  43         int     (*probe)(struct pci_dev *dev);
  44         int     (*init)(struct pci_dev *dev);
  45         int     (*setup)(struct serial_private *,
  46                          const struct pciserial_board *,
  47                          struct uart_8250_port *, int);
  48         void    (*exit)(struct pci_dev *dev);
  49 };
  50
  51 #define PCI_NUM_BAR_RESOURCES   6
  52
  53 struct serial_private {
  54         struct pci_dev          *dev;
  55         unsigned int            nr;
  56         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  57         struct pci_serial_quirk *quirk;
  58         int                     line[0];
  59 };
  60
  61 static int pci_default_setup(struct serial_private*,
  62           const struct pciserial_board*, struct uart_8250_port *, int);
  63
  64 static void moan_device(const char *str, struct pci_dev *dev)
  65 {
  66         printk(KERN_WARNING
  67                "%s: %s\n"
  68                "Please send the output of lspci -vv, this\n"
  69                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  70                "manufacturer and name of serial board or\n"
  71                "modem board to rmk+serial@arm.linux.org.uk.\n",
  72                pci_name(dev), str, dev->vendor, dev->device,
  73                dev->subsystem_vendor, dev->subsystem_device);
  74 }
  75
  76 static int
  77 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  78            int bar, int offset, int regshift)
  79 {
  80         struct pci_dev *dev = priv->dev;
  81         unsigned long base, len;
  82
  83         if (bar >= PCI_NUM_BAR_RESOURCES)
  84                 return -EINVAL;
  85
  86         base = pci_resource_start(dev, bar);
  87
  88         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  89                 len =  pci_resource_len(dev, bar);
  90
  91                 if (!priv->remapped_bar[bar])
  92                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  93                 if (!priv->remapped_bar[bar])
  94                         return -ENOMEM;
  95
  96                 port->port.iotype = UPIO_MEM;
  97                 port->port.iobase = 0;
  98                 port->port.mapbase = base + offset;
  99                 port->port.membase = priv->remapped_bar[bar] + offset;
 100                 port->port.regshift = regshift;
 101         } else {
 102                 port->port.iotype = UPIO_PORT;
 103                 port->port.iobase = base + offset;
 104                 port->port.mapbase = 0;
 105                 port->port.membase = NULL;
 106                 port->port.regshift = 0;
 107         }
 108         return 0;
 109 }
 110
 111 /*
 112  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 113  */
 114 static int addidata_apci7800_setup(struct serial_private *priv,
 115                                 const struct pciserial_board *board,
 116                                 struct uart_8250_port *port, int idx)
 117 {
 118         unsigned int bar = 0, offset = board->first_offset;
 119         bar = FL_GET_BASE(board->flags);
 120
 121         if (idx < 2) {
 122                 offset += idx * board->uart_offset;
 123         } else if ((idx >= 2) && (idx < 4)) {
 124                 bar += 1;
 125                 offset += ((idx - 2) * board->uart_offset);
 126         } else if ((idx >= 4) && (idx < 6)) {
 127                 bar += 2;
 128                 offset += ((idx - 4) * board->uart_offset);
 129         } else if (idx >= 6) {
 130                 bar += 3;
 131                 offset += ((idx - 6) * board->uart_offset);
 132         }
 133
 134         return setup_port(priv, port, bar, offset, board->reg_shift);
 135 }
 136
 137 /*
 138  * AFAVLAB uses a different mixture of BARs and offsets
 139  * Not that ugly ;) -- HW
 140  */
 141 static int
 142 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 143               struct uart_8250_port *port, int idx)
 144 {
 145         unsigned int bar, offset = board->first_offset;
 146
 147         bar = FL_GET_BASE(board->flags);
 148         if (idx < 4)
 149                 bar += idx;
 150         else {
 151                 bar = 4;
 152                 offset += (idx - 4) * board->uart_offset;
 153         }
 154
 155         return setup_port(priv, port, bar, offset, board->reg_shift);
 156 }
 157
 158 /*
 159  * HP's Remote Management Console.  The Diva chip came in several
 160  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 161  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 162  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 163  * one Diva chip, but it has been expanded to 5 UARTs.
 164  */
 165 static int pci_hp_diva_init(struct pci_dev *dev)
 166 {
 167         int rc = 0;
 168
 169         switch (dev->subsystem_device) {
 170         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 171         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 172         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 173         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 174                 rc = 3;
 175                 break;
 176         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 177                 rc = 2;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 180                 rc = 4;
 181                 break;
 182         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 183         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 184                 rc = 1;
 185                 break;
 186         }
 187
 188         return rc;
 189 }
 190
 191 /*
 192  * HP's Diva chip puts the 4th/5th serial port further out, and
 193  * some serial ports are supposed to be hidden on certain models.
 194  */
 195 static int
 196 pci_hp_diva_setup(struct serial_private *priv,
 197                 const struct pciserial_board *board,
 198                 struct uart_8250_port *port, int idx)
 199 {
 200         unsigned int offset = board->first_offset;
 201         unsigned int bar = FL_GET_BASE(board->flags);
 202
 203         switch (priv->dev->subsystem_device) {
 204         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 205                 if (idx == 3)
 206                         idx++;
 207                 break;
 208         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 209                 if (idx > 0)
 210                         idx++;
 211                 if (idx > 2)
 212                         idx++;
 213                 break;
 214         }
 215         if (idx > 2)
 216                 offset = 0x18;
 217
 218         offset += idx * board->uart_offset;
 219
 220         return setup_port(priv, port, bar, offset, board->reg_shift);
 221 }
 222
 223 /*
 224  * Added for EKF Intel i960 serial boards
 225  */
 226 static int pci_inteli960ni_init(struct pci_dev *dev)
 227 {
 228         unsigned long oldval;
 229
 230         if (!(dev->subsystem_device & 0x1000))
 231                 return -ENODEV;
 232
 233         /* is firmware started? */
 234         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 235         if (oldval == 0x00001000L) { /* RESET value */
 236                 printk(KERN_DEBUG "Local i960 firmware missing");
 237                 return -ENODEV;
 238         }
 239         return 0;
 240 }
 241
 242 /*
 243  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 244  * that the card interrupt be explicitly enabled or disabled.  This
 245  * seems to be mainly needed on card using the PLX which also use I/O
 246  * mapped memory.
 247  */
 248 static int pci_plx9050_init(struct pci_dev *dev)
 249 {
 250         u8 irq_config;
 251         void __iomem *p;
 252
 253         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 254                 moan_device("no memory in bar 0", dev);
 255                 return 0;
 256         }
 257
 258         irq_config = 0x41;
 259         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 260             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 261                 irq_config = 0x43;
 262
 263         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 264             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 265                 /*
 266                  * As the megawolf cards have the int pins active
 267                  * high, and have 2 UART chips, both ints must be
 268                  * enabled on the 9050. Also, the UARTS are set in
 269                  * 16450 mode by default, so we have to enable the
 270                  * 16C950 'enhanced' mode so that we can use the
 271                  * deep FIFOs
 272                  */
 273                 irq_config = 0x5b;
 274         /*
 275          * enable/disable interrupts
 276          */
 277         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 278         if (p == NULL)
 279                 return -ENOMEM;
 280         writel(irq_config, p + 0x4c);
 281
 282         /*
 283          * Read the register back to ensure that it took effect.
 284          */
 285         readl(p + 0x4c);
 286         iounmap(p);
 287
 288         return 0;
 289 }
 290
 291 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
 292 {
 293         u8 __iomem *p;
 294
 295         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 296                 return;
 297
 298         /*
 299          * disable interrupts
 300          */
 301         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 302         if (p != NULL) {
 303                 writel(0, p + 0x4c);
 304
 305                 /*
 306                  * Read the register back to ensure that it took effect.
 307                  */
 308                 readl(p + 0x4c);
 309                 iounmap(p);
 310         }
 311 }
 312
 313 #define NI8420_INT_ENABLE_REG   0x38
 314 #define NI8420_INT_ENABLE_BIT   0x2000
 315
 316 static void __devexit pci_ni8420_exit(struct pci_dev *dev)
 317 {
 318         void __iomem *p;
 319         unsigned long base, len;
 320         unsigned int bar = 0;
 321
 322         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 323                 moan_device("no memory in bar", dev);
 324                 return;
 325         }
 326
 327         base = pci_resource_start(dev, bar);
 328         len =  pci_resource_len(dev, bar);
 329         p = ioremap_nocache(base, len);
 330         if (p == NULL)
 331                 return;
 332
 333         /* Disable the CPU Interrupt */
 334         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 335                p + NI8420_INT_ENABLE_REG);
 336         iounmap(p);
 337 }
 338
 339
 340 /* MITE registers */
 341 #define MITE_IOWBSR1    0xc4
 342 #define MITE_IOWCR1     0xf4
 343 #define MITE_LCIMR1     0x08
 344 #define MITE_LCIMR2     0x10
 345
 346 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 347
 348 static void __devexit pci_ni8430_exit(struct pci_dev *dev)
 349 {
 350         void __iomem *p;
 351         unsigned long base, len;
 352         unsigned int bar = 0;
 353
 354         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 355                 moan_device("no memory in bar", dev);
 356                 return;
 357         }
 358
 359         base = pci_resource_start(dev, bar);
 360         len =  pci_resource_len(dev, bar);
 361         p = ioremap_nocache(base, len);
 362         if (p == NULL)
 363                 return;
 364
 365         /* Disable the CPU Interrupt */
 366         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 367         iounmap(p);
 368 }
 369
 370 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 371 static int
 372 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 373                 struct uart_8250_port *port, int idx)
 374 {
 375         unsigned int bar, offset = board->first_offset;
 376
 377         bar = 0;
 378
 379         if (idx < 4) {
 380                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 381                 offset += idx * board->uart_offset;
 382         } else if (idx < 8) {
 383                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 384                 offset += idx * board->uart_offset + 0xC00;
 385         } else /* we have only 8 ports on PMC-OCTALPRO */
 386                 return 1;
 387
 388         return setup_port(priv, port, bar, offset, board->reg_shift);
 389 }
 390
 391 /*
 392 * This does initialization for PMC OCTALPRO cards:
 393 * maps the device memory, resets the UARTs (needed, bc
 394 * if the module is removed and inserted again, the card
 395 * is in the sleep mode) and enables global interrupt.
 396 */
 397
 398 /* global control register offset for SBS PMC-OctalPro */
 399 #define OCT_REG_CR_OFF          0x500
 400
 401 static int sbs_init(struct pci_dev *dev)
 402 {
 403         u8 __iomem *p;
 404
 405         p = pci_ioremap_bar(dev, 0);
 406
 407         if (p == NULL)
 408                 return -ENOMEM;
 409         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 410         writeb(0x10, p + OCT_REG_CR_OFF);
 411         udelay(50);
 412         writeb(0x0, p + OCT_REG_CR_OFF);
 413
 414         /* Set bit-2 (INTENABLE) of Control Register */
 415         writeb(0x4, p + OCT_REG_CR_OFF);
 416         iounmap(p);
 417
 418         return 0;
 419 }
 420
 421 /*
 422  * Disables the global interrupt of PMC-OctalPro
 423  */
 424
 425 static void __devexit sbs_exit(struct pci_dev *dev)
 426 {
 427         u8 __iomem *p;
 428
 429         p = pci_ioremap_bar(dev, 0);
 430         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 431         if (p != NULL)
 432                 writeb(0, p + OCT_REG_CR_OFF);
 433         iounmap(p);
 434 }
 435
 436 /*
 437  * SIIG serial cards have an PCI interface chip which also controls
 438  * the UART clocking frequency. Each UART can be clocked independently
 439  * (except cards equipped with 4 UARTs) and initial clocking settings
 440  * are stored in the EEPROM chip. It can cause problems because this
 441  * version of serial driver doesn't support differently clocked UART's
 442  * on single PCI card. To prevent this, initialization functions set
 443  * high frequency clocking for all UART's on given card. It is safe (I
 444  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 445  * with other OSes (like M$ DOS).
 446  *
 447  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 448  *
 449  * There is two family of SIIG serial cards with different PCI
 450  * interface chip and different configuration methods:
 451  *     - 10x cards have control registers in IO and/or memory space;
 452  *     - 20x cards have control registers in standard PCI configuration space.
 453  *
 454  * Note: all 10x cards have PCI device ids 0x10..
 455  *       all 20x cards have PCI device ids 0x20..
 456  *
 457  * There are also Quartet Serial cards which use Oxford Semiconductor
 458  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 459  *
 460  * Note: some SIIG cards are probed by the parport_serial object.
 461  */
 462
 463 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 464 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 465
 466 static int pci_siig10x_init(struct pci_dev *dev)
 467 {
 468         u16 data;
 469         void __iomem *p;
 470
 471         switch (dev->device & 0xfff8) {
 472         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 473                 data = 0xffdf;
 474                 break;
 475         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 476                 data = 0xf7ff;
 477                 break;
 478         default:                        /* 1S1P, 4S */
 479                 data = 0xfffb;
 480                 break;
 481         }
 482
 483         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 484         if (p == NULL)
 485                 return -ENOMEM;
 486
 487         writew(readw(p + 0x28) & data, p + 0x28);
 488         readw(p + 0x28);
 489         iounmap(p);
 490         return 0;
 491 }
 492
 493 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 494 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 495
 496 static int pci_siig20x_init(struct pci_dev *dev)
 497 {
 498         u8 data;
 499
 500         /* Change clock frequency for the first UART. */
 501         pci_read_config_byte(dev, 0x6f, &data);
 502         pci_write_config_byte(dev, 0x6f, data & 0xef);
 503
 504         /* If this card has 2 UART, we have to do the same with second UART. */
 505         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 506             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 507                 pci_read_config_byte(dev, 0x73, &data);
 508                 pci_write_config_byte(dev, 0x73, data & 0xef);
 509         }
 510         return 0;
 511 }
 512
 513 static int pci_siig_init(struct pci_dev *dev)
 514 {
 515         unsigned int type = dev->device & 0xff00;
 516
 517         if (type == 0x1000)
 518                 return pci_siig10x_init(dev);
 519         else if (type == 0x2000)
 520                 return pci_siig20x_init(dev);
 521
 522         moan_device("Unknown SIIG card", dev);
 523         return -ENODEV;
 524 }
 525
 526 static int pci_siig_setup(struct serial_private *priv,
 527                           const struct pciserial_board *board,
 528                           struct uart_8250_port *port, int idx)
 529 {
 530         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 531
 532         if (idx > 3) {
 533                 bar = 4;
 534                 offset = (idx - 4) * 8;
 535         }
 536
 537         return setup_port(priv, port, bar, offset, 0);
 538 }
 539
 540 /*
 541  * Timedia has an explosion of boards, and to avoid the PCI table from
 542  * growing *huge*, we use this function to collapse some 70 entries
 543  * in the PCI table into one, for sanity's and compactness's sake.
 544  */
 545 static const unsigned short timedia_single_port[] = {
 546         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 547 };
 548
 549 static const unsigned short timedia_dual_port[] = {
 550         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 551         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 552         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 553         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 554         0xD079, 0
 555 };
 556
 557 static const unsigned short timedia_quad_port[] = {
 558         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 559         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 560         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 561         0xB157, 0
 562 };
 563
 564 static const unsigned short timedia_eight_port[] = {
 565         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 566         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 567 };
 568
 569 static const struct timedia_struct {
 570         int num;
 571         const unsigned short *ids;
 572 } timedia_data[] = {
 573         { 1, timedia_single_port },
 574         { 2, timedia_dual_port },
 575         { 4, timedia_quad_port },
 576         { 8, timedia_eight_port }
 577 };
 578
 579 /*
 580  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 581  * listing them individually, this driver merely grabs them all with
 582  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 583  * and should be left free to be claimed by parport_serial instead.
 584  */
 585 static int pci_timedia_probe(struct pci_dev *dev)
 586 {
 587         /*
 588          * Check the third digit of the subdevice ID
 589          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 590          */
 591         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 592                 dev_info(&dev->dev,
 593                         "ignoring Timedia subdevice %04x for parport_serial\n",
 594                         dev->subsystem_device);
 595                 return -ENODEV;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static int pci_timedia_init(struct pci_dev *dev)
 602 {
 603         const unsigned short *ids;
 604         int i, j;
 605
 606         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 607                 ids = timedia_data[i].ids;
 608                 for (j = 0; ids[j]; j++)
 609                         if (dev->subsystem_device == ids[j])
 610                                 return timedia_data[i].num;
 611         }
 612         return 0;
 613 }
 614
 615 /*
 616  * Timedia/SUNIX uses a mixture of BARs and offsets
 617  * Ugh, this is ugly as all hell --- TYT
 618  */
 619 static int
 620 pci_timedia_setup(struct serial_private *priv,
 621                   const struct pciserial_board *board,
 622                   struct uart_8250_port *port, int idx)
 623 {
 624         unsigned int bar = 0, offset = board->first_offset;
 625
 626         switch (idx) {
 627         case 0:
 628                 bar = 0;
 629                 break;
 630         case 1:
 631                 offset = board->uart_offset;
 632                 bar = 0;
 633                 break;
 634         case 2:
 635                 bar = 1;
 636                 break;
 637         case 3:
 638                 offset = board->uart_offset;
 639                 /* FALLTHROUGH */
 640         case 4: /* BAR 2 */
 641         case 5: /* BAR 3 */
 642         case 6: /* BAR 4 */
 643         case 7: /* BAR 5 */
 644                 bar = idx - 2;
 645         }
 646
 647         return setup_port(priv, port, bar, offset, board->reg_shift);
 648 }
 649
 650 /*
 651  * Some Titan cards are also a little weird
 652  */
 653 static int
 654 titan_400l_800l_setup(struct serial_private *priv,
 655                       const struct pciserial_board *board,
 656                       struct uart_8250_port *port, int idx)
 657 {
 658         unsigned int bar, offset = board->first_offset;
 659
 660         switch (idx) {
 661         case 0:
 662                 bar = 1;
 663                 break;
 664         case 1:
 665                 bar = 2;
 666                 break;
 667         default:
 668                 bar = 4;
 669                 offset = (idx - 2) * board->uart_offset;
 670         }
 671
 672         return setup_port(priv, port, bar, offset, board->reg_shift);
 673 }
 674
 675 static int pci_xircom_init(struct pci_dev *dev)
 676 {
 677         msleep(100);
 678         return 0;
 679 }
 680
 681 static int pci_ni8420_init(struct pci_dev *dev)
 682 {
 683         void __iomem *p;
 684         unsigned long base, len;
 685         unsigned int bar = 0;
 686
 687         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 688                 moan_device("no memory in bar", dev);
 689                 return 0;
 690         }
 691
 692         base = pci_resource_start(dev, bar);
 693         len =  pci_resource_len(dev, bar);
 694         p = ioremap_nocache(base, len);
 695         if (p == NULL)
 696                 return -ENOMEM;
 697
 698         /* Enable CPU Interrupt */
 699         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 700                p + NI8420_INT_ENABLE_REG);
 701
 702         iounmap(p);
 703         return 0;
 704 }
 705
 706 #define MITE_IOWBSR1_WSIZE      0xa
 707 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 708 #define MITE_IOWBSR1_WENAB      (1 << 7)
 709 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 710 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 711 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 712
 713 static int pci_ni8430_init(struct pci_dev *dev)
 714 {
 715         void __iomem *p;
 716         unsigned long base, len;
 717         u32 device_window;
 718         unsigned int bar = 0;
 719
 720         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 721                 moan_device("no memory in bar", dev);
 722                 return 0;
 723         }
 724
 725         base = pci_resource_start(dev, bar);
 726         len =  pci_resource_len(dev, bar);
 727         p = ioremap_nocache(base, len);
 728         if (p == NULL)
 729                 return -ENOMEM;
 730
 731         /* Set device window address and size in BAR0 */
 732         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 733                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 734         writel(device_window, p + MITE_IOWBSR1);
 735
 736         /* Set window access to go to RAMSEL IO address space */
 737         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 738                p + MITE_IOWCR1);
 739
 740         /* Enable IO Bus Interrupt 0 */
 741         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 742
 743         /* Enable CPU Interrupt */
 744         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 745
 746         iounmap(p);
 747         return 0;
 748 }
 749
 750 /* UART Port Control Register */
 751 #define NI8430_PORTCON  0x0f
 752 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 753
 754 static int
 755 pci_ni8430_setup(struct serial_private *priv,
 756                  const struct pciserial_board *board,
 757                  struct uart_8250_port *port, int idx)
 758 {
 759         void __iomem *p;
 760         unsigned long base, len;
 761         unsigned int bar, offset = board->first_offset;
 762
 763         if (idx >= board->num_ports)
 764                 return 1;
 765
 766         bar = FL_GET_BASE(board->flags);
 767         offset += idx * board->uart_offset;
 768
 769         base = pci_resource_start(priv->dev, bar);
 770         len =  pci_resource_len(priv->dev, bar);
 771         p = ioremap_nocache(base, len);
 772
 773         /* enable the transceiver */
 774         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 775                p + offset + NI8430_PORTCON);
 776
 777         iounmap(p);
 778
 779         return setup_port(priv, port, bar, offset, board->reg_shift);
 780 }
 781
 782 static int pci_netmos_9900_setup(struct serial_private *priv,
 783                                 const struct pciserial_board *board,
 784                                 struct uart_8250_port *port, int idx)
 785 {
 786         unsigned int bar;
 787
 788         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
 789                 /* netmos apparently orders BARs by datasheet layout, so serial
 790                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 791                  */
 792                 bar = 3 * idx;
 793
 794                 return setup_port(priv, port, bar, 0, board->reg_shift);
 795         } else {
 796                 return pci_default_setup(priv, board, port, idx);
 797         }
 798 }
 799
 800 /* the 99xx series comes with a range of device IDs and a variety
 801  * of capabilities:
 802  *
 803  * 9900 has varying capabilities and can cascade to sub-controllers
 804  *   (cascading should be purely internal)
 805  * 9904 is hardwired with 4 serial ports
 806  * 9912 and 9922 are hardwired with 2 serial ports
 807  */
 808 static int pci_netmos_9900_numports(struct pci_dev *dev)
 809 {
 810         unsigned int c = dev->class;
 811         unsigned int pi;
 812         unsigned short sub_serports;
 813
 814         pi = (c & 0xff);
 815
 816         if (pi == 2) {
 817                 return 1;
 818         } else if ((pi == 0) &&
 819                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 820                 /* two possibilities: 0x30ps encodes number of parallel and
 821                  * serial ports, or 0x1000 indicates *something*. This is not
 822                  * immediately obvious, since the 2s1p+4s configuration seems
 823                  * to offer all functionality on functions 0..2, while still
 824                  * advertising the same function 3 as the 4s+2s1p config.
 825                  */
 826                 sub_serports = dev->subsystem_device & 0xf;
 827                 if (sub_serports > 0) {
 828                         return sub_serports;
 829                 } else {
 830                         printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 831                         return 0;
 832                 }
 833         }
 834
 835         moan_device("unknown NetMos/Mostech program interface", dev);
 836         return 0;
 837 }
 838
 839 static int pci_netmos_init(struct pci_dev *dev)
 840 {
 841         /* subdevice 0x00PS means <P> parallel, <S> serial */
 842         unsigned int num_serial = dev->subsystem_device & 0xf;
 843
 844         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 845                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 846                 return 0;
 847
 848         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 849                         dev->subsystem_device == 0x0299)
 850                 return 0;
 851
 852         switch (dev->device) { /* FALLTHROUGH on all */
 853                 case PCI_DEVICE_ID_NETMOS_9904:
 854                 case PCI_DEVICE_ID_NETMOS_9912:
 855                 case PCI_DEVICE_ID_NETMOS_9922:
 856                 case PCI_DEVICE_ID_NETMOS_9900:
 857                         num_serial = pci_netmos_9900_numports(dev);
 858                         break;
 859
 860                 default:
 861                         if (num_serial == 0 ) {
 862                                 moan_device("unknown NetMos/Mostech device", dev);
 863                         }
 864         }
 865
 866         if (num_serial == 0)
 867                 return -ENODEV;
 868
 869         return num_serial;
 870 }
 871
 872 /*
 873  * These chips are available with optionally one parallel port and up to
 874  * two serial ports. Unfortunately they all have the same product id.
 875  *
 876  * Basic configuration is done over a region of 32 I/O ports. The base
 877  * ioport is called INTA or INTC, depending on docs/other drivers.
 878  *
 879  * The region of the 32 I/O ports is configured in POSIO0R...
 880  */
 881
 882 /* registers */
 883 #define ITE_887x_MISCR          0x9c
 884 #define ITE_887x_INTCBAR        0x78
 885 #define ITE_887x_UARTBAR        0x7c
 886 #define ITE_887x_PS0BAR         0x10
 887 #define ITE_887x_POSIO0         0x60
 888
 889 /* I/O space size */
 890 #define ITE_887x_IOSIZE         32
 891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 892 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 894 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 896 #define ITE_887x_POSIO_SPEED            (3 << 29)
 897 /* enable IO_Space bit */
 898 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 899
 900 static int pci_ite887x_init(struct pci_dev *dev)
 901 {
 902         /* inta_addr are the configuration addresses of the ITE */
 903         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 904                                                         0x200, 0x280, 0 };
 905         int ret, i, type;
 906         struct resource *iobase = NULL;
 907         u32 miscr, uartbar, ioport;
 908
 909         /* search for the base-ioport */
 910         i = 0;
 911         while (inta_addr[i] && iobase == NULL) {
 912                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 913                                                                 "ite887x");
 914                 if (iobase != NULL) {
 915                         /* write POSIO0R - speed | size | ioport */
 916                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 917                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 918                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 919                         /* write INTCBAR - ioport */
 920                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 921                                                                 inta_addr[i]);
 922                         ret = inb(inta_addr[i]);
 923                         if (ret != 0xff) {
 924                                 /* ioport connected */
 925                                 break;
 926                         }
 927                         release_region(iobase->start, ITE_887x_IOSIZE);
 928                         iobase = NULL;
 929                 }
 930                 i++;
 931         }
 932
 933         if (!inta_addr[i]) {
 934                 printk(KERN_ERR "ite887x: could not find iobase\n");
 935                 return -ENODEV;
 936         }
 937
 938         /* start of undocumented type checking (see parport_pc.c) */
 939         type = inb(iobase->start + 0x18) & 0x0f;
 940
 941         switch (type) {
 942         case 0x2:       /* ITE8871 (1P) */
 943         case 0xa:       /* ITE8875 (1P) */
 944                 ret = 0;
 945                 break;
 946         case 0xe:       /* ITE8872 (2S1P) */
 947                 ret = 2;
 948                 break;
 949         case 0x6:       /* ITE8873 (1S) */
 950                 ret = 1;
 951                 break;
 952         case 0x8:       /* ITE8874 (2S) */
 953                 ret = 2;
 954                 break;
 955         default:
 956                 moan_device("Unknown ITE887x", dev);
 957                 ret = -ENODEV;
 958         }
 959
 960         /* configure all serial ports */
 961         for (i = 0; i < ret; i++) {
 962                 /* read the I/O port from the device */
 963                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 964                                                                 &ioport);
 965                 ioport &= 0x0000FF00;   /* the actual base address */
 966                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 967                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 968                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 969
 970                 /* write the ioport to the UARTBAR */
 971                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 972                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 973                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 974                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 975
 976                 /* get current config */
 977                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 978                 /* disable interrupts (UARTx_Routing[3:0]) */
 979                 miscr &= ~(0xf << (12 - 4 * i));
 980                 /* activate the UART (UARTx_En) */
 981                 miscr |= 1 << (23 - i);
 982                 /* write new config with activated UART */
 983                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 984         }
 985
 986         if (ret <= 0) {
 987                 /* the device has no UARTs if we get here */
 988                 release_region(iobase->start, ITE_887x_IOSIZE);
 989         }
 990
 991         return ret;
 992 }
 993
 994 static void __devexit pci_ite887x_exit(struct pci_dev *dev)
 995 {
 996         u32 ioport;
 997         /* the ioport is bit 0-15 in POSIO0R */
 998         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 999         ioport &= 0xffff;
1000         release_region(ioport, ITE_887x_IOSIZE);
1001 }
1002
1003 /*
1004  * Oxford Semiconductor Inc.
1005  * Check that device is part of the Tornado range of devices, then determine
1006  * the number of ports available on the device.
1007  */
1008 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1009 {
1010         u8 __iomem *p;
1011         unsigned long deviceID;
1012         unsigned int  number_uarts = 0;
1013
1014         /* OxSemi Tornado devices are all 0xCxxx */
1015         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016             (dev->device & 0xF000) != 0xC000)
1017                 return 0;
1018
1019         p = pci_iomap(dev, 0, 5);
1020         if (p == NULL)
1021                 return -ENOMEM;
1022
1023         deviceID = ioread32(p);
1024         /* Tornado device */
1025         if (deviceID == 0x07000200) {
1026                 number_uarts = ioread8(p + 4);
1027                 printk(KERN_DEBUG
1028                         "%d ports detected on Oxford PCI Express device\n",
1029                                                                 number_uarts);
1030         }
1031         pci_iounmap(dev, p);
1032         return number_uarts;
1033 }
1034
1035 static int pci_asix_setup(struct serial_private *priv,
1036                   const struct pciserial_board *board,
1037                   struct uart_8250_port *port, int idx)
1038 {
1039         port->bugs |= UART_BUG_PARITY;
1040         return pci_default_setup(priv, board, port, idx);
1041 }
1042
1043 static int pci_default_setup(struct serial_private *priv,
1044                   const struct pciserial_board *board,
1045                   struct uart_8250_port *port, int idx)
1046 {
1047         unsigned int bar, offset = board->first_offset, maxnr;
1048
1049         bar = FL_GET_BASE(board->flags);
1050         if (board->flags & FL_BASE_BARS)
1051                 bar += idx;
1052         else
1053                 offset += idx * board->uart_offset;
1054
1055         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1056                 (board->reg_shift + 3);
1057
1058         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1059                 return 1;
1060
1061         return setup_port(priv, port, bar, offset, board->reg_shift);
1062 }
1063
1064 static int
1065 ce4100_serial_setup(struct serial_private *priv,
1066                   const struct pciserial_board *board,
1067                   struct uart_8250_port *port, int idx)
1068 {
1069         int ret;
1070
1071         ret = setup_port(priv, port, 0, 0, board->reg_shift);
1072         port->port.iotype = UPIO_MEM32;
1073         port->port.type = PORT_XSCALE;
1074         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1075         port->port.regshift = 2;
1076
1077         return ret;
1078 }
1079
1080 static int
1081 pci_omegapci_setup(struct serial_private *priv,
1082                       const struct pciserial_board *board,
1083                       struct uart_8250_port *port, int idx)
1084 {
1085         return setup_port(priv, port, 2, idx * 8, 0);
1086 }
1087
1088 static int skip_tx_en_setup(struct serial_private *priv,
1089                         const struct pciserial_board *board,
1090                         struct uart_8250_port *port, int idx)
1091 {
1092         port->port.flags |= UPF_NO_TXEN_TEST;
1093         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1094                           "[%04x:%04x] subsystem [%04x:%04x]\n",
1095                           priv->dev->vendor,
1096                           priv->dev->device,
1097                           priv->dev->subsystem_vendor,
1098                           priv->dev->subsystem_device);
1099
1100         return pci_default_setup(priv, board, port, idx);
1101 }
1102
1103 static void kt_handle_break(struct uart_port *p)
1104 {
1105         struct uart_8250_port *up =
1106                 container_of(p, struct uart_8250_port, port);
1107         /*
1108          * On receipt of a BI, serial device in Intel ME (Intel
1109          * management engine) needs to have its fifos cleared for sane
1110          * SOL (Serial Over Lan) output.
1111          */
1112         serial8250_clear_and_reinit_fifos(up);
1113 }
1114
1115 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1116 {
1117         struct uart_8250_port *up =
1118                 container_of(p, struct uart_8250_port, port);
1119         unsigned int val;
1120
1121         /*
1122          * When the Intel ME (management engine) gets reset its serial
1123          * port registers could return 0 momentarily.  Functions like
1124          * serial8250_console_write, read and save the IER, perform
1125          * some operation and then restore it.  In order to avoid
1126          * setting IER register inadvertently to 0, if the value read
1127          * is 0, double check with ier value in uart_8250_port and use
1128          * that instead.  up->ier should be the same value as what is
1129          * currently configured.
1130          */
1131         val = inb(p->iobase + offset);
1132         if (offset == UART_IER) {
1133                 if (val == 0)
1134                         val = up->ier;
1135         }
1136         return val;
1137 }
1138
1139 static int kt_serial_setup(struct serial_private *priv,
1140                            const struct pciserial_board *board,
1141                            struct uart_8250_port *port, int idx)
1142 {
1143         port->port.flags |= UPF_BUG_THRE;
1144         port->port.serial_in = kt_serial_in;
1145         port->port.handle_break = kt_handle_break;
1146         return skip_tx_en_setup(priv, board, port, idx);
1147 }
1148
1149 static int pci_eg20t_init(struct pci_dev *dev)
1150 {
1151 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1152         return -ENODEV;
1153 #else
1154         return 0;
1155 #endif
1156 }
1157
1158 static int
1159 pci_xr17c154_setup(struct serial_private *priv,
1160                   const struct pciserial_board *board,
1161                   struct uart_8250_port *port, int idx)
1162 {
1163         port->port.flags |= UPF_EXAR_EFR;
1164         return pci_default_setup(priv, board, port, idx);
1165 }
1166
1167 static int
1168 pci_wch_ch353_setup(struct serial_private *priv,
1169                     const struct pciserial_board *board,
1170                     struct uart_8250_port *port, int idx)
1171 {
1172         port->port.flags |= UPF_FIXED_TYPE;
1173         port->port.type = PORT_16550A;
1174         return pci_default_setup(priv, board, port, idx);
1175 }
1176
1177 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1178 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1179 #define PCI_DEVICE_ID_OCTPRO            0x0001
1180 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1181 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1182 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1183 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1184 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1185 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1186 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1187 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1188 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1189 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1190 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1191 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1192 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1193 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1194 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1195 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1196 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1197 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1198 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1199 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1200 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1201 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1202 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1203 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1204 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1205 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1206 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1207 #define PCI_VENDOR_ID_WCH               0x4348
1208 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1209 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1210 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1211 #define PCI_VENDOR_ID_AGESTAR           0x5372
1212 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1213 #define PCI_VENDOR_ID_ASIX              0x9710
1214
1215 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1216 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1217
1218 /*
1219  * Master list of serial port init/setup/exit quirks.
1220  * This does not describe the general nature of the port.
1221  * (ie, baud base, number and location of ports, etc)
1222  *
1223  * This list is ordered alphabetically by vendor then device.
1224  * Specific entries must come before more generic entries.
1225  */
1226 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1227         /*
1228         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1229         */
1230         {
1231                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1232                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1233                 .subvendor      = PCI_ANY_ID,
1234                 .subdevice      = PCI_ANY_ID,
1235                 .setup          = addidata_apci7800_setup,
1236         },
1237         /*
1238          * AFAVLAB cards - these may be called via parport_serial
1239          *  It is not clear whether this applies to all products.
1240          */
1241         {
1242                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1243                 .device         = PCI_ANY_ID,
1244                 .subvendor      = PCI_ANY_ID,
1245                 .subdevice      = PCI_ANY_ID,
1246                 .setup          = afavlab_setup,
1247         },
1248         /*
1249          * HP Diva
1250          */
1251         {
1252                 .vendor         = PCI_VENDOR_ID_HP,
1253                 .device         = PCI_DEVICE_ID_HP_DIVA,
1254                 .subvendor      = PCI_ANY_ID,
1255                 .subdevice      = PCI_ANY_ID,
1256                 .init           = pci_hp_diva_init,
1257                 .setup          = pci_hp_diva_setup,
1258         },
1259         /*
1260          * Intel
1261          */
1262         {
1263                 .vendor         = PCI_VENDOR_ID_INTEL,
1264                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1265                 .subvendor      = 0xe4bf,
1266                 .subdevice      = PCI_ANY_ID,
1267                 .init           = pci_inteli960ni_init,
1268                 .setup          = pci_default_setup,
1269         },
1270         {
1271                 .vendor         = PCI_VENDOR_ID_INTEL,
1272                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1273                 .subvendor      = PCI_ANY_ID,
1274                 .subdevice      = PCI_ANY_ID,
1275                 .setup          = skip_tx_en_setup,
1276         },
1277         {
1278                 .vendor         = PCI_VENDOR_ID_INTEL,
1279                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1280                 .subvendor      = PCI_ANY_ID,
1281                 .subdevice      = PCI_ANY_ID,
1282                 .setup          = skip_tx_en_setup,
1283         },
1284         {
1285                 .vendor         = PCI_VENDOR_ID_INTEL,
1286                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1287                 .subvendor      = PCI_ANY_ID,
1288                 .subdevice      = PCI_ANY_ID,
1289                 .setup          = skip_tx_en_setup,
1290         },
1291         {
1292                 .vendor         = PCI_VENDOR_ID_INTEL,
1293                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1294                 .subvendor      = PCI_ANY_ID,
1295                 .subdevice      = PCI_ANY_ID,
1296                 .setup          = ce4100_serial_setup,
1297         },
1298         {
1299                 .vendor         = PCI_VENDOR_ID_INTEL,
1300                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1301                 .subvendor      = PCI_ANY_ID,
1302                 .subdevice      = PCI_ANY_ID,
1303                 .setup          = kt_serial_setup,
1304         },
1305         /*
1306          * ITE
1307          */
1308         {
1309                 .vendor         = PCI_VENDOR_ID_ITE,
1310                 .device         = PCI_DEVICE_ID_ITE_8872,
1311                 .subvendor      = PCI_ANY_ID,
1312                 .subdevice      = PCI_ANY_ID,
1313                 .init           = pci_ite887x_init,
1314                 .setup          = pci_default_setup,
1315                 .exit           = __devexit_p(pci_ite887x_exit),
1316         },
1317         /*
1318          * National Instruments
1319          */
1320         {
1321                 .vendor         = PCI_VENDOR_ID_NI,
1322                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1323                 .subvendor      = PCI_ANY_ID,
1324                 .subdevice      = PCI_ANY_ID,
1325                 .init           = pci_ni8420_init,
1326                 .setup          = pci_default_setup,
1327                 .exit           = __devexit_p(pci_ni8420_exit),
1328         },
1329         {
1330                 .vendor         = PCI_VENDOR_ID_NI,
1331                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1332                 .subvendor      = PCI_ANY_ID,
1333                 .subdevice      = PCI_ANY_ID,
1334                 .init           = pci_ni8420_init,
1335                 .setup          = pci_default_setup,
1336                 .exit           = __devexit_p(pci_ni8420_exit),
1337         },
1338         {
1339                 .vendor         = PCI_VENDOR_ID_NI,
1340                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1341                 .subvendor      = PCI_ANY_ID,
1342                 .subdevice      = PCI_ANY_ID,
1343                 .init           = pci_ni8420_init,
1344                 .setup          = pci_default_setup,
1345                 .exit           = __devexit_p(pci_ni8420_exit),
1346         },
1347         {
1348                 .vendor         = PCI_VENDOR_ID_NI,
1349                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1350                 .subvendor      = PCI_ANY_ID,
1351                 .subdevice      = PCI_ANY_ID,
1352                 .init           = pci_ni8420_init,
1353                 .setup          = pci_default_setup,
1354                 .exit           = __devexit_p(pci_ni8420_exit),
1355         },
1356         {
1357                 .vendor         = PCI_VENDOR_ID_NI,
1358                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1359                 .subvendor      = PCI_ANY_ID,
1360                 .subdevice      = PCI_ANY_ID,
1361                 .init           = pci_ni8420_init,
1362                 .setup          = pci_default_setup,
1363                 .exit           = __devexit_p(pci_ni8420_exit),
1364         },
1365         {
1366                 .vendor         = PCI_VENDOR_ID_NI,
1367                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1368                 .subvendor      = PCI_ANY_ID,
1369                 .subdevice      = PCI_ANY_ID,
1370                 .init           = pci_ni8420_init,
1371                 .setup          = pci_default_setup,
1372                 .exit           = __devexit_p(pci_ni8420_exit),
1373         },
1374         {
1375                 .vendor         = PCI_VENDOR_ID_NI,
1376                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1377                 .subvendor      = PCI_ANY_ID,
1378                 .subdevice      = PCI_ANY_ID,
1379                 .init           = pci_ni8420_init,
1380                 .setup          = pci_default_setup,
1381                 .exit           = __devexit_p(pci_ni8420_exit),
1382         },
1383         {
1384                 .vendor         = PCI_VENDOR_ID_NI,
1385                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1386                 .subvendor      = PCI_ANY_ID,
1387                 .subdevice      = PCI_ANY_ID,
1388                 .init           = pci_ni8420_init,
1389                 .setup          = pci_default_setup,
1390                 .exit           = __devexit_p(pci_ni8420_exit),
1391         },
1392         {
1393                 .vendor         = PCI_VENDOR_ID_NI,
1394                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1395                 .subvendor      = PCI_ANY_ID,
1396                 .subdevice      = PCI_ANY_ID,
1397                 .init           = pci_ni8420_init,
1398                 .setup          = pci_default_setup,
1399                 .exit           = __devexit_p(pci_ni8420_exit),
1400         },
1401         {
1402                 .vendor         = PCI_VENDOR_ID_NI,
1403                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1404                 .subvendor      = PCI_ANY_ID,
1405                 .subdevice      = PCI_ANY_ID,
1406                 .init           = pci_ni8420_init,
1407                 .setup          = pci_default_setup,
1408                 .exit           = __devexit_p(pci_ni8420_exit),
1409         },
1410         {
1411                 .vendor         = PCI_VENDOR_ID_NI,
1412                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1413                 .subvendor      = PCI_ANY_ID,
1414                 .subdevice      = PCI_ANY_ID,
1415                 .init           = pci_ni8420_init,
1416                 .setup          = pci_default_setup,
1417                 .exit           = __devexit_p(pci_ni8420_exit),
1418         },
1419         {
1420                 .vendor         = PCI_VENDOR_ID_NI,
1421                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1422                 .subvendor      = PCI_ANY_ID,
1423                 .subdevice      = PCI_ANY_ID,
1424                 .init           = pci_ni8420_init,
1425                 .setup          = pci_default_setup,
1426                 .exit           = __devexit_p(pci_ni8420_exit),
1427         },
1428         {
1429                 .vendor         = PCI_VENDOR_ID_NI,
1430                 .device         = PCI_ANY_ID,
1431                 .subvendor      = PCI_ANY_ID,
1432                 .subdevice      = PCI_ANY_ID,
1433                 .init           = pci_ni8430_init,
1434                 .setup          = pci_ni8430_setup,
1435                 .exit           = __devexit_p(pci_ni8430_exit),
1436         },
1437         /*
1438          * Panacom
1439          */
1440         {
1441                 .vendor         = PCI_VENDOR_ID_PANACOM,
1442                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1443                 .subvendor      = PCI_ANY_ID,
1444                 .subdevice      = PCI_ANY_ID,
1445                 .init           = pci_plx9050_init,
1446                 .setup          = pci_default_setup,
1447                 .exit           = __devexit_p(pci_plx9050_exit),
1448         },
1449         {
1450                 .vendor         = PCI_VENDOR_ID_PANACOM,
1451                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1452                 .subvendor      = PCI_ANY_ID,
1453                 .subdevice      = PCI_ANY_ID,
1454                 .init           = pci_plx9050_init,
1455                 .setup          = pci_default_setup,
1456                 .exit           = __devexit_p(pci_plx9050_exit),
1457         },
1458         /*
1459          * PLX
1460          */
1461         {
1462                 .vendor         = PCI_VENDOR_ID_PLX,
1463                 .device         = PCI_DEVICE_ID_PLX_9030,
1464                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1465                 .subdevice      = PCI_ANY_ID,
1466                 .setup          = pci_default_setup,
1467         },
1468         {
1469                 .vendor         = PCI_VENDOR_ID_PLX,
1470                 .device         = PCI_DEVICE_ID_PLX_9050,
1471                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1472                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1473                 .init           = pci_plx9050_init,
1474                 .setup          = pci_default_setup,
1475                 .exit           = __devexit_p(pci_plx9050_exit),
1476         },
1477         {
1478                 .vendor         = PCI_VENDOR_ID_PLX,
1479                 .device         = PCI_DEVICE_ID_PLX_9050,
1480                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1481                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1482                 .init           = pci_plx9050_init,
1483                 .setup          = pci_default_setup,
1484                 .exit           = __devexit_p(pci_plx9050_exit),
1485         },
1486         {
1487                 .vendor         = PCI_VENDOR_ID_PLX,
1488                 .device         = PCI_DEVICE_ID_PLX_9050,
1489                 .subvendor      = PCI_VENDOR_ID_PLX,
1490                 .subdevice      = PCI_SUBDEVICE_ID_UNKNOWN_0x1584,
1491                 .init           = pci_plx9050_init,
1492                 .setup          = pci_default_setup,
1493                 .exit           = __devexit_p(pci_plx9050_exit),
1494         },
1495         {
1496                 .vendor         = PCI_VENDOR_ID_PLX,
1497                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1498                 .subvendor      = PCI_VENDOR_ID_PLX,
1499                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1500                 .init           = pci_plx9050_init,
1501                 .setup          = pci_default_setup,
1502                 .exit           = __devexit_p(pci_plx9050_exit),
1503         },
1504         /*
1505          * SBS Technologies, Inc., PMC-OCTALPRO 232
1506          */
1507         {
1508                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1509                 .device         = PCI_DEVICE_ID_OCTPRO,
1510                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1511                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1512                 .init           = sbs_init,
1513                 .setup          = sbs_setup,
1514                 .exit           = __devexit_p(sbs_exit),
1515         },
1516         /*
1517          * SBS Technologies, Inc., PMC-OCTALPRO 422
1518          */
1519         {
1520                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1521                 .device         = PCI_DEVICE_ID_OCTPRO,
1522                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1523                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1524                 .init           = sbs_init,
1525                 .setup          = sbs_setup,
1526                 .exit           = __devexit_p(sbs_exit),
1527         },
1528         /*
1529          * SBS Technologies, Inc., P-Octal 232
1530          */
1531         {
1532                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1533                 .device         = PCI_DEVICE_ID_OCTPRO,
1534                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1535                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1536                 .init           = sbs_init,
1537                 .setup          = sbs_setup,
1538                 .exit           = __devexit_p(sbs_exit),
1539         },
1540         /*
1541          * SBS Technologies, Inc., P-Octal 422
1542          */
1543         {
1544                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1545                 .device         = PCI_DEVICE_ID_OCTPRO,
1546                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1547                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1548                 .init           = sbs_init,
1549                 .setup          = sbs_setup,
1550                 .exit           = __devexit_p(sbs_exit),
1551         },
1552         /*
1553          * SIIG cards - these may be called via parport_serial
1554          */
1555         {
1556                 .vendor         = PCI_VENDOR_ID_SIIG,
1557                 .device         = PCI_ANY_ID,
1558                 .subvendor      = PCI_ANY_ID,
1559                 .subdevice      = PCI_ANY_ID,
1560                 .init           = pci_siig_init,
1561                 .setup          = pci_siig_setup,
1562         },
1563         /*
1564          * Titan cards
1565          */
1566         {
1567                 .vendor         = PCI_VENDOR_ID_TITAN,
1568                 .device         = PCI_DEVICE_ID_TITAN_400L,
1569                 .subvendor      = PCI_ANY_ID,
1570                 .subdevice      = PCI_ANY_ID,
1571                 .setup          = titan_400l_800l_setup,
1572         },
1573         {
1574                 .vendor         = PCI_VENDOR_ID_TITAN,
1575                 .device         = PCI_DEVICE_ID_TITAN_800L,
1576                 .subvendor      = PCI_ANY_ID,
1577                 .subdevice      = PCI_ANY_ID,
1578                 .setup          = titan_400l_800l_setup,
1579         },
1580         /*
1581          * Timedia cards
1582          */
1583         {
1584                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1585                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1586                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1587                 .subdevice      = PCI_ANY_ID,
1588                 .probe          = pci_timedia_probe,
1589                 .init           = pci_timedia_init,
1590                 .setup          = pci_timedia_setup,
1591         },
1592         {
1593                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1594                 .device         = PCI_ANY_ID,
1595                 .subvendor      = PCI_ANY_ID,
1596                 .subdevice      = PCI_ANY_ID,
1597                 .setup          = pci_timedia_setup,
1598         },
1599         /*
1600          * Exar cards
1601          */
1602         {
1603                 .vendor = PCI_VENDOR_ID_EXAR,
1604                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1605                 .subvendor      = PCI_ANY_ID,
1606                 .subdevice      = PCI_ANY_ID,
1607                 .setup          = pci_xr17c154_setup,
1608         },
1609         {
1610                 .vendor = PCI_VENDOR_ID_EXAR,
1611                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1612                 .subvendor      = PCI_ANY_ID,
1613                 .subdevice      = PCI_ANY_ID,
1614                 .setup          = pci_xr17c154_setup,
1615         },
1616         {
1617                 .vendor = PCI_VENDOR_ID_EXAR,
1618                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1619                 .subvendor      = PCI_ANY_ID,
1620                 .subdevice      = PCI_ANY_ID,
1621                 .setup          = pci_xr17c154_setup,
1622         },
1623         /*
1624          * Xircom cards
1625          */
1626         {
1627                 .vendor         = PCI_VENDOR_ID_XIRCOM,
1628                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
1629                 .subvendor      = PCI_ANY_ID,
1630                 .subdevice      = PCI_ANY_ID,
1631                 .init           = pci_xircom_init,
1632                 .setup          = pci_default_setup,
1633         },
1634         /*
1635          * Netmos cards - these may be called via parport_serial
1636          */
1637         {
1638                 .vendor         = PCI_VENDOR_ID_NETMOS,
1639                 .device         = PCI_ANY_ID,
1640                 .subvendor      = PCI_ANY_ID,
1641                 .subdevice      = PCI_ANY_ID,
1642                 .init           = pci_netmos_init,
1643                 .setup          = pci_netmos_9900_setup,
1644         },
1645         /*
1646          * For Oxford Semiconductor Tornado based devices
1647          */
1648         {
1649                 .vendor         = PCI_VENDOR_ID_OXSEMI,
1650                 .device         = PCI_ANY_ID,
1651                 .subvendor      = PCI_ANY_ID,
1652                 .subdevice      = PCI_ANY_ID,
1653                 .init           = pci_oxsemi_tornado_init,
1654                 .setup          = pci_default_setup,
1655         },
1656         {
1657                 .vendor         = PCI_VENDOR_ID_MAINPINE,
1658                 .device         = PCI_ANY_ID,
1659                 .subvendor      = PCI_ANY_ID,
1660                 .subdevice      = PCI_ANY_ID,
1661                 .init           = pci_oxsemi_tornado_init,
1662                 .setup          = pci_default_setup,
1663         },
1664         {
1665                 .vendor         = PCI_VENDOR_ID_DIGI,
1666                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
1667                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
1668                 .subdevice              = PCI_ANY_ID,
1669                 .init                   = pci_oxsemi_tornado_init,
1670                 .setup          = pci_default_setup,
1671         },
1672         {
1673                 .vendor         = PCI_VENDOR_ID_INTEL,
1674                 .device         = 0x8811,
1675                 .subvendor      = PCI_ANY_ID,
1676                 .subdevice      = PCI_ANY_ID,
1677                 .init           = pci_eg20t_init,
1678                 .setup          = pci_default_setup,
1679         },
1680         {
1681                 .vendor         = PCI_VENDOR_ID_INTEL,
1682                 .device         = 0x8812,
1683                 .subvendor      = PCI_ANY_ID,
1684                 .subdevice      = PCI_ANY_ID,
1685                 .init           = pci_eg20t_init,
1686                 .setup          = pci_default_setup,
1687         },
1688         {
1689                 .vendor         = PCI_VENDOR_ID_INTEL,
1690                 .device         = 0x8813,
1691                 .subvendor      = PCI_ANY_ID,
1692                 .subdevice      = PCI_ANY_ID,
1693                 .init           = pci_eg20t_init,
1694                 .setup          = pci_default_setup,
1695         },
1696         {
1697                 .vendor         = PCI_VENDOR_ID_INTEL,
1698                 .device         = 0x8814,
1699                 .subvendor      = PCI_ANY_ID,
1700                 .subdevice      = PCI_ANY_ID,
1701                 .init           = pci_eg20t_init,
1702                 .setup          = pci_default_setup,
1703         },
1704         {
1705                 .vendor         = 0x10DB,
1706                 .device         = 0x8027,
1707                 .subvendor      = PCI_ANY_ID,
1708                 .subdevice      = PCI_ANY_ID,
1709                 .init           = pci_eg20t_init,
1710                 .setup          = pci_default_setup,
1711         },
1712         {
1713                 .vendor         = 0x10DB,
1714                 .device         = 0x8028,
1715                 .subvendor      = PCI_ANY_ID,
1716                 .subdevice      = PCI_ANY_ID,
1717                 .init           = pci_eg20t_init,
1718                 .setup          = pci_default_setup,
1719         },
1720         {
1721                 .vendor         = 0x10DB,
1722                 .device         = 0x8029,
1723                 .subvendor      = PCI_ANY_ID,
1724                 .subdevice      = PCI_ANY_ID,
1725                 .init           = pci_eg20t_init,
1726                 .setup          = pci_default_setup,
1727         },
1728         {
1729                 .vendor         = 0x10DB,
1730                 .device         = 0x800C,
1731                 .subvendor      = PCI_ANY_ID,
1732                 .subdevice      = PCI_ANY_ID,
1733                 .init           = pci_eg20t_init,
1734                 .setup          = pci_default_setup,
1735         },
1736         {
1737                 .vendor         = 0x10DB,
1738                 .device         = 0x800D,
1739                 .subvendor      = PCI_ANY_ID,
1740                 .subdevice      = PCI_ANY_ID,
1741                 .init           = pci_eg20t_init,
1742                 .setup          = pci_default_setup,
1743         },
1744         /*
1745          * Cronyx Omega PCI (PLX-chip based)
1746          */
1747         {
1748                 .vendor         = PCI_VENDOR_ID_PLX,
1749                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
1750                 .subvendor      = PCI_ANY_ID,
1751                 .subdevice      = PCI_ANY_ID,
1752                 .setup          = pci_omegapci_setup,
1753         },
1754         /* WCH CH353 2S1P card (16550 clone) */
1755         {
1756                 .vendor         = PCI_VENDOR_ID_WCH,
1757                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
1758                 .subvendor      = PCI_ANY_ID,
1759                 .subdevice      = PCI_ANY_ID,
1760                 .setup          = pci_wch_ch353_setup,
1761         },
1762         /* WCH CH353 4S card (16550 clone) */
1763         {
1764                 .vendor         = PCI_VENDOR_ID_WCH,
1765                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
1766                 .subvendor      = PCI_ANY_ID,
1767                 .subdevice      = PCI_ANY_ID,
1768                 .setup          = pci_wch_ch353_setup,
1769         },
1770         /* WCH CH353 2S1PF card (16550 clone) */
1771         {
1772                 .vendor         = PCI_VENDOR_ID_WCH,
1773                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
1774                 .subvendor      = PCI_ANY_ID,
1775                 .subdevice      = PCI_ANY_ID,
1776                 .setup          = pci_wch_ch353_setup,
1777         },
1778         /*
1779          * ASIX devices with FIFO bug
1780          */
1781         {
1782                 .vendor         = PCI_VENDOR_ID_ASIX,
1783                 .device         = PCI_ANY_ID,
1784                 .subvendor      = PCI_ANY_ID,
1785                 .subdevice      = PCI_ANY_ID,
1786                 .setup          = pci_asix_setup,
1787         },
1788         /*
1789          * Default "match everything" terminator entry
1790          */
1791         {
1792                 .vendor         = PCI_ANY_ID,
1793                 .device         = PCI_ANY_ID,
1794                 .subvendor      = PCI_ANY_ID,
1795                 .subdevice      = PCI_ANY_ID,
1796                 .setup          = pci_default_setup,
1797         }
1798 };
1799
1800 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
1801 {
1802         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
1803 }
1804
1805 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
1806 {
1807         struct pci_serial_quirk *quirk;
1808
1809         for (quirk = pci_serial_quirks; ; quirk++)
1810                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
1811                     quirk_id_matches(quirk->device, dev->device) &&
1812                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
1813                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
1814                         break;
1815         return quirk;
1816 }
1817
1818 static inline int get_pci_irq(struct pci_dev *dev,
1819                                 const struct pciserial_board *board)
1820 {
1821         if (board->flags & FL_NOIRQ)
1822                 return 0;
1823         else
1824                 return dev->irq;
1825 }
1826
1827 /*
1828  * This is the configuration table for all of the PCI serial boards
1829  * which we support.  It is directly indexed by the pci_board_num_t enum
1830  * value, which is encoded in the pci_device_id PCI probe table's
1831  * driver_data member.
1832  *
1833  * The makeup of these names are:
1834  *  pbn_bn{_bt}_n_baud{_offsetinhex}
1835  *
1836  *  bn          = PCI BAR number
1837  *  bt          = Index using PCI BARs
1838  *  n           = number of serial ports
1839  *  baud        = baud rate
1840  *  offsetinhex = offset for each sequential port (in hex)
1841  *
1842  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
1843  *
1844  * Please note: in theory if n = 1, _bt infix should make no difference.
1845  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
1846  */
1847 enum pci_board_num_t {
1848         pbn_default = 0,
1849
1850         pbn_b0_1_115200,
1851         pbn_b0_2_115200,
1852         pbn_b0_4_115200,
1853         pbn_b0_5_115200,
1854         pbn_b0_8_115200,
1855
1856         pbn_b0_1_921600,
1857         pbn_b0_2_921600,
1858         pbn_b0_4_921600,
1859
1860         pbn_b0_2_1130000,
1861
1862         pbn_b0_4_1152000,
1863
1864         pbn_b0_2_1843200,
1865         pbn_b0_4_1843200,
1866
1867         pbn_b0_2_1843200_200,
1868         pbn_b0_4_1843200_200,
1869         pbn_b0_8_1843200_200,
1870
1871         pbn_b0_1_4000000,
1872
1873         pbn_b0_bt_1_115200,
1874         pbn_b0_bt_2_115200,
1875         pbn_b0_bt_4_115200,
1876         pbn_b0_bt_8_115200,
1877
1878         pbn_b0_bt_1_460800,
1879         pbn_b0_bt_2_460800,
1880         pbn_b0_bt_4_460800,
1881
1882         pbn_b0_bt_1_921600,
1883         pbn_b0_bt_2_921600,
1884         pbn_b0_bt_4_921600,
1885         pbn_b0_bt_8_921600,
1886
1887         pbn_b1_1_115200,
1888         pbn_b1_2_115200,
1889         pbn_b1_4_115200,
1890         pbn_b1_8_115200,
1891         pbn_b1_16_115200,
1892
1893         pbn_b1_1_921600,
1894         pbn_b1_2_921600,
1895         pbn_b1_4_921600,
1896         pbn_b1_8_921600,
1897
1898         pbn_b1_2_1250000,
1899
1900         pbn_b1_bt_1_115200,
1901         pbn_b1_bt_2_115200,
1902         pbn_b1_bt_4_115200,
1903
1904         pbn_b1_bt_2_921600,
1905
1906         pbn_b1_1_1382400,
1907         pbn_b1_2_1382400,
1908         pbn_b1_4_1382400,
1909         pbn_b1_8_1382400,
1910
1911         pbn_b2_1_115200,
1912         pbn_b2_2_115200,
1913         pbn_b2_4_115200,
1914         pbn_b2_8_115200,
1915
1916         pbn_b2_1_460800,
1917         pbn_b2_4_460800,
1918         pbn_b2_8_460800,
1919         pbn_b2_16_460800,
1920
1921         pbn_b2_1_921600,
1922         pbn_b2_4_921600,
1923         pbn_b2_8_921600,
1924
1925         pbn_b2_8_1152000,
1926
1927         pbn_b2_bt_1_115200,
1928         pbn_b2_bt_2_115200,
1929         pbn_b2_bt_4_115200,
1930
1931         pbn_b2_bt_2_921600,
1932         pbn_b2_bt_4_921600,
1933
1934         pbn_b3_2_115200,
1935         pbn_b3_4_115200,
1936         pbn_b3_8_115200,
1937
1938         pbn_b4_bt_2_921600,
1939         pbn_b4_bt_4_921600,
1940         pbn_b4_bt_8_921600,
1941
1942         /*
1943          * Board-specific versions.
1944          */
1945         pbn_panacom,
1946         pbn_panacom2,
1947         pbn_panacom4,
1948         pbn_plx_romulus,
1949         pbn_oxsemi,
1950         pbn_oxsemi_1_4000000,
1951         pbn_oxsemi_2_4000000,
1952         pbn_oxsemi_4_4000000,
1953         pbn_oxsemi_8_4000000,
1954         pbn_intel_i960,
1955         pbn_sgi_ioc3,
1956         pbn_computone_4,
1957         pbn_computone_6,
1958         pbn_computone_8,
1959         pbn_sbsxrsio,
1960         pbn_exar_XR17C152,
1961         pbn_exar_XR17C154,
1962         pbn_exar_XR17C158,
1963         pbn_exar_ibm_saturn,
1964         pbn_pasemi_1682M,
1965         pbn_ni8430_2,
1966         pbn_ni8430_4,
1967         pbn_ni8430_8,
1968         pbn_ni8430_16,
1969         pbn_ADDIDATA_PCIe_1_3906250,
1970         pbn_ADDIDATA_PCIe_2_3906250,
1971         pbn_ADDIDATA_PCIe_4_3906250,
1972         pbn_ADDIDATA_PCIe_8_3906250,
1973         pbn_ce4100_1_115200,
1974         pbn_omegapci,
1975         pbn_NETMOS9900_2s_115200,
1976 };
1977
1978 /*
1979  * uart_offset - the space between channels
1980  * reg_shift   - describes how the UART registers are mapped
1981  *               to PCI memory by the card.
1982  * For example IER register on SBS, Inc. PMC-OctPro is located at
1983  * offset 0x10 from the UART base, while UART_IER is defined as 1
1984  * in include/linux/serial_reg.h,
1985  * see first lines of serial_in() and serial_out() in 8250.c
1986 */
1987
1988 static struct pciserial_board pci_boards[] __devinitdata = {
1989         [pbn_default] = {
1990                 .flags          = FL_BASE0,
1991                 .num_ports      = 1,
1992                 .base_baud      = 115200,
1993                 .uart_offset    = 8,
1994         },
1995         [pbn_b0_1_115200] = {
1996                 .flags          = FL_BASE0,
1997                 .num_ports      = 1,
1998                 .base_baud      = 115200,
1999                 .uart_offset    = 8,
2000         },
2001         [pbn_b0_2_115200] = {
2002                 .flags          = FL_BASE0,
2003                 .num_ports      = 2,
2004                 .base_baud      = 115200,
2005                 .uart_offset    = 8,
2006         },
2007         [pbn_b0_4_115200] = {
2008                 .flags          = FL_BASE0,
2009                 .num_ports      = 4,
2010                 .base_baud      = 115200,
2011                 .uart_offset    = 8,
2012         },
2013         [pbn_b0_5_115200] = {
2014                 .flags          = FL_BASE0,
2015                 .num_ports      = 5,
2016                 .base_baud      = 115200,
2017                 .uart_offset    = 8,
2018         },
2019         [pbn_b0_8_115200] = {
2020                 .flags          = FL_BASE0,
2021                 .num_ports      = 8,
2022                 .base_baud      = 115200,
2023                 .uart_offset    = 8,
2024         },
2025         [pbn_b0_1_921600] = {
2026                 .flags          = FL_BASE0,
2027                 .num_ports      = 1,
2028                 .base_baud      = 921600,
2029                 .uart_offset    = 8,
2030         },
2031         [pbn_b0_2_921600] = {
2032                 .flags          = FL_BASE0,
2033                 .num_ports      = 2,
2034                 .base_baud      = 921600,
2035                 .uart_offset    = 8,
2036         },
2037         [pbn_b0_4_921600] = {
2038                 .flags          = FL_BASE0,
2039                 .num_ports      = 4,
2040                 .base_baud      = 921600,
2041                 .uart_offset    = 8,
2042         },
2043
2044         [pbn_b0_2_1130000] = {
2045                 .flags          = FL_BASE0,
2046                 .num_ports      = 2,
2047                 .base_baud      = 1130000,
2048                 .uart_offset    = 8,
2049         },
2050
2051         [pbn_b0_4_1152000] = {
2052                 .flags          = FL_BASE0,
2053                 .num_ports      = 4,
2054                 .base_baud      = 1152000,
2055                 .uart_offset    = 8,
2056         },
2057
2058         [pbn_b0_2_1843200] = {
2059                 .flags          = FL_BASE0,
2060                 .num_ports      = 2,
2061                 .base_baud      = 1843200,
2062                 .uart_offset    = 8,
2063         },
2064         [pbn_b0_4_1843200] = {
2065                 .flags          = FL_BASE0,
2066                 .num_ports      = 4,
2067                 .base_baud      = 1843200,
2068                 .uart_offset    = 8,
2069         },
2070
2071         [pbn_b0_2_1843200_200] = {
2072                 .flags          = FL_BASE0,
2073                 .num_ports      = 2,
2074                 .base_baud      = 1843200,
2075                 .uart_offset    = 0x200,
2076         },
2077         [pbn_b0_4_1843200_200] = {
2078                 .flags          = FL_BASE0,
2079                 .num_ports      = 4,
2080                 .base_baud      = 1843200,
2081                 .uart_offset    = 0x200,
2082         },
2083         [pbn_b0_8_1843200_200] = {
2084                 .flags          = FL_BASE0,
2085                 .num_ports      = 8,
2086                 .base_baud      = 1843200,
2087                 .uart_offset    = 0x200,
2088         },
2089         [pbn_b0_1_4000000] = {
2090                 .flags          = FL_BASE0,
2091                 .num_ports      = 1,
2092                 .base_baud      = 4000000,
2093                 .uart_offset    = 8,
2094         },
2095
2096         [pbn_b0_bt_1_115200] = {
2097                 .flags          = FL_BASE0|FL_BASE_BARS,
2098                 .num_ports      = 1,
2099                 .base_baud      = 115200,
2100                 .uart_offset    = 8,
2101         },
2102         [pbn_b0_bt_2_115200] = {
2103                 .flags          = FL_BASE0|FL_BASE_BARS,
2104                 .num_ports      = 2,
2105                 .base_baud      = 115200,
2106                 .uart_offset    = 8,
2107         },
2108         [pbn_b0_bt_4_115200] = {
2109                 .flags          = FL_BASE0|FL_BASE_BARS,
2110                 .num_ports      = 4,
2111                 .base_baud      = 115200,
2112                 .uart_offset    = 8,
2113         },
2114         [pbn_b0_bt_8_115200] = {
2115                 .flags          = FL_BASE0|FL_BASE_BARS,
2116                 .num_ports      = 8,
2117                 .base_baud      = 115200,
2118                 .uart_offset    = 8,
2119         },
2120
2121         [pbn_b0_bt_1_460800] = {
2122                 .flags          = FL_BASE0|FL_BASE_BARS,
2123                 .num_ports      = 1,
2124                 .base_baud      = 460800,
2125                 .uart_offset    = 8,
2126         },
2127         [pbn_b0_bt_2_460800] = {
2128                 .flags          = FL_BASE0|FL_BASE_BARS,
2129                 .num_ports      = 2,
2130                 .base_baud      = 460800,
2131                 .uart_offset    = 8,
2132         },
2133         [pbn_b0_bt_4_460800] = {
2134                 .flags          = FL_BASE0|FL_BASE_BARS,
2135                 .num_ports      = 4,
2136                 .base_baud      = 460800,
2137                 .uart_offset    = 8,
2138         },
2139
2140         [pbn_b0_bt_1_921600] = {
2141                 .flags          = FL_BASE0|FL_BASE_BARS,
2142                 .num_ports      = 1,
2143                 .base_baud      = 921600,
2144                 .uart_offset    = 8,
2145         },
2146         [pbn_b0_bt_2_921600] = {
2147                 .flags          = FL_BASE0|FL_BASE_BARS,
2148                 .num_ports      = 2,
2149                 .base_baud      = 921600,
2150                 .uart_offset    = 8,
2151         },
2152         [pbn_b0_bt_4_921600] = {
2153                 .flags          = FL_BASE0|FL_BASE_BARS,
2154                 .num_ports      = 4,
2155                 .base_baud      = 921600,
2156                 .uart_offset    = 8,
2157         },
2158         [pbn_b0_bt_8_921600] = {
2159                 .flags          = FL_BASE0|FL_BASE_BARS,
2160                 .num_ports      = 8,
2161                 .base_baud      = 921600,
2162                 .uart_offset    = 8,
2163         },
2164
2165         [pbn_b1_1_115200] = {
2166                 .flags          = FL_BASE1,
2167                 .num_ports      = 1,
2168                 .base_baud      = 115200,
2169                 .uart_offset    = 8,
2170         },
2171         [pbn_b1_2_115200] = {
2172                 .flags          = FL_BASE1,
2173                 .num_ports      = 2,
2174                 .base_baud      = 115200,
2175                 .uart_offset    = 8,
2176         },
2177         [pbn_b1_4_115200] = {
2178                 .flags          = FL_BASE1,
2179                 .num_ports      = 4,
2180                 .base_baud      = 115200,
2181                 .uart_offset    = 8,
2182         },
2183         [pbn_b1_8_115200] = {
2184                 .flags          = FL_BASE1,
2185                 .num_ports      = 8,
2186                 .base_baud      = 115200,
2187                 .uart_offset    = 8,
2188         },
2189         [pbn_b1_16_115200] = {
2190                 .flags          = FL_BASE1,
2191                 .num_ports      = 16,
2192                 .base_baud      = 115200,
2193                 .uart_offset    = 8,
2194         },
2195
2196         [pbn_b1_1_921600] = {
2197                 .flags          = FL_BASE1,
2198                 .num_ports      = 1,
2199                 .base_baud      = 921600,
2200                 .uart_offset    = 8,
2201         },
2202         [pbn_b1_2_921600] = {
2203                 .flags          = FL_BASE1,
2204                 .num_ports      = 2,
2205                 .base_baud      = 921600,
2206                 .uart_offset    = 8,
2207         },
2208         [pbn_b1_4_921600] = {
2209                 .flags          = FL_BASE1,
2210                 .num_ports      = 4,
2211                 .base_baud      = 921600,
2212                 .uart_offset    = 8,
2213         },
2214         [pbn_b1_8_921600] = {
2215                 .flags          = FL_BASE1,
2216                 .num_ports      = 8,
2217                 .base_baud      = 921600,
2218                 .uart_offset    = 8,
2219         },
2220         [pbn_b1_2_1250000] = {
2221                 .flags          = FL_BASE1,
2222                 .num_ports      = 2,
2223                 .base_baud      = 1250000,
2224                 .uart_offset    = 8,
2225         },
2226
2227         [pbn_b1_bt_1_115200] = {
2228                 .flags          = FL_BASE1|FL_BASE_BARS,
2229                 .num_ports      = 1,
2230                 .base_baud      = 115200,
2231                 .uart_offset    = 8,
2232         },
2233         [pbn_b1_bt_2_115200] = {
2234                 .flags          = FL_BASE1|FL_BASE_BARS,
2235                 .num_ports      = 2,
2236                 .base_baud      = 115200,
2237                 .uart_offset    = 8,
2238         },
2239         [pbn_b1_bt_4_115200] = {
2240                 .flags          = FL_BASE1|FL_BASE_BARS,
2241                 .num_ports      = 4,
2242                 .base_baud      = 115200,
2243                 .uart_offset    = 8,
2244         },
2245
2246         [pbn_b1_bt_2_921600] = {
2247                 .flags          = FL_BASE1|FL_BASE_BARS,
2248                 .num_ports      = 2,
2249                 .base_baud      = 921600,
2250                 .uart_offset    = 8,
2251         },
2252
2253         [pbn_b1_1_1382400] = {
2254                 .flags          = FL_BASE1,
2255                 .num_ports      = 1,
2256                 .base_baud      = 1382400,
2257                 .uart_offset    = 8,
2258         },
2259         [pbn_b1_2_1382400] = {
2260                 .flags          = FL_BASE1,
2261                 .num_ports      = 2,
2262                 .base_baud      = 1382400,
2263                 .uart_offset    = 8,
2264         },
2265         [pbn_b1_4_1382400] = {
2266                 .flags          = FL_BASE1,
2267                 .num_ports      = 4,
2268                 .base_baud      = 1382400,
2269                 .uart_offset    = 8,
2270         },
2271         [pbn_b1_8_1382400] = {
2272                 .flags          = FL_BASE1,
2273                 .num_ports      = 8,
2274                 .base_baud      = 1382400,
2275                 .uart_offset    = 8,
2276         },
2277
2278         [pbn_b2_1_115200] = {
2279                 .flags          = FL_BASE2,
2280                 .num_ports      = 1,
2281                 .base_baud      = 115200,
2282                 .uart_offset    = 8,
2283         },
2284         [pbn_b2_2_115200] = {
2285                 .flags          = FL_BASE2,
2286                 .num_ports      = 2,
2287                 .base_baud      = 115200,
2288                 .uart_offset    = 8,
2289         },
2290         [pbn_b2_4_115200] = {
2291                 .flags          = FL_BASE2,
2292                 .num_ports      = 4,
2293                 .base_baud      = 115200,
2294                 .uart_offset    = 8,
2295         },
2296         [pbn_b2_8_115200] = {
2297                 .flags          = FL_BASE2,
2298                 .num_ports      = 8,
2299                 .base_baud      = 115200,
2300                 .uart_offset    = 8,
2301         },
2302
2303         [pbn_b2_1_460800] = {
2304                 .flags          = FL_BASE2,
2305                 .num_ports      = 1,
2306                 .base_baud      = 460800,
2307                 .uart_offset    = 8,
2308         },
2309         [pbn_b2_4_460800] = {
2310                 .flags          = FL_BASE2,
2311                 .num_ports      = 4,
2312                 .base_baud      = 460800,
2313                 .uart_offset    = 8,
2314         },
2315         [pbn_b2_8_460800] = {
2316                 .flags          = FL_BASE2,
2317                 .num_ports      = 8,
2318                 .base_baud      = 460800,
2319                 .uart_offset    = 8,
2320         },
2321         [pbn_b2_16_460800] = {
2322                 .flags          = FL_BASE2,
2323                 .num_ports      = 16,
2324                 .base_baud      = 460800,
2325                 .uart_offset    = 8,
2326          },
2327
2328         [pbn_b2_1_921600] = {
2329                 .flags          = FL_BASE2,
2330                 .num_ports      = 1,
2331                 .base_baud      = 921600,
2332                 .uart_offset    = 8,
2333         },
2334         [pbn_b2_4_921600] = {
2335                 .flags          = FL_BASE2,
2336                 .num_ports      = 4,
2337                 .base_baud      = 921600,
2338                 .uart_offset    = 8,
2339         },
2340         [pbn_b2_8_921600] = {
2341                 .flags          = FL_BASE2,
2342                 .num_ports      = 8,
2343                 .base_baud      = 921600,
2344                 .uart_offset    = 8,
2345         },
2346
2347         [pbn_b2_8_1152000] = {
2348                 .flags          = FL_BASE2,
2349                 .num_ports      = 8,
2350                 .base_baud      = 1152000,
2351                 .uart_offset    = 8,
2352         },
2353
2354         [pbn_b2_bt_1_115200] = {
2355                 .flags          = FL_BASE2|FL_BASE_BARS,
2356                 .num_ports      = 1,
2357                 .base_baud      = 115200,
2358                 .uart_offset    = 8,
2359         },
2360         [pbn_b2_bt_2_115200] = {
2361                 .flags          = FL_BASE2|FL_BASE_BARS,
2362                 .num_ports      = 2,
2363                 .base_baud      = 115200,
2364                 .uart_offset    = 8,
2365         },
2366         [pbn_b2_bt_4_115200] = {
2367                 .flags          = FL_BASE2|FL_BASE_BARS,
2368                 .num_ports      = 4,
2369                 .base_baud      = 115200,
2370                 .uart_offset    = 8,
2371         },
2372
2373         [pbn_b2_bt_2_921600] = {
2374                 .flags          = FL_BASE2|FL_BASE_BARS,
2375                 .num_ports      = 2,
2376                 .base_baud      = 921600,
2377                 .uart_offset    = 8,
2378         },
2379         [pbn_b2_bt_4_921600] = {
2380                 .flags          = FL_BASE2|FL_BASE_BARS,
2381                 .num_ports      = 4,
2382                 .base_baud      = 921600,
2383                 .uart_offset    = 8,
2384         },
2385
2386         [pbn_b3_2_115200] = {
2387                 .flags          = FL_BASE3,
2388                 .num_ports      = 2,
2389                 .base_baud      = 115200,
2390                 .uart_offset    = 8,
2391         },
2392         [pbn_b3_4_115200] = {
2393                 .flags          = FL_BASE3,
2394                 .num_ports      = 4,
2395                 .base_baud      = 115200,
2396                 .uart_offset    = 8,
2397         },
2398         [pbn_b3_8_115200] = {
2399                 .flags          = FL_BASE3,
2400                 .num_ports      = 8,
2401                 .base_baud      = 115200,
2402                 .uart_offset    = 8,
2403         },
2404
2405         [pbn_b4_bt_2_921600] = {
2406                 .flags          = FL_BASE4,
2407                 .num_ports      = 2,
2408                 .base_baud      = 921600,
2409                 .uart_offset    = 8,
2410         },
2411         [pbn_b4_bt_4_921600] = {
2412                 .flags          = FL_BASE4,
2413                 .num_ports      = 4,
2414                 .base_baud      = 921600,
2415                 .uart_offset    = 8,
2416         },
2417         [pbn_b4_bt_8_921600] = {
2418                 .flags          = FL_BASE4,
2419                 .num_ports      = 8,
2420                 .base_baud      = 921600,
2421                 .uart_offset    = 8,
2422         },
2423
2424         /*
2425          * Entries following this are board-specific.
2426          */
2427
2428         /*
2429          * Panacom - IOMEM
2430          */
2431         [pbn_panacom] = {
2432                 .flags          = FL_BASE2,
2433                 .num_ports      = 2,
2434                 .base_baud      = 921600,
2435                 .uart_offset    = 0x400,
2436                 .reg_shift      = 7,
2437         },
2438         [pbn_panacom2] = {
2439                 .flags          = FL_BASE2|FL_BASE_BARS,
2440                 .num_ports      = 2,
2441                 .base_baud      = 921600,
2442                 .uart_offset    = 0x400,
2443                 .reg_shift      = 7,
2444         },
2445         [pbn_panacom4] = {
2446                 .flags          = FL_BASE2|FL_BASE_BARS,
2447                 .num_ports      = 4,
2448                 .base_baud      = 921600,
2449                 .uart_offset    = 0x400,
2450                 .reg_shift      = 7,
2451         },
2452
2453         /* I think this entry is broken - the first_offset looks wrong --rmk */
2454         [pbn_plx_romulus] = {
2455                 .flags          = FL_BASE2,
2456                 .num_ports      = 4,
2457                 .base_baud      = 921600,
2458                 .uart_offset    = 8 << 2,
2459                 .reg_shift      = 2,
2460                 .first_offset   = 0x03,
2461         },
2462
2463         /*
2464          * This board uses the size of PCI Base region 0 to
2465          * signal now many ports are available
2466          */
2467         [pbn_oxsemi] = {
2468                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2469                 .num_ports      = 32,
2470                 .base_baud      = 115200,
2471                 .uart_offset    = 8,
2472         },
2473         [pbn_oxsemi_1_4000000] = {
2474                 .flags          = FL_BASE0,
2475                 .num_ports      = 1,
2476                 .base_baud      = 4000000,
2477                 .uart_offset    = 0x200,
2478                 .first_offset   = 0x1000,
2479         },
2480         [pbn_oxsemi_2_4000000] = {
2481                 .flags          = FL_BASE0,
2482                 .num_ports      = 2,
2483                 .base_baud      = 4000000,
2484                 .uart_offset    = 0x200,
2485                 .first_offset   = 0x1000,
2486         },
2487         [pbn_oxsemi_4_4000000] = {
2488                 .flags          = FL_BASE0,
2489                 .num_ports      = 4,
2490                 .base_baud      = 4000000,
2491                 .uart_offset    = 0x200,
2492                 .first_offset   = 0x1000,
2493         },
2494         [pbn_oxsemi_8_4000000] = {
2495                 .flags          = FL_BASE0,
2496                 .num_ports      = 8,
2497                 .base_baud      = 4000000,
2498                 .uart_offset    = 0x200,
2499                 .first_offset   = 0x1000,
2500         },
2501
2502
2503         /*
2504          * EKF addition for i960 Boards form EKF with serial port.
2505          * Max 256 ports.
2506          */
2507         [pbn_intel_i960] = {
2508                 .flags          = FL_BASE0,
2509                 .num_ports      = 32,
2510                 .base_baud      = 921600,
2511                 .uart_offset    = 8 << 2,
2512                 .reg_shift      = 2,
2513                 .first_offset   = 0x10000,
2514         },
2515         [pbn_sgi_ioc3] = {
2516                 .flags          = FL_BASE0|FL_NOIRQ,
2517                 .num_ports      = 1,
2518                 .base_baud      = 458333,
2519                 .uart_offset    = 8,
2520                 .reg_shift      = 0,
2521                 .first_offset   = 0x20178,
2522         },
2523
2524         /*
2525          * Computone - uses IOMEM.
2526          */
2527         [pbn_computone_4] = {
2528                 .flags          = FL_BASE0,
2529                 .num_ports      = 4,
2530                 .base_baud      = 921600,
2531                 .uart_offset    = 0x40,
2532                 .reg_shift      = 2,
2533                 .first_offset   = 0x200,
2534         },
2535         [pbn_computone_6] = {
2536                 .flags          = FL_BASE0,
2537                 .num_ports      = 6,
2538                 .base_baud      = 921600,
2539                 .uart_offset    = 0x40,
2540                 .reg_shift      = 2,
2541                 .first_offset   = 0x200,
2542         },
2543         [pbn_computone_8] = {
2544                 .flags          = FL_BASE0,
2545                 .num_ports      = 8,
2546                 .base_baud      = 921600,
2547                 .uart_offset    = 0x40,
2548                 .reg_shift      = 2,
2549                 .first_offset   = 0x200,
2550         },
2551         [pbn_sbsxrsio] = {
2552                 .flags          = FL_BASE0,
2553                 .num_ports      = 8,
2554                 .base_baud      = 460800,
2555                 .uart_offset    = 256,
2556                 .reg_shift      = 4,
2557         },
2558         /*
2559          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2560          *  Only basic 16550A support.
2561          *  XR17C15[24] are not tested, but they should work.
2562          */
2563         [pbn_exar_XR17C152] = {
2564                 .flags          = FL_BASE0,
2565                 .num_ports      = 2,
2566                 .base_baud      = 921600,
2567                 .uart_offset    = 0x200,
2568         },
2569         [pbn_exar_XR17C154] = {
2570                 .flags          = FL_BASE0,
2571                 .num_ports      = 4,
2572                 .base_baud      = 921600,
2573                 .uart_offset    = 0x200,
2574         },
2575         [pbn_exar_XR17C158] = {
2576                 .flags          = FL_BASE0,
2577                 .num_ports      = 8,
2578                 .base_baud      = 921600,
2579                 .uart_offset    = 0x200,
2580         },
2581         [pbn_exar_ibm_saturn] = {
2582                 .flags          = FL_BASE0,
2583                 .num_ports      = 1,
2584                 .base_baud      = 921600,
2585                 .uart_offset    = 0x200,
2586         },
2587
2588         /*
2589          * PA Semi PWRficient PA6T-1682M on-chip UART
2590          */
2591         [pbn_pasemi_1682M] = {
2592                 .flags          = FL_BASE0,
2593                 .num_ports      = 1,
2594                 .base_baud      = 8333333,
2595         },
2596         /*
2597          * National Instruments 843x
2598          */
2599         [pbn_ni8430_16] = {
2600                 .flags          = FL_BASE0,
2601                 .num_ports      = 16,
2602                 .base_baud      = 3686400,
2603                 .uart_offset    = 0x10,
2604                 .first_offset   = 0x800,
2605         },
2606         [pbn_ni8430_8] = {
2607                 .flags          = FL_BASE0,
2608                 .num_ports      = 8,
2609                 .base_baud      = 3686400,
2610                 .uart_offset    = 0x10,
2611                 .first_offset   = 0x800,
2612         },
2613         [pbn_ni8430_4] = {
2614                 .flags          = FL_BASE0,
2615                 .num_ports      = 4,
2616                 .base_baud      = 3686400,
2617                 .uart_offset    = 0x10,
2618                 .first_offset   = 0x800,
2619         },
2620         [pbn_ni8430_2] = {
2621                 .flags          = FL_BASE0,
2622                 .num_ports      = 2,
2623                 .base_baud      = 3686400,
2624                 .uart_offset    = 0x10,
2625                 .first_offset   = 0x800,
2626         },
2627         /*
2628          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
2629          */
2630         [pbn_ADDIDATA_PCIe_1_3906250] = {
2631                 .flags          = FL_BASE0,
2632                 .num_ports      = 1,
2633                 .base_baud      = 3906250,
2634                 .uart_offset    = 0x200,
2635                 .first_offset   = 0x1000,
2636         },
2637         [pbn_ADDIDATA_PCIe_2_3906250] = {
2638                 .flags          = FL_BASE0,
2639                 .num_ports      = 2,
2640                 .base_baud      = 3906250,
2641                 .uart_offset    = 0x200,
2642                 .first_offset   = 0x1000,
2643         },
2644         [pbn_ADDIDATA_PCIe_4_3906250] = {
2645                 .flags          = FL_BASE0,
2646                 .num_ports      = 4,
2647                 .base_baud      = 3906250,
2648                 .uart_offset    = 0x200,
2649                 .first_offset   = 0x1000,
2650         },
2651         [pbn_ADDIDATA_PCIe_8_3906250] = {
2652                 .flags          = FL_BASE0,
2653                 .num_ports      = 8,
2654                 .base_baud      = 3906250,
2655                 .uart_offset    = 0x200,
2656                 .first_offset   = 0x1000,
2657         },
2658         [pbn_ce4100_1_115200] = {
2659                 .flags          = FL_BASE0,
2660                 .num_ports      = 1,
2661                 .base_baud      = 921600,
2662                 .reg_shift      = 2,
2663         },
2664         [pbn_omegapci] = {
2665                 .flags          = FL_BASE0,
2666                 .num_ports      = 8,
2667                 .base_baud      = 115200,
2668                 .uart_offset    = 0x200,
2669         },
2670         [pbn_NETMOS9900_2s_115200] = {
2671                 .flags          = FL_BASE0,
2672                 .num_ports      = 2,
2673                 .base_baud      = 115200,
2674         },
2675 };
2676
2677 static const struct pci_device_id blacklist[] = {
2678         /* softmodems */
2679         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
2680         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
2681         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
2682
2683         /* multi-io cards handled by parport_serial */
2684         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
2685 };
2686
2687 /*
2688  * Given a complete unknown PCI device, try to use some heuristics to
2689  * guess what the configuration might be, based on the pitiful PCI
2690  * serial specs.  Returns 0 on success, 1 on failure.
2691  */
2692 static int __devinit
2693 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
2694 {
2695         const struct pci_device_id *bldev;
2696         int num_iomem, num_port, first_port = -1, i;
2697
2698         /*
2699          * If it is not a communications device or the programming
2700          * interface is greater than 6, give up.
2701          *
2702          * (Should we try to make guesses for multiport serial devices
2703          * later?)
2704          */
2705         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
2706              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
2707             (dev->class & 0xff) > 6)
2708                 return -ENODEV;
2709
2710         /*
2711          * Do not access blacklisted devices that are known not to
2712          * feature serial ports or are handled by other modules.
2713          */
2714         for (bldev = blacklist;
2715              bldev < blacklist + ARRAY_SIZE(blacklist);
2716              bldev++) {
2717                 if (dev->vendor == bldev->vendor &&
2718                     dev->device == bldev->device)
2719                         return -ENODEV;
2720         }
2721
2722         num_iomem = num_port = 0;
2723         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2724                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
2725                         num_port++;
2726                         if (first_port == -1)
2727                                 first_port = i;
2728                 }
2729                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
2730                         num_iomem++;
2731         }
2732
2733         /*
2734          * If there is 1 or 0 iomem regions, and exactly one port,
2735          * use it.  We guess the number of ports based on the IO
2736          * region size.
2737          */
2738         if (num_iomem <= 1 && num_port == 1) {
2739                 board->flags = first_port;
2740                 board->num_ports = pci_resource_len(dev, first_port) / 8;
2741                 return 0;
2742         }
2743
2744         /*
2745          * Now guess if we've got a board which indexes by BARs.
2746          * Each IO BAR should be 8 bytes, and they should follow
2747          * consecutively.
2748          */
2749         first_port = -1;
2750         num_port = 0;
2751         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2752                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
2753                     pci_resource_len(dev, i) == 8 &&
2754                     (first_port == -1 || (first_port + num_port) == i)) {
2755                         num_port++;
2756                         if (first_port == -1)
2757                                 first_port = i;
2758                 }
2759         }
2760
2761         if (num_port > 1) {
2762                 board->flags = first_port | FL_BASE_BARS;
2763                 board->num_ports = num_port;
2764                 return 0;
2765         }
2766
2767         return -ENODEV;
2768 }
2769
2770 static inline int
2771 serial_pci_matches(const struct pciserial_board *board,
2772                    const struct pciserial_board *guessed)
2773 {
2774         return
2775             board->num_ports == guessed->num_ports &&
2776             board->base_baud == guessed->base_baud &&
2777             board->uart_offset == guessed->uart_offset &&
2778             board->reg_shift == guessed->reg_shift &&
2779             board->first_offset == guessed->first_offset;
2780 }
2781
2782 struct serial_private *
2783 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
2784 {
2785         struct uart_8250_port uart;
2786         struct serial_private *priv;
2787         struct pci_serial_quirk *quirk;
2788         int rc, nr_ports, i;
2789
2790         nr_ports = board->num_ports;
2791
2792         /*
2793          * Find an init and setup quirks.
2794          */
2795         quirk = find_quirk(dev);
2796
2797         /*
2798          * Run the new-style initialization function.
2799          * The initialization function returns:
2800          *  <0  - error
2801          *   0  - use board->num_ports
2802          *  >0  - number of ports
2803          */
2804         if (quirk->init) {
2805                 rc = quirk->init(dev);
2806                 if (rc < 0) {
2807                         priv = ERR_PTR(rc);
2808                         goto err_out;
2809                 }
2810                 if (rc)
2811                         nr_ports = rc;
2812         }
2813
2814         priv = kzalloc(sizeof(struct serial_private) +
2815                        sizeof(unsigned int) * nr_ports,
2816                        GFP_KERNEL);
2817         if (!priv) {
2818                 priv = ERR_PTR(-ENOMEM);
2819                 goto err_deinit;
2820         }
2821
2822         priv->dev = dev;
2823         priv->quirk = quirk;
2824
2825         memset(&uart, 0, sizeof(uart));
2826         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
2827         uart.port.uartclk = board->base_baud * 16;
2828         uart.port.irq = get_pci_irq(dev, board);
2829         uart.port.dev = &dev->dev;
2830
2831         for (i = 0; i < nr_ports; i++) {
2832                 if (quirk->setup(priv, board, &uart, i))
2833                         break;
2834
2835 #ifdef SERIAL_DEBUG_PCI
2836                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
2837                        uart.port.iobase, uart.port.irq, uart.port.iotype);
2838 #endif
2839
2840                 priv->line[i] = serial8250_register_8250_port(&uart);
2841                 if (priv->line[i] < 0) {
2842                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
2843                         break;
2844                 }
2845         }
2846         priv->nr = i;
2847         return priv;
2848
2849 err_deinit:
2850         if (quirk->exit)
2851                 quirk->exit(dev);
2852 err_out:
2853         return priv;
2854 }
2855 EXPORT_SYMBOL_GPL(pciserial_init_ports);
2856
2857 void pciserial_remove_ports(struct serial_private *priv)
2858 {
2859         struct pci_serial_quirk *quirk;
2860         int i;
2861
2862         for (i = 0; i < priv->nr; i++)
2863                 serial8250_unregister_port(priv->line[i]);
2864
2865         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
2866                 if (priv->remapped_bar[i])
2867                         iounmap(priv->remapped_bar[i]);
2868                 priv->remapped_bar[i] = NULL;
2869         }
2870
2871         /*
2872          * Find the exit quirks.
2873          */
2874         quirk = find_quirk(priv->dev);
2875         if (quirk->exit)
2876                 quirk->exit(priv->dev);
2877
2878         kfree(priv);
2879 }
2880 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
2881
2882 void pciserial_suspend_ports(struct serial_private *priv)
2883 {
2884         int i;
2885
2886         for (i = 0; i < priv->nr; i++)
2887                 if (priv->line[i] >= 0)
2888                         serial8250_suspend_port(priv->line[i]);
2889
2890         /*
2891          * Ensure that every init quirk is properly torn down
2892          */
2893         if (priv->quirk->exit)
2894                 priv->quirk->exit(priv->dev);
2895 }
2896 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
2897
2898 void pciserial_resume_ports(struct serial_private *priv)
2899 {
2900         int i;
2901
2902         /*
2903          * Ensure that the board is correctly configured.
2904          */
2905         if (priv->quirk->init)
2906                 priv->quirk->init(priv->dev);
2907
2908         for (i = 0; i < priv->nr; i++)
2909                 if (priv->line[i] >= 0)
2910                         serial8250_resume_port(priv->line[i]);
2911 }
2912 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
2913
2914 /*
2915  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
2916  * to the arrangement of serial ports on a PCI card.
2917  */
2918 static int __devinit
2919 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
2920 {
2921         struct pci_serial_quirk *quirk;
2922         struct serial_private *priv;
2923         const struct pciserial_board *board;
2924         struct pciserial_board tmp;
2925         int rc;
2926
2927         quirk = find_quirk(dev);
2928         if (quirk->probe) {
2929                 rc = quirk->probe(dev);
2930                 if (rc)
2931                         return rc;
2932         }
2933
2934         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
2935                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
2936                         ent->driver_data);
2937                 return -EINVAL;
2938         }
2939
2940         board = &pci_boards[ent->driver_data];
2941
2942         rc = pci_enable_device(dev);
2943         pci_save_state(dev);
2944         if (rc)
2945                 return rc;
2946
2947         if (ent->driver_data == pbn_default) {
2948                 /*
2949                  * Use a copy of the pci_board entry for this;
2950                  * avoid changing entries in the table.
2951                  */
2952                 memcpy(&tmp, board, sizeof(struct pciserial_board));
2953                 board = &tmp;
2954
2955                 /*
2956                  * We matched one of our class entries.  Try to
2957                  * determine the parameters of this board.
2958                  */
2959                 rc = serial_pci_guess_board(dev, &tmp);
2960                 if (rc)
2961                         goto disable;
2962         } else {
2963                 /*
2964                  * We matched an explicit entry.  If we are able to
2965                  * detect this boards settings with our heuristic,
2966                  * then we no longer need this entry.
2967                  */
2968                 memcpy(&tmp, &pci_boards[pbn_default],
2969                        sizeof(struct pciserial_board));
2970                 rc = serial_pci_guess_board(dev, &tmp);
2971                 if (rc == 0 && serial_pci_matches(board, &tmp))
2972                         moan_device("Redundant entry in serial pci_table.",
2973                                     dev);
2974         }
2975
2976         priv = pciserial_init_ports(dev, board);
2977         if (!IS_ERR(priv)) {
2978                 pci_set_drvdata(dev, priv);
2979                 return 0;
2980         }
2981
2982         rc = PTR_ERR(priv);
2983
2984  disable:
2985         pci_disable_device(dev);
2986         return rc;
2987 }
2988
2989 static void __devexit pciserial_remove_one(struct pci_dev *dev)
2990 {
2991         struct serial_private *priv = pci_get_drvdata(dev);
2992
2993         pci_set_drvdata(dev, NULL);
2994
2995         pciserial_remove_ports(priv);
2996
2997         pci_disable_device(dev);
2998 }
2999
3000 #ifdef CONFIG_PM
3001 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3002 {
3003         struct serial_private *priv = pci_get_drvdata(dev);
3004
3005         if (priv)
3006                 pciserial_suspend_ports(priv);
3007
3008         pci_save_state(dev);
3009         pci_set_power_state(dev, pci_choose_state(dev, state));
3010         return 0;
3011 }
3012
3013 static int pciserial_resume_one(struct pci_dev *dev)
3014 {
3015         int err;
3016         struct serial_private *priv = pci_get_drvdata(dev);
3017
3018         pci_set_power_state(dev, PCI_D0);
3019         pci_restore_state(dev);
3020
3021         if (priv) {
3022                 /*
3023                  * The device may have been disabled.  Re-enable it.
3024                  */
3025                 err = pci_enable_device(dev);
3026                 /* FIXME: We cannot simply error out here */
3027                 if (err)
3028                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
3029                 pciserial_resume_ports(priv);
3030         }
3031         return 0;
3032 }
3033 #endif
3034
3035 static struct pci_device_id serial_pci_tbl[] = {
3036         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3037         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3038                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3039                 pbn_b2_8_921600 },
3040         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3041                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3042                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3043                 pbn_b1_8_1382400 },
3044         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3045                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3046                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3047                 pbn_b1_4_1382400 },
3048         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3049                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3050                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3051                 pbn_b1_2_1382400 },
3052         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3053                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3054                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3055                 pbn_b1_8_1382400 },
3056         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3057                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3058                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3059                 pbn_b1_4_1382400 },
3060         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3061                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3062                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3063                 pbn_b1_2_1382400 },
3064         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3065                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3066                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3067                 pbn_b1_8_921600 },
3068         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3069                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3070                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3071                 pbn_b1_8_921600 },
3072         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3073                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3074                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3075                 pbn_b1_4_921600 },
3076         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3077                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3078                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3079                 pbn_b1_4_921600 },
3080         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3081                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3082                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3083                 pbn_b1_2_921600 },
3084         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3085                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3086                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3087                 pbn_b1_8_921600 },
3088         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3089                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3090                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3091                 pbn_b1_8_921600 },
3092         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3093                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3094                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3095                 pbn_b1_4_921600 },
3096         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3097                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3098                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3099                 pbn_b1_2_1250000 },
3100         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3101                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3102                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3103                 pbn_b0_2_1843200 },
3104         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3105                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3106                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3107                 pbn_b0_4_1843200 },
3108         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3109                 PCI_VENDOR_ID_AFAVLAB,
3110                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3111                 pbn_b0_4_1152000 },
3112         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3113                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3114                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3115                 pbn_b0_2_1843200_200 },
3116         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3117                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3118                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3119                 pbn_b0_4_1843200_200 },
3120         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3121                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3122                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3123                 pbn_b0_8_1843200_200 },
3124         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3125                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3126                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3127                 pbn_b0_2_1843200_200 },
3128         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3129                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3130                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3131                 pbn_b0_4_1843200_200 },
3132         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3133                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3134                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3135                 pbn_b0_8_1843200_200 },
3136         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3137                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3138                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3139                 pbn_b0_2_1843200_200 },
3140         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3141                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3142                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3143                 pbn_b0_4_1843200_200 },
3144         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3145                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3146                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3147                 pbn_b0_8_1843200_200 },
3148         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3149                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3150                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3151                 pbn_b0_2_1843200_200 },
3152         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3153                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3154                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3155                 pbn_b0_4_1843200_200 },
3156         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3157                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3158                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3159                 pbn_b0_8_1843200_200 },
3160         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3161                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3162                 0, 0, pbn_exar_ibm_saturn },
3163
3164         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3165                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3166                 pbn_b2_bt_1_115200 },
3167         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3168                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3169                 pbn_b2_bt_2_115200 },
3170         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3171                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3172                 pbn_b2_bt_4_115200 },
3173         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3174                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3175                 pbn_b2_bt_2_115200 },
3176         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3177                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3178                 pbn_b2_bt_4_115200 },
3179         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3180                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3181                 pbn_b2_8_115200 },
3182         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3183                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3184                 pbn_b2_8_460800 },
3185         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3186                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3187                 pbn_b2_8_115200 },
3188
3189         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3190                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3191                 pbn_b2_bt_2_115200 },
3192         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3193                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3194                 pbn_b2_bt_2_921600 },
3195         /*
3196          * VScom SPCOM800, from sl@s.pl
3197          */
3198         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3199                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3200                 pbn_b2_8_921600 },
3201         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3202                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3203                 pbn_b2_4_921600 },
3204         /* Unknown card - subdevice 0x1584 */
3205         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3206                 PCI_VENDOR_ID_PLX,
3207                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3208                 pbn_b0_4_115200 },
3209         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3210                 PCI_SUBVENDOR_ID_KEYSPAN,
3211                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3212                 pbn_panacom },
3213         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3214                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3215                 pbn_panacom4 },
3216         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3217                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3218                 pbn_panacom2 },
3219         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3220                 PCI_VENDOR_ID_ESDGMBH,
3221                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3222                 pbn_b2_4_115200 },
3223         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3224                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3225                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3226                 pbn_b2_4_460800 },
3227         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3228                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3229                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3230                 pbn_b2_8_460800 },
3231         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3232                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3233                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3234                 pbn_b2_16_460800 },
3235         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3236                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3237                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3238                 pbn_b2_16_460800 },
3239         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3240                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3241                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3242                 pbn_b2_4_460800 },
3243         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3244                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3245                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3246                 pbn_b2_8_460800 },
3247         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3248                 PCI_SUBVENDOR_ID_EXSYS,
3249                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3250                 pbn_b2_4_115200 },
3251         /*
3252          * Megawolf Romulus PCI Serial Card, from Mike Hudson
3253          * (Exoray@isys.ca)
3254          */
3255         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3256                 0x10b5, 0x106a, 0, 0,
3257                 pbn_plx_romulus },
3258         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3259                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3260                 pbn_b1_4_115200 },
3261         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3262                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3263                 pbn_b1_2_115200 },
3264         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3265                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3266                 pbn_b1_8_115200 },
3267         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3268                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3269                 pbn_b1_8_115200 },
3270         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3271                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3272                 0, 0,
3273                 pbn_b0_4_921600 },
3274         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3275                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3276                 0, 0,
3277                 pbn_b0_4_1152000 },
3278         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
3279                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3280                 pbn_b0_bt_2_921600 },
3281
3282                 /*
3283                  * The below card is a little controversial since it is the
3284                  * subject of a PCI vendor/device ID clash.  (See
3285                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3286                  * For now just used the hex ID 0x950a.
3287                  */
3288         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3289                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_SERIAL, 0, 0,
3290                 pbn_b0_2_115200 },
3291         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3292                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3293                 pbn_b0_2_1130000 },
3294         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3295                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3296                 pbn_b0_1_921600 },
3297         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3298                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3299                 pbn_b0_4_115200 },
3300         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3301                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3302                 pbn_b0_bt_2_921600 },
3303         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3304                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3305                 pbn_b2_8_1152000 },
3306
3307         /*
3308          * Oxford Semiconductor Inc. Tornado PCI express device range.
3309          */
3310         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
3311                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3312                 pbn_b0_1_4000000 },
3313         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
3314                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3315                 pbn_b0_1_4000000 },
3316         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
3317                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3318                 pbn_oxsemi_1_4000000 },
3319         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
3320                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3321                 pbn_oxsemi_1_4000000 },
3322         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
3323                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3324                 pbn_b0_1_4000000 },
3325         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
3326                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3327                 pbn_b0_1_4000000 },
3328         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
3329                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3330                 pbn_oxsemi_1_4000000 },
3331         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
3332                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3333                 pbn_oxsemi_1_4000000 },
3334         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
3335                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3336                 pbn_b0_1_4000000 },
3337         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
3338                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3339                 pbn_b0_1_4000000 },
3340         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
3341                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3342                 pbn_b0_1_4000000 },
3343         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
3344                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3345                 pbn_b0_1_4000000 },
3346         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3347                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3348                 pbn_oxsemi_2_4000000 },
3349         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3350                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3351                 pbn_oxsemi_2_4000000 },
3352         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3353                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3354                 pbn_oxsemi_4_4000000 },
3355         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3356                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3357                 pbn_oxsemi_4_4000000 },
3358         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3359                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3360                 pbn_oxsemi_8_4000000 },
3361         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3362                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3363                 pbn_oxsemi_8_4000000 },
3364         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3365                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3366                 pbn_oxsemi_1_4000000 },
3367         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3368                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3369                 pbn_oxsemi_1_4000000 },
3370         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3371                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3372                 pbn_oxsemi_1_4000000 },
3373         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3374                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3375                 pbn_oxsemi_1_4000000 },
3376         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3377                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3378                 pbn_oxsemi_1_4000000 },
3379         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3380                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3381                 pbn_oxsemi_1_4000000 },
3382         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3383                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3384                 pbn_oxsemi_1_4000000 },
3385         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3386                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3387                 pbn_oxsemi_1_4000000 },
3388         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3389                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3390                 pbn_oxsemi_1_4000000 },
3391         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3392                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3393                 pbn_oxsemi_1_4000000 },
3394         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3395                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3396                 pbn_oxsemi_1_4000000 },
3397         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3398                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3399                 pbn_oxsemi_1_4000000 },
3400         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3401                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3402                 pbn_oxsemi_1_4000000 },
3403         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3404                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3405                 pbn_oxsemi_1_4000000 },
3406         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3407                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3408                 pbn_oxsemi_1_4000000 },
3409         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3410                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3411                 pbn_oxsemi_1_4000000 },
3412         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3413                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3414                 pbn_oxsemi_1_4000000 },
3415         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3416                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3417                 pbn_oxsemi_1_4000000 },
3418         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3419                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3420                 pbn_oxsemi_1_4000000 },
3421         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
3422                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3423                 pbn_oxsemi_1_4000000 },
3424         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
3425                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3426                 pbn_oxsemi_1_4000000 },
3427         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
3428                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3429                 pbn_oxsemi_1_4000000 },
3430         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
3431                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3432                 pbn_oxsemi_1_4000000 },
3433         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
3434                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3435                 pbn_oxsemi_1_4000000 },
3436         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
3437                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3438                 pbn_oxsemi_1_4000000 },
3439         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
3440                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3441                 pbn_oxsemi_1_4000000 },
3442         /*
3443          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
3444          */
3445         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
3446                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
3447                 pbn_oxsemi_1_4000000 },
3448         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
3449                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
3450                 pbn_oxsemi_2_4000000 },
3451         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
3452                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
3453                 pbn_oxsemi_4_4000000 },
3454         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
3455                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
3456                 pbn_oxsemi_8_4000000 },
3457
3458         /*
3459          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
3460          */
3461         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
3462                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
3463                 pbn_oxsemi_2_4000000 },
3464
3465         /*
3466          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
3467          * from skokodyn@yahoo.com
3468          */
3469         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3470                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
3471                 pbn_sbsxrsio },
3472         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3473                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
3474                 pbn_sbsxrsio },
3475         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3476                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
3477                 pbn_sbsxrsio },
3478         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
3479                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
3480                 pbn_sbsxrsio },
3481
3482         /*
3483          * Digitan DS560-558, from jimd@esoft.com
3484          */
3485         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
3486                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3487                 pbn_b1_1_115200 },
3488
3489         /*
3490          * Titan Electronic cards
3491          *  The 400L and 800L have a custom setup quirk.
3492          */
3493         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
3494                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3495                 pbn_b0_1_921600 },
3496         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
3497                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3498                 pbn_b0_2_921600 },
3499         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
3500                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3501                 pbn_b0_4_921600 },
3502         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
3503                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3504                 pbn_b0_4_921600 },
3505         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
3506                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3507                 pbn_b1_1_921600 },
3508         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
3509                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3510                 pbn_b1_bt_2_921600 },
3511         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
3512                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3513                 pbn_b0_bt_4_921600 },
3514         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
3515                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3516                 pbn_b0_bt_8_921600 },
3517         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
3518                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3519                 pbn_b4_bt_2_921600 },
3520         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
3521                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3522                 pbn_b4_bt_4_921600 },
3523         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
3524                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3525                 pbn_b4_bt_8_921600 },
3526         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
3527                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3528                 pbn_b0_4_921600 },
3529         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
3530                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3531                 pbn_b0_4_921600 },
3532         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
3533                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3534                 pbn_b0_4_921600 },
3535         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
3536                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3537                 pbn_oxsemi_1_4000000 },
3538         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
3539                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3540                 pbn_oxsemi_2_4000000 },
3541         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
3542                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3543                 pbn_oxsemi_4_4000000 },
3544         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
3545                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3546                 pbn_oxsemi_8_4000000 },
3547         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
3548                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3549                 pbn_oxsemi_2_4000000 },
3550         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
3551                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3552                 pbn_oxsemi_2_4000000 },
3553         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
3554                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3555                 pbn_b0_4_921600 },
3556         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
3557                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3558                 pbn_b0_4_921600 },
3559         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
3560                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3561                 pbn_b0_4_921600 },
3562         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
3563                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3564                 pbn_b0_4_921600 },
3565
3566         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
3567                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3568                 pbn_b2_1_460800 },
3569         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
3570                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3571                 pbn_b2_1_460800 },
3572         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
3573                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3574                 pbn_b2_1_460800 },
3575         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
3576                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3577                 pbn_b2_bt_2_921600 },
3578         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
3579                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3580                 pbn_b2_bt_2_921600 },
3581         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
3582                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3583                 pbn_b2_bt_2_921600 },
3584         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
3585                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3586                 pbn_b2_bt_4_921600 },
3587         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
3588                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3589                 pbn_b2_bt_4_921600 },
3590         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
3591                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3592                 pbn_b2_bt_4_921600 },
3593         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
3594                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3595                 pbn_b0_1_921600 },
3596         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
3597                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3598                 pbn_b0_1_921600 },
3599         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
3600                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3601                 pbn_b0_1_921600 },
3602         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
3603                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3604                 pbn_b0_bt_2_921600 },
3605         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
3606                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3607                 pbn_b0_bt_2_921600 },
3608         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
3609                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3610                 pbn_b0_bt_2_921600 },
3611         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
3612                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3613                 pbn_b0_bt_4_921600 },
3614         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
3615                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3616                 pbn_b0_bt_4_921600 },
3617         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
3618                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3619                 pbn_b0_bt_4_921600 },
3620         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
3621                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3622                 pbn_b0_bt_8_921600 },
3623         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
3624                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3625                 pbn_b0_bt_8_921600 },
3626         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
3627                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3628                 pbn_b0_bt_8_921600 },
3629
3630         /*
3631          * Computone devices submitted by Doug McNash dmcnash@computone.com
3632          */
3633         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3634                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
3635                 0, 0, pbn_computone_4 },
3636         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3637                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
3638                 0, 0, pbn_computone_8 },
3639         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
3640                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
3641                 0, 0, pbn_computone_6 },
3642
3643         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
3644                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3645                 pbn_oxsemi },
3646         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
3647                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
3648                 pbn_b0_bt_1_921600 },
3649
3650         /*
3651          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
3652          */
3653         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
3654                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3655                 pbn_b0_bt_8_115200 },
3656         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
3657                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3658                 pbn_b0_bt_8_115200 },
3659
3660         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
3661                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3662                 pbn_b0_bt_2_115200 },
3663         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
3664                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3665                 pbn_b0_bt_2_115200 },
3666         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
3667                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3668                 pbn_b0_bt_2_115200 },
3669         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
3670                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3671                 pbn_b0_bt_2_115200 },
3672         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
3673                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3674                 pbn_b0_bt_2_115200 },
3675         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
3676                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3677                 pbn_b0_bt_4_460800 },
3678         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
3679                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3680                 pbn_b0_bt_4_460800 },
3681         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
3682                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3683                 pbn_b0_bt_2_460800 },
3684         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
3685                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3686                 pbn_b0_bt_2_460800 },
3687         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
3688                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3689                 pbn_b0_bt_2_460800 },
3690         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
3691                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3692                 pbn_b0_bt_1_115200 },
3693         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
3694                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3695                 pbn_b0_bt_1_460800 },
3696
3697         /*
3698          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
3699          * Cards are identified by their subsystem vendor IDs, which
3700          * (in hex) match the model number.
3701          *
3702          * Note that JC140x are RS422/485 cards which require ox950
3703          * ACR = 0x10, and as such are not currently fully supported.
3704          */
3705         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3706                 0x1204, 0x0004, 0, 0,
3707                 pbn_b0_4_921600 },
3708         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3709                 0x1208, 0x0004, 0, 0,
3710                 pbn_b0_4_921600 },
3711 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3712                 0x1402, 0x0002, 0, 0,
3713                 pbn_b0_2_921600 }, */
3714 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
3715                 0x1404, 0x0004, 0, 0,
3716                 pbn_b0_4_921600 }, */
3717         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
3718                 0x1208, 0x0004, 0, 0,
3719                 pbn_b0_4_921600 },
3720
3721         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3722                 0x1204, 0x0004, 0, 0,
3723                 pbn_b0_4_921600 },
3724         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
3725                 0x1208, 0x0004, 0, 0,
3726                 pbn_b0_4_921600 },
3727         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
3728                 0x1208, 0x0004, 0, 0,
3729                 pbn_b0_4_921600 },
3730         /*
3731          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
3732          */
3733         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
3734                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3735                 pbn_b1_1_1382400 },
3736
3737         /*
3738          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
3739          */
3740         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
3741                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3742                 pbn_b1_1_1382400 },
3743
3744         /*
3745          * RAStel 2 port modem, gerg@moreton.com.au
3746          */
3747         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
3748                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3749                 pbn_b2_bt_2_115200 },
3750
3751         /*
3752          * EKF addition for i960 Boards form EKF with serial port
3753          */
3754         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
3755                 0xE4BF, PCI_ANY_ID, 0, 0,
3756                 pbn_intel_i960 },
3757
3758         /*
3759          * Xircom Cardbus/Ethernet combos
3760          */
3761         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
3762                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3763                 pbn_b0_1_115200 },
3764         /*
3765          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
3766          */
3767         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
3768                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3769                 pbn_b0_1_115200 },
3770
3771         /*
3772          * Untested PCI modems, sent in from various folks...
3773          */
3774
3775         /*
3776          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
3777          */
3778         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
3779                 0x1048, 0x1500, 0, 0,
3780                 pbn_b1_1_115200 },
3781
3782         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
3783                 0xFF00, 0, 0, 0,
3784                 pbn_sgi_ioc3 },
3785
3786         /*
3787          * HP Diva card
3788          */
3789         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3790                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
3791                 pbn_b1_1_115200 },
3792         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
3793                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3794                 pbn_b0_5_115200 },
3795         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
3796                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3797                 pbn_b2_1_115200 },
3798
3799         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
3800                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3801                 pbn_b3_2_115200 },
3802         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
3803                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3804                 pbn_b3_4_115200 },
3805         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
3806                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3807                 pbn_b3_8_115200 },
3808
3809         /*
3810          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3811          */
3812         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3813                 PCI_ANY_ID, PCI_ANY_ID,
3814                 0,
3815                 0, pbn_exar_XR17C152 },
3816         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3817                 PCI_ANY_ID, PCI_ANY_ID,
3818                 0,
3819                 0, pbn_exar_XR17C154 },
3820         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3821                 PCI_ANY_ID, PCI_ANY_ID,
3822                 0,
3823                 0, pbn_exar_XR17C158 },
3824
3825         /*
3826          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
3827          */
3828         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
3829                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3830                 pbn_b0_1_115200 },
3831         /*
3832          * ITE
3833          */
3834         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
3835                 PCI_ANY_ID, PCI_ANY_ID,
3836                 0, 0,
3837                 pbn_b1_bt_1_115200 },
3838
3839         /*
3840          * IntaShield IS-200
3841          */
3842         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
3843                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
3844                 pbn_b2_2_115200 },
3845         /*
3846          * IntaShield IS-400
3847          */
3848         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
3849                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
3850                 pbn_b2_4_115200 },
3851         /*
3852          * Perle PCI-RAS cards
3853          */
3854         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3855                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
3856                 0, 0, pbn_b2_4_921600 },
3857         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3858                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
3859                 0, 0, pbn_b2_8_921600 },
3860
3861         /*
3862          * Mainpine series cards: Fairly standard layout but fools
3863          * parts of the autodetect in some cases and uses otherwise
3864          * unmatched communications subclasses in the PCI Express case
3865          */
3866
3867         {       /* RockForceDUO */
3868                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3869                 PCI_VENDOR_ID_MAINPINE, 0x0200,
3870                 0, 0, pbn_b0_2_115200 },
3871         {       /* RockForceQUATRO */
3872                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3873                 PCI_VENDOR_ID_MAINPINE, 0x0300,
3874                 0, 0, pbn_b0_4_115200 },
3875         {       /* RockForceDUO+ */
3876                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3877                 PCI_VENDOR_ID_MAINPINE, 0x0400,
3878                 0, 0, pbn_b0_2_115200 },
3879         {       /* RockForceQUATRO+ */
3880                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3881                 PCI_VENDOR_ID_MAINPINE, 0x0500,
3882                 0, 0, pbn_b0_4_115200 },
3883         {       /* RockForce+ */
3884                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3885                 PCI_VENDOR_ID_MAINPINE, 0x0600,
3886                 0, 0, pbn_b0_2_115200 },
3887         {       /* RockForce+ */
3888                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3889                 PCI_VENDOR_ID_MAINPINE, 0x0700,
3890                 0, 0, pbn_b0_4_115200 },
3891         {       /* RockForceOCTO+ */
3892                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3893                 PCI_VENDOR_ID_MAINPINE, 0x0800,
3894                 0, 0, pbn_b0_8_115200 },
3895         {       /* RockForceDUO+ */
3896                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3897                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
3898                 0, 0, pbn_b0_2_115200 },
3899         {       /* RockForceQUARTRO+ */
3900                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3901                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
3902                 0, 0, pbn_b0_4_115200 },
3903         {       /* RockForceOCTO+ */
3904                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3905                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
3906                 0, 0, pbn_b0_8_115200 },
3907         {       /* RockForceD1 */
3908                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3909                 PCI_VENDOR_ID_MAINPINE, 0x2000,
3910                 0, 0, pbn_b0_1_115200 },
3911         {       /* RockForceF1 */
3912                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3913                 PCI_VENDOR_ID_MAINPINE, 0x2100,
3914                 0, 0, pbn_b0_1_115200 },
3915         {       /* RockForceD2 */
3916                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3917                 PCI_VENDOR_ID_MAINPINE, 0x2200,
3918                 0, 0, pbn_b0_2_115200 },
3919         {       /* RockForceF2 */
3920                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3921                 PCI_VENDOR_ID_MAINPINE, 0x2300,
3922                 0, 0, pbn_b0_2_115200 },
3923         {       /* RockForceD4 */
3924                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3925                 PCI_VENDOR_ID_MAINPINE, 0x2400,
3926                 0, 0, pbn_b0_4_115200 },
3927         {       /* RockForceF4 */
3928                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3929                 PCI_VENDOR_ID_MAINPINE, 0x2500,
3930                 0, 0, pbn_b0_4_115200 },
3931         {       /* RockForceD8 */
3932                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3933                 PCI_VENDOR_ID_MAINPINE, 0x2600,
3934                 0, 0, pbn_b0_8_115200 },
3935         {       /* RockForceF8 */
3936                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3937                 PCI_VENDOR_ID_MAINPINE, 0x2700,
3938                 0, 0, pbn_b0_8_115200 },
3939         {       /* IQ Express D1 */
3940                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3941                 PCI_VENDOR_ID_MAINPINE, 0x3000,
3942                 0, 0, pbn_b0_1_115200 },
3943         {       /* IQ Express F1 */
3944                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3945                 PCI_VENDOR_ID_MAINPINE, 0x3100,
3946                 0, 0, pbn_b0_1_115200 },
3947         {       /* IQ Express D2 */
3948                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3949                 PCI_VENDOR_ID_MAINPINE, 0x3200,
3950                 0, 0, pbn_b0_2_115200 },
3951         {       /* IQ Express F2 */
3952                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3953                 PCI_VENDOR_ID_MAINPINE, 0x3300,
3954                 0, 0, pbn_b0_2_115200 },
3955         {       /* IQ Express D4 */
3956                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3957                 PCI_VENDOR_ID_MAINPINE, 0x3400,
3958                 0, 0, pbn_b0_4_115200 },
3959         {       /* IQ Express F4 */
3960                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3961                 PCI_VENDOR_ID_MAINPINE, 0x3500,
3962                 0, 0, pbn_b0_4_115200 },
3963         {       /* IQ Express D8 */
3964                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3965                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
3966                 0, 0, pbn_b0_8_115200 },
3967         {       /* IQ Express F8 */
3968                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
3969                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
3970                 0, 0, pbn_b0_8_115200 },
3971
3972
3973         /*
3974          * PA Semi PA6T-1682M on-chip UART
3975          */
3976         {       PCI_VENDOR_ID_PASEMI, 0xa004,
3977                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3978                 pbn_pasemi_1682M },
3979
3980         /*
3981          * National Instruments
3982          */
3983         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
3984                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3985                 pbn_b1_16_115200 },
3986         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
3987                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3988                 pbn_b1_8_115200 },
3989         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
3990                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3991                 pbn_b1_bt_4_115200 },
3992         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
3993                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3994                 pbn_b1_bt_2_115200 },
3995         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
3996                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3997                 pbn_b1_bt_4_115200 },
3998         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
3999                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4000                 pbn_b1_bt_2_115200 },
4001         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4002                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4003                 pbn_b1_16_115200 },
4004         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4005                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4006                 pbn_b1_8_115200 },
4007         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4008                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4009                 pbn_b1_bt_4_115200 },
4010         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4011                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4012                 pbn_b1_bt_2_115200 },
4013         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4014                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4015                 pbn_b1_bt_4_115200 },
4016         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4017                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4018                 pbn_b1_bt_2_115200 },
4019         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4020                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4021                 pbn_ni8430_2 },
4022         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4023                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4024                 pbn_ni8430_2 },
4025         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4026                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4027                 pbn_ni8430_4 },
4028         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4029                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4030                 pbn_ni8430_4 },
4031         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4032                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4033                 pbn_ni8430_8 },
4034         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4035                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4036                 pbn_ni8430_8 },
4037         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4038                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4039                 pbn_ni8430_16 },
4040         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4041                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4042                 pbn_ni8430_16 },
4043         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4044                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4045                 pbn_ni8430_2 },
4046         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4047                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4048                 pbn_ni8430_2 },
4049         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4050                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4051                 pbn_ni8430_4 },
4052         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4053                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4054                 pbn_ni8430_4 },
4055
4056         /*
4057         * ADDI-DATA GmbH communication cards <info@addi-data.com>
4058         */
4059         {       PCI_VENDOR_ID_ADDIDATA,
4060                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4061                 PCI_ANY_ID,
4062                 PCI_ANY_ID,
4063                 0,
4064                 0,
4065                 pbn_b0_4_115200 },
4066
4067         {       PCI_VENDOR_ID_ADDIDATA,
4068                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4069                 PCI_ANY_ID,
4070                 PCI_ANY_ID,
4071                 0,
4072                 0,
4073                 pbn_b0_2_115200 },
4074
4075         {       PCI_VENDOR_ID_ADDIDATA,
4076                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4077                 PCI_ANY_ID,
4078                 PCI_ANY_ID,
4079                 0,
4080                 0,
4081                 pbn_b0_1_115200 },
4082
4083         {       PCI_VENDOR_ID_ADDIDATA_OLD,
4084                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4085                 PCI_ANY_ID,
4086                 PCI_ANY_ID,
4087                 0,
4088                 0,
4089                 pbn_b1_8_115200 },
4090
4091         {       PCI_VENDOR_ID_ADDIDATA,
4092                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4093                 PCI_ANY_ID,
4094                 PCI_ANY_ID,
4095                 0,
4096                 0,
4097                 pbn_b0_4_115200 },
4098
4099         {       PCI_VENDOR_ID_ADDIDATA,
4100                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4101                 PCI_ANY_ID,
4102                 PCI_ANY_ID,
4103                 0,
4104                 0,
4105                 pbn_b0_2_115200 },
4106
4107         {       PCI_VENDOR_ID_ADDIDATA,
4108                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4109                 PCI_ANY_ID,
4110                 PCI_ANY_ID,
4111                 0,
4112                 0,
4113                 pbn_b0_1_115200 },
4114
4115         {       PCI_VENDOR_ID_ADDIDATA,
4116                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4117                 PCI_ANY_ID,
4118                 PCI_ANY_ID,
4119                 0,
4120                 0,
4121                 pbn_b0_4_115200 },
4122
4123         {       PCI_VENDOR_ID_ADDIDATA,
4124                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4125                 PCI_ANY_ID,
4126                 PCI_ANY_ID,
4127                 0,
4128                 0,
4129                 pbn_b0_2_115200 },
4130
4131         {       PCI_VENDOR_ID_ADDIDATA,
4132                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4133                 PCI_ANY_ID,
4134                 PCI_ANY_ID,
4135                 0,
4136                 0,
4137                 pbn_b0_1_115200 },
4138
4139         {       PCI_VENDOR_ID_ADDIDATA,
4140                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4141                 PCI_ANY_ID,
4142                 PCI_ANY_ID,
4143                 0,
4144                 0,
4145                 pbn_b0_8_115200 },
4146
4147         {       PCI_VENDOR_ID_ADDIDATA,
4148                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4149                 PCI_ANY_ID,
4150                 PCI_ANY_ID,
4151                 0,
4152                 0,
4153                 pbn_ADDIDATA_PCIe_4_3906250 },
4154
4155         {       PCI_VENDOR_ID_ADDIDATA,
4156                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4157                 PCI_ANY_ID,
4158                 PCI_ANY_ID,
4159                 0,
4160                 0,
4161                 pbn_ADDIDATA_PCIe_2_3906250 },
4162
4163         {       PCI_VENDOR_ID_ADDIDATA,
4164                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4165                 PCI_ANY_ID,
4166                 PCI_ANY_ID,
4167                 0,
4168                 0,
4169                 pbn_ADDIDATA_PCIe_1_3906250 },
4170
4171         {       PCI_VENDOR_ID_ADDIDATA,
4172                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4173                 PCI_ANY_ID,
4174                 PCI_ANY_ID,
4175                 0,
4176                 0,
4177                 pbn_ADDIDATA_PCIe_8_3906250 },
4178
4179         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4180                 PCI_VENDOR_ID_IBM, 0x0299,
4181                 0, 0, pbn_b0_bt_2_115200 },
4182
4183         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4184                 0xA000, 0x1000,
4185                 0, 0, pbn_b0_1_115200 },
4186
4187         /* the 9901 is a rebranded 9912 */
4188         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4189                 0xA000, 0x1000,
4190                 0, 0, pbn_b0_1_115200 },
4191
4192         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4193                 0xA000, 0x1000,
4194                 0, 0, pbn_b0_1_115200 },
4195
4196         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4197                 0xA000, 0x1000,
4198                 0, 0, pbn_b0_1_115200 },
4199
4200         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4201                 0xA000, 0x1000,
4202                 0, 0, pbn_b0_1_115200 },
4203
4204         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4205                 0xA000, 0x3002,
4206                 0, 0, pbn_NETMOS9900_2s_115200 },
4207
4208         /*
4209          * Best Connectivity and Rosewill PCI Multi I/O cards
4210          */
4211
4212         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4213                 0xA000, 0x1000,
4214                 0, 0, pbn_b0_1_115200 },
4215
4216         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4217                 0xA000, 0x3002,
4218                 0, 0, pbn_b0_bt_2_115200 },
4219
4220         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4221                 0xA000, 0x3004,
4222                 0, 0, pbn_b0_bt_4_115200 },
4223         /* Intel CE4100 */
4224         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4225                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
4226                 pbn_ce4100_1_115200 },
4227
4228         /*
4229          * Cronyx Omega PCI
4230          */
4231         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4232                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4233                 pbn_omegapci },
4234
4235         /*
4236          * AgeStar as-prs2-009
4237          */
4238         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4239                 PCI_ANY_ID, PCI_ANY_ID,
4240                 0, 0, pbn_b0_bt_2_115200 },
4241
4242         /*
4243          * WCH CH353 series devices: The 2S1P is handled by parport_serial
4244          * so not listed here.
4245          */
4246         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
4247                 PCI_ANY_ID, PCI_ANY_ID,
4248                 0, 0, pbn_b0_bt_4_115200 },
4249
4250         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
4251                 PCI_ANY_ID, PCI_ANY_ID,
4252                 0, 0, pbn_b0_bt_2_115200 },
4253
4254         /*
4255          * These entries match devices with class COMMUNICATION_SERIAL,
4256          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4257          */
4258         {       PCI_ANY_ID, PCI_ANY_ID,
4259                 PCI_ANY_ID, PCI_ANY_ID,
4260                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4261                 0xffff00, pbn_default },
4262         {       PCI_ANY_ID, PCI_ANY_ID,
4263                 PCI_ANY_ID, PCI_ANY_ID,
4264                 PCI_CLASS_COMMUNICATION_MODEM << 8,
4265                 0xffff00, pbn_default },
4266         {       PCI_ANY_ID, PCI_ANY_ID,
4267                 PCI_ANY_ID, PCI_ANY_ID,
4268                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4269                 0xffff00, pbn_default },
4270         { 0, }
4271 };
4272
4273 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4274                                                 pci_channel_state_t state)
4275 {
4276         struct serial_private *priv = pci_get_drvdata(dev);
4277
4278         if (state == pci_channel_io_perm_failure)
4279                 return PCI_ERS_RESULT_DISCONNECT;
4280
4281         if (priv)
4282                 pciserial_suspend_ports(priv);
4283
4284         pci_disable_device(dev);
4285
4286         return PCI_ERS_RESULT_NEED_RESET;
4287 }
4288
4289 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4290 {
4291         int rc;
4292
4293         rc = pci_enable_device(dev);
4294
4295         if (rc)
4296                 return PCI_ERS_RESULT_DISCONNECT;
4297
4298         pci_restore_state(dev);
4299         pci_save_state(dev);
4300
4301         return PCI_ERS_RESULT_RECOVERED;
4302 }
4303
4304 static void serial8250_io_resume(struct pci_dev *dev)
4305 {
4306         struct serial_private *priv = pci_get_drvdata(dev);
4307
4308         if (priv)
4309                 pciserial_resume_ports(priv);
4310 }
4311
4312 static struct pci_error_handlers serial8250_err_handler = {
4313         .error_detected = serial8250_io_error_detected,
4314         .slot_reset = serial8250_io_slot_reset,
4315         .resume = serial8250_io_resume,
4316 };
4317
4318 static struct pci_driver serial_pci_driver = {
4319         .name           = "serial",
4320         .probe          = pciserial_init_one,
4321         .remove         = __devexit_p(pciserial_remove_one),
4322 #ifdef CONFIG_PM
4323         .suspend        = pciserial_suspend_one,
4324         .resume         = pciserial_resume_one,
4325 #endif
4326         .id_table       = serial_pci_tbl,
4327         .err_handler    = &serial8250_err_handler,
4328 };
4329
4330 static int __init serial8250_pci_init(void)
4331 {
4332         return pci_register_driver(&serial_pci_driver);
4333 }
4334
4335 static void __exit serial8250_pci_exit(void)
4336 {
4337         pci_unregister_driver(&serial_pci_driver);
4338 }
4339
4340 module_init(serial8250_pci_init);
4341 module_exit(serial8250_pci_exit);
4342
4343 MODULE_LICENSE("GPL");
4344 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4345 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);