1 // SPDX-License-Identifier: GPL-2.0
3 * 8250-core based driver for the OMAP internal UART
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
7 * Copyright (C) 2014 Sebastian Andrzej Siewior
11 #include <linux/clk.h>
12 #include <linux/device.h>
14 #include <linux/module.h>
15 #include <linux/serial_8250.h>
16 #include <linux/serial_reg.h>
17 #include <linux/tty_flip.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/delay.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/console.h>
26 #include <linux/pm_qos.h>
27 #include <linux/pm_wakeirq.h>
28 #include <linux/dma-mapping.h>
29 #include <linux/sys_soc.h>
33 #define DEFAULT_CLK_SPEED 48000000
34 #define OMAP_UART_REGSHIFT 2
36 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
37 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
38 #define OMAP_DMA_TX_KICK (1 << 2)
40 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
41 * The same errata is applicable to AM335x and DRA7x processors too.
43 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
44 #define UART_HAS_EFR2 BIT(4)
45 #define UART_HAS_RHR_IT_DIS BIT(5)
46 #define UART_RX_TIMEOUT_QUIRK BIT(6)
47 #define UART_HAS_NATIVE_RS485 BIT(7)
49 #define OMAP_UART_FCR_RX_TRIG 6
50 #define OMAP_UART_FCR_TX_TRIG 4
52 /* SCR register bitmasks */
53 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
54 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
55 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
56 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
57 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
58 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
60 /* MVR register bitmasks */
61 #define OMAP_UART_MVR_SCHEME_SHIFT 30
62 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
63 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
64 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
65 #define OMAP_UART_MVR_MAJ_MASK 0x700
66 #define OMAP_UART_MVR_MAJ_SHIFT 8
67 #define OMAP_UART_MVR_MIN_MASK 0x3f
69 /* SYSC register bitmasks */
70 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
72 /* SYSS register bitmasks */
73 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
75 #define UART_TI752_TLR_TX 0
76 #define UART_TI752_TLR_RX 4
78 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
79 #define TRIGGER_FCR_MASK(x) (x & 3)
81 /* Enable XON/XOFF flow control on output */
82 #define OMAP_UART_SW_TX 0x08
83 /* Enable XON/XOFF flow control on input */
84 #define OMAP_UART_SW_RX 0x02
86 #define OMAP_UART_WER_MOD_WKUP 0x7f
87 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
92 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
93 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
95 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
97 #define OMAP_UART_REV_46 0x0406
98 #define OMAP_UART_REV_52 0x0502
99 #define OMAP_UART_REV_63 0x0603
101 /* Interrupt Enable Register 2 */
102 #define UART_OMAP_IER2 0x1B
103 #define UART_OMAP_IER2_RHR_IT_DIS BIT(2)
105 /* Mode Definition Register 3 */
106 #define UART_OMAP_MDR3 0x20
107 #define UART_OMAP_MDR3_DIR_POL BIT(3)
108 #define UART_OMAP_MDR3_DIR_EN BIT(4)
110 /* Enhanced features register 2 */
111 #define UART_OMAP_EFR2 0x23
112 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE BIT(6)
114 /* RX FIFO occupancy indicator */
115 #define UART_OMAP_RX_LVL 0x19
117 struct omap8250_priv {
118 void __iomem *membase;
138 struct pm_qos_request pm_qos_request;
139 struct work_struct qos_work;
140 struct uart_8250_dma omap8250_dma;
141 spinlock_t rx_dma_lock;
146 struct omap8250_dma_params {
152 struct omap8250_platdata {
153 struct omap8250_dma_params *dma_params;
157 #ifdef CONFIG_SERIAL_8250_DMA
158 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
160 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
163 static u32 uart_read(struct omap8250_priv *priv, u32 reg)
165 return readl(priv->membase + (reg << OMAP_UART_REGSHIFT));
169 * Called on runtime PM resume path from omap8250_restore_regs(), and
170 * omap8250_set_mctrl().
172 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
174 struct uart_8250_port *up = up_to_u8250p(port);
175 struct omap8250_priv *priv = up->port.private_data;
178 serial8250_do_set_mctrl(port, mctrl);
180 if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
182 * Turn off autoRTS if RTS is lowered and restore autoRTS
183 * setting if RTS is raised
185 lcr = serial_in(up, UART_LCR);
186 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
187 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
188 priv->efr |= UART_EFR_RTS;
190 priv->efr &= ~UART_EFR_RTS;
191 serial_out(up, UART_EFR, priv->efr);
192 serial_out(up, UART_LCR, lcr);
196 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
200 err = pm_runtime_resume_and_get(port->dev);
204 __omap8250_set_mctrl(port, mctrl);
206 pm_runtime_mark_last_busy(port->dev);
207 pm_runtime_put_autosuspend(port->dev);
211 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
212 * The access to uart register after MDR1 Access
213 * causes UART to corrupt data.
216 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
217 * give 10 times as much
219 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
220 struct omap8250_priv *priv)
222 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
224 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
225 UART_FCR_CLEAR_RCVR);
228 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
229 struct omap8250_priv *priv)
231 unsigned int uartclk = port->uartclk;
232 unsigned int div_13, div_16;
233 unsigned int abs_d13, abs_d16;
236 * Old custom speed handling.
238 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
239 priv->quot = port->custom_divisor & UART_DIV_MAX;
241 * I assume that nobody is using this. But hey, if somebody
242 * would like to specify the divisor _and_ the mode then the
243 * driver is ready and waiting for it.
245 if (port->custom_divisor & (1 << 16))
246 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
248 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
251 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
252 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
259 abs_d13 = abs(baud - uartclk / 13 / div_13);
260 abs_d16 = abs(baud - uartclk / 16 / div_16);
262 if (abs_d13 >= abs_d16) {
263 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
266 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
271 static void omap8250_update_scr(struct uart_8250_port *up,
272 struct omap8250_priv *priv)
276 old_scr = serial_in(up, UART_OMAP_SCR);
277 if (old_scr == priv->scr)
281 * The manual recommends not to enable the DMA mode selector in the SCR
282 * (instead of the FCR) register _and_ selecting the DMA mode as one
283 * register write because this may lead to malfunction.
285 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
286 serial_out(up, UART_OMAP_SCR,
287 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
288 serial_out(up, UART_OMAP_SCR, priv->scr);
291 static void omap8250_update_mdr1(struct uart_8250_port *up,
292 struct omap8250_priv *priv)
294 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
295 omap_8250_mdr1_errataset(up, priv);
297 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
300 static void omap8250_restore_regs(struct uart_8250_port *up)
302 struct omap8250_priv *priv = up->port.private_data;
303 struct uart_8250_dma *dma = up->dma;
304 u8 mcr = serial8250_in_MCR(up);
306 /* Port locked to synchronize UART_IER access against the console. */
307 lockdep_assert_held_once(&up->port.lock);
309 if (dma && dma->tx_running) {
311 * TCSANOW requests the change to occur immediately however if
312 * we have a TX-DMA operation in progress then it has been
313 * observed that it might stall and never complete. Therefore we
314 * delay DMA completes to prevent this hang from happen.
316 priv->delayed_restore = 1;
320 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
321 serial_out(up, UART_EFR, UART_EFR_ECB);
323 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
324 serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR);
325 serial_out(up, UART_FCR, up->fcr);
327 omap8250_update_scr(up, priv);
329 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
331 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
332 OMAP_UART_TCR_HALT(52));
333 serial_out(up, UART_TI752_TLR,
334 TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
335 TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
337 serial_out(up, UART_LCR, 0);
339 /* drop TCR + TLR access, we setup XON/XOFF later */
340 serial8250_out_MCR(up, mcr);
342 serial_out(up, UART_IER, up->ier);
344 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
345 serial_dl_write(up, priv->quot);
347 serial_out(up, UART_EFR, priv->efr);
349 /* Configure flow control */
350 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
351 serial_out(up, UART_XON1, priv->xon);
352 serial_out(up, UART_XOFF1, priv->xoff);
354 serial_out(up, UART_LCR, up->lcr);
356 omap8250_update_mdr1(up, priv);
358 __omap8250_set_mctrl(&up->port, up->port.mctrl);
360 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
362 if (up->port.rs485.flags & SER_RS485_ENABLED &&
363 up->port.rs485_config == serial8250_em485_config)
364 serial8250_em485_stop_tx(up);
368 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
369 * some differences in how we want to handle flow control.
371 static void omap_8250_set_termios(struct uart_port *port,
372 struct ktermios *termios,
373 const struct ktermios *old)
375 struct uart_8250_port *up = up_to_u8250p(port);
376 struct omap8250_priv *priv = up->port.private_data;
377 unsigned char cval = 0;
380 cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
382 if (termios->c_cflag & CSTOPB)
383 cval |= UART_LCR_STOP;
384 if (termios->c_cflag & PARENB)
385 cval |= UART_LCR_PARITY;
386 if (!(termios->c_cflag & PARODD))
387 cval |= UART_LCR_EPAR;
388 if (termios->c_cflag & CMSPAR)
389 cval |= UART_LCR_SPAR;
392 * Ask the core to calculate the divisor for us.
394 baud = uart_get_baud_rate(port, termios, old,
395 port->uartclk / 16 / UART_DIV_MAX,
397 omap_8250_get_divisor(port, baud, priv);
400 * Ok, we're now changing the port state. Do it with
401 * interrupts disabled.
403 pm_runtime_get_sync(port->dev);
404 spin_lock_irq(&port->lock);
407 * Update the per-port timeout.
409 uart_update_timeout(port, termios->c_cflag, baud);
411 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
412 if (termios->c_iflag & INPCK)
413 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
414 if (termios->c_iflag & (IGNBRK | PARMRK))
415 up->port.read_status_mask |= UART_LSR_BI;
418 * Characters to ignore
420 up->port.ignore_status_mask = 0;
421 if (termios->c_iflag & IGNPAR)
422 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
423 if (termios->c_iflag & IGNBRK) {
424 up->port.ignore_status_mask |= UART_LSR_BI;
426 * If we're ignoring parity and break indicators,
427 * ignore overruns too (for real raw support).
429 if (termios->c_iflag & IGNPAR)
430 up->port.ignore_status_mask |= UART_LSR_OE;
434 * ignore all characters if CREAD is not set
436 if ((termios->c_cflag & CREAD) == 0)
437 up->port.ignore_status_mask |= UART_LSR_DR;
440 * Modem status interrupts
442 up->ier &= ~UART_IER_MSI;
443 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
444 up->ier |= UART_IER_MSI;
447 /* Up to here it was mostly serial8250_do_set_termios() */
450 * We enable TRIG_GRANU for RX and TX and additionally we set
451 * SCR_TX_EMPTY bit. The result is the following:
452 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
453 * - less than RX_TRIGGER number of bytes will also cause an interrupt
454 * once the UART decides that there no new bytes arriving.
455 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
456 * empty - the trigger level is ignored here.
458 * Once DMA is enabled:
459 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
460 * bytes in the TX FIFO. On each assert the DMA engine will move
461 * TX_TRIGGER bytes into the FIFO.
462 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
463 * the FIFO and move RX_TRIGGER bytes.
464 * This is because threshold and trigger values are the same.
466 up->fcr = UART_FCR_ENABLE_FIFO;
467 up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
468 up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
470 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
471 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
474 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
475 OMAP_UART_SCR_DMAMODE_CTL;
477 priv->xon = termios->c_cc[VSTART];
478 priv->xoff = termios->c_cc[VSTOP];
481 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
483 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
484 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
485 !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
486 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
487 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
488 priv->efr |= UART_EFR_CTS;
489 } else if (up->port.flags & UPF_SOFT_FLOW) {
491 * OMAP rx s/w flow control is borked; the transmitter remains
492 * stuck off even if rx flow control is subsequently disabled
497 * Enable XON/XOFF flow control on output.
498 * Transmit XON1, XOFF1
500 if (termios->c_iflag & IXOFF) {
501 up->port.status |= UPSTAT_AUTOXOFF;
502 priv->efr |= OMAP_UART_SW_TX;
505 omap8250_restore_regs(up);
507 spin_unlock_irq(&up->port.lock);
508 pm_runtime_mark_last_busy(port->dev);
509 pm_runtime_put_autosuspend(port->dev);
511 /* calculate wakeup latency constraint */
512 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
513 priv->latency = priv->calc_latency;
515 schedule_work(&priv->qos_work);
517 /* Don't rewrite B0 */
518 if (tty_termios_baud_rate(termios))
519 tty_termios_encode_baud_rate(termios, baud, baud);
522 /* same as 8250 except that we may have extra flow bits set in EFR */
523 static void omap_8250_pm(struct uart_port *port, unsigned int state,
524 unsigned int oldstate)
526 struct uart_8250_port *up = up_to_u8250p(port);
529 pm_runtime_get_sync(port->dev);
531 /* Synchronize UART_IER access against the console. */
532 spin_lock_irq(&port->lock);
534 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
535 efr = serial_in(up, UART_EFR);
536 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
537 serial_out(up, UART_LCR, 0);
539 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
540 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
541 serial_out(up, UART_EFR, efr);
542 serial_out(up, UART_LCR, 0);
544 spin_unlock_irq(&port->lock);
546 pm_runtime_mark_last_busy(port->dev);
547 pm_runtime_put_autosuspend(port->dev);
550 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
551 struct omap8250_priv *priv)
553 static const struct soc_device_attribute k3_soc_devices[] = {
554 { .family = "AM65X", },
555 { .family = "J721E", .revision = "SR1.0" },
559 u16 revision, major, minor;
561 mvr = uart_read(priv, UART_OMAP_MVER);
563 /* Check revision register scheme */
564 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
567 case 0: /* Legacy Scheme: OMAP2/3 */
568 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
569 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
570 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
571 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
574 /* New Scheme: OMAP4+ */
575 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
576 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
577 OMAP_UART_MVR_MAJ_SHIFT;
578 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
581 dev_warn(up->port.dev,
582 "Unknown revision, defaulting to highest\n");
583 /* highest possible revision */
587 /* normalize revision for the driver */
588 revision = UART_BUILD_REVISION(major, minor);
591 case OMAP_UART_REV_46:
592 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
594 case OMAP_UART_REV_52:
595 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
596 OMAP_UART_WER_HAS_TX_WAKEUP;
598 case OMAP_UART_REV_63:
599 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
600 OMAP_UART_WER_HAS_TX_WAKEUP;
607 * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
608 * don't have RHR_IT_DIS bit in IER2 register. So drop to flag
609 * to enable errata workaround.
611 if (soc_device_match(k3_soc_devices))
612 priv->habit &= ~UART_HAS_RHR_IT_DIS;
615 static void omap8250_uart_qos_work(struct work_struct *work)
617 struct omap8250_priv *priv;
619 priv = container_of(work, struct omap8250_priv, qos_work);
620 cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
623 #ifdef CONFIG_SERIAL_8250_DMA
624 static int omap_8250_dma_handle_irq(struct uart_port *port);
627 static irqreturn_t omap8250_irq(int irq, void *dev_id)
629 struct omap8250_priv *priv = dev_id;
630 struct uart_8250_port *up = serial8250_get_port(priv->line);
631 struct uart_port *port = &up->port;
632 unsigned int iir, lsr;
635 #ifdef CONFIG_SERIAL_8250_DMA
637 ret = omap_8250_dma_handle_irq(port);
638 return IRQ_RETVAL(ret);
642 serial8250_rpm_get(up);
643 lsr = serial_port_in(port, UART_LSR);
644 iir = serial_port_in(port, UART_IIR);
645 ret = serial8250_handle_irq(port, iir);
648 * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
649 * FIFO has been drained, in which case a dummy read of RX FIFO
650 * is required to clear RX TIMEOUT condition.
652 if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
653 (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
654 serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
655 serial_port_in(port, UART_RX);
658 /* Stop processing interrupts on input overrun */
659 if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
662 /* Synchronize UART_IER access against the console. */
663 spin_lock(&port->lock);
664 up->ier = port->serial_in(port, UART_IER);
665 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
666 port->ops->stop_rx(port);
668 /* Keep restarting the timer until
669 * the input overrun subsides.
671 cancel_delayed_work(&up->overrun_backoff);
673 spin_unlock(&port->lock);
675 delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
676 schedule_delayed_work(&up->overrun_backoff, delay);
679 serial8250_rpm_put(up);
681 return IRQ_RETVAL(ret);
684 static int omap_8250_startup(struct uart_port *port)
686 struct uart_8250_port *up = up_to_u8250p(port);
687 struct omap8250_priv *priv = port->private_data;
688 struct uart_8250_dma *dma = &priv->omap8250_dma;
692 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
697 pm_runtime_get_sync(port->dev);
699 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
701 serial_out(up, UART_LCR, UART_LCR_WLEN8);
703 up->lsr_saved_flags = 0;
704 up->msr_saved_flags = 0;
706 /* Disable DMA for console UART */
707 if (dma->fn && !uart_console(port)) {
708 up->dma = &priv->omap8250_dma;
709 ret = serial8250_request_dma(up);
711 dev_warn_ratelimited(port->dev,
712 "failed to request DMA\n");
719 /* Synchronize UART_IER access against the console. */
720 spin_lock_irq(&port->lock);
721 up->ier = UART_IER_RLSI | UART_IER_RDI;
722 serial_out(up, UART_IER, up->ier);
723 spin_unlock_irq(&port->lock);
726 up->capabilities |= UART_CAP_RPM;
729 /* Enable module level wake up */
730 priv->wer = OMAP_UART_WER_MOD_WKUP;
731 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
732 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
733 serial_out(up, UART_OMAP_WER, priv->wer);
735 if (up->dma && !(priv->habit & UART_HAS_EFR2)) {
736 spin_lock_irq(&port->lock);
738 spin_unlock_irq(&port->lock);
741 enable_irq(up->port.irq);
743 pm_runtime_mark_last_busy(port->dev);
744 pm_runtime_put_autosuspend(port->dev);
748 static void omap_8250_shutdown(struct uart_port *port)
750 struct uart_8250_port *up = up_to_u8250p(port);
751 struct omap8250_priv *priv = port->private_data;
753 flush_work(&priv->qos_work);
755 omap_8250_rx_dma_flush(up);
757 pm_runtime_get_sync(port->dev);
759 serial_out(up, UART_OMAP_WER, 0);
760 if (priv->habit & UART_HAS_EFR2)
761 serial_out(up, UART_OMAP_EFR2, 0x0);
763 /* Synchronize UART_IER access against the console. */
764 spin_lock_irq(&port->lock);
766 serial_out(up, UART_IER, 0);
767 spin_unlock_irq(&port->lock);
768 disable_irq_nosync(up->port.irq);
769 dev_pm_clear_wake_irq(port->dev);
771 serial8250_release_dma(up);
775 * Disable break condition and FIFOs
777 if (up->lcr & UART_LCR_SBC)
778 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
779 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
781 pm_runtime_mark_last_busy(port->dev);
782 pm_runtime_put_autosuspend(port->dev);
785 static void omap_8250_throttle(struct uart_port *port)
787 struct omap8250_priv *priv = port->private_data;
790 pm_runtime_get_sync(port->dev);
792 spin_lock_irqsave(&port->lock, flags);
793 port->ops->stop_rx(port);
794 priv->throttled = true;
795 spin_unlock_irqrestore(&port->lock, flags);
797 pm_runtime_mark_last_busy(port->dev);
798 pm_runtime_put_autosuspend(port->dev);
801 static void omap_8250_unthrottle(struct uart_port *port)
803 struct omap8250_priv *priv = port->private_data;
804 struct uart_8250_port *up = up_to_u8250p(port);
807 pm_runtime_get_sync(port->dev);
809 /* Synchronize UART_IER access against the console. */
810 spin_lock_irqsave(&port->lock, flags);
811 priv->throttled = false;
814 up->ier |= UART_IER_RLSI | UART_IER_RDI;
815 port->read_status_mask |= UART_LSR_DR;
816 serial_out(up, UART_IER, up->ier);
817 spin_unlock_irqrestore(&port->lock, flags);
819 pm_runtime_mark_last_busy(port->dev);
820 pm_runtime_put_autosuspend(port->dev);
823 static int omap8250_rs485_config(struct uart_port *port,
824 struct ktermios *termios,
825 struct serial_rs485 *rs485)
827 struct omap8250_priv *priv = port->private_data;
828 struct uart_8250_port *up = up_to_u8250p(port);
829 u32 fixed_delay_rts_before_send = 0;
830 u32 fixed_delay_rts_after_send = 0;
834 * There is a fixed delay of 3 bit clock cycles after the TX shift
835 * register is going empty to allow time for the stop bit to transition
836 * through the transceiver before direction is changed to receive.
838 * Additionally there appears to be a 1 bit clock delay between writing
839 * to the THR register and transmission of the start bit, per page 8783
840 * of the AM65 TRM: https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
843 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE)
844 baud = port->uartclk / (16 * priv->quot);
846 baud = port->uartclk / (13 * priv->quot);
848 fixed_delay_rts_after_send = 3 * MSEC_PER_SEC / baud;
849 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud;
853 * Fall back to RS485 software emulation if the UART is missing
854 * hardware support, if the device tree specifies an mctrl_gpio
855 * (indicates that RTS is unavailable due to a pinmux conflict)
856 * or if the requested delays exceed the fixed hardware delays.
858 if (!(priv->habit & UART_HAS_NATIVE_RS485) ||
859 mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) ||
860 rs485->delay_rts_after_send > fixed_delay_rts_after_send ||
861 rs485->delay_rts_before_send > fixed_delay_rts_before_send) {
862 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN;
863 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
865 port->rs485_config = serial8250_em485_config;
866 return serial8250_em485_config(port, termios, rs485);
869 rs485->delay_rts_after_send = fixed_delay_rts_after_send;
870 rs485->delay_rts_before_send = fixed_delay_rts_before_send;
872 if (rs485->flags & SER_RS485_ENABLED)
873 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN;
875 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN;
878 * Retain same polarity semantics as RS485 software emulation,
879 * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send.
881 if (rs485->flags & SER_RS485_RTS_ON_SEND)
882 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL;
884 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL;
886 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
891 #ifdef CONFIG_SERIAL_8250_DMA
892 static int omap_8250_rx_dma(struct uart_8250_port *p);
894 /* Must be called while priv->rx_dma_lock is held */
895 static void __dma_rx_do_complete(struct uart_8250_port *p)
897 struct uart_8250_dma *dma = p->dma;
898 struct tty_port *tty_port = &p->port.state->port;
899 struct omap8250_priv *priv = p->port.private_data;
900 struct dma_chan *rxchan = dma->rxchan;
902 struct dma_tx_state state;
907 if (!dma->rx_running)
910 cookie = dma->rx_cookie;
913 /* Re-enable RX FIFO interrupt now that transfer is complete */
914 if (priv->habit & UART_HAS_RHR_IT_DIS) {
915 reg = serial_in(p, UART_OMAP_IER2);
916 reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
917 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
920 dmaengine_tx_status(rxchan, cookie, &state);
922 count = dma->rx_size - state.residue + state.in_flight_bytes;
923 if (count < dma->rx_size) {
924 dmaengine_terminate_async(rxchan);
927 * Poll for teardown to complete which guarantees in
928 * flight data is drained.
930 if (state.in_flight_bytes) {
933 while (dmaengine_tx_status(rxchan, cookie, NULL) &&
937 if (poll_count == -1)
938 dev_err(p->port.dev, "teardown incomplete\n");
943 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
945 p->port.icount.rx += ret;
946 p->port.icount.buf_overrun += count - ret;
949 tty_flip_buffer_push(tty_port);
952 static void __dma_rx_complete(void *param)
954 struct uart_8250_port *p = param;
955 struct omap8250_priv *priv = p->port.private_data;
956 struct uart_8250_dma *dma = p->dma;
957 struct dma_tx_state state;
960 /* Synchronize UART_IER access against the console. */
961 spin_lock_irqsave(&p->port.lock, flags);
964 * If the tx status is not DMA_COMPLETE, then this is a delayed
965 * completion callback. A previous RX timeout flush would have
966 * already pushed the data, so exit.
968 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
970 spin_unlock_irqrestore(&p->port.lock, flags);
973 __dma_rx_do_complete(p);
974 if (!priv->throttled) {
975 p->ier |= UART_IER_RLSI | UART_IER_RDI;
976 serial_out(p, UART_IER, p->ier);
977 if (!(priv->habit & UART_HAS_EFR2))
981 spin_unlock_irqrestore(&p->port.lock, flags);
984 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
986 struct omap8250_priv *priv = p->port.private_data;
987 struct uart_8250_dma *dma = p->dma;
988 struct dma_tx_state state;
992 spin_lock_irqsave(&priv->rx_dma_lock, flags);
994 if (!dma->rx_running) {
995 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
999 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
1000 if (ret == DMA_IN_PROGRESS) {
1001 ret = dmaengine_pause(dma->rxchan);
1002 if (WARN_ON_ONCE(ret))
1003 priv->rx_dma_broken = true;
1005 __dma_rx_do_complete(p);
1006 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
1009 static int omap_8250_rx_dma(struct uart_8250_port *p)
1011 struct omap8250_priv *priv = p->port.private_data;
1012 struct uart_8250_dma *dma = p->dma;
1014 struct dma_async_tx_descriptor *desc;
1015 unsigned long flags;
1018 /* Port locked to synchronize UART_IER access against the console. */
1019 lockdep_assert_held_once(&p->port.lock);
1021 if (priv->rx_dma_broken)
1024 spin_lock_irqsave(&priv->rx_dma_lock, flags);
1026 if (dma->rx_running) {
1027 enum dma_status state;
1029 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
1030 if (state == DMA_COMPLETE) {
1032 * Disable RX interrupts to allow RX DMA completion
1035 p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1036 serial_out(p, UART_IER, p->ier);
1041 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
1042 dma->rx_size, DMA_DEV_TO_MEM,
1043 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1049 dma->rx_running = 1;
1050 desc->callback = __dma_rx_complete;
1051 desc->callback_param = p;
1053 dma->rx_cookie = dmaengine_submit(desc);
1056 * Disable RX FIFO interrupt while RX DMA is enabled, else
1057 * spurious interrupt may be raised when data is in the RX FIFO
1058 * but is yet to be drained by DMA.
1060 if (priv->habit & UART_HAS_RHR_IT_DIS) {
1061 reg = serial_in(p, UART_OMAP_IER2);
1062 reg |= UART_OMAP_IER2_RHR_IT_DIS;
1063 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
1066 dma_async_issue_pending(dma->rxchan);
1068 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
1072 static int omap_8250_tx_dma(struct uart_8250_port *p);
1074 static void omap_8250_dma_tx_complete(void *param)
1076 struct uart_8250_port *p = param;
1077 struct uart_8250_dma *dma = p->dma;
1078 struct circ_buf *xmit = &p->port.state->xmit;
1079 unsigned long flags;
1080 bool en_thri = false;
1081 struct omap8250_priv *priv = p->port.private_data;
1083 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
1084 UART_XMIT_SIZE, DMA_TO_DEVICE);
1086 spin_lock_irqsave(&p->port.lock, flags);
1088 dma->tx_running = 0;
1090 uart_xmit_advance(&p->port, dma->tx_size);
1092 if (priv->delayed_restore) {
1093 priv->delayed_restore = 0;
1094 omap8250_restore_regs(p);
1097 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1098 uart_write_wakeup(&p->port);
1100 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
1103 ret = omap_8250_tx_dma(p);
1106 } else if (p->capabilities & UART_CAP_RPM) {
1112 serial8250_set_THRI(p);
1115 spin_unlock_irqrestore(&p->port.lock, flags);
1118 static int omap_8250_tx_dma(struct uart_8250_port *p)
1120 struct uart_8250_dma *dma = p->dma;
1121 struct omap8250_priv *priv = p->port.private_data;
1122 struct circ_buf *xmit = &p->port.state->xmit;
1123 struct dma_async_tx_descriptor *desc;
1124 unsigned int skip_byte = 0;
1127 if (dma->tx_running)
1129 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
1132 * Even if no data, we need to return an error for the two cases
1133 * below so serial8250_tx_chars() is invoked and properly clears
1134 * THRI and/or runtime suspend.
1136 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
1140 serial8250_clear_THRI(p);
1144 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1145 if (priv->habit & OMAP_DMA_TX_KICK) {
1149 * We need to put the first byte into the FIFO in order to start
1150 * the DMA transfer. For transfers smaller than four bytes we
1151 * don't bother doing DMA at all. It seem not matter if there
1152 * are still bytes in the FIFO from the last transfer (in case
1153 * we got here directly from omap_8250_dma_tx_complete()). Bytes
1154 * leaving the FIFO seem not to trigger the DMA transfer. It is
1155 * really the byte that we put into the FIFO.
1156 * If the FIFO is already full then we most likely got here from
1157 * omap_8250_dma_tx_complete(). And this means the DMA engine
1158 * just completed its work. We don't have to wait the complete
1159 * 86us at 115200,8n1 but around 60us (not to mention lower
1160 * baudrates). So in that case we take the interrupt and try
1161 * again with an empty FIFO.
1163 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
1164 if (tx_lvl == p->tx_loadsz) {
1168 if (dma->tx_size < 4) {
1175 desc = dmaengine_prep_slave_single(dma->txchan,
1176 dma->tx_addr + xmit->tail + skip_byte,
1177 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1178 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1184 dma->tx_running = 1;
1186 desc->callback = omap_8250_dma_tx_complete;
1187 desc->callback_param = p;
1189 dma->tx_cookie = dmaengine_submit(desc);
1191 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1192 UART_XMIT_SIZE, DMA_TO_DEVICE);
1194 dma_async_issue_pending(dma->txchan);
1198 serial8250_clear_THRI(p);
1200 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1207 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1209 switch (iir & 0x3f) {
1211 case UART_IIR_RX_TIMEOUT:
1213 omap_8250_rx_dma_flush(up);
1216 return omap_8250_rx_dma(up);
1219 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status)
1221 if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1222 (iir & UART_IIR_RDI)) {
1223 if (handle_rx_dma(up, iir)) {
1224 status = serial8250_rx_chars(up, status);
1225 omap_8250_rx_dma(up);
1232 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
1235 /* Port locked to synchronize UART_IER access against the console. */
1236 lockdep_assert_held_once(&up->port.lock);
1239 * Queue a new transfer if FIFO has data.
1241 if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1242 (up->ier & UART_IER_RDI)) {
1243 omap_8250_rx_dma(up);
1244 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
1245 } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
1247 * Disable RX timeout, read IIR to clear
1248 * current timeout condition, clear EFR2 to
1249 * periodic timeouts, re-enable interrupts.
1251 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1252 serial_out(up, UART_IER, up->ier);
1253 omap_8250_rx_dma_flush(up);
1254 serial_in(up, UART_IIR);
1255 serial_out(up, UART_OMAP_EFR2, 0x0);
1256 up->ier |= UART_IER_RLSI | UART_IER_RDI;
1257 serial_out(up, UART_IER, up->ier);
1262 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1263 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1264 * use the default routine in the non-DMA case and this one for with DMA.
1266 static int omap_8250_dma_handle_irq(struct uart_port *port)
1268 struct uart_8250_port *up = up_to_u8250p(port);
1269 struct omap8250_priv *priv = up->port.private_data;
1273 serial8250_rpm_get(up);
1275 iir = serial_port_in(port, UART_IIR);
1276 if (iir & UART_IIR_NO_INT) {
1277 serial8250_rpm_put(up);
1281 spin_lock(&port->lock);
1283 status = serial_port_in(port, UART_LSR);
1285 if (priv->habit & UART_HAS_EFR2)
1286 am654_8250_handle_rx_dma(up, iir, status);
1288 status = omap_8250_handle_rx_dma(up, iir, status);
1290 serial8250_modem_status(up);
1291 if (status & UART_LSR_THRE && up->dma->tx_err) {
1292 if (uart_tx_stopped(&up->port) ||
1293 uart_circ_empty(&up->port.state->xmit)) {
1294 up->dma->tx_err = 0;
1295 serial8250_tx_chars(up);
1298 * try again due to an earlier failer which
1299 * might have been resolved by now.
1301 if (omap_8250_tx_dma(up))
1302 serial8250_tx_chars(up);
1306 uart_unlock_and_check_sysrq(port);
1308 serial8250_rpm_put(up);
1312 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1319 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1325 static int omap8250_no_handle_irq(struct uart_port *port)
1327 /* IRQ has not been requested but handling irq? */
1328 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1332 static struct omap8250_dma_params am654_dma = {
1335 .tx_trigger = TX_TRIGGER,
1338 static struct omap8250_dma_params am33xx_dma = {
1339 .rx_size = RX_TRIGGER,
1340 .rx_trigger = RX_TRIGGER,
1341 .tx_trigger = TX_TRIGGER,
1344 static struct omap8250_platdata am654_platdata = {
1345 .dma_params = &am654_dma,
1346 .habit = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS |
1347 UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485,
1350 static struct omap8250_platdata am33xx_platdata = {
1351 .dma_params = &am33xx_dma,
1352 .habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE,
1355 static struct omap8250_platdata omap4_platdata = {
1356 .dma_params = &am33xx_dma,
1357 .habit = UART_ERRATA_CLOCK_DISABLE,
1360 static const struct of_device_id omap8250_dt_ids[] = {
1361 { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1362 { .compatible = "ti,omap2-uart" },
1363 { .compatible = "ti,omap3-uart" },
1364 { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1365 { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1366 { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1367 { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1370 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1372 static int omap8250_probe(struct platform_device *pdev)
1374 struct device_node *np = pdev->dev.of_node;
1375 struct omap8250_priv *priv;
1376 const struct omap8250_platdata *pdata;
1377 struct uart_8250_port up;
1378 struct resource *regs;
1379 void __iomem *membase;
1382 irq = platform_get_irq(pdev, 0);
1386 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1388 dev_err(&pdev->dev, "missing registers\n");
1392 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1396 membase = devm_ioremap(&pdev->dev, regs->start,
1397 resource_size(regs));
1401 memset(&up, 0, sizeof(up));
1402 up.port.dev = &pdev->dev;
1403 up.port.mapbase = regs->start;
1404 up.port.membase = membase;
1407 * It claims to be 16C750 compatible however it is a little different.
1408 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1409 * have) is enabled via EFR instead of MCR. The type is set here 8250
1410 * just to get things going. UNKNOWN does not work for a few reasons and
1411 * we don't need our own type since we don't use 8250's set_termios()
1414 up.port.type = PORT_8250;
1415 up.port.iotype = UPIO_MEM;
1416 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1418 up.port.private_data = priv;
1420 up.port.regshift = OMAP_UART_REGSHIFT;
1421 up.port.fifosize = 64;
1423 up.capabilities = UART_CAP_FIFO;
1426 * Runtime PM is mostly transparent. However to do it right we need to a
1427 * TX empty interrupt before we can put the device to auto idle. So if
1428 * PM is not enabled we don't add that flag and can spare that one extra
1429 * interrupt in the TX path.
1431 up.capabilities |= UART_CAP_RPM;
1433 up.port.set_termios = omap_8250_set_termios;
1434 up.port.set_mctrl = omap8250_set_mctrl;
1435 up.port.pm = omap_8250_pm;
1436 up.port.startup = omap_8250_startup;
1437 up.port.shutdown = omap_8250_shutdown;
1438 up.port.throttle = omap_8250_throttle;
1439 up.port.unthrottle = omap_8250_unthrottle;
1440 up.port.rs485_config = omap8250_rs485_config;
1441 /* same rs485_supported for software emulation and native RS485 */
1442 up.port.rs485_supported = serial8250_em485_supported;
1443 up.rs485_start_tx = serial8250_em485_start_tx;
1444 up.rs485_stop_tx = serial8250_em485_stop_tx;
1445 up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1447 ret = of_alias_get_id(np, "serial");
1449 dev_err(&pdev->dev, "failed to get alias\n");
1454 if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1457 clk = devm_clk_get(&pdev->dev, NULL);
1459 if (PTR_ERR(clk) == -EPROBE_DEFER)
1460 return -EPROBE_DEFER;
1462 up.port.uartclk = clk_get_rate(clk);
1466 if (of_property_read_u32(np, "overrun-throttle-ms",
1467 &up.overrun_backoff_time_ms) != 0)
1468 up.overrun_backoff_time_ms = 0;
1470 pdata = of_device_get_match_data(&pdev->dev);
1472 priv->habit |= pdata->habit;
1474 if (!up.port.uartclk) {
1475 up.port.uartclk = DEFAULT_CLK_SPEED;
1476 dev_warn(&pdev->dev,
1477 "No clock speed specified: using default: %d\n",
1481 priv->membase = membase;
1482 priv->line = -ENODEV;
1483 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1484 priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1485 cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
1486 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1488 spin_lock_init(&priv->rx_dma_lock);
1490 platform_set_drvdata(pdev, priv);
1492 device_init_wakeup(&pdev->dev, true);
1493 pm_runtime_enable(&pdev->dev);
1494 pm_runtime_use_autosuspend(&pdev->dev);
1497 * Disable runtime PM until autosuspend delay unless specifically
1498 * enabled by the user via sysfs. This is the historic way to
1499 * prevent an unsafe default policy with lossy characters on wake-up.
1500 * For serdev devices this is not needed, the policy can be managed by
1501 * the serdev driver.
1503 if (!of_get_available_child_count(pdev->dev.of_node))
1504 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1506 pm_runtime_irq_safe(&pdev->dev);
1508 pm_runtime_get_sync(&pdev->dev);
1510 omap_serial_fill_features_erratas(&up, priv);
1511 up.port.handle_irq = omap8250_no_handle_irq;
1512 priv->rx_trigger = RX_TRIGGER;
1513 priv->tx_trigger = TX_TRIGGER;
1514 #ifdef CONFIG_SERIAL_8250_DMA
1516 * Oh DMA support. If there are no DMA properties in the DT then
1517 * we will fall back to a generic DMA channel which does not
1518 * really work here. To ensure that we do not get a generic DMA
1519 * channel assigned, we have the the_no_dma_filter_fn() here.
1520 * To avoid "failed to request DMA" messages we check for DMA
1523 ret = of_property_count_strings(np, "dma-names");
1525 struct omap8250_dma_params *dma_params = NULL;
1526 struct uart_8250_dma *dma = &priv->omap8250_dma;
1528 dma->fn = the_no_dma_filter_fn;
1529 dma->tx_dma = omap_8250_tx_dma;
1530 dma->rx_dma = omap_8250_rx_dma;
1532 dma_params = pdata->dma_params;
1535 dma->rx_size = dma_params->rx_size;
1536 dma->rxconf.src_maxburst = dma_params->rx_trigger;
1537 dma->txconf.dst_maxburst = dma_params->tx_trigger;
1538 priv->rx_trigger = dma_params->rx_trigger;
1539 priv->tx_trigger = dma_params->tx_trigger;
1541 dma->rx_size = RX_TRIGGER;
1542 dma->rxconf.src_maxburst = RX_TRIGGER;
1543 dma->txconf.dst_maxburst = TX_TRIGGER;
1548 irq_set_status_flags(irq, IRQ_NOAUTOEN);
1549 ret = devm_request_irq(&pdev->dev, irq, omap8250_irq, 0,
1550 dev_name(&pdev->dev), priv);
1554 priv->wakeirq = irq_of_parse_and_map(np, 1);
1556 ret = serial8250_register_8250_port(&up);
1558 dev_err(&pdev->dev, "unable to register 8250 port\n");
1562 pm_runtime_mark_last_busy(&pdev->dev);
1563 pm_runtime_put_autosuspend(&pdev->dev);
1566 pm_runtime_dont_use_autosuspend(&pdev->dev);
1567 pm_runtime_put_sync(&pdev->dev);
1568 flush_work(&priv->qos_work);
1569 pm_runtime_disable(&pdev->dev);
1570 cpu_latency_qos_remove_request(&priv->pm_qos_request);
1574 static int omap8250_remove(struct platform_device *pdev)
1576 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1577 struct uart_8250_port *up;
1580 err = pm_runtime_resume_and_get(&pdev->dev);
1584 up = serial8250_get_port(priv->line);
1585 omap_8250_shutdown(&up->port);
1586 serial8250_unregister_port(priv->line);
1587 priv->line = -ENODEV;
1588 pm_runtime_dont_use_autosuspend(&pdev->dev);
1589 pm_runtime_put_sync(&pdev->dev);
1590 flush_work(&priv->qos_work);
1591 pm_runtime_disable(&pdev->dev);
1592 cpu_latency_qos_remove_request(&priv->pm_qos_request);
1593 device_init_wakeup(&pdev->dev, false);
1597 static int omap8250_prepare(struct device *dev)
1599 struct omap8250_priv *priv = dev_get_drvdata(dev);
1603 priv->is_suspending = true;
1607 static void omap8250_complete(struct device *dev)
1609 struct omap8250_priv *priv = dev_get_drvdata(dev);
1613 priv->is_suspending = false;
1616 static int omap8250_suspend(struct device *dev)
1618 struct omap8250_priv *priv = dev_get_drvdata(dev);
1619 struct uart_8250_port *up = serial8250_get_port(priv->line);
1622 serial8250_suspend_port(priv->line);
1624 err = pm_runtime_resume_and_get(dev);
1627 if (!device_may_wakeup(dev))
1629 serial_out(up, UART_OMAP_WER, priv->wer);
1630 err = pm_runtime_force_suspend(dev);
1631 flush_work(&priv->qos_work);
1636 static int omap8250_resume(struct device *dev)
1638 struct omap8250_priv *priv = dev_get_drvdata(dev);
1641 err = pm_runtime_force_resume(dev);
1644 serial8250_resume_port(priv->line);
1645 /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */
1646 pm_runtime_mark_last_busy(dev);
1647 pm_runtime_put_autosuspend(dev);
1652 static int omap8250_lost_context(struct uart_8250_port *up)
1656 val = serial_in(up, UART_OMAP_SCR);
1658 * If we lose context, then SCR is set to its reset value of zero.
1659 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1660 * among other bits, to never set the register back to zero again.
1667 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val)
1669 writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT));
1672 /* TODO: in future, this should happen via API in drivers/reset/ */
1673 static int omap8250_soft_reset(struct device *dev)
1675 struct omap8250_priv *priv = dev_get_drvdata(dev);
1681 * At least on omap4, unused uarts may not idle after reset without
1682 * a basic scr dma configuration even with no dma in use. The
1683 * module clkctrl status bits will be 1 instead of 3 blocking idle
1684 * for the whole clockdomain. The softreset below will clear scr,
1685 * and we restore it on resume so this is safe to do on all SoCs
1686 * needing omap8250_soft_reset() quirk. Do it in two writes as
1687 * recommended in the comment for omap8250_update_scr().
1689 uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1690 uart_write(priv, UART_OMAP_SCR,
1691 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1693 sysc = uart_read(priv, UART_OMAP_SYSC);
1695 /* softreset the UART */
1696 sysc |= OMAP_UART_SYSC_SOFTRESET;
1697 uart_write(priv, UART_OMAP_SYSC, sysc);
1699 /* By experiments, 1us enough for reset complete on AM335x */
1702 syss = uart_read(priv, UART_OMAP_SYSS);
1703 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1706 dev_err(dev, "timed out waiting for reset done\n");
1713 static int omap8250_runtime_suspend(struct device *dev)
1715 struct omap8250_priv *priv = dev_get_drvdata(dev);
1716 struct uart_8250_port *up = NULL;
1718 if (priv->line >= 0)
1719 up = serial8250_get_port(priv->line);
1721 * When using 'no_console_suspend', the console UART must not be
1722 * suspended. Since driver suspend is managed by runtime suspend,
1723 * preventing runtime suspend (by returning error) will keep device
1724 * active during suspend.
1726 if (priv->is_suspending && !console_suspend_enabled) {
1727 if (up && uart_console(&up->port))
1731 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1734 ret = omap8250_soft_reset(dev);
1739 /* Restore to UART mode after reset (for wakeup) */
1740 omap8250_update_mdr1(up, priv);
1741 /* Restore wakeup enable register */
1742 serial_out(up, UART_OMAP_WER, priv->wer);
1746 if (up && up->dma && up->dma->rxchan)
1747 omap_8250_rx_dma_flush(up);
1749 priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1750 schedule_work(&priv->qos_work);
1755 static int omap8250_runtime_resume(struct device *dev)
1757 struct omap8250_priv *priv = dev_get_drvdata(dev);
1758 struct uart_8250_port *up = NULL;
1760 if (priv->line >= 0)
1761 up = serial8250_get_port(priv->line);
1763 if (up && omap8250_lost_context(up)) {
1764 spin_lock_irq(&up->port.lock);
1765 omap8250_restore_regs(up);
1766 spin_unlock_irq(&up->port.lock);
1769 if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2)) {
1770 spin_lock_irq(&up->port.lock);
1771 omap_8250_rx_dma(up);
1772 spin_unlock_irq(&up->port.lock);
1775 priv->latency = priv->calc_latency;
1776 schedule_work(&priv->qos_work);
1780 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1781 static int __init omap8250_console_fixup(void)
1787 if (strstr(boot_command_line, "console=ttyS"))
1788 /* user set a ttyS based name for the console */
1791 omap_str = strstr(boot_command_line, "console=ttyO");
1793 /* user did not set ttyO based console, so we don't care */
1797 if ('0' <= *omap_str && *omap_str <= '9')
1798 idx = *omap_str - '0';
1803 if (omap_str[0] == ',') {
1810 add_preferred_console("ttyS", idx, options);
1811 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1813 pr_err("This ensures that you still see kernel messages. Please\n");
1814 pr_err("update your kernel commandline.\n");
1817 console_initcall(omap8250_console_fixup);
1820 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1821 SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1822 RUNTIME_PM_OPS(omap8250_runtime_suspend,
1823 omap8250_runtime_resume, NULL)
1824 .prepare = pm_sleep_ptr(omap8250_prepare),
1825 .complete = pm_sleep_ptr(omap8250_complete),
1828 static struct platform_driver omap8250_platform_driver = {
1831 .pm = pm_ptr(&omap8250_dev_pm_ops),
1832 .of_match_table = omap8250_dt_ids,
1834 .probe = omap8250_probe,
1835 .remove = omap8250_remove,
1837 module_platform_driver(omap8250_platform_driver);
1839 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1840 MODULE_DESCRIPTION("OMAP 8250 Driver");
1841 MODULE_LICENSE("GPL v2");