drivers/tty/serial/8250/8250_omap.c

   1 /*
   2  * 8250-core based driver for the OMAP internal UART
   3  *
   4  * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
   5  *
   6  * Copyright (C) 2014 Sebastian Andrzej Siewior
   7  *
   8  */
   9
  10 #include <linux/device.h>
  11 #include <linux/io.h>
  12 #include <linux/module.h>
  13 #include <linux/serial_8250.h>
  14 #include <linux/serial_reg.h>
  15 #include <linux/tty_flip.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/slab.h>
  18 #include <linux/of.h>
  19 #include <linux/of_device.h>
  20 #include <linux/of_gpio.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/delay.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/console.h>
  25 #include <linux/pm_qos.h>
  26 #include <linux/pm_wakeirq.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include "8250.h"
  30
  31 #define DEFAULT_CLK_SPEED       48000000
  32
  33 #define UART_ERRATA_i202_MDR1_ACCESS    (1 << 0)
  34 #define OMAP_UART_WER_HAS_TX_WAKEUP     (1 << 1)
  35 #define OMAP_DMA_TX_KICK                (1 << 2)
  36 /*
  37  * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
  38  * The same errata is applicable to AM335x and DRA7x processors too.
  39  */
  40 #define UART_ERRATA_CLOCK_DISABLE       (1 << 3)
  41
  42 #define OMAP_UART_FCR_RX_TRIG           6
  43 #define OMAP_UART_FCR_TX_TRIG           4
  44
  45 /* SCR register bitmasks */
  46 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK       (1 << 7)
  47 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK       (1 << 6)
  48 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  49 #define OMAP_UART_SCR_DMAMODE_MASK              (3 << 1)
  50 #define OMAP_UART_SCR_DMAMODE_1                 (1 << 1)
  51 #define OMAP_UART_SCR_DMAMODE_CTL               (1 << 0)
  52
  53 /* MVR register bitmasks */
  54 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  55 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  56 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  57 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  58 #define OMAP_UART_MVR_MAJ_MASK          0x700
  59 #define OMAP_UART_MVR_MAJ_SHIFT         8
  60 #define OMAP_UART_MVR_MIN_MASK          0x3f
  61
  62 /* SYSC register bitmasks */
  63 #define OMAP_UART_SYSC_SOFTRESET        (1 << 1)
  64
  65 /* SYSS register bitmasks */
  66 #define OMAP_UART_SYSS_RESETDONE        (1 << 0)
  67
  68 #define UART_TI752_TLR_TX       0
  69 #define UART_TI752_TLR_RX       4
  70
  71 #define TRIGGER_TLR_MASK(x)     ((x & 0x3c) >> 2)
  72 #define TRIGGER_FCR_MASK(x)     (x & 3)
  73
  74 /* Enable XON/XOFF flow control on output */
  75 #define OMAP_UART_SW_TX         0x08
  76 /* Enable XON/XOFF flow control on input */
  77 #define OMAP_UART_SW_RX         0x02
  78
  79 #define OMAP_UART_WER_MOD_WKUP  0x7f
  80 #define OMAP_UART_TX_WAKEUP_EN  (1 << 7)
  81
  82 #define TX_TRIGGER      1
  83 #define RX_TRIGGER      48
  84
  85 #define OMAP_UART_TCR_RESTORE(x)        ((x / 4) << 4)
  86 #define OMAP_UART_TCR_HALT(x)           ((x / 4) << 0)
  87
  88 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  89
  90 #define OMAP_UART_REV_46 0x0406
  91 #define OMAP_UART_REV_52 0x0502
  92 #define OMAP_UART_REV_63 0x0603
  93
  94 struct omap8250_priv {
  95         int line;
  96         u8 habit;
  97         u8 mdr1;
  98         u8 efr;
  99         u8 scr;
 100         u8 wer;
 101         u8 xon;
 102         u8 xoff;
 103         u8 delayed_restore;
 104         u16 quot;
 105
 106         bool is_suspending;
 107         int wakeirq;
 108         int wakeups_enabled;
 109         u32 latency;
 110         u32 calc_latency;
 111         struct pm_qos_request pm_qos_request;
 112         struct work_struct qos_work;
 113         struct uart_8250_dma omap8250_dma;
 114         spinlock_t rx_dma_lock;
 115         bool rx_dma_broken;
 116 };
 117
 118 #ifdef CONFIG_SERIAL_8250_DMA
 119 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
 120 #else
 121 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
 122 #endif
 123
 124 static u32 uart_read(struct uart_8250_port *up, u32 reg)
 125 {
 126         return readl(up->port.membase + (reg << up->port.regshift));
 127 }
 128
 129 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
 130 {
 131         struct uart_8250_port *up = up_to_u8250p(port);
 132         struct omap8250_priv *priv = up->port.private_data;
 133         u8 lcr;
 134
 135         serial8250_do_set_mctrl(port, mctrl);
 136
 137         if (IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(up->gpios,
 138                                                 UART_GPIO_RTS))) {
 139                 /*
 140                  * Turn off autoRTS if RTS is lowered and restore autoRTS
 141                  * setting if RTS is raised
 142                  */
 143                 lcr = serial_in(up, UART_LCR);
 144                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 145                 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 146                         priv->efr |= UART_EFR_RTS;
 147                 else
 148                         priv->efr &= ~UART_EFR_RTS;
 149                 serial_out(up, UART_EFR, priv->efr);
 150                 serial_out(up, UART_LCR, lcr);
 151         }
 152 }
 153
 154 /*
 155  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
 156  * The access to uart register after MDR1 Access
 157  * causes UART to corrupt data.
 158  *
 159  * Need a delay =
 160  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 161  * give 10 times as much
 162  */
 163 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
 164                                      struct omap8250_priv *priv)
 165 {
 166         u8 timeout = 255;
 167         u8 old_mdr1;
 168
 169         old_mdr1 = serial_in(up, UART_OMAP_MDR1);
 170         if (old_mdr1 == priv->mdr1)
 171                 return;
 172
 173         serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 174         udelay(2);
 175         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
 176                         UART_FCR_CLEAR_RCVR);
 177         /*
 178          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
 179          * TX_FIFO_E bit is 1.
 180          */
 181         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
 182                                 (UART_LSR_THRE | UART_LSR_DR))) {
 183                 timeout--;
 184                 if (!timeout) {
 185                         /* Should *never* happen. we warn and carry on */
 186                         dev_crit(up->port.dev, "Errata i202: timedout %x\n",
 187                                  serial_in(up, UART_LSR));
 188                         break;
 189                 }
 190                 udelay(1);
 191         }
 192 }
 193
 194 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
 195                                   struct omap8250_priv *priv)
 196 {
 197         unsigned int uartclk = port->uartclk;
 198         unsigned int div_13, div_16;
 199         unsigned int abs_d13, abs_d16;
 200
 201         /*
 202          * Old custom speed handling.
 203          */
 204         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
 205                 priv->quot = port->custom_divisor & 0xffff;
 206                 /*
 207                  * I assume that nobody is using this. But hey, if somebody
 208                  * would like to specify the divisor _and_ the mode then the
 209                  * driver is ready and waiting for it.
 210                  */
 211                 if (port->custom_divisor & (1 << 16))
 212                         priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 213                 else
 214                         priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 215                 return;
 216         }
 217         div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
 218         div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
 219
 220         if (!div_13)
 221                 div_13 = 1;
 222         if (!div_16)
 223                 div_16 = 1;
 224
 225         abs_d13 = abs(baud - uartclk / 13 / div_13);
 226         abs_d16 = abs(baud - uartclk / 16 / div_16);
 227
 228         if (abs_d13 >= abs_d16) {
 229                 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 230                 priv->quot = div_16;
 231         } else {
 232                 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 233                 priv->quot = div_13;
 234         }
 235 }
 236
 237 static void omap8250_update_scr(struct uart_8250_port *up,
 238                                 struct omap8250_priv *priv)
 239 {
 240         u8 old_scr;
 241
 242         old_scr = serial_in(up, UART_OMAP_SCR);
 243         if (old_scr == priv->scr)
 244                 return;
 245
 246         /*
 247          * The manual recommends not to enable the DMA mode selector in the SCR
 248          * (instead of the FCR) register _and_ selecting the DMA mode as one
 249          * register write because this may lead to malfunction.
 250          */
 251         if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
 252                 serial_out(up, UART_OMAP_SCR,
 253                            priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
 254         serial_out(up, UART_OMAP_SCR, priv->scr);
 255 }
 256
 257 static void omap8250_update_mdr1(struct uart_8250_port *up,
 258                                  struct omap8250_priv *priv)
 259 {
 260         if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
 261                 omap_8250_mdr1_errataset(up, priv);
 262         else
 263                 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 264 }
 265
 266 static void omap8250_restore_regs(struct uart_8250_port *up)
 267 {
 268         struct omap8250_priv *priv = up->port.private_data;
 269         struct uart_8250_dma    *dma = up->dma;
 270
 271         if (dma && dma->tx_running) {
 272                 /*
 273                  * TCSANOW requests the change to occur immediately however if
 274                  * we have a TX-DMA operation in progress then it has been
 275                  * observed that it might stall and never complete. Therefore we
 276                  * delay DMA completes to prevent this hang from happen.
 277                  */
 278                 priv->delayed_restore = 1;
 279                 return;
 280         }
 281
 282         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 283         serial_out(up, UART_EFR, UART_EFR_ECB);
 284
 285         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 286         serial8250_out_MCR(up, UART_MCR_TCRTLR);
 287         serial_out(up, UART_FCR, up->fcr);
 288
 289         omap8250_update_scr(up, priv);
 290
 291         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 292
 293         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
 294                         OMAP_UART_TCR_HALT(52));
 295         serial_out(up, UART_TI752_TLR,
 296                    TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
 297                    TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
 298
 299         serial_out(up, UART_LCR, 0);
 300
 301         /* drop TCR + TLR access, we setup XON/XOFF later */
 302         serial8250_out_MCR(up, up->mcr);
 303         serial_out(up, UART_IER, up->ier);
 304
 305         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 306         serial_dl_write(up, priv->quot);
 307
 308         serial_out(up, UART_EFR, priv->efr);
 309
 310         /* Configure flow control */
 311         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 312         serial_out(up, UART_XON1, priv->xon);
 313         serial_out(up, UART_XOFF1, priv->xoff);
 314
 315         serial_out(up, UART_LCR, up->lcr);
 316
 317         omap8250_update_mdr1(up, priv);
 318
 319         up->port.ops->set_mctrl(&up->port, up->port.mctrl);
 320 }
 321
 322 /*
 323  * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
 324  * some differences in how we want to handle flow control.
 325  */
 326 static void omap_8250_set_termios(struct uart_port *port,
 327                                   struct ktermios *termios,
 328                                   struct ktermios *old)
 329 {
 330         struct uart_8250_port *up = up_to_u8250p(port);
 331         struct omap8250_priv *priv = up->port.private_data;
 332         unsigned char cval = 0;
 333         unsigned int baud;
 334
 335         switch (termios->c_cflag & CSIZE) {
 336         case CS5:
 337                 cval = UART_LCR_WLEN5;
 338                 break;
 339         case CS6:
 340                 cval = UART_LCR_WLEN6;
 341                 break;
 342         case CS7:
 343                 cval = UART_LCR_WLEN7;
 344                 break;
 345         default:
 346         case CS8:
 347                 cval = UART_LCR_WLEN8;
 348                 break;
 349         }
 350
 351         if (termios->c_cflag & CSTOPB)
 352                 cval |= UART_LCR_STOP;
 353         if (termios->c_cflag & PARENB)
 354                 cval |= UART_LCR_PARITY;
 355         if (!(termios->c_cflag & PARODD))
 356                 cval |= UART_LCR_EPAR;
 357         if (termios->c_cflag & CMSPAR)
 358                 cval |= UART_LCR_SPAR;
 359
 360         /*
 361          * Ask the core to calculate the divisor for us.
 362          */
 363         baud = uart_get_baud_rate(port, termios, old,
 364                                   port->uartclk / 16 / 0xffff,
 365                                   port->uartclk / 13);
 366         omap_8250_get_divisor(port, baud, priv);
 367
 368         /*
 369          * Ok, we're now changing the port state. Do it with
 370          * interrupts disabled.
 371          */
 372         pm_runtime_get_sync(port->dev);
 373         spin_lock_irq(&port->lock);
 374
 375         /*
 376          * Update the per-port timeout.
 377          */
 378         uart_update_timeout(port, termios->c_cflag, baud);
 379
 380         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 381         if (termios->c_iflag & INPCK)
 382                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 383         if (termios->c_iflag & (IGNBRK | PARMRK))
 384                 up->port.read_status_mask |= UART_LSR_BI;
 385
 386         /*
 387          * Characters to ignore
 388          */
 389         up->port.ignore_status_mask = 0;
 390         if (termios->c_iflag & IGNPAR)
 391                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 392         if (termios->c_iflag & IGNBRK) {
 393                 up->port.ignore_status_mask |= UART_LSR_BI;
 394                 /*
 395                  * If we're ignoring parity and break indicators,
 396                  * ignore overruns too (for real raw support).
 397                  */
 398                 if (termios->c_iflag & IGNPAR)
 399                         up->port.ignore_status_mask |= UART_LSR_OE;
 400         }
 401
 402         /*
 403          * ignore all characters if CREAD is not set
 404          */
 405         if ((termios->c_cflag & CREAD) == 0)
 406                 up->port.ignore_status_mask |= UART_LSR_DR;
 407
 408         /*
 409          * Modem status interrupts
 410          */
 411         up->ier &= ~UART_IER_MSI;
 412         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 413                 up->ier |= UART_IER_MSI;
 414
 415         up->lcr = cval;
 416         /* Up to here it was mostly serial8250_do_set_termios() */
 417
 418         /*
 419          * We enable TRIG_GRANU for RX and TX and additionaly we set
 420          * SCR_TX_EMPTY bit. The result is the following:
 421          * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
 422          * - less than RX_TRIGGER number of bytes will also cause an interrupt
 423          *   once the UART decides that there no new bytes arriving.
 424          * - Once THRE is enabled, the interrupt will be fired once the FIFO is
 425          *   empty - the trigger level is ignored here.
 426          *
 427          * Once DMA is enabled:
 428          * - UART will assert the TX DMA line once there is room for TX_TRIGGER
 429          *   bytes in the TX FIFO. On each assert the DMA engine will move
 430          *   TX_TRIGGER bytes into the FIFO.
 431          * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
 432          *   the FIFO and move RX_TRIGGER bytes.
 433          * This is because threshold and trigger values are the same.
 434          */
 435         up->fcr = UART_FCR_ENABLE_FIFO;
 436         up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
 437         up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
 438
 439         priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
 440                 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
 441
 442         if (up->dma)
 443                 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
 444                         OMAP_UART_SCR_DMAMODE_CTL;
 445
 446         priv->xon = termios->c_cc[VSTART];
 447         priv->xoff = termios->c_cc[VSTOP];
 448
 449         priv->efr = 0;
 450         up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
 451
 452         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW
 453                 && IS_ERR_OR_NULL(mctrl_gpio_to_gpiod(up->gpios,
 454                                                         UART_GPIO_RTS))) {
 455                 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
 456                 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 457                 priv->efr |= UART_EFR_CTS;
 458         } else  if (up->port.flags & UPF_SOFT_FLOW) {
 459                 /*
 460                  * OMAP rx s/w flow control is borked; the transmitter remains
 461                  * stuck off even if rx flow control is subsequently disabled
 462                  */
 463
 464                 /*
 465                  * IXOFF Flag:
 466                  * Enable XON/XOFF flow control on output.
 467                  * Transmit XON1, XOFF1
 468                  */
 469                 if (termios->c_iflag & IXOFF) {
 470                         up->port.status |= UPSTAT_AUTOXOFF;
 471                         priv->efr |= OMAP_UART_SW_TX;
 472                 }
 473         }
 474         omap8250_restore_regs(up);
 475
 476         spin_unlock_irq(&up->port.lock);
 477         pm_runtime_mark_last_busy(port->dev);
 478         pm_runtime_put_autosuspend(port->dev);
 479
 480         /* calculate wakeup latency constraint */
 481         priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
 482         priv->latency = priv->calc_latency;
 483
 484         schedule_work(&priv->qos_work);
 485
 486         /* Don't rewrite B0 */
 487         if (tty_termios_baud_rate(termios))
 488                 tty_termios_encode_baud_rate(termios, baud, baud);
 489 }
 490
 491 /* same as 8250 except that we may have extra flow bits set in EFR */
 492 static void omap_8250_pm(struct uart_port *port, unsigned int state,
 493                          unsigned int oldstate)
 494 {
 495         struct uart_8250_port *up = up_to_u8250p(port);
 496         u8 efr;
 497
 498         pm_runtime_get_sync(port->dev);
 499         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 500         efr = serial_in(up, UART_EFR);
 501         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 502         serial_out(up, UART_LCR, 0);
 503
 504         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 505         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 506         serial_out(up, UART_EFR, efr);
 507         serial_out(up, UART_LCR, 0);
 508
 509         pm_runtime_mark_last_busy(port->dev);
 510         pm_runtime_put_autosuspend(port->dev);
 511 }
 512
 513 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
 514                                               struct omap8250_priv *priv)
 515 {
 516         u32 mvr, scheme;
 517         u16 revision, major, minor;
 518
 519         mvr = uart_read(up, UART_OMAP_MVER);
 520
 521         /* Check revision register scheme */
 522         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
 523
 524         switch (scheme) {
 525         case 0: /* Legacy Scheme: OMAP2/3 */
 526                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
 527                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
 528                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
 529                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
 530                 break;
 531         case 1:
 532                 /* New Scheme: OMAP4+ */
 533                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
 534                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
 535                         OMAP_UART_MVR_MAJ_SHIFT;
 536                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
 537                 break;
 538         default:
 539                 dev_warn(up->port.dev,
 540                          "Unknown revision, defaulting to highest\n");
 541                 /* highest possible revision */
 542                 major = 0xff;
 543                 minor = 0xff;
 544         }
 545         /* normalize revision for the driver */
 546         revision = UART_BUILD_REVISION(major, minor);
 547
 548         switch (revision) {
 549         case OMAP_UART_REV_46:
 550                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
 551                 break;
 552         case OMAP_UART_REV_52:
 553                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 554                                 OMAP_UART_WER_HAS_TX_WAKEUP;
 555                 break;
 556         case OMAP_UART_REV_63:
 557                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 558                         OMAP_UART_WER_HAS_TX_WAKEUP;
 559                 break;
 560         default:
 561                 break;
 562         }
 563 }
 564
 565 static void omap8250_uart_qos_work(struct work_struct *work)
 566 {
 567         struct omap8250_priv *priv;
 568
 569         priv = container_of(work, struct omap8250_priv, qos_work);
 570         pm_qos_update_request(&priv->pm_qos_request, priv->latency);
 571 }
 572
 573 #ifdef CONFIG_SERIAL_8250_DMA
 574 static int omap_8250_dma_handle_irq(struct uart_port *port);
 575 #endif
 576
 577 static irqreturn_t omap8250_irq(int irq, void *dev_id)
 578 {
 579         struct uart_port *port = dev_id;
 580         struct uart_8250_port *up = up_to_u8250p(port);
 581         unsigned int iir;
 582         int ret;
 583
 584 #ifdef CONFIG_SERIAL_8250_DMA
 585         if (up->dma) {
 586                 ret = omap_8250_dma_handle_irq(port);
 587                 return IRQ_RETVAL(ret);
 588         }
 589 #endif
 590
 591         serial8250_rpm_get(up);
 592         iir = serial_port_in(port, UART_IIR);
 593         ret = serial8250_handle_irq(port, iir);
 594         serial8250_rpm_put(up);
 595
 596         return IRQ_RETVAL(ret);
 597 }
 598
 599 static int omap_8250_startup(struct uart_port *port)
 600 {
 601         struct uart_8250_port *up = up_to_u8250p(port);
 602         struct omap8250_priv *priv = port->private_data;
 603         int ret;
 604
 605         if (priv->wakeirq) {
 606                 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
 607                 if (ret)
 608                         return ret;
 609         }
 610
 611         pm_runtime_get_sync(port->dev);
 612
 613         up->mcr = 0;
 614         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 615
 616         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 617
 618         up->lsr_saved_flags = 0;
 619         up->msr_saved_flags = 0;
 620
 621         if (up->dma) {
 622                 ret = serial8250_request_dma(up);
 623                 if (ret) {
 624                         dev_warn_ratelimited(port->dev,
 625                                              "failed to request DMA\n");
 626                         up->dma = NULL;
 627                 }
 628         }
 629
 630         ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
 631                           dev_name(port->dev), port);
 632         if (ret < 0)
 633                 goto err;
 634
 635         up->ier = UART_IER_RLSI | UART_IER_RDI;
 636         serial_out(up, UART_IER, up->ier);
 637
 638 #ifdef CONFIG_PM
 639         up->capabilities |= UART_CAP_RPM;
 640 #endif
 641
 642         /* Enable module level wake up */
 643         priv->wer = OMAP_UART_WER_MOD_WKUP;
 644         if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
 645                 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
 646         serial_out(up, UART_OMAP_WER, priv->wer);
 647
 648         if (up->dma)
 649                 up->dma->rx_dma(up);
 650
 651         pm_runtime_mark_last_busy(port->dev);
 652         pm_runtime_put_autosuspend(port->dev);
 653         return 0;
 654 err:
 655         pm_runtime_mark_last_busy(port->dev);
 656         pm_runtime_put_autosuspend(port->dev);
 657         dev_pm_clear_wake_irq(port->dev);
 658         return ret;
 659 }
 660
 661 static void omap_8250_shutdown(struct uart_port *port)
 662 {
 663         struct uart_8250_port *up = up_to_u8250p(port);
 664         struct omap8250_priv *priv = port->private_data;
 665
 666         flush_work(&priv->qos_work);
 667         if (up->dma)
 668                 omap_8250_rx_dma_flush(up);
 669
 670         pm_runtime_get_sync(port->dev);
 671
 672         serial_out(up, UART_OMAP_WER, 0);
 673
 674         up->ier = 0;
 675         serial_out(up, UART_IER, 0);
 676
 677         if (up->dma)
 678                 serial8250_release_dma(up);
 679
 680         /*
 681          * Disable break condition and FIFOs
 682          */
 683         if (up->lcr & UART_LCR_SBC)
 684                 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
 685         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 686
 687         pm_runtime_mark_last_busy(port->dev);
 688         pm_runtime_put_autosuspend(port->dev);
 689         free_irq(port->irq, port);
 690         dev_pm_clear_wake_irq(port->dev);
 691 }
 692
 693 static void omap_8250_throttle(struct uart_port *port)
 694 {
 695         struct uart_8250_port *up = up_to_u8250p(port);
 696         unsigned long flags;
 697
 698         pm_runtime_get_sync(port->dev);
 699
 700         spin_lock_irqsave(&port->lock, flags);
 701         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 702         serial_out(up, UART_IER, up->ier);
 703         spin_unlock_irqrestore(&port->lock, flags);
 704
 705         pm_runtime_mark_last_busy(port->dev);
 706         pm_runtime_put_autosuspend(port->dev);
 707 }
 708
 709 static int omap_8250_rs485_config(struct uart_port *port,
 710                                   struct serial_rs485 *rs485)
 711 {
 712         struct uart_8250_port *up = up_to_u8250p(port);
 713
 714         /* Clamp the delays to [0, 100ms] */
 715         rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
 716         rs485->delay_rts_after_send  = min(rs485->delay_rts_after_send, 100U);
 717
 718         port->rs485 = *rs485;
 719
 720         /*
 721          * Both serial8250_em485_init and serial8250_em485_destroy
 722          * are idempotent
 723          */
 724         if (rs485->flags & SER_RS485_ENABLED) {
 725                 int ret = serial8250_em485_init(up);
 726
 727                 if (ret) {
 728                         rs485->flags &= ~SER_RS485_ENABLED;
 729                         port->rs485.flags &= ~SER_RS485_ENABLED;
 730                 }
 731                 return ret;
 732         }
 733
 734         serial8250_em485_destroy(up);
 735
 736         return 0;
 737 }
 738
 739 static void omap_8250_unthrottle(struct uart_port *port)
 740 {
 741         struct uart_8250_port *up = up_to_u8250p(port);
 742         unsigned long flags;
 743
 744         pm_runtime_get_sync(port->dev);
 745
 746         spin_lock_irqsave(&port->lock, flags);
 747         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 748         serial_out(up, UART_IER, up->ier);
 749         spin_unlock_irqrestore(&port->lock, flags);
 750
 751         pm_runtime_mark_last_busy(port->dev);
 752         pm_runtime_put_autosuspend(port->dev);
 753 }
 754
 755 #ifdef CONFIG_SERIAL_8250_DMA
 756 static int omap_8250_rx_dma(struct uart_8250_port *p);
 757
 758 static void __dma_rx_do_complete(struct uart_8250_port *p)
 759 {
 760         struct omap8250_priv    *priv = p->port.private_data;
 761         struct uart_8250_dma    *dma = p->dma;
 762         struct tty_port         *tty_port = &p->port.state->port;
 763         struct dma_tx_state     state;
 764         int                     count;
 765         unsigned long           flags;
 766         int                     ret;
 767
 768         spin_lock_irqsave(&priv->rx_dma_lock, flags);
 769
 770         if (!dma->rx_running)
 771                 goto unlock;
 772
 773         dma->rx_running = 0;
 774         dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
 775
 776         count = dma->rx_size - state.residue;
 777
 778         ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
 779
 780         p->port.icount.rx += ret;
 781         p->port.icount.buf_overrun += count - ret;
 782 unlock:
 783         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 784
 785         tty_flip_buffer_push(tty_port);
 786 }
 787
 788 static void __dma_rx_complete(void *param)
 789 {
 790         __dma_rx_do_complete(param);
 791         omap_8250_rx_dma(param);
 792 }
 793
 794 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
 795 {
 796         struct omap8250_priv    *priv = p->port.private_data;
 797         struct uart_8250_dma    *dma = p->dma;
 798         unsigned long           flags;
 799         int ret;
 800
 801         spin_lock_irqsave(&priv->rx_dma_lock, flags);
 802
 803         if (!dma->rx_running) {
 804                 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 805                 return;
 806         }
 807
 808         ret = dmaengine_pause(dma->rxchan);
 809         if (WARN_ON_ONCE(ret))
 810                 priv->rx_dma_broken = true;
 811
 812         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 813
 814         __dma_rx_do_complete(p);
 815         dmaengine_terminate_all(dma->rxchan);
 816 }
 817
 818 static int omap_8250_rx_dma(struct uart_8250_port *p)
 819 {
 820         struct omap8250_priv            *priv = p->port.private_data;
 821         struct uart_8250_dma            *dma = p->dma;
 822         int                             err = 0;
 823         struct dma_async_tx_descriptor  *desc;
 824         unsigned long                   flags;
 825
 826         if (priv->rx_dma_broken)
 827                 return -EINVAL;
 828
 829         spin_lock_irqsave(&priv->rx_dma_lock, flags);
 830
 831         if (dma->rx_running)
 832                 goto out;
 833
 834         desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
 835                                            dma->rx_size, DMA_DEV_TO_MEM,
 836                                            DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 837         if (!desc) {
 838                 err = -EBUSY;
 839                 goto out;
 840         }
 841
 842         dma->rx_running = 1;
 843         desc->callback = __dma_rx_complete;
 844         desc->callback_param = p;
 845
 846         dma->rx_cookie = dmaengine_submit(desc);
 847
 848         dma_async_issue_pending(dma->rxchan);
 849 out:
 850         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 851         return err;
 852 }
 853
 854 static int omap_8250_tx_dma(struct uart_8250_port *p);
 855
 856 static void omap_8250_dma_tx_complete(void *param)
 857 {
 858         struct uart_8250_port   *p = param;
 859         struct uart_8250_dma    *dma = p->dma;
 860         struct circ_buf         *xmit = &p->port.state->xmit;
 861         unsigned long           flags;
 862         bool                    en_thri = false;
 863         struct omap8250_priv    *priv = p->port.private_data;
 864
 865         dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
 866                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 867
 868         spin_lock_irqsave(&p->port.lock, flags);
 869
 870         dma->tx_running = 0;
 871
 872         xmit->tail += dma->tx_size;
 873         xmit->tail &= UART_XMIT_SIZE - 1;
 874         p->port.icount.tx += dma->tx_size;
 875
 876         if (priv->delayed_restore) {
 877                 priv->delayed_restore = 0;
 878                 omap8250_restore_regs(p);
 879         }
 880
 881         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 882                 uart_write_wakeup(&p->port);
 883
 884         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
 885                 int ret;
 886
 887                 ret = omap_8250_tx_dma(p);
 888                 if (ret)
 889                         en_thri = true;
 890
 891         } else if (p->capabilities & UART_CAP_RPM) {
 892                 en_thri = true;
 893         }
 894
 895         if (en_thri) {
 896                 dma->tx_err = 1;
 897                 p->ier |= UART_IER_THRI;
 898                 serial_port_out(&p->port, UART_IER, p->ier);
 899         }
 900
 901         spin_unlock_irqrestore(&p->port.lock, flags);
 902 }
 903
 904 static int omap_8250_tx_dma(struct uart_8250_port *p)
 905 {
 906         struct uart_8250_dma            *dma = p->dma;
 907         struct omap8250_priv            *priv = p->port.private_data;
 908         struct circ_buf                 *xmit = &p->port.state->xmit;
 909         struct dma_async_tx_descriptor  *desc;
 910         unsigned int    skip_byte = 0;
 911         int ret;
 912
 913         if (dma->tx_running)
 914                 return 0;
 915         if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
 916
 917                 /*
 918                  * Even if no data, we need to return an error for the two cases
 919                  * below so serial8250_tx_chars() is invoked and properly clears
 920                  * THRI and/or runtime suspend.
 921                  */
 922                 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
 923                         ret = -EBUSY;
 924                         goto err;
 925                 }
 926                 if (p->ier & UART_IER_THRI) {
 927                         p->ier &= ~UART_IER_THRI;
 928                         serial_out(p, UART_IER, p->ier);
 929                 }
 930                 return 0;
 931         }
 932
 933         dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 934         if (priv->habit & OMAP_DMA_TX_KICK) {
 935                 u8 tx_lvl;
 936
 937                 /*
 938                  * We need to put the first byte into the FIFO in order to start
 939                  * the DMA transfer. For transfers smaller than four bytes we
 940                  * don't bother doing DMA at all. It seem not matter if there
 941                  * are still bytes in the FIFO from the last transfer (in case
 942                  * we got here directly from omap_8250_dma_tx_complete()). Bytes
 943                  * leaving the FIFO seem not to trigger the DMA transfer. It is
 944                  * really the byte that we put into the FIFO.
 945                  * If the FIFO is already full then we most likely got here from
 946                  * omap_8250_dma_tx_complete(). And this means the DMA engine
 947                  * just completed its work. We don't have to wait the complete
 948                  * 86us at 115200,8n1 but around 60us (not to mention lower
 949                  * baudrates). So in that case we take the interrupt and try
 950                  * again with an empty FIFO.
 951                  */
 952                 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
 953                 if (tx_lvl == p->tx_loadsz) {
 954                         ret = -EBUSY;
 955                         goto err;
 956                 }
 957                 if (dma->tx_size < 4) {
 958                         ret = -EINVAL;
 959                         goto err;
 960                 }
 961                 skip_byte = 1;
 962         }
 963
 964         desc = dmaengine_prep_slave_single(dma->txchan,
 965                         dma->tx_addr + xmit->tail + skip_byte,
 966                         dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
 967                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 968         if (!desc) {
 969                 ret = -EBUSY;
 970                 goto err;
 971         }
 972
 973         dma->tx_running = 1;
 974
 975         desc->callback = omap_8250_dma_tx_complete;
 976         desc->callback_param = p;
 977
 978         dma->tx_cookie = dmaengine_submit(desc);
 979
 980         dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
 981                                    UART_XMIT_SIZE, DMA_TO_DEVICE);
 982
 983         dma_async_issue_pending(dma->txchan);
 984         if (dma->tx_err)
 985                 dma->tx_err = 0;
 986
 987         if (p->ier & UART_IER_THRI) {
 988                 p->ier &= ~UART_IER_THRI;
 989                 serial_out(p, UART_IER, p->ier);
 990         }
 991         if (skip_byte)
 992                 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
 993         return 0;
 994 err:
 995         dma->tx_err = 1;
 996         return ret;
 997 }
 998
 999 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1000 {
1001         switch (iir & 0x3f) {
1002         case UART_IIR_RLSI:
1003         case UART_IIR_RX_TIMEOUT:
1004         case UART_IIR_RDI:
1005                 omap_8250_rx_dma_flush(up);
1006                 return true;
1007         }
1008         return omap_8250_rx_dma(up);
1009 }
1010
1011 /*
1012  * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1013  * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1014  * use the default routine in the non-DMA case and this one for with DMA.
1015  */
1016 static int omap_8250_dma_handle_irq(struct uart_port *port)
1017 {
1018         struct uart_8250_port *up = up_to_u8250p(port);
1019         unsigned char status;
1020         unsigned long flags;
1021         u8 iir;
1022
1023         serial8250_rpm_get(up);
1024
1025         iir = serial_port_in(port, UART_IIR);
1026         if (iir & UART_IIR_NO_INT) {
1027                 serial8250_rpm_put(up);
1028                 return 0;
1029         }
1030
1031         spin_lock_irqsave(&port->lock, flags);
1032
1033         status = serial_port_in(port, UART_LSR);
1034
1035         if (status & (UART_LSR_DR | UART_LSR_BI)) {
1036                 if (handle_rx_dma(up, iir)) {
1037                         status = serial8250_rx_chars(up, status);
1038                         omap_8250_rx_dma(up);
1039                 }
1040         }
1041         serial8250_modem_status(up);
1042         if (status & UART_LSR_THRE && up->dma->tx_err) {
1043                 if (uart_tx_stopped(&up->port) ||
1044                     uart_circ_empty(&up->port.state->xmit)) {
1045                         up->dma->tx_err = 0;
1046                         serial8250_tx_chars(up);
1047                 } else  {
1048                         /*
1049                          * try again due to an earlier failer which
1050                          * might have been resolved by now.
1051                          */
1052                         if (omap_8250_tx_dma(up))
1053                                 serial8250_tx_chars(up);
1054                 }
1055         }
1056
1057         spin_unlock_irqrestore(&port->lock, flags);
1058         serial8250_rpm_put(up);
1059         return 1;
1060 }
1061
1062 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1063 {
1064         return false;
1065 }
1066
1067 #else
1068
1069 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1070 {
1071         return -EINVAL;
1072 }
1073 #endif
1074
1075 static int omap8250_no_handle_irq(struct uart_port *port)
1076 {
1077         /* IRQ has not been requested but handling irq? */
1078         WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1079         return 0;
1080 }
1081
1082 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1083 static const u8 am4372_habit = UART_ERRATA_CLOCK_DISABLE;
1084
1085 static const struct of_device_id omap8250_dt_ids[] = {
1086         { .compatible = "ti,omap2-uart" },
1087         { .compatible = "ti,omap3-uart" },
1088         { .compatible = "ti,omap4-uart" },
1089         { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1090         { .compatible = "ti,am4372-uart", .data = &am4372_habit, },
1091         { .compatible = "ti,dra742-uart", .data = &am4372_habit, },
1092         {},
1093 };
1094 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1095
1096 static int omap8250_probe(struct platform_device *pdev)
1097 {
1098         struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1099         struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1100         struct omap8250_priv *priv;
1101         struct uart_8250_port up;
1102         int ret;
1103         void __iomem *membase;
1104
1105         if (!regs || !irq) {
1106                 dev_err(&pdev->dev, "missing registers or irq\n");
1107                 return -EINVAL;
1108         }
1109
1110         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1111         if (!priv)
1112                 return -ENOMEM;
1113
1114         membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1115                                        resource_size(regs));
1116         if (!membase)
1117                 return -ENODEV;
1118
1119         memset(&up, 0, sizeof(up));
1120         up.port.dev = &pdev->dev;
1121         up.port.mapbase = regs->start;
1122         up.port.membase = membase;
1123         up.port.irq = irq->start;
1124         /*
1125          * It claims to be 16C750 compatible however it is a little different.
1126          * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1127          * have) is enabled via EFR instead of MCR. The type is set here 8250
1128          * just to get things going. UNKNOWN does not work for a few reasons and
1129          * we don't need our own type since we don't use 8250's set_termios()
1130          * or pm callback.
1131          */
1132         up.port.type = PORT_8250;
1133         up.port.iotype = UPIO_MEM;
1134         up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1135                 UPF_HARD_FLOW;
1136         up.port.private_data = priv;
1137
1138         up.port.regshift = 2;
1139         up.port.fifosize = 64;
1140         up.tx_loadsz = 64;
1141         up.capabilities = UART_CAP_FIFO;
1142 #ifdef CONFIG_PM
1143         /*
1144          * Runtime PM is mostly transparent. However to do it right we need to a
1145          * TX empty interrupt before we can put the device to auto idle. So if
1146          * PM is not enabled we don't add that flag and can spare that one extra
1147          * interrupt in the TX path.
1148          */
1149         up.capabilities |= UART_CAP_RPM;
1150 #endif
1151         up.port.set_termios = omap_8250_set_termios;
1152         up.port.set_mctrl = omap8250_set_mctrl;
1153         up.port.pm = omap_8250_pm;
1154         up.port.startup = omap_8250_startup;
1155         up.port.shutdown = omap_8250_shutdown;
1156         up.port.throttle = omap_8250_throttle;
1157         up.port.unthrottle = omap_8250_unthrottle;
1158         up.port.rs485_config = omap_8250_rs485_config;
1159
1160         if (pdev->dev.of_node) {
1161                 const struct of_device_id *id;
1162
1163                 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1164
1165                 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1166                                      &up.port.uartclk);
1167                 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1168
1169                 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1170                 if (id && id->data)
1171                         priv->habit |= *(u8 *)id->data;
1172         } else {
1173                 ret = pdev->id;
1174         }
1175         if (ret < 0) {
1176                 dev_err(&pdev->dev, "failed to get alias/pdev id\n");
1177                 return ret;
1178         }
1179         up.port.line = ret;
1180
1181         if (!up.port.uartclk) {
1182                 up.port.uartclk = DEFAULT_CLK_SPEED;
1183                 dev_warn(&pdev->dev,
1184                          "No clock speed specified: using default: %d\n",
1185                          DEFAULT_CLK_SPEED);
1186         }
1187
1188         priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1189         priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1190         pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1191                            priv->latency);
1192         INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1193
1194         spin_lock_init(&priv->rx_dma_lock);
1195
1196         device_init_wakeup(&pdev->dev, true);
1197         pm_runtime_use_autosuspend(&pdev->dev);
1198         pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1199
1200         pm_runtime_irq_safe(&pdev->dev);
1201         pm_runtime_enable(&pdev->dev);
1202
1203         pm_runtime_get_sync(&pdev->dev);
1204
1205         omap_serial_fill_features_erratas(&up, priv);
1206         up.port.handle_irq = omap8250_no_handle_irq;
1207 #ifdef CONFIG_SERIAL_8250_DMA
1208         if (pdev->dev.of_node) {
1209                 /*
1210                  * Oh DMA support. If there are no DMA properties in the DT then
1211                  * we will fall back to a generic DMA channel which does not
1212                  * really work here. To ensure that we do not get a generic DMA
1213                  * channel assigned, we have the the_no_dma_filter_fn() here.
1214                  * To avoid "failed to request DMA" messages we check for DMA
1215                  * properties in DT.
1216                  */
1217                 ret = of_property_count_strings(pdev->dev.of_node, "dma-names");
1218                 if (ret == 2) {
1219                         up.dma = &priv->omap8250_dma;
1220                         priv->omap8250_dma.fn = the_no_dma_filter_fn;
1221                         priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1222                         priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1223                         priv->omap8250_dma.rx_size = RX_TRIGGER;
1224                         priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1225                         priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1226
1227                         if (of_machine_is_compatible("ti,am33xx"))
1228                                 priv->habit |= OMAP_DMA_TX_KICK;
1229                         /*
1230                          * pause is currently not supported atleast on omap-sdma
1231                          * and edma on most earlier kernels.
1232                          */
1233                         priv->rx_dma_broken = true;
1234                 }
1235         }
1236 #endif
1237         ret = serial8250_register_8250_port(&up);
1238         if (ret < 0) {
1239                 dev_err(&pdev->dev, "unable to register 8250 port\n");
1240                 goto err;
1241         }
1242         priv->line = ret;
1243         platform_set_drvdata(pdev, priv);
1244         pm_runtime_mark_last_busy(&pdev->dev);
1245         pm_runtime_put_autosuspend(&pdev->dev);
1246         return 0;
1247 err:
1248         pm_runtime_put(&pdev->dev);
1249         pm_runtime_disable(&pdev->dev);
1250         return ret;
1251 }
1252
1253 static int omap8250_remove(struct platform_device *pdev)
1254 {
1255         struct omap8250_priv *priv = platform_get_drvdata(pdev);
1256
1257         pm_runtime_put_sync(&pdev->dev);
1258         pm_runtime_disable(&pdev->dev);
1259         serial8250_unregister_port(priv->line);
1260         pm_qos_remove_request(&priv->pm_qos_request);
1261         device_init_wakeup(&pdev->dev, false);
1262         return 0;
1263 }
1264
1265 #ifdef CONFIG_PM_SLEEP
1266 static int omap8250_prepare(struct device *dev)
1267 {
1268         struct omap8250_priv *priv = dev_get_drvdata(dev);
1269
1270         if (!priv)
1271                 return 0;
1272         priv->is_suspending = true;
1273         return 0;
1274 }
1275
1276 static void omap8250_complete(struct device *dev)
1277 {
1278         struct omap8250_priv *priv = dev_get_drvdata(dev);
1279
1280         if (!priv)
1281                 return;
1282         priv->is_suspending = false;
1283 }
1284
1285 static int omap8250_suspend(struct device *dev)
1286 {
1287         struct omap8250_priv *priv = dev_get_drvdata(dev);
1288
1289         serial8250_suspend_port(priv->line);
1290         flush_work(&priv->qos_work);
1291         return 0;
1292 }
1293
1294 static int omap8250_resume(struct device *dev)
1295 {
1296         struct omap8250_priv *priv = dev_get_drvdata(dev);
1297
1298         serial8250_resume_port(priv->line);
1299         return 0;
1300 }
1301 #else
1302 #define omap8250_prepare NULL
1303 #define omap8250_complete NULL
1304 #endif
1305
1306 #ifdef CONFIG_PM
1307 static int omap8250_lost_context(struct uart_8250_port *up)
1308 {
1309         u32 val;
1310
1311         val = serial_in(up, UART_OMAP_SCR);
1312         /*
1313          * If we lose context, then SCR is set to its reset value of zero.
1314          * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1315          * among other bits, to never set the register back to zero again.
1316          */
1317         if (!val)
1318                 return 1;
1319         return 0;
1320 }
1321
1322 /* TODO: in future, this should happen via API in drivers/reset/ */
1323 static int omap8250_soft_reset(struct device *dev)
1324 {
1325         struct omap8250_priv *priv = dev_get_drvdata(dev);
1326         struct uart_8250_port *up = serial8250_get_port(priv->line);
1327         int timeout = 100;
1328         int sysc;
1329         int syss;
1330
1331         sysc = serial_in(up, UART_OMAP_SYSC);
1332
1333         /* softreset the UART */
1334         sysc |= OMAP_UART_SYSC_SOFTRESET;
1335         serial_out(up, UART_OMAP_SYSC, sysc);
1336
1337         /* By experiments, 1us enough for reset complete on AM335x */
1338         do {
1339                 udelay(1);
1340                 syss = serial_in(up, UART_OMAP_SYSS);
1341         } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1342
1343         if (!timeout) {
1344                 dev_err(dev, "timed out waiting for reset done\n");
1345                 return -ETIMEDOUT;
1346         }
1347
1348         return 0;
1349 }
1350
1351 static int omap8250_runtime_suspend(struct device *dev)
1352 {
1353         struct omap8250_priv *priv = dev_get_drvdata(dev);
1354         struct uart_8250_port *up;
1355
1356         up = serial8250_get_port(priv->line);
1357         /*
1358          * When using 'no_console_suspend', the console UART must not be
1359          * suspended. Since driver suspend is managed by runtime suspend,
1360          * preventing runtime suspend (by returning error) will keep device
1361          * active during suspend.
1362          */
1363         if (priv->is_suspending && !console_suspend_enabled) {
1364                 if (uart_console(&up->port))
1365                         return -EBUSY;
1366         }
1367
1368         if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1369                 int ret;
1370
1371                 ret = omap8250_soft_reset(dev);
1372                 if (ret)
1373                         return ret;
1374
1375                 /* Restore to UART mode after reset (for wakeup) */
1376                 omap8250_update_mdr1(up, priv);
1377         }
1378
1379         if (up->dma && up->dma->rxchan)
1380                 omap_8250_rx_dma_flush(up);
1381
1382         priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1383         schedule_work(&priv->qos_work);
1384
1385         return 0;
1386 }
1387
1388 static int omap8250_runtime_resume(struct device *dev)
1389 {
1390         struct omap8250_priv *priv = dev_get_drvdata(dev);
1391         struct uart_8250_port *up;
1392
1393         /* In case runtime-pm tries this before we are setup */
1394         if (!priv)
1395                 return 0;
1396
1397         up = serial8250_get_port(priv->line);
1398
1399         if (omap8250_lost_context(up))
1400                 omap8250_restore_regs(up);
1401
1402         if (up->dma && up->dma->rxchan)
1403                 omap_8250_rx_dma(up);
1404
1405         priv->latency = priv->calc_latency;
1406         schedule_work(&priv->qos_work);
1407         return 0;
1408 }
1409 #endif
1410
1411 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1412 static int __init omap8250_console_fixup(void)
1413 {
1414         char *omap_str;
1415         char *options;
1416         u8 idx;
1417
1418         if (strstr(boot_command_line, "console=ttyS"))
1419                 /* user set a ttyS based name for the console */
1420                 return 0;
1421
1422         omap_str = strstr(boot_command_line, "console=ttyO");
1423         if (!omap_str)
1424                 /* user did not set ttyO based console, so we don't care */
1425                 return 0;
1426
1427         omap_str += 12;
1428         if ('0' <= *omap_str && *omap_str <= '9')
1429                 idx = *omap_str - '0';
1430         else
1431                 return 0;
1432
1433         omap_str++;
1434         if (omap_str[0] == ',') {
1435                 omap_str++;
1436                 options = omap_str;
1437         } else {
1438                 options = NULL;
1439         }
1440
1441         add_preferred_console("ttyS", idx, options);
1442         pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1443                idx, idx);
1444         pr_err("This ensures that you still see kernel messages. Please\n");
1445         pr_err("update your kernel commandline.\n");
1446         return 0;
1447 }
1448 console_initcall(omap8250_console_fixup);
1449 #endif
1450
1451 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1452         SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1453         SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1454                            omap8250_runtime_resume, NULL)
1455         .prepare        = omap8250_prepare,
1456         .complete       = omap8250_complete,
1457 };
1458
1459 static struct platform_driver omap8250_platform_driver = {
1460         .driver = {
1461                 .name           = "omap8250",
1462                 .pm             = &omap8250_dev_pm_ops,
1463                 .of_match_table = omap8250_dt_ids,
1464         },
1465         .probe                  = omap8250_probe,
1466         .remove                 = omap8250_remove,
1467 };
1468 module_platform_driver(omap8250_platform_driver);
1469
1470 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1471 MODULE_DESCRIPTION("OMAP 8250 Driver");
1472 MODULE_LICENSE("GPL v2");