drivers/tty/serial/8250/8250_omap.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * 8250-core based driver for the OMAP internal UART
   4  *
   5  * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Copyright (C) 2014 Sebastian Andrzej Siewior
   8  *
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/device.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/serial_8250.h>
  16 #include <linux/serial_reg.h>
  17 #include <linux/tty_flip.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/slab.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_gpio.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/delay.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/console.h>
  27 #include <linux/pm_qos.h>
  28 #include <linux/pm_wakeirq.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/sys_soc.h>
  31
  32 #include "8250.h"
  33
  34 #define DEFAULT_CLK_SPEED       48000000
  35 #define OMAP_UART_REGSHIFT      2
  36
  37 #define UART_ERRATA_i202_MDR1_ACCESS    (1 << 0)
  38 #define OMAP_UART_WER_HAS_TX_WAKEUP     (1 << 1)
  39 #define OMAP_DMA_TX_KICK                (1 << 2)
  40 /*
  41  * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
  42  * The same errata is applicable to AM335x and DRA7x processors too.
  43  */
  44 #define UART_ERRATA_CLOCK_DISABLE       (1 << 3)
  45 #define UART_HAS_EFR2                   BIT(4)
  46 #define UART_HAS_RHR_IT_DIS             BIT(5)
  47 #define UART_RX_TIMEOUT_QUIRK           BIT(6)
  48 #define UART_HAS_NATIVE_RS485           BIT(7)
  49
  50 #define OMAP_UART_FCR_RX_TRIG           6
  51 #define OMAP_UART_FCR_TX_TRIG           4
  52
  53 /* SCR register bitmasks */
  54 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK       (1 << 7)
  55 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK       (1 << 6)
  56 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  57 #define OMAP_UART_SCR_DMAMODE_MASK              (3 << 1)
  58 #define OMAP_UART_SCR_DMAMODE_1                 (1 << 1)
  59 #define OMAP_UART_SCR_DMAMODE_CTL               (1 << 0)
  60
  61 /* MVR register bitmasks */
  62 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  63 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  64 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  65 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  66 #define OMAP_UART_MVR_MAJ_MASK          0x700
  67 #define OMAP_UART_MVR_MAJ_SHIFT         8
  68 #define OMAP_UART_MVR_MIN_MASK          0x3f
  69
  70 /* SYSC register bitmasks */
  71 #define OMAP_UART_SYSC_SOFTRESET        (1 << 1)
  72
  73 /* SYSS register bitmasks */
  74 #define OMAP_UART_SYSS_RESETDONE        (1 << 0)
  75
  76 #define UART_TI752_TLR_TX       0
  77 #define UART_TI752_TLR_RX       4
  78
  79 #define TRIGGER_TLR_MASK(x)     ((x & 0x3c) >> 2)
  80 #define TRIGGER_FCR_MASK(x)     (x & 3)
  81
  82 /* Enable XON/XOFF flow control on output */
  83 #define OMAP_UART_SW_TX         0x08
  84 /* Enable XON/XOFF flow control on input */
  85 #define OMAP_UART_SW_RX         0x02
  86
  87 #define OMAP_UART_WER_MOD_WKUP  0x7f
  88 #define OMAP_UART_TX_WAKEUP_EN  (1 << 7)
  89
  90 #define TX_TRIGGER      1
  91 #define RX_TRIGGER      48
  92
  93 #define OMAP_UART_TCR_RESTORE(x)        ((x / 4) << 4)
  94 #define OMAP_UART_TCR_HALT(x)           ((x / 4) << 0)
  95
  96 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  97
  98 #define OMAP_UART_REV_46 0x0406
  99 #define OMAP_UART_REV_52 0x0502
 100 #define OMAP_UART_REV_63 0x0603
 101
 102 /* Interrupt Enable Register 2 */
 103 #define UART_OMAP_IER2                  0x1B
 104 #define UART_OMAP_IER2_RHR_IT_DIS       BIT(2)
 105
 106 /* Mode Definition Register 3 */
 107 #define UART_OMAP_MDR3                  0x20
 108 #define UART_OMAP_MDR3_DIR_POL          BIT(3)
 109 #define UART_OMAP_MDR3_DIR_EN           BIT(4)
 110
 111 /* Enhanced features register 2 */
 112 #define UART_OMAP_EFR2                  0x23
 113 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE   BIT(6)
 114
 115 /* RX FIFO occupancy indicator */
 116 #define UART_OMAP_RX_LVL                0x19
 117
 118 struct omap8250_priv {
 119         void __iomem *membase;
 120         int line;
 121         u8 habit;
 122         u8 mdr1;
 123         u8 mdr3;
 124         u8 efr;
 125         u8 scr;
 126         u8 wer;
 127         u8 xon;
 128         u8 xoff;
 129         u8 delayed_restore;
 130         u16 quot;
 131
 132         u8 tx_trigger;
 133         u8 rx_trigger;
 134         bool is_suspending;
 135         int wakeirq;
 136         int wakeups_enabled;
 137         u32 latency;
 138         u32 calc_latency;
 139         struct pm_qos_request pm_qos_request;
 140         struct work_struct qos_work;
 141         struct uart_8250_dma omap8250_dma;
 142         spinlock_t rx_dma_lock;
 143         bool rx_dma_broken;
 144         bool throttled;
 145 };
 146
 147 struct omap8250_dma_params {
 148         u32 rx_size;
 149         u8 rx_trigger;
 150         u8 tx_trigger;
 151 };
 152
 153 struct omap8250_platdata {
 154         struct omap8250_dma_params *dma_params;
 155         u8 habit;
 156 };
 157
 158 #ifdef CONFIG_SERIAL_8250_DMA
 159 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
 160 #else
 161 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
 162 #endif
 163
 164 static u32 uart_read(struct omap8250_priv *priv, u32 reg)
 165 {
 166         return readl(priv->membase + (reg << OMAP_UART_REGSHIFT));
 167 }
 168
 169 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val)
 170 {
 171         writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT));
 172 }
 173
 174 /*
 175  * Called on runtime PM resume path from omap8250_restore_regs(), and
 176  * omap8250_set_mctrl().
 177  */
 178 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
 179 {
 180         struct uart_8250_port *up = up_to_u8250p(port);
 181         struct omap8250_priv *priv = up->port.private_data;
 182         u8 lcr;
 183
 184         serial8250_do_set_mctrl(port, mctrl);
 185
 186         if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
 187                 /*
 188                  * Turn off autoRTS if RTS is lowered and restore autoRTS
 189                  * setting if RTS is raised
 190                  */
 191                 lcr = serial_in(up, UART_LCR);
 192                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 193                 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 194                         priv->efr |= UART_EFR_RTS;
 195                 else
 196                         priv->efr &= ~UART_EFR_RTS;
 197                 serial_out(up, UART_EFR, priv->efr);
 198                 serial_out(up, UART_LCR, lcr);
 199         }
 200 }
 201
 202 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
 203 {
 204         int err;
 205
 206         err = pm_runtime_resume_and_get(port->dev);
 207         if (err)
 208                 return;
 209
 210         __omap8250_set_mctrl(port, mctrl);
 211
 212         pm_runtime_mark_last_busy(port->dev);
 213         pm_runtime_put_autosuspend(port->dev);
 214 }
 215
 216 /*
 217  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
 218  * The access to uart register after MDR1 Access
 219  * causes UART to corrupt data.
 220  *
 221  * Need a delay =
 222  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 223  * give 10 times as much
 224  */
 225 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
 226                                      struct omap8250_priv *priv)
 227 {
 228         serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 229         udelay(2);
 230         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
 231                         UART_FCR_CLEAR_RCVR);
 232 }
 233
 234 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
 235                                   struct omap8250_priv *priv)
 236 {
 237         unsigned int uartclk = port->uartclk;
 238         unsigned int div_13, div_16;
 239         unsigned int abs_d13, abs_d16;
 240
 241         /*
 242          * Old custom speed handling.
 243          */
 244         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
 245                 priv->quot = port->custom_divisor & UART_DIV_MAX;
 246                 /*
 247                  * I assume that nobody is using this. But hey, if somebody
 248                  * would like to specify the divisor _and_ the mode then the
 249                  * driver is ready and waiting for it.
 250                  */
 251                 if (port->custom_divisor & (1 << 16))
 252                         priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 253                 else
 254                         priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 255                 return;
 256         }
 257         div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
 258         div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
 259
 260         if (!div_13)
 261                 div_13 = 1;
 262         if (!div_16)
 263                 div_16 = 1;
 264
 265         abs_d13 = abs(baud - uartclk / 13 / div_13);
 266         abs_d16 = abs(baud - uartclk / 16 / div_16);
 267
 268         if (abs_d13 >= abs_d16) {
 269                 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 270                 priv->quot = div_16;
 271         } else {
 272                 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 273                 priv->quot = div_13;
 274         }
 275 }
 276
 277 static void omap8250_update_scr(struct uart_8250_port *up,
 278                                 struct omap8250_priv *priv)
 279 {
 280         u8 old_scr;
 281
 282         old_scr = serial_in(up, UART_OMAP_SCR);
 283         if (old_scr == priv->scr)
 284                 return;
 285
 286         /*
 287          * The manual recommends not to enable the DMA mode selector in the SCR
 288          * (instead of the FCR) register _and_ selecting the DMA mode as one
 289          * register write because this may lead to malfunction.
 290          */
 291         if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
 292                 serial_out(up, UART_OMAP_SCR,
 293                            priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
 294         serial_out(up, UART_OMAP_SCR, priv->scr);
 295 }
 296
 297 static void omap8250_update_mdr1(struct uart_8250_port *up,
 298                                  struct omap8250_priv *priv)
 299 {
 300         if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
 301                 omap_8250_mdr1_errataset(up, priv);
 302         else
 303                 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 304 }
 305
 306 static void omap8250_restore_regs(struct uart_8250_port *up)
 307 {
 308         struct omap8250_priv *priv = up->port.private_data;
 309         struct uart_8250_dma    *dma = up->dma;
 310         u8 mcr = serial8250_in_MCR(up);
 311
 312         if (dma && dma->tx_running) {
 313                 /*
 314                  * TCSANOW requests the change to occur immediately however if
 315                  * we have a TX-DMA operation in progress then it has been
 316                  * observed that it might stall and never complete. Therefore we
 317                  * delay DMA completes to prevent this hang from happen.
 318                  */
 319                 priv->delayed_restore = 1;
 320                 return;
 321         }
 322
 323         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 324         serial_out(up, UART_EFR, UART_EFR_ECB);
 325
 326         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 327         serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR);
 328         serial_out(up, UART_FCR, up->fcr);
 329
 330         omap8250_update_scr(up, priv);
 331
 332         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 333
 334         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
 335                         OMAP_UART_TCR_HALT(52));
 336         serial_out(up, UART_TI752_TLR,
 337                    TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
 338                    TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
 339
 340         serial_out(up, UART_LCR, 0);
 341
 342         /* drop TCR + TLR access, we setup XON/XOFF later */
 343         serial8250_out_MCR(up, mcr);
 344
 345         serial_out(up, UART_IER, up->ier);
 346
 347         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 348         serial_dl_write(up, priv->quot);
 349
 350         serial_out(up, UART_EFR, priv->efr);
 351
 352         /* Configure flow control */
 353         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 354         serial_out(up, UART_XON1, priv->xon);
 355         serial_out(up, UART_XOFF1, priv->xoff);
 356
 357         serial_out(up, UART_LCR, up->lcr);
 358
 359         omap8250_update_mdr1(up, priv);
 360
 361         __omap8250_set_mctrl(&up->port, up->port.mctrl);
 362
 363         serial_out(up, UART_OMAP_MDR3, priv->mdr3);
 364
 365         if (up->port.rs485.flags & SER_RS485_ENABLED &&
 366             up->port.rs485_config == serial8250_em485_config)
 367                 serial8250_em485_stop_tx(up);
 368 }
 369
 370 /*
 371  * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
 372  * some differences in how we want to handle flow control.
 373  */
 374 static void omap_8250_set_termios(struct uart_port *port,
 375                                   struct ktermios *termios,
 376                                   const struct ktermios *old)
 377 {
 378         struct uart_8250_port *up = up_to_u8250p(port);
 379         struct omap8250_priv *priv = up->port.private_data;
 380         unsigned char cval = 0;
 381         unsigned int baud;
 382
 383         cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
 384
 385         if (termios->c_cflag & CSTOPB)
 386                 cval |= UART_LCR_STOP;
 387         if (termios->c_cflag & PARENB)
 388                 cval |= UART_LCR_PARITY;
 389         if (!(termios->c_cflag & PARODD))
 390                 cval |= UART_LCR_EPAR;
 391         if (termios->c_cflag & CMSPAR)
 392                 cval |= UART_LCR_SPAR;
 393
 394         /*
 395          * Ask the core to calculate the divisor for us.
 396          */
 397         baud = uart_get_baud_rate(port, termios, old,
 398                                   port->uartclk / 16 / UART_DIV_MAX,
 399                                   port->uartclk / 13);
 400         omap_8250_get_divisor(port, baud, priv);
 401
 402         /*
 403          * Ok, we're now changing the port state. Do it with
 404          * interrupts disabled.
 405          */
 406         pm_runtime_get_sync(port->dev);
 407         spin_lock_irq(&port->lock);
 408
 409         /*
 410          * Update the per-port timeout.
 411          */
 412         uart_update_timeout(port, termios->c_cflag, baud);
 413
 414         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 415         if (termios->c_iflag & INPCK)
 416                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 417         if (termios->c_iflag & (IGNBRK | PARMRK))
 418                 up->port.read_status_mask |= UART_LSR_BI;
 419
 420         /*
 421          * Characters to ignore
 422          */
 423         up->port.ignore_status_mask = 0;
 424         if (termios->c_iflag & IGNPAR)
 425                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 426         if (termios->c_iflag & IGNBRK) {
 427                 up->port.ignore_status_mask |= UART_LSR_BI;
 428                 /*
 429                  * If we're ignoring parity and break indicators,
 430                  * ignore overruns too (for real raw support).
 431                  */
 432                 if (termios->c_iflag & IGNPAR)
 433                         up->port.ignore_status_mask |= UART_LSR_OE;
 434         }
 435
 436         /*
 437          * ignore all characters if CREAD is not set
 438          */
 439         if ((termios->c_cflag & CREAD) == 0)
 440                 up->port.ignore_status_mask |= UART_LSR_DR;
 441
 442         /*
 443          * Modem status interrupts
 444          */
 445         up->ier &= ~UART_IER_MSI;
 446         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 447                 up->ier |= UART_IER_MSI;
 448
 449         up->lcr = cval;
 450         /* Up to here it was mostly serial8250_do_set_termios() */
 451
 452         /*
 453          * We enable TRIG_GRANU for RX and TX and additionally we set
 454          * SCR_TX_EMPTY bit. The result is the following:
 455          * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
 456          * - less than RX_TRIGGER number of bytes will also cause an interrupt
 457          *   once the UART decides that there no new bytes arriving.
 458          * - Once THRE is enabled, the interrupt will be fired once the FIFO is
 459          *   empty - the trigger level is ignored here.
 460          *
 461          * Once DMA is enabled:
 462          * - UART will assert the TX DMA line once there is room for TX_TRIGGER
 463          *   bytes in the TX FIFO. On each assert the DMA engine will move
 464          *   TX_TRIGGER bytes into the FIFO.
 465          * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
 466          *   the FIFO and move RX_TRIGGER bytes.
 467          * This is because threshold and trigger values are the same.
 468          */
 469         up->fcr = UART_FCR_ENABLE_FIFO;
 470         up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
 471         up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
 472
 473         priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
 474                 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
 475
 476         if (up->dma)
 477                 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
 478                         OMAP_UART_SCR_DMAMODE_CTL;
 479
 480         priv->xon = termios->c_cc[VSTART];
 481         priv->xoff = termios->c_cc[VSTOP];
 482
 483         priv->efr = 0;
 484         up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
 485
 486         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
 487             !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
 488             !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
 489                 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
 490                 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 491                 priv->efr |= UART_EFR_CTS;
 492         } else  if (up->port.flags & UPF_SOFT_FLOW) {
 493                 /*
 494                  * OMAP rx s/w flow control is borked; the transmitter remains
 495                  * stuck off even if rx flow control is subsequently disabled
 496                  */
 497
 498                 /*
 499                  * IXOFF Flag:
 500                  * Enable XON/XOFF flow control on output.
 501                  * Transmit XON1, XOFF1
 502                  */
 503                 if (termios->c_iflag & IXOFF) {
 504                         up->port.status |= UPSTAT_AUTOXOFF;
 505                         priv->efr |= OMAP_UART_SW_TX;
 506                 }
 507         }
 508         omap8250_restore_regs(up);
 509
 510         spin_unlock_irq(&up->port.lock);
 511         pm_runtime_mark_last_busy(port->dev);
 512         pm_runtime_put_autosuspend(port->dev);
 513
 514         /* calculate wakeup latency constraint */
 515         priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
 516         priv->latency = priv->calc_latency;
 517
 518         schedule_work(&priv->qos_work);
 519
 520         /* Don't rewrite B0 */
 521         if (tty_termios_baud_rate(termios))
 522                 tty_termios_encode_baud_rate(termios, baud, baud);
 523 }
 524
 525 /* same as 8250 except that we may have extra flow bits set in EFR */
 526 static void omap_8250_pm(struct uart_port *port, unsigned int state,
 527                          unsigned int oldstate)
 528 {
 529         struct uart_8250_port *up = up_to_u8250p(port);
 530         u8 efr;
 531
 532         pm_runtime_get_sync(port->dev);
 533         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 534         efr = serial_in(up, UART_EFR);
 535         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 536         serial_out(up, UART_LCR, 0);
 537
 538         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 539         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 540         serial_out(up, UART_EFR, efr);
 541         serial_out(up, UART_LCR, 0);
 542
 543         pm_runtime_mark_last_busy(port->dev);
 544         pm_runtime_put_autosuspend(port->dev);
 545 }
 546
 547 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
 548                                               struct omap8250_priv *priv)
 549 {
 550         static const struct soc_device_attribute k3_soc_devices[] = {
 551                 { .family = "AM65X",  },
 552                 { .family = "J721E", .revision = "SR1.0" },
 553                 { /* sentinel */ }
 554         };
 555         u32 mvr, scheme;
 556         u16 revision, major, minor;
 557
 558         mvr = uart_read(priv, UART_OMAP_MVER);
 559
 560         /* Check revision register scheme */
 561         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
 562
 563         switch (scheme) {
 564         case 0: /* Legacy Scheme: OMAP2/3 */
 565                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
 566                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
 567                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
 568                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
 569                 break;
 570         case 1:
 571                 /* New Scheme: OMAP4+ */
 572                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
 573                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
 574                         OMAP_UART_MVR_MAJ_SHIFT;
 575                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
 576                 break;
 577         default:
 578                 dev_warn(up->port.dev,
 579                          "Unknown revision, defaulting to highest\n");
 580                 /* highest possible revision */
 581                 major = 0xff;
 582                 minor = 0xff;
 583         }
 584         /* normalize revision for the driver */
 585         revision = UART_BUILD_REVISION(major, minor);
 586
 587         switch (revision) {
 588         case OMAP_UART_REV_46:
 589                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
 590                 break;
 591         case OMAP_UART_REV_52:
 592                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 593                                 OMAP_UART_WER_HAS_TX_WAKEUP;
 594                 break;
 595         case OMAP_UART_REV_63:
 596                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 597                         OMAP_UART_WER_HAS_TX_WAKEUP;
 598                 break;
 599         default:
 600                 break;
 601         }
 602
 603         /*
 604          * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
 605          * don't have RHR_IT_DIS bit in IER2 register. So drop to flag
 606          * to enable errata workaround.
 607          */
 608         if (soc_device_match(k3_soc_devices))
 609                 priv->habit &= ~UART_HAS_RHR_IT_DIS;
 610 }
 611
 612 static void omap8250_uart_qos_work(struct work_struct *work)
 613 {
 614         struct omap8250_priv *priv;
 615
 616         priv = container_of(work, struct omap8250_priv, qos_work);
 617         cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
 618 }
 619
 620 #ifdef CONFIG_SERIAL_8250_DMA
 621 static int omap_8250_dma_handle_irq(struct uart_port *port);
 622 #endif
 623
 624 static irqreturn_t omap8250_irq(int irq, void *dev_id)
 625 {
 626         struct omap8250_priv *priv = dev_id;
 627         struct uart_8250_port *up = serial8250_get_port(priv->line);
 628         struct uart_port *port = &up->port;
 629         unsigned int iir, lsr;
 630         int ret;
 631
 632 #ifdef CONFIG_SERIAL_8250_DMA
 633         if (up->dma) {
 634                 ret = omap_8250_dma_handle_irq(port);
 635                 return IRQ_RETVAL(ret);
 636         }
 637 #endif
 638
 639         serial8250_rpm_get(up);
 640         lsr = serial_port_in(port, UART_LSR);
 641         iir = serial_port_in(port, UART_IIR);
 642         ret = serial8250_handle_irq(port, iir);
 643
 644         /*
 645          * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
 646          * FIFO has been drained, in which case a dummy read of RX FIFO
 647          * is required to clear RX TIMEOUT condition.
 648          */
 649         if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
 650             (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
 651             serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
 652                 serial_port_in(port, UART_RX);
 653         }
 654
 655         /* Stop processing interrupts on input overrun */
 656         if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
 657                 unsigned long delay;
 658
 659                 up->ier = port->serial_in(port, UART_IER);
 660                 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
 661                         port->ops->stop_rx(port);
 662                 } else {
 663                         /* Keep restarting the timer until
 664                          * the input overrun subsides.
 665                          */
 666                         cancel_delayed_work(&up->overrun_backoff);
 667                 }
 668
 669                 delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
 670                 schedule_delayed_work(&up->overrun_backoff, delay);
 671         }
 672
 673         serial8250_rpm_put(up);
 674
 675         return IRQ_RETVAL(ret);
 676 }
 677
 678 static int omap_8250_startup(struct uart_port *port)
 679 {
 680         struct uart_8250_port *up = up_to_u8250p(port);
 681         struct omap8250_priv *priv = port->private_data;
 682         int ret;
 683
 684         if (priv->wakeirq) {
 685                 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
 686                 if (ret)
 687                         return ret;
 688         }
 689
 690         pm_runtime_get_sync(port->dev);
 691
 692         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 693
 694         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 695
 696         up->lsr_saved_flags = 0;
 697         up->msr_saved_flags = 0;
 698
 699         /* Disable DMA for console UART */
 700         if (uart_console(port))
 701                 up->dma = NULL;
 702
 703         if (up->dma) {
 704                 ret = serial8250_request_dma(up);
 705                 if (ret) {
 706                         dev_warn_ratelimited(port->dev,
 707                                              "failed to request DMA\n");
 708                         up->dma = NULL;
 709                 }
 710         }
 711
 712         up->ier = UART_IER_RLSI | UART_IER_RDI;
 713         serial_out(up, UART_IER, up->ier);
 714
 715 #ifdef CONFIG_PM
 716         up->capabilities |= UART_CAP_RPM;
 717 #endif
 718
 719         /* Enable module level wake up */
 720         priv->wer = OMAP_UART_WER_MOD_WKUP;
 721         if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
 722                 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
 723         serial_out(up, UART_OMAP_WER, priv->wer);
 724
 725         if (up->dma && !(priv->habit & UART_HAS_EFR2))
 726                 up->dma->rx_dma(up);
 727
 728         enable_irq(up->port.irq);
 729
 730         pm_runtime_mark_last_busy(port->dev);
 731         pm_runtime_put_autosuspend(port->dev);
 732         return 0;
 733 }
 734
 735 static void omap_8250_shutdown(struct uart_port *port)
 736 {
 737         struct uart_8250_port *up = up_to_u8250p(port);
 738         struct omap8250_priv *priv = port->private_data;
 739
 740         flush_work(&priv->qos_work);
 741         if (up->dma)
 742                 omap_8250_rx_dma_flush(up);
 743
 744         pm_runtime_get_sync(port->dev);
 745
 746         serial_out(up, UART_OMAP_WER, 0);
 747         if (priv->habit & UART_HAS_EFR2)
 748                 serial_out(up, UART_OMAP_EFR2, 0x0);
 749
 750         up->ier = 0;
 751         serial_out(up, UART_IER, 0);
 752         disable_irq_nosync(up->port.irq);
 753         dev_pm_clear_wake_irq(port->dev);
 754
 755         if (up->dma)
 756                 serial8250_release_dma(up);
 757
 758         /*
 759          * Disable break condition and FIFOs
 760          */
 761         if (up->lcr & UART_LCR_SBC)
 762                 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
 763         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 764
 765         pm_runtime_mark_last_busy(port->dev);
 766         pm_runtime_put_autosuspend(port->dev);
 767 }
 768
 769 static void omap_8250_throttle(struct uart_port *port)
 770 {
 771         struct omap8250_priv *priv = port->private_data;
 772         unsigned long flags;
 773
 774         pm_runtime_get_sync(port->dev);
 775
 776         spin_lock_irqsave(&port->lock, flags);
 777         port->ops->stop_rx(port);
 778         priv->throttled = true;
 779         spin_unlock_irqrestore(&port->lock, flags);
 780
 781         pm_runtime_mark_last_busy(port->dev);
 782         pm_runtime_put_autosuspend(port->dev);
 783 }
 784
 785 static void omap_8250_unthrottle(struct uart_port *port)
 786 {
 787         struct omap8250_priv *priv = port->private_data;
 788         struct uart_8250_port *up = up_to_u8250p(port);
 789         unsigned long flags;
 790
 791         pm_runtime_get_sync(port->dev);
 792
 793         spin_lock_irqsave(&port->lock, flags);
 794         priv->throttled = false;
 795         if (up->dma)
 796                 up->dma->rx_dma(up);
 797         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 798         port->read_status_mask |= UART_LSR_DR;
 799         serial_out(up, UART_IER, up->ier);
 800         spin_unlock_irqrestore(&port->lock, flags);
 801
 802         pm_runtime_mark_last_busy(port->dev);
 803         pm_runtime_put_autosuspend(port->dev);
 804 }
 805
 806 static int omap8250_rs485_config(struct uart_port *port,
 807                                  struct ktermios *termios,
 808                                  struct serial_rs485 *rs485)
 809 {
 810         struct omap8250_priv *priv = port->private_data;
 811         struct uart_8250_port *up = up_to_u8250p(port);
 812         u32 fixed_delay_rts_before_send = 0;
 813         u32 fixed_delay_rts_after_send = 0;
 814         unsigned int baud;
 815
 816         /*
 817          * There is a fixed delay of 3 bit clock cycles after the TX shift
 818          * register is going empty to allow time for the stop bit to transition
 819          * through the transceiver before direction is changed to receive.
 820          *
 821          * Additionally there appears to be a 1 bit clock delay between writing
 822          * to the THR register and transmission of the start bit, per page 8783
 823          * of the AM65 TRM:  https://www.ti.com/lit/ug/spruid7e/spruid7e.pdf
 824          */
 825         if (priv->quot) {
 826                 if (priv->mdr1 == UART_OMAP_MDR1_16X_MODE)
 827                         baud = port->uartclk / (16 * priv->quot);
 828                 else
 829                         baud = port->uartclk / (13 * priv->quot);
 830
 831                 fixed_delay_rts_after_send  = 3 * MSEC_PER_SEC / baud;
 832                 fixed_delay_rts_before_send = 1 * MSEC_PER_SEC / baud;
 833         }
 834
 835         /*
 836          * Fall back to RS485 software emulation if the UART is missing
 837          * hardware support, if the device tree specifies an mctrl_gpio
 838          * (indicates that RTS is unavailable due to a pinmux conflict)
 839          * or if the requested delays exceed the fixed hardware delays.
 840          */
 841         if (!(priv->habit & UART_HAS_NATIVE_RS485) ||
 842             mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) ||
 843             rs485->delay_rts_after_send  > fixed_delay_rts_after_send ||
 844             rs485->delay_rts_before_send > fixed_delay_rts_before_send) {
 845                 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN;
 846                 serial_out(up, UART_OMAP_MDR3, priv->mdr3);
 847
 848                 port->rs485_config = serial8250_em485_config;
 849                 return serial8250_em485_config(port, termios, rs485);
 850         }
 851
 852         rs485->delay_rts_after_send  = fixed_delay_rts_after_send;
 853         rs485->delay_rts_before_send = fixed_delay_rts_before_send;
 854
 855         if (rs485->flags & SER_RS485_ENABLED)
 856                 priv->mdr3 |= UART_OMAP_MDR3_DIR_EN;
 857         else
 858                 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_EN;
 859
 860         /*
 861          * Retain same polarity semantics as RS485 software emulation,
 862          * i.e. SER_RS485_RTS_ON_SEND means driving RTS low on send.
 863          */
 864         if (rs485->flags & SER_RS485_RTS_ON_SEND)
 865                 priv->mdr3 &= ~UART_OMAP_MDR3_DIR_POL;
 866         else
 867                 priv->mdr3 |= UART_OMAP_MDR3_DIR_POL;
 868
 869         serial_out(up, UART_OMAP_MDR3, priv->mdr3);
 870
 871         return 0;
 872 }
 873
 874 #ifdef CONFIG_SERIAL_8250_DMA
 875 static int omap_8250_rx_dma(struct uart_8250_port *p);
 876
 877 /* Must be called while priv->rx_dma_lock is held */
 878 static void __dma_rx_do_complete(struct uart_8250_port *p)
 879 {
 880         struct uart_8250_dma    *dma = p->dma;
 881         struct tty_port         *tty_port = &p->port.state->port;
 882         struct omap8250_priv    *priv = p->port.private_data;
 883         struct dma_chan         *rxchan = dma->rxchan;
 884         dma_cookie_t            cookie;
 885         struct dma_tx_state     state;
 886         int                     count;
 887         int                     ret;
 888         u32                     reg;
 889
 890         if (!dma->rx_running)
 891                 goto out;
 892
 893         cookie = dma->rx_cookie;
 894         dma->rx_running = 0;
 895
 896         /* Re-enable RX FIFO interrupt now that transfer is complete */
 897         if (priv->habit & UART_HAS_RHR_IT_DIS) {
 898                 reg = serial_in(p, UART_OMAP_IER2);
 899                 reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
 900                 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
 901         }
 902
 903         dmaengine_tx_status(rxchan, cookie, &state);
 904
 905         count = dma->rx_size - state.residue + state.in_flight_bytes;
 906         if (count < dma->rx_size) {
 907                 dmaengine_terminate_async(rxchan);
 908
 909                 /*
 910                  * Poll for teardown to complete which guarantees in
 911                  * flight data is drained.
 912                  */
 913                 if (state.in_flight_bytes) {
 914                         int poll_count = 25;
 915
 916                         while (dmaengine_tx_status(rxchan, cookie, NULL) &&
 917                                poll_count--)
 918                                 cpu_relax();
 919
 920                         if (poll_count == -1)
 921                                 dev_err(p->port.dev, "teardown incomplete\n");
 922                 }
 923         }
 924         if (!count)
 925                 goto out;
 926         ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
 927
 928         p->port.icount.rx += ret;
 929         p->port.icount.buf_overrun += count - ret;
 930 out:
 931
 932         tty_flip_buffer_push(tty_port);
 933 }
 934
 935 static void __dma_rx_complete(void *param)
 936 {
 937         struct uart_8250_port *p = param;
 938         struct omap8250_priv *priv = p->port.private_data;
 939         struct uart_8250_dma *dma = p->dma;
 940         struct dma_tx_state     state;
 941         unsigned long flags;
 942
 943         spin_lock_irqsave(&p->port.lock, flags);
 944
 945         /*
 946          * If the tx status is not DMA_COMPLETE, then this is a delayed
 947          * completion callback. A previous RX timeout flush would have
 948          * already pushed the data, so exit.
 949          */
 950         if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
 951                         DMA_COMPLETE) {
 952                 spin_unlock_irqrestore(&p->port.lock, flags);
 953                 return;
 954         }
 955         __dma_rx_do_complete(p);
 956         if (!priv->throttled) {
 957                 p->ier |= UART_IER_RLSI | UART_IER_RDI;
 958                 serial_out(p, UART_IER, p->ier);
 959                 if (!(priv->habit & UART_HAS_EFR2))
 960                         omap_8250_rx_dma(p);
 961         }
 962
 963         spin_unlock_irqrestore(&p->port.lock, flags);
 964 }
 965
 966 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
 967 {
 968         struct omap8250_priv    *priv = p->port.private_data;
 969         struct uart_8250_dma    *dma = p->dma;
 970         struct dma_tx_state     state;
 971         unsigned long           flags;
 972         int ret;
 973
 974         spin_lock_irqsave(&priv->rx_dma_lock, flags);
 975
 976         if (!dma->rx_running) {
 977                 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 978                 return;
 979         }
 980
 981         ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
 982         if (ret == DMA_IN_PROGRESS) {
 983                 ret = dmaengine_pause(dma->rxchan);
 984                 if (WARN_ON_ONCE(ret))
 985                         priv->rx_dma_broken = true;
 986         }
 987         __dma_rx_do_complete(p);
 988         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 989 }
 990
 991 static int omap_8250_rx_dma(struct uart_8250_port *p)
 992 {
 993         struct omap8250_priv            *priv = p->port.private_data;
 994         struct uart_8250_dma            *dma = p->dma;
 995         int                             err = 0;
 996         struct dma_async_tx_descriptor  *desc;
 997         unsigned long                   flags;
 998         u32                             reg;
 999
1000         if (priv->rx_dma_broken)
1001                 return -EINVAL;
1002
1003         spin_lock_irqsave(&priv->rx_dma_lock, flags);
1004
1005         if (dma->rx_running) {
1006                 enum dma_status state;
1007
1008                 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
1009                 if (state == DMA_COMPLETE) {
1010                         /*
1011                          * Disable RX interrupts to allow RX DMA completion
1012                          * callback to run.
1013                          */
1014                         p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1015                         serial_out(p, UART_IER, p->ier);
1016                 }
1017                 goto out;
1018         }
1019
1020         desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
1021                                            dma->rx_size, DMA_DEV_TO_MEM,
1022                                            DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1023         if (!desc) {
1024                 err = -EBUSY;
1025                 goto out;
1026         }
1027
1028         dma->rx_running = 1;
1029         desc->callback = __dma_rx_complete;
1030         desc->callback_param = p;
1031
1032         dma->rx_cookie = dmaengine_submit(desc);
1033
1034         /*
1035          * Disable RX FIFO interrupt while RX DMA is enabled, else
1036          * spurious interrupt may be raised when data is in the RX FIFO
1037          * but is yet to be drained by DMA.
1038          */
1039         if (priv->habit & UART_HAS_RHR_IT_DIS) {
1040                 reg = serial_in(p, UART_OMAP_IER2);
1041                 reg |= UART_OMAP_IER2_RHR_IT_DIS;
1042                 serial_out(p, UART_OMAP_IER2, UART_OMAP_IER2_RHR_IT_DIS);
1043         }
1044
1045         dma_async_issue_pending(dma->rxchan);
1046 out:
1047         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
1048         return err;
1049 }
1050
1051 static int omap_8250_tx_dma(struct uart_8250_port *p);
1052
1053 static void omap_8250_dma_tx_complete(void *param)
1054 {
1055         struct uart_8250_port   *p = param;
1056         struct uart_8250_dma    *dma = p->dma;
1057         struct circ_buf         *xmit = &p->port.state->xmit;
1058         unsigned long           flags;
1059         bool                    en_thri = false;
1060         struct omap8250_priv    *priv = p->port.private_data;
1061
1062         dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
1063                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
1064
1065         spin_lock_irqsave(&p->port.lock, flags);
1066
1067         dma->tx_running = 0;
1068
1069         uart_xmit_advance(&p->port, dma->tx_size);
1070
1071         if (priv->delayed_restore) {
1072                 priv->delayed_restore = 0;
1073                 omap8250_restore_regs(p);
1074         }
1075
1076         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1077                 uart_write_wakeup(&p->port);
1078
1079         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
1080                 int ret;
1081
1082                 ret = omap_8250_tx_dma(p);
1083                 if (ret)
1084                         en_thri = true;
1085         } else if (p->capabilities & UART_CAP_RPM) {
1086                 en_thri = true;
1087         }
1088
1089         if (en_thri) {
1090                 dma->tx_err = 1;
1091                 serial8250_set_THRI(p);
1092         }
1093
1094         spin_unlock_irqrestore(&p->port.lock, flags);
1095 }
1096
1097 static int omap_8250_tx_dma(struct uart_8250_port *p)
1098 {
1099         struct uart_8250_dma            *dma = p->dma;
1100         struct omap8250_priv            *priv = p->port.private_data;
1101         struct circ_buf                 *xmit = &p->port.state->xmit;
1102         struct dma_async_tx_descriptor  *desc;
1103         unsigned int    skip_byte = 0;
1104         int ret;
1105
1106         if (dma->tx_running)
1107                 return 0;
1108         if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
1109
1110                 /*
1111                  * Even if no data, we need to return an error for the two cases
1112                  * below so serial8250_tx_chars() is invoked and properly clears
1113                  * THRI and/or runtime suspend.
1114                  */
1115                 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
1116                         ret = -EBUSY;
1117                         goto err;
1118                 }
1119                 serial8250_clear_THRI(p);
1120                 return 0;
1121         }
1122
1123         dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1124         if (priv->habit & OMAP_DMA_TX_KICK) {
1125                 u8 tx_lvl;
1126
1127                 /*
1128                  * We need to put the first byte into the FIFO in order to start
1129                  * the DMA transfer. For transfers smaller than four bytes we
1130                  * don't bother doing DMA at all. It seem not matter if there
1131                  * are still bytes in the FIFO from the last transfer (in case
1132                  * we got here directly from omap_8250_dma_tx_complete()). Bytes
1133                  * leaving the FIFO seem not to trigger the DMA transfer. It is
1134                  * really the byte that we put into the FIFO.
1135                  * If the FIFO is already full then we most likely got here from
1136                  * omap_8250_dma_tx_complete(). And this means the DMA engine
1137                  * just completed its work. We don't have to wait the complete
1138                  * 86us at 115200,8n1 but around 60us (not to mention lower
1139                  * baudrates). So in that case we take the interrupt and try
1140                  * again with an empty FIFO.
1141                  */
1142                 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
1143                 if (tx_lvl == p->tx_loadsz) {
1144                         ret = -EBUSY;
1145                         goto err;
1146                 }
1147                 if (dma->tx_size < 4) {
1148                         ret = -EINVAL;
1149                         goto err;
1150                 }
1151                 skip_byte = 1;
1152         }
1153
1154         desc = dmaengine_prep_slave_single(dma->txchan,
1155                         dma->tx_addr + xmit->tail + skip_byte,
1156                         dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1157                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1158         if (!desc) {
1159                 ret = -EBUSY;
1160                 goto err;
1161         }
1162
1163         dma->tx_running = 1;
1164
1165         desc->callback = omap_8250_dma_tx_complete;
1166         desc->callback_param = p;
1167
1168         dma->tx_cookie = dmaengine_submit(desc);
1169
1170         dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1171                                    UART_XMIT_SIZE, DMA_TO_DEVICE);
1172
1173         dma_async_issue_pending(dma->txchan);
1174         if (dma->tx_err)
1175                 dma->tx_err = 0;
1176
1177         serial8250_clear_THRI(p);
1178         if (skip_byte)
1179                 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1180         return 0;
1181 err:
1182         dma->tx_err = 1;
1183         return ret;
1184 }
1185
1186 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1187 {
1188         switch (iir & 0x3f) {
1189         case UART_IIR_RLSI:
1190         case UART_IIR_RX_TIMEOUT:
1191         case UART_IIR_RDI:
1192                 omap_8250_rx_dma_flush(up);
1193                 return true;
1194         }
1195         return omap_8250_rx_dma(up);
1196 }
1197
1198 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status)
1199 {
1200         if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1201             (iir & UART_IIR_RDI)) {
1202                 if (handle_rx_dma(up, iir)) {
1203                         status = serial8250_rx_chars(up, status);
1204                         omap_8250_rx_dma(up);
1205                 }
1206         }
1207
1208         return status;
1209 }
1210
1211 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
1212                                      u16 status)
1213 {
1214         /*
1215          * Queue a new transfer if FIFO has data.
1216          */
1217         if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1218             (up->ier & UART_IER_RDI)) {
1219                 omap_8250_rx_dma(up);
1220                 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
1221         } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
1222                 /*
1223                  * Disable RX timeout, read IIR to clear
1224                  * current timeout condition, clear EFR2 to
1225                  * periodic timeouts, re-enable interrupts.
1226                  */
1227                 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1228                 serial_out(up, UART_IER, up->ier);
1229                 omap_8250_rx_dma_flush(up);
1230                 serial_in(up, UART_IIR);
1231                 serial_out(up, UART_OMAP_EFR2, 0x0);
1232                 up->ier |= UART_IER_RLSI | UART_IER_RDI;
1233                 serial_out(up, UART_IER, up->ier);
1234         }
1235 }
1236
1237 /*
1238  * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1239  * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1240  * use the default routine in the non-DMA case and this one for with DMA.
1241  */
1242 static int omap_8250_dma_handle_irq(struct uart_port *port)
1243 {
1244         struct uart_8250_port *up = up_to_u8250p(port);
1245         struct omap8250_priv *priv = up->port.private_data;
1246         u16 status;
1247         u8 iir;
1248
1249         serial8250_rpm_get(up);
1250
1251         iir = serial_port_in(port, UART_IIR);
1252         if (iir & UART_IIR_NO_INT) {
1253                 serial8250_rpm_put(up);
1254                 return IRQ_HANDLED;
1255         }
1256
1257         spin_lock(&port->lock);
1258
1259         status = serial_port_in(port, UART_LSR);
1260
1261         if (priv->habit & UART_HAS_EFR2)
1262                 am654_8250_handle_rx_dma(up, iir, status);
1263         else
1264                 status = omap_8250_handle_rx_dma(up, iir, status);
1265
1266         serial8250_modem_status(up);
1267         if (status & UART_LSR_THRE && up->dma->tx_err) {
1268                 if (uart_tx_stopped(&up->port) ||
1269                     uart_circ_empty(&up->port.state->xmit)) {
1270                         up->dma->tx_err = 0;
1271                         serial8250_tx_chars(up);
1272                 } else  {
1273                         /*
1274                          * try again due to an earlier failer which
1275                          * might have been resolved by now.
1276                          */
1277                         if (omap_8250_tx_dma(up))
1278                                 serial8250_tx_chars(up);
1279                 }
1280         }
1281
1282         uart_unlock_and_check_sysrq(port);
1283
1284         serial8250_rpm_put(up);
1285         return 1;
1286 }
1287
1288 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1289 {
1290         return false;
1291 }
1292
1293 #else
1294
1295 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1296 {
1297         return -EINVAL;
1298 }
1299 #endif
1300
1301 static int omap8250_no_handle_irq(struct uart_port *port)
1302 {
1303         /* IRQ has not been requested but handling irq? */
1304         WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1305         return 0;
1306 }
1307
1308 static struct omap8250_dma_params am654_dma = {
1309         .rx_size = SZ_2K,
1310         .rx_trigger = 1,
1311         .tx_trigger = TX_TRIGGER,
1312 };
1313
1314 static struct omap8250_dma_params am33xx_dma = {
1315         .rx_size = RX_TRIGGER,
1316         .rx_trigger = RX_TRIGGER,
1317         .tx_trigger = TX_TRIGGER,
1318 };
1319
1320 static struct omap8250_platdata am654_platdata = {
1321         .dma_params     = &am654_dma,
1322         .habit          = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS |
1323                           UART_RX_TIMEOUT_QUIRK | UART_HAS_NATIVE_RS485,
1324 };
1325
1326 static struct omap8250_platdata am33xx_platdata = {
1327         .dma_params     = &am33xx_dma,
1328         .habit          = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE,
1329 };
1330
1331 static struct omap8250_platdata omap4_platdata = {
1332         .dma_params     = &am33xx_dma,
1333         .habit          = UART_ERRATA_CLOCK_DISABLE,
1334 };
1335
1336 static const struct of_device_id omap8250_dt_ids[] = {
1337         { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1338         { .compatible = "ti,omap2-uart" },
1339         { .compatible = "ti,omap3-uart" },
1340         { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1341         { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1342         { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1343         { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1344         {},
1345 };
1346 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1347
1348 static int omap8250_probe(struct platform_device *pdev)
1349 {
1350         struct device_node *np = pdev->dev.of_node;
1351         struct omap8250_priv *priv;
1352         const struct omap8250_platdata *pdata;
1353         struct uart_8250_port up;
1354         struct resource *regs;
1355         void __iomem *membase;
1356         int irq, ret;
1357
1358         irq = platform_get_irq(pdev, 0);
1359         if (irq < 0)
1360                 return irq;
1361
1362         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1363         if (!regs) {
1364                 dev_err(&pdev->dev, "missing registers\n");
1365                 return -EINVAL;
1366         }
1367
1368         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1369         if (!priv)
1370                 return -ENOMEM;
1371
1372         membase = devm_ioremap(&pdev->dev, regs->start,
1373                                        resource_size(regs));
1374         if (!membase)
1375                 return -ENODEV;
1376
1377         memset(&up, 0, sizeof(up));
1378         up.port.dev = &pdev->dev;
1379         up.port.mapbase = regs->start;
1380         up.port.membase = membase;
1381         up.port.irq = irq;
1382         /*
1383          * It claims to be 16C750 compatible however it is a little different.
1384          * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1385          * have) is enabled via EFR instead of MCR. The type is set here 8250
1386          * just to get things going. UNKNOWN does not work for a few reasons and
1387          * we don't need our own type since we don't use 8250's set_termios()
1388          * or pm callback.
1389          */
1390         up.port.type = PORT_8250;
1391         up.port.iotype = UPIO_MEM;
1392         up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1393                 UPF_HARD_FLOW;
1394         up.port.private_data = priv;
1395
1396         up.port.regshift = OMAP_UART_REGSHIFT;
1397         up.port.fifosize = 64;
1398         up.tx_loadsz = 64;
1399         up.capabilities = UART_CAP_FIFO;
1400 #ifdef CONFIG_PM
1401         /*
1402          * Runtime PM is mostly transparent. However to do it right we need to a
1403          * TX empty interrupt before we can put the device to auto idle. So if
1404          * PM is not enabled we don't add that flag and can spare that one extra
1405          * interrupt in the TX path.
1406          */
1407         up.capabilities |= UART_CAP_RPM;
1408 #endif
1409         up.port.set_termios = omap_8250_set_termios;
1410         up.port.set_mctrl = omap8250_set_mctrl;
1411         up.port.pm = omap_8250_pm;
1412         up.port.startup = omap_8250_startup;
1413         up.port.shutdown = omap_8250_shutdown;
1414         up.port.throttle = omap_8250_throttle;
1415         up.port.unthrottle = omap_8250_unthrottle;
1416         up.port.rs485_config = omap8250_rs485_config;
1417         /* same rs485_supported for software emulation and native RS485 */
1418         up.port.rs485_supported = serial8250_em485_supported;
1419         up.rs485_start_tx = serial8250_em485_start_tx;
1420         up.rs485_stop_tx = serial8250_em485_stop_tx;
1421         up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1422
1423         ret = of_alias_get_id(np, "serial");
1424         if (ret < 0) {
1425                 dev_err(&pdev->dev, "failed to get alias\n");
1426                 return ret;
1427         }
1428         up.port.line = ret;
1429
1430         if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1431                 struct clk *clk;
1432
1433                 clk = devm_clk_get(&pdev->dev, NULL);
1434                 if (IS_ERR(clk)) {
1435                         if (PTR_ERR(clk) == -EPROBE_DEFER)
1436                                 return -EPROBE_DEFER;
1437                 } else {
1438                         up.port.uartclk = clk_get_rate(clk);
1439                 }
1440         }
1441
1442         if (of_property_read_u32(np, "overrun-throttle-ms",
1443                                  &up.overrun_backoff_time_ms) != 0)
1444                 up.overrun_backoff_time_ms = 0;
1445
1446         pdata = of_device_get_match_data(&pdev->dev);
1447         if (pdata)
1448                 priv->habit |= pdata->habit;
1449
1450         if (!up.port.uartclk) {
1451                 up.port.uartclk = DEFAULT_CLK_SPEED;
1452                 dev_warn(&pdev->dev,
1453                          "No clock speed specified: using default: %d\n",
1454                          DEFAULT_CLK_SPEED);
1455         }
1456
1457         priv->membase = membase;
1458         priv->line = -ENODEV;
1459         priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1460         priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1461         cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
1462         INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1463
1464         spin_lock_init(&priv->rx_dma_lock);
1465
1466         platform_set_drvdata(pdev, priv);
1467
1468         device_init_wakeup(&pdev->dev, true);
1469         pm_runtime_enable(&pdev->dev);
1470         pm_runtime_use_autosuspend(&pdev->dev);
1471
1472         /*
1473          * Disable runtime PM until autosuspend delay unless specifically
1474          * enabled by the user via sysfs. This is the historic way to
1475          * prevent an unsafe default policy with lossy characters on wake-up.
1476          * For serdev devices this is not needed, the policy can be managed by
1477          * the serdev driver.
1478          */
1479         if (!of_get_available_child_count(pdev->dev.of_node))
1480                 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1481
1482         pm_runtime_irq_safe(&pdev->dev);
1483
1484         pm_runtime_get_sync(&pdev->dev);
1485
1486         omap_serial_fill_features_erratas(&up, priv);
1487         up.port.handle_irq = omap8250_no_handle_irq;
1488         priv->rx_trigger = RX_TRIGGER;
1489         priv->tx_trigger = TX_TRIGGER;
1490 #ifdef CONFIG_SERIAL_8250_DMA
1491         /*
1492          * Oh DMA support. If there are no DMA properties in the DT then
1493          * we will fall back to a generic DMA channel which does not
1494          * really work here. To ensure that we do not get a generic DMA
1495          * channel assigned, we have the the_no_dma_filter_fn() here.
1496          * To avoid "failed to request DMA" messages we check for DMA
1497          * properties in DT.
1498          */
1499         ret = of_property_count_strings(np, "dma-names");
1500         if (ret == 2) {
1501                 struct omap8250_dma_params *dma_params = NULL;
1502
1503                 up.dma = &priv->omap8250_dma;
1504                 up.dma->fn = the_no_dma_filter_fn;
1505                 up.dma->tx_dma = omap_8250_tx_dma;
1506                 up.dma->rx_dma = omap_8250_rx_dma;
1507                 if (pdata)
1508                         dma_params = pdata->dma_params;
1509
1510                 if (dma_params) {
1511                         up.dma->rx_size = dma_params->rx_size;
1512                         up.dma->rxconf.src_maxburst = dma_params->rx_trigger;
1513                         up.dma->txconf.dst_maxburst = dma_params->tx_trigger;
1514                         priv->rx_trigger = dma_params->rx_trigger;
1515                         priv->tx_trigger = dma_params->tx_trigger;
1516                 } else {
1517                         up.dma->rx_size = RX_TRIGGER;
1518                         up.dma->rxconf.src_maxburst = RX_TRIGGER;
1519                         up.dma->txconf.dst_maxburst = TX_TRIGGER;
1520                 }
1521         }
1522 #endif
1523
1524         irq_set_status_flags(irq, IRQ_NOAUTOEN);
1525         ret = devm_request_irq(&pdev->dev, irq, omap8250_irq, 0,
1526                                dev_name(&pdev->dev), priv);
1527         if (ret < 0)
1528                 return ret;
1529
1530         priv->wakeirq = irq_of_parse_and_map(np, 1);
1531
1532         ret = serial8250_register_8250_port(&up);
1533         if (ret < 0) {
1534                 dev_err(&pdev->dev, "unable to register 8250 port\n");
1535                 goto err;
1536         }
1537         priv->line = ret;
1538         pm_runtime_mark_last_busy(&pdev->dev);
1539         pm_runtime_put_autosuspend(&pdev->dev);
1540         return 0;
1541 err:
1542         pm_runtime_dont_use_autosuspend(&pdev->dev);
1543         pm_runtime_put_sync(&pdev->dev);
1544         flush_work(&priv->qos_work);
1545         pm_runtime_disable(&pdev->dev);
1546         cpu_latency_qos_remove_request(&priv->pm_qos_request);
1547         return ret;
1548 }
1549
1550 static int omap8250_remove(struct platform_device *pdev)
1551 {
1552         struct omap8250_priv *priv = platform_get_drvdata(pdev);
1553         int err;
1554
1555         err = pm_runtime_resume_and_get(&pdev->dev);
1556         if (err)
1557                 return err;
1558
1559         serial8250_unregister_port(priv->line);
1560         priv->line = -ENODEV;
1561         pm_runtime_dont_use_autosuspend(&pdev->dev);
1562         pm_runtime_put_sync(&pdev->dev);
1563         flush_work(&priv->qos_work);
1564         pm_runtime_disable(&pdev->dev);
1565         cpu_latency_qos_remove_request(&priv->pm_qos_request);
1566         device_init_wakeup(&pdev->dev, false);
1567         return 0;
1568 }
1569
1570 #ifdef CONFIG_PM_SLEEP
1571 static int omap8250_prepare(struct device *dev)
1572 {
1573         struct omap8250_priv *priv = dev_get_drvdata(dev);
1574
1575         if (!priv)
1576                 return 0;
1577         priv->is_suspending = true;
1578         return 0;
1579 }
1580
1581 static void omap8250_complete(struct device *dev)
1582 {
1583         struct omap8250_priv *priv = dev_get_drvdata(dev);
1584
1585         if (!priv)
1586                 return;
1587         priv->is_suspending = false;
1588 }
1589
1590 static int omap8250_suspend(struct device *dev)
1591 {
1592         struct omap8250_priv *priv = dev_get_drvdata(dev);
1593         struct uart_8250_port *up = serial8250_get_port(priv->line);
1594
1595         serial8250_suspend_port(priv->line);
1596
1597         pm_runtime_get_sync(dev);
1598         if (!device_may_wakeup(dev))
1599                 priv->wer = 0;
1600         serial_out(up, UART_OMAP_WER, priv->wer);
1601         pm_runtime_mark_last_busy(dev);
1602         pm_runtime_put_autosuspend(dev);
1603
1604         flush_work(&priv->qos_work);
1605         return 0;
1606 }
1607
1608 static int omap8250_resume(struct device *dev)
1609 {
1610         struct omap8250_priv *priv = dev_get_drvdata(dev);
1611
1612         serial8250_resume_port(priv->line);
1613         return 0;
1614 }
1615 #else
1616 #define omap8250_prepare NULL
1617 #define omap8250_complete NULL
1618 #endif
1619
1620 #ifdef CONFIG_PM
1621 static int omap8250_lost_context(struct uart_8250_port *up)
1622 {
1623         u32 val;
1624
1625         val = serial_in(up, UART_OMAP_SCR);
1626         /*
1627          * If we lose context, then SCR is set to its reset value of zero.
1628          * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1629          * among other bits, to never set the register back to zero again.
1630          */
1631         if (!val)
1632                 return 1;
1633         return 0;
1634 }
1635
1636 /* TODO: in future, this should happen via API in drivers/reset/ */
1637 static int omap8250_soft_reset(struct device *dev)
1638 {
1639         struct omap8250_priv *priv = dev_get_drvdata(dev);
1640         int timeout = 100;
1641         int sysc;
1642         int syss;
1643
1644         /*
1645          * At least on omap4, unused uarts may not idle after reset without
1646          * a basic scr dma configuration even with no dma in use. The
1647          * module clkctrl status bits will be 1 instead of 3 blocking idle
1648          * for the whole clockdomain. The softreset below will clear scr,
1649          * and we restore it on resume so this is safe to do on all SoCs
1650          * needing omap8250_soft_reset() quirk. Do it in two writes as
1651          * recommended in the comment for omap8250_update_scr().
1652          */
1653         uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1654         uart_write(priv, UART_OMAP_SCR,
1655                    OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1656
1657         sysc = uart_read(priv, UART_OMAP_SYSC);
1658
1659         /* softreset the UART */
1660         sysc |= OMAP_UART_SYSC_SOFTRESET;
1661         uart_write(priv, UART_OMAP_SYSC, sysc);
1662
1663         /* By experiments, 1us enough for reset complete on AM335x */
1664         do {
1665                 udelay(1);
1666                 syss = uart_read(priv, UART_OMAP_SYSS);
1667         } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1668
1669         if (!timeout) {
1670                 dev_err(dev, "timed out waiting for reset done\n");
1671                 return -ETIMEDOUT;
1672         }
1673
1674         return 0;
1675 }
1676
1677 static int omap8250_runtime_suspend(struct device *dev)
1678 {
1679         struct omap8250_priv *priv = dev_get_drvdata(dev);
1680         struct uart_8250_port *up = NULL;
1681
1682         if (priv->line >= 0)
1683                 up = serial8250_get_port(priv->line);
1684         /*
1685          * When using 'no_console_suspend', the console UART must not be
1686          * suspended. Since driver suspend is managed by runtime suspend,
1687          * preventing runtime suspend (by returning error) will keep device
1688          * active during suspend.
1689          */
1690         if (priv->is_suspending && !console_suspend_enabled) {
1691                 if (up && uart_console(&up->port))
1692                         return -EBUSY;
1693         }
1694
1695         if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1696                 int ret;
1697
1698                 ret = omap8250_soft_reset(dev);
1699                 if (ret)
1700                         return ret;
1701
1702                 if (up) {
1703                         /* Restore to UART mode after reset (for wakeup) */
1704                         omap8250_update_mdr1(up, priv);
1705                         /* Restore wakeup enable register */
1706                         serial_out(up, UART_OMAP_WER, priv->wer);
1707                 }
1708         }
1709
1710         if (up && up->dma && up->dma->rxchan)
1711                 omap_8250_rx_dma_flush(up);
1712
1713         priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1714         schedule_work(&priv->qos_work);
1715
1716         return 0;
1717 }
1718
1719 static int omap8250_runtime_resume(struct device *dev)
1720 {
1721         struct omap8250_priv *priv = dev_get_drvdata(dev);
1722         struct uart_8250_port *up = NULL;
1723
1724         if (priv->line >= 0)
1725                 up = serial8250_get_port(priv->line);
1726
1727         if (up && omap8250_lost_context(up))
1728                 omap8250_restore_regs(up);
1729
1730         if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2))
1731                 omap_8250_rx_dma(up);
1732
1733         priv->latency = priv->calc_latency;
1734         schedule_work(&priv->qos_work);
1735         return 0;
1736 }
1737 #endif
1738
1739 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1740 static int __init omap8250_console_fixup(void)
1741 {
1742         char *omap_str;
1743         char *options;
1744         u8 idx;
1745
1746         if (strstr(boot_command_line, "console=ttyS"))
1747                 /* user set a ttyS based name for the console */
1748                 return 0;
1749
1750         omap_str = strstr(boot_command_line, "console=ttyO");
1751         if (!omap_str)
1752                 /* user did not set ttyO based console, so we don't care */
1753                 return 0;
1754
1755         omap_str += 12;
1756         if ('0' <= *omap_str && *omap_str <= '9')
1757                 idx = *omap_str - '0';
1758         else
1759                 return 0;
1760
1761         omap_str++;
1762         if (omap_str[0] == ',') {
1763                 omap_str++;
1764                 options = omap_str;
1765         } else {
1766                 options = NULL;
1767         }
1768
1769         add_preferred_console("ttyS", idx, options);
1770         pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1771                idx, idx);
1772         pr_err("This ensures that you still see kernel messages. Please\n");
1773         pr_err("update your kernel commandline.\n");
1774         return 0;
1775 }
1776 console_initcall(omap8250_console_fixup);
1777 #endif
1778
1779 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1780         SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1781         SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1782                            omap8250_runtime_resume, NULL)
1783         .prepare        = omap8250_prepare,
1784         .complete       = omap8250_complete,
1785 };
1786
1787 static struct platform_driver omap8250_platform_driver = {
1788         .driver = {
1789                 .name           = "omap8250",
1790                 .pm             = &omap8250_dev_pm_ops,
1791                 .of_match_table = omap8250_dt_ids,
1792         },
1793         .probe                  = omap8250_probe,
1794         .remove                 = omap8250_remove,
1795 };
1796 module_platform_driver(omap8250_platform_driver);
1797
1798 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1799 MODULE_DESCRIPTION("OMAP 8250 Driver");
1800 MODULE_LICENSE("GPL v2");