drivers/tty/serial/8250/8250_omap.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * 8250-core based driver for the OMAP internal UART
   4  *
   5  * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
   6  *
   7  * Copyright (C) 2014 Sebastian Andrzej Siewior
   8  *
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/device.h>
  13 #include <linux/io.h>
  14 #include <linux/module.h>
  15 #include <linux/serial_8250.h>
  16 #include <linux/serial_reg.h>
  17 #include <linux/tty_flip.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/slab.h>
  20 #include <linux/of.h>
  21 #include <linux/of_device.h>
  22 #include <linux/of_gpio.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/delay.h>
  25 #include <linux/pm_runtime.h>
  26 #include <linux/console.h>
  27 #include <linux/pm_qos.h>
  28 #include <linux/pm_wakeirq.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/sys_soc.h>
  31
  32 #include "8250.h"
  33
  34 #define DEFAULT_CLK_SPEED       48000000
  35 #define OMAP_UART_REGSHIFT      2
  36
  37 #define UART_ERRATA_i202_MDR1_ACCESS    (1 << 0)
  38 #define OMAP_UART_WER_HAS_TX_WAKEUP     (1 << 1)
  39 #define OMAP_DMA_TX_KICK                (1 << 2)
  40 /*
  41  * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
  42  * The same errata is applicable to AM335x and DRA7x processors too.
  43  */
  44 #define UART_ERRATA_CLOCK_DISABLE       (1 << 3)
  45 #define UART_HAS_EFR2                   BIT(4)
  46 #define UART_HAS_RHR_IT_DIS             BIT(5)
  47 #define UART_RX_TIMEOUT_QUIRK           BIT(6)
  48
  49 #define OMAP_UART_FCR_RX_TRIG           6
  50 #define OMAP_UART_FCR_TX_TRIG           4
  51
  52 /* SCR register bitmasks */
  53 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK       (1 << 7)
  54 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK       (1 << 6)
  55 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  56 #define OMAP_UART_SCR_DMAMODE_MASK              (3 << 1)
  57 #define OMAP_UART_SCR_DMAMODE_1                 (1 << 1)
  58 #define OMAP_UART_SCR_DMAMODE_CTL               (1 << 0)
  59
  60 /* MVR register bitmasks */
  61 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  62 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  63 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  64 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  65 #define OMAP_UART_MVR_MAJ_MASK          0x700
  66 #define OMAP_UART_MVR_MAJ_SHIFT         8
  67 #define OMAP_UART_MVR_MIN_MASK          0x3f
  68
  69 /* SYSC register bitmasks */
  70 #define OMAP_UART_SYSC_SOFTRESET        (1 << 1)
  71
  72 /* SYSS register bitmasks */
  73 #define OMAP_UART_SYSS_RESETDONE        (1 << 0)
  74
  75 #define UART_TI752_TLR_TX       0
  76 #define UART_TI752_TLR_RX       4
  77
  78 #define TRIGGER_TLR_MASK(x)     ((x & 0x3c) >> 2)
  79 #define TRIGGER_FCR_MASK(x)     (x & 3)
  80
  81 /* Enable XON/XOFF flow control on output */
  82 #define OMAP_UART_SW_TX         0x08
  83 /* Enable XON/XOFF flow control on input */
  84 #define OMAP_UART_SW_RX         0x02
  85
  86 #define OMAP_UART_WER_MOD_WKUP  0x7f
  87 #define OMAP_UART_TX_WAKEUP_EN  (1 << 7)
  88
  89 #define TX_TRIGGER      1
  90 #define RX_TRIGGER      48
  91
  92 #define OMAP_UART_TCR_RESTORE(x)        ((x / 4) << 4)
  93 #define OMAP_UART_TCR_HALT(x)           ((x / 4) << 0)
  94
  95 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  96
  97 #define OMAP_UART_REV_46 0x0406
  98 #define OMAP_UART_REV_52 0x0502
  99 #define OMAP_UART_REV_63 0x0603
 100
 101 /* Interrupt Enable Register 2 */
 102 #define UART_OMAP_IER2                  0x1B
 103 #define UART_OMAP_IER2_RHR_IT_DIS       BIT(2)
 104
 105 /* Enhanced features register 2 */
 106 #define UART_OMAP_EFR2                  0x23
 107 #define UART_OMAP_EFR2_TIMEOUT_BEHAVE   BIT(6)
 108
 109 /* RX FIFO occupancy indicator */
 110 #define UART_OMAP_RX_LVL                0x19
 111
 112 struct omap8250_priv {
 113         void __iomem *membase;
 114         int line;
 115         u8 habit;
 116         u8 mdr1;
 117         u8 efr;
 118         u8 scr;
 119         u8 wer;
 120         u8 xon;
 121         u8 xoff;
 122         u8 delayed_restore;
 123         u16 quot;
 124
 125         u8 tx_trigger;
 126         u8 rx_trigger;
 127         bool is_suspending;
 128         int wakeirq;
 129         int wakeups_enabled;
 130         u32 latency;
 131         u32 calc_latency;
 132         struct pm_qos_request pm_qos_request;
 133         struct work_struct qos_work;
 134         struct uart_8250_dma omap8250_dma;
 135         spinlock_t rx_dma_lock;
 136         bool rx_dma_broken;
 137         bool throttled;
 138 };
 139
 140 struct omap8250_dma_params {
 141         u32 rx_size;
 142         u8 rx_trigger;
 143         u8 tx_trigger;
 144 };
 145
 146 struct omap8250_platdata {
 147         struct omap8250_dma_params *dma_params;
 148         u8 habit;
 149 };
 150
 151 #ifdef CONFIG_SERIAL_8250_DMA
 152 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
 153 #else
 154 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
 155 #endif
 156
 157 static u32 uart_read(struct omap8250_priv *priv, u32 reg)
 158 {
 159         return readl(priv->membase + (reg << OMAP_UART_REGSHIFT));
 160 }
 161
 162 /*
 163  * Called on runtime PM resume path from omap8250_restore_regs(), and
 164  * omap8250_set_mctrl().
 165  */
 166 static void __omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
 167 {
 168         struct uart_8250_port *up = up_to_u8250p(port);
 169         struct omap8250_priv *priv = up->port.private_data;
 170         u8 lcr;
 171
 172         serial8250_do_set_mctrl(port, mctrl);
 173
 174         if (!mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS)) {
 175                 /*
 176                  * Turn off autoRTS if RTS is lowered and restore autoRTS
 177                  * setting if RTS is raised
 178                  */
 179                 lcr = serial_in(up, UART_LCR);
 180                 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 181                 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 182                         priv->efr |= UART_EFR_RTS;
 183                 else
 184                         priv->efr &= ~UART_EFR_RTS;
 185                 serial_out(up, UART_EFR, priv->efr);
 186                 serial_out(up, UART_LCR, lcr);
 187         }
 188 }
 189
 190 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
 191 {
 192         int err;
 193
 194         err = pm_runtime_resume_and_get(port->dev);
 195         if (err)
 196                 return;
 197
 198         __omap8250_set_mctrl(port, mctrl);
 199
 200         pm_runtime_mark_last_busy(port->dev);
 201         pm_runtime_put_autosuspend(port->dev);
 202 }
 203
 204 /*
 205  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
 206  * The access to uart register after MDR1 Access
 207  * causes UART to corrupt data.
 208  *
 209  * Need a delay =
 210  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
 211  * give 10 times as much
 212  */
 213 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
 214                                      struct omap8250_priv *priv)
 215 {
 216         serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 217         udelay(2);
 218         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
 219                         UART_FCR_CLEAR_RCVR);
 220 }
 221
 222 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
 223                                   struct omap8250_priv *priv)
 224 {
 225         unsigned int uartclk = port->uartclk;
 226         unsigned int div_13, div_16;
 227         unsigned int abs_d13, abs_d16;
 228
 229         /*
 230          * Old custom speed handling.
 231          */
 232         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
 233                 priv->quot = port->custom_divisor & UART_DIV_MAX;
 234                 /*
 235                  * I assume that nobody is using this. But hey, if somebody
 236                  * would like to specify the divisor _and_ the mode then the
 237                  * driver is ready and waiting for it.
 238                  */
 239                 if (port->custom_divisor & (1 << 16))
 240                         priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 241                 else
 242                         priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 243                 return;
 244         }
 245         div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
 246         div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
 247
 248         if (!div_13)
 249                 div_13 = 1;
 250         if (!div_16)
 251                 div_16 = 1;
 252
 253         abs_d13 = abs(baud - uartclk / 13 / div_13);
 254         abs_d16 = abs(baud - uartclk / 16 / div_16);
 255
 256         if (abs_d13 >= abs_d16) {
 257                 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
 258                 priv->quot = div_16;
 259         } else {
 260                 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
 261                 priv->quot = div_13;
 262         }
 263 }
 264
 265 static void omap8250_update_scr(struct uart_8250_port *up,
 266                                 struct omap8250_priv *priv)
 267 {
 268         u8 old_scr;
 269
 270         old_scr = serial_in(up, UART_OMAP_SCR);
 271         if (old_scr == priv->scr)
 272                 return;
 273
 274         /*
 275          * The manual recommends not to enable the DMA mode selector in the SCR
 276          * (instead of the FCR) register _and_ selecting the DMA mode as one
 277          * register write because this may lead to malfunction.
 278          */
 279         if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
 280                 serial_out(up, UART_OMAP_SCR,
 281                            priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
 282         serial_out(up, UART_OMAP_SCR, priv->scr);
 283 }
 284
 285 static void omap8250_update_mdr1(struct uart_8250_port *up,
 286                                  struct omap8250_priv *priv)
 287 {
 288         if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
 289                 omap_8250_mdr1_errataset(up, priv);
 290         else
 291                 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
 292 }
 293
 294 static void omap8250_restore_regs(struct uart_8250_port *up)
 295 {
 296         struct omap8250_priv *priv = up->port.private_data;
 297         struct uart_8250_dma    *dma = up->dma;
 298         u8 mcr = serial8250_in_MCR(up);
 299
 300         if (dma && dma->tx_running) {
 301                 /*
 302                  * TCSANOW requests the change to occur immediately however if
 303                  * we have a TX-DMA operation in progress then it has been
 304                  * observed that it might stall and never complete. Therefore we
 305                  * delay DMA completes to prevent this hang from happen.
 306                  */
 307                 priv->delayed_restore = 1;
 308                 return;
 309         }
 310
 311         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 312         serial_out(up, UART_EFR, UART_EFR_ECB);
 313
 314         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 315         serial8250_out_MCR(up, mcr | UART_MCR_TCRTLR);
 316         serial_out(up, UART_FCR, up->fcr);
 317
 318         omap8250_update_scr(up, priv);
 319
 320         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 321
 322         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
 323                         OMAP_UART_TCR_HALT(52));
 324         serial_out(up, UART_TI752_TLR,
 325                    TRIGGER_TLR_MASK(priv->tx_trigger) << UART_TI752_TLR_TX |
 326                    TRIGGER_TLR_MASK(priv->rx_trigger) << UART_TI752_TLR_RX);
 327
 328         serial_out(up, UART_LCR, 0);
 329
 330         /* drop TCR + TLR access, we setup XON/XOFF later */
 331         serial8250_out_MCR(up, mcr);
 332
 333         serial_out(up, UART_IER, up->ier);
 334
 335         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 336         serial_dl_write(up, priv->quot);
 337
 338         serial_out(up, UART_EFR, priv->efr);
 339
 340         /* Configure flow control */
 341         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 342         serial_out(up, UART_XON1, priv->xon);
 343         serial_out(up, UART_XOFF1, priv->xoff);
 344
 345         serial_out(up, UART_LCR, up->lcr);
 346
 347         omap8250_update_mdr1(up, priv);
 348
 349         __omap8250_set_mctrl(&up->port, up->port.mctrl);
 350
 351         if (up->port.rs485.flags & SER_RS485_ENABLED)
 352                 serial8250_em485_stop_tx(up);
 353 }
 354
 355 /*
 356  * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
 357  * some differences in how we want to handle flow control.
 358  */
 359 static void omap_8250_set_termios(struct uart_port *port,
 360                                   struct ktermios *termios,
 361                                   const struct ktermios *old)
 362 {
 363         struct uart_8250_port *up = up_to_u8250p(port);
 364         struct omap8250_priv *priv = up->port.private_data;
 365         unsigned char cval = 0;
 366         unsigned int baud;
 367
 368         cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
 369
 370         if (termios->c_cflag & CSTOPB)
 371                 cval |= UART_LCR_STOP;
 372         if (termios->c_cflag & PARENB)
 373                 cval |= UART_LCR_PARITY;
 374         if (!(termios->c_cflag & PARODD))
 375                 cval |= UART_LCR_EPAR;
 376         if (termios->c_cflag & CMSPAR)
 377                 cval |= UART_LCR_SPAR;
 378
 379         /*
 380          * Ask the core to calculate the divisor for us.
 381          */
 382         baud = uart_get_baud_rate(port, termios, old,
 383                                   port->uartclk / 16 / UART_DIV_MAX,
 384                                   port->uartclk / 13);
 385         omap_8250_get_divisor(port, baud, priv);
 386
 387         /*
 388          * Ok, we're now changing the port state. Do it with
 389          * interrupts disabled.
 390          */
 391         pm_runtime_get_sync(port->dev);
 392         spin_lock_irq(&port->lock);
 393
 394         /*
 395          * Update the per-port timeout.
 396          */
 397         uart_update_timeout(port, termios->c_cflag, baud);
 398
 399         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 400         if (termios->c_iflag & INPCK)
 401                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 402         if (termios->c_iflag & (IGNBRK | PARMRK))
 403                 up->port.read_status_mask |= UART_LSR_BI;
 404
 405         /*
 406          * Characters to ignore
 407          */
 408         up->port.ignore_status_mask = 0;
 409         if (termios->c_iflag & IGNPAR)
 410                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 411         if (termios->c_iflag & IGNBRK) {
 412                 up->port.ignore_status_mask |= UART_LSR_BI;
 413                 /*
 414                  * If we're ignoring parity and break indicators,
 415                  * ignore overruns too (for real raw support).
 416                  */
 417                 if (termios->c_iflag & IGNPAR)
 418                         up->port.ignore_status_mask |= UART_LSR_OE;
 419         }
 420
 421         /*
 422          * ignore all characters if CREAD is not set
 423          */
 424         if ((termios->c_cflag & CREAD) == 0)
 425                 up->port.ignore_status_mask |= UART_LSR_DR;
 426
 427         /*
 428          * Modem status interrupts
 429          */
 430         up->ier &= ~UART_IER_MSI;
 431         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 432                 up->ier |= UART_IER_MSI;
 433
 434         up->lcr = cval;
 435         /* Up to here it was mostly serial8250_do_set_termios() */
 436
 437         /*
 438          * We enable TRIG_GRANU for RX and TX and additionally we set
 439          * SCR_TX_EMPTY bit. The result is the following:
 440          * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
 441          * - less than RX_TRIGGER number of bytes will also cause an interrupt
 442          *   once the UART decides that there no new bytes arriving.
 443          * - Once THRE is enabled, the interrupt will be fired once the FIFO is
 444          *   empty - the trigger level is ignored here.
 445          *
 446          * Once DMA is enabled:
 447          * - UART will assert the TX DMA line once there is room for TX_TRIGGER
 448          *   bytes in the TX FIFO. On each assert the DMA engine will move
 449          *   TX_TRIGGER bytes into the FIFO.
 450          * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
 451          *   the FIFO and move RX_TRIGGER bytes.
 452          * This is because threshold and trigger values are the same.
 453          */
 454         up->fcr = UART_FCR_ENABLE_FIFO;
 455         up->fcr |= TRIGGER_FCR_MASK(priv->tx_trigger) << OMAP_UART_FCR_TX_TRIG;
 456         up->fcr |= TRIGGER_FCR_MASK(priv->rx_trigger) << OMAP_UART_FCR_RX_TRIG;
 457
 458         priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
 459                 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
 460
 461         if (up->dma)
 462                 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
 463                         OMAP_UART_SCR_DMAMODE_CTL;
 464
 465         priv->xon = termios->c_cc[VSTART];
 466         priv->xoff = termios->c_cc[VSTOP];
 467
 468         priv->efr = 0;
 469         up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
 470
 471         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW &&
 472             !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_RTS) &&
 473             !mctrl_gpio_to_gpiod(up->gpios, UART_GPIO_CTS)) {
 474                 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
 475                 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 476                 priv->efr |= UART_EFR_CTS;
 477         } else  if (up->port.flags & UPF_SOFT_FLOW) {
 478                 /*
 479                  * OMAP rx s/w flow control is borked; the transmitter remains
 480                  * stuck off even if rx flow control is subsequently disabled
 481                  */
 482
 483                 /*
 484                  * IXOFF Flag:
 485                  * Enable XON/XOFF flow control on output.
 486                  * Transmit XON1, XOFF1
 487                  */
 488                 if (termios->c_iflag & IXOFF) {
 489                         up->port.status |= UPSTAT_AUTOXOFF;
 490                         priv->efr |= OMAP_UART_SW_TX;
 491                 }
 492         }
 493         omap8250_restore_regs(up);
 494
 495         spin_unlock_irq(&up->port.lock);
 496         pm_runtime_mark_last_busy(port->dev);
 497         pm_runtime_put_autosuspend(port->dev);
 498
 499         /* calculate wakeup latency constraint */
 500         priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
 501         priv->latency = priv->calc_latency;
 502
 503         schedule_work(&priv->qos_work);
 504
 505         /* Don't rewrite B0 */
 506         if (tty_termios_baud_rate(termios))
 507                 tty_termios_encode_baud_rate(termios, baud, baud);
 508 }
 509
 510 /* same as 8250 except that we may have extra flow bits set in EFR */
 511 static void omap_8250_pm(struct uart_port *port, unsigned int state,
 512                          unsigned int oldstate)
 513 {
 514         struct uart_8250_port *up = up_to_u8250p(port);
 515         u8 efr;
 516
 517         pm_runtime_get_sync(port->dev);
 518         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 519         efr = serial_in(up, UART_EFR);
 520         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
 521         serial_out(up, UART_LCR, 0);
 522
 523         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
 524         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 525         serial_out(up, UART_EFR, efr);
 526         serial_out(up, UART_LCR, 0);
 527
 528         pm_runtime_mark_last_busy(port->dev);
 529         pm_runtime_put_autosuspend(port->dev);
 530 }
 531
 532 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
 533                                               struct omap8250_priv *priv)
 534 {
 535         static const struct soc_device_attribute k3_soc_devices[] = {
 536                 { .family = "AM65X",  },
 537                 { .family = "J721E", .revision = "SR1.0" },
 538                 { /* sentinel */ }
 539         };
 540         u32 mvr, scheme;
 541         u16 revision, major, minor;
 542
 543         mvr = uart_read(priv, UART_OMAP_MVER);
 544
 545         /* Check revision register scheme */
 546         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
 547
 548         switch (scheme) {
 549         case 0: /* Legacy Scheme: OMAP2/3 */
 550                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
 551                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
 552                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
 553                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
 554                 break;
 555         case 1:
 556                 /* New Scheme: OMAP4+ */
 557                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
 558                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
 559                         OMAP_UART_MVR_MAJ_SHIFT;
 560                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
 561                 break;
 562         default:
 563                 dev_warn(up->port.dev,
 564                          "Unknown revision, defaulting to highest\n");
 565                 /* highest possible revision */
 566                 major = 0xff;
 567                 minor = 0xff;
 568         }
 569         /* normalize revision for the driver */
 570         revision = UART_BUILD_REVISION(major, minor);
 571
 572         switch (revision) {
 573         case OMAP_UART_REV_46:
 574                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
 575                 break;
 576         case OMAP_UART_REV_52:
 577                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 578                                 OMAP_UART_WER_HAS_TX_WAKEUP;
 579                 break;
 580         case OMAP_UART_REV_63:
 581                 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
 582                         OMAP_UART_WER_HAS_TX_WAKEUP;
 583                 break;
 584         default:
 585                 break;
 586         }
 587
 588         /*
 589          * AM65x SR1.0, AM65x SR2.0 and J721e SR1.0 don't
 590          * don't have RHR_IT_DIS bit in IER2 register. So drop to flag
 591          * to enable errata workaround.
 592          */
 593         if (soc_device_match(k3_soc_devices))
 594                 priv->habit &= ~UART_HAS_RHR_IT_DIS;
 595 }
 596
 597 static void omap8250_uart_qos_work(struct work_struct *work)
 598 {
 599         struct omap8250_priv *priv;
 600
 601         priv = container_of(work, struct omap8250_priv, qos_work);
 602         cpu_latency_qos_update_request(&priv->pm_qos_request, priv->latency);
 603 }
 604
 605 #ifdef CONFIG_SERIAL_8250_DMA
 606 static int omap_8250_dma_handle_irq(struct uart_port *port);
 607 #endif
 608
 609 static irqreturn_t omap8250_irq(int irq, void *dev_id)
 610 {
 611         struct uart_port *port = dev_id;
 612         struct omap8250_priv *priv = port->private_data;
 613         struct uart_8250_port *up = up_to_u8250p(port);
 614         unsigned int iir, lsr;
 615         int ret;
 616
 617 #ifdef CONFIG_SERIAL_8250_DMA
 618         if (up->dma) {
 619                 ret = omap_8250_dma_handle_irq(port);
 620                 return IRQ_RETVAL(ret);
 621         }
 622 #endif
 623
 624         serial8250_rpm_get(up);
 625         lsr = serial_port_in(port, UART_LSR);
 626         iir = serial_port_in(port, UART_IIR);
 627         ret = serial8250_handle_irq(port, iir);
 628
 629         /*
 630          * On K3 SoCs, it is observed that RX TIMEOUT is signalled after
 631          * FIFO has been drained, in which case a dummy read of RX FIFO
 632          * is required to clear RX TIMEOUT condition.
 633          */
 634         if (priv->habit & UART_RX_TIMEOUT_QUIRK &&
 635             (iir & UART_IIR_RX_TIMEOUT) == UART_IIR_RX_TIMEOUT &&
 636             serial_port_in(port, UART_OMAP_RX_LVL) == 0) {
 637                 serial_port_in(port, UART_RX);
 638         }
 639
 640         /* Stop processing interrupts on input overrun */
 641         if ((lsr & UART_LSR_OE) && up->overrun_backoff_time_ms > 0) {
 642                 unsigned long delay;
 643
 644                 /* Synchronize UART_IER access against the console. */
 645                 spin_lock(&port->lock);
 646                 up->ier = port->serial_in(port, UART_IER);
 647                 if (up->ier & (UART_IER_RLSI | UART_IER_RDI)) {
 648                         port->ops->stop_rx(port);
 649                 } else {
 650                         /* Keep restarting the timer until
 651                          * the input overrun subsides.
 652                          */
 653                         cancel_delayed_work(&up->overrun_backoff);
 654                 }
 655                 spin_unlock(&port->lock);
 656
 657                 delay = msecs_to_jiffies(up->overrun_backoff_time_ms);
 658                 schedule_delayed_work(&up->overrun_backoff, delay);
 659         }
 660
 661         serial8250_rpm_put(up);
 662
 663         return IRQ_RETVAL(ret);
 664 }
 665
 666 static int omap_8250_startup(struct uart_port *port)
 667 {
 668         struct uart_8250_port *up = up_to_u8250p(port);
 669         struct omap8250_priv *priv = port->private_data;
 670         int ret;
 671
 672         if (priv->wakeirq) {
 673                 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
 674                 if (ret)
 675                         return ret;
 676         }
 677
 678         pm_runtime_get_sync(port->dev);
 679
 680         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 681
 682         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 683
 684         up->lsr_saved_flags = 0;
 685         up->msr_saved_flags = 0;
 686
 687         /* Disable DMA for console UART */
 688         if (uart_console(port))
 689                 up->dma = NULL;
 690
 691         if (up->dma) {
 692                 ret = serial8250_request_dma(up);
 693                 if (ret) {
 694                         dev_warn_ratelimited(port->dev,
 695                                              "failed to request DMA\n");
 696                         up->dma = NULL;
 697                 }
 698         }
 699
 700         ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
 701                           dev_name(port->dev), port);
 702         if (ret < 0)
 703                 goto err;
 704
 705         up->ier = UART_IER_RLSI | UART_IER_RDI;
 706         serial_out(up, UART_IER, up->ier);
 707
 708 #ifdef CONFIG_PM
 709         up->capabilities |= UART_CAP_RPM;
 710 #endif
 711
 712         /* Enable module level wake up */
 713         priv->wer = OMAP_UART_WER_MOD_WKUP;
 714         if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
 715                 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
 716         serial_out(up, UART_OMAP_WER, priv->wer);
 717
 718         if (up->dma && !(priv->habit & UART_HAS_EFR2))
 719                 up->dma->rx_dma(up);
 720
 721         pm_runtime_mark_last_busy(port->dev);
 722         pm_runtime_put_autosuspend(port->dev);
 723         return 0;
 724 err:
 725         pm_runtime_mark_last_busy(port->dev);
 726         pm_runtime_put_autosuspend(port->dev);
 727         dev_pm_clear_wake_irq(port->dev);
 728         return ret;
 729 }
 730
 731 static void omap_8250_shutdown(struct uart_port *port)
 732 {
 733         struct uart_8250_port *up = up_to_u8250p(port);
 734         struct omap8250_priv *priv = port->private_data;
 735
 736         flush_work(&priv->qos_work);
 737         if (up->dma)
 738                 omap_8250_rx_dma_flush(up);
 739
 740         pm_runtime_get_sync(port->dev);
 741
 742         serial_out(up, UART_OMAP_WER, 0);
 743         if (priv->habit & UART_HAS_EFR2)
 744                 serial_out(up, UART_OMAP_EFR2, 0x0);
 745
 746         up->ier = 0;
 747         serial_out(up, UART_IER, 0);
 748
 749         if (up->dma)
 750                 serial8250_release_dma(up);
 751
 752         /*
 753          * Disable break condition and FIFOs
 754          */
 755         if (up->lcr & UART_LCR_SBC)
 756                 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
 757         serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 758
 759         pm_runtime_mark_last_busy(port->dev);
 760         pm_runtime_put_autosuspend(port->dev);
 761         free_irq(port->irq, port);
 762         dev_pm_clear_wake_irq(port->dev);
 763 }
 764
 765 static void omap_8250_throttle(struct uart_port *port)
 766 {
 767         struct omap8250_priv *priv = port->private_data;
 768         unsigned long flags;
 769
 770         pm_runtime_get_sync(port->dev);
 771
 772         spin_lock_irqsave(&port->lock, flags);
 773         port->ops->stop_rx(port);
 774         priv->throttled = true;
 775         spin_unlock_irqrestore(&port->lock, flags);
 776
 777         pm_runtime_mark_last_busy(port->dev);
 778         pm_runtime_put_autosuspend(port->dev);
 779 }
 780
 781 static void omap_8250_unthrottle(struct uart_port *port)
 782 {
 783         struct omap8250_priv *priv = port->private_data;
 784         struct uart_8250_port *up = up_to_u8250p(port);
 785         unsigned long flags;
 786
 787         pm_runtime_get_sync(port->dev);
 788
 789         spin_lock_irqsave(&port->lock, flags);
 790         priv->throttled = false;
 791         if (up->dma)
 792                 up->dma->rx_dma(up);
 793         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 794         port->read_status_mask |= UART_LSR_DR;
 795         serial_out(up, UART_IER, up->ier);
 796         spin_unlock_irqrestore(&port->lock, flags);
 797
 798         pm_runtime_mark_last_busy(port->dev);
 799         pm_runtime_put_autosuspend(port->dev);
 800 }
 801
 802 #ifdef CONFIG_SERIAL_8250_DMA
 803 static int omap_8250_rx_dma(struct uart_8250_port *p);
 804
 805 /* Must be called while priv->rx_dma_lock is held */
 806 static void __dma_rx_do_complete(struct uart_8250_port *p)
 807 {
 808         struct uart_8250_dma    *dma = p->dma;
 809         struct tty_port         *tty_port = &p->port.state->port;
 810         struct omap8250_priv    *priv = p->port.private_data;
 811         struct dma_chan         *rxchan = dma->rxchan;
 812         dma_cookie_t            cookie;
 813         struct dma_tx_state     state;
 814         int                     count;
 815         int                     ret;
 816         u32                     reg;
 817
 818         if (!dma->rx_running)
 819                 goto out;
 820
 821         cookie = dma->rx_cookie;
 822         dma->rx_running = 0;
 823
 824         /* Re-enable RX FIFO interrupt now that transfer is complete */
 825         if (priv->habit & UART_HAS_RHR_IT_DIS) {
 826                 reg = serial_in(p, UART_OMAP_IER2);
 827                 reg &= ~UART_OMAP_IER2_RHR_IT_DIS;
 828                 serial_out(p, UART_OMAP_IER2, reg);
 829         }
 830
 831         dmaengine_tx_status(rxchan, cookie, &state);
 832
 833         count = dma->rx_size - state.residue + state.in_flight_bytes;
 834         if (count < dma->rx_size) {
 835                 dmaengine_terminate_async(rxchan);
 836
 837                 /*
 838                  * Poll for teardown to complete which guarantees in
 839                  * flight data is drained.
 840                  */
 841                 if (state.in_flight_bytes) {
 842                         int poll_count = 25;
 843
 844                         while (dmaengine_tx_status(rxchan, cookie, NULL) &&
 845                                poll_count--)
 846                                 cpu_relax();
 847
 848                         if (poll_count == -1)
 849                                 dev_err(p->port.dev, "teardown incomplete\n");
 850                 }
 851         }
 852         if (!count)
 853                 goto out;
 854         ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
 855
 856         p->port.icount.rx += ret;
 857         p->port.icount.buf_overrun += count - ret;
 858 out:
 859
 860         tty_flip_buffer_push(tty_port);
 861 }
 862
 863 static void __dma_rx_complete(void *param)
 864 {
 865         struct uart_8250_port *p = param;
 866         struct omap8250_priv *priv = p->port.private_data;
 867         struct uart_8250_dma *dma = p->dma;
 868         struct dma_tx_state     state;
 869         unsigned long flags;
 870
 871         spin_lock_irqsave(&p->port.lock, flags);
 872
 873         /*
 874          * If the tx status is not DMA_COMPLETE, then this is a delayed
 875          * completion callback. A previous RX timeout flush would have
 876          * already pushed the data, so exit.
 877          */
 878         if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
 879                         DMA_COMPLETE) {
 880                 spin_unlock_irqrestore(&p->port.lock, flags);
 881                 return;
 882         }
 883         __dma_rx_do_complete(p);
 884         if (!priv->throttled) {
 885                 p->ier |= UART_IER_RLSI | UART_IER_RDI;
 886                 serial_out(p, UART_IER, p->ier);
 887                 if (!(priv->habit & UART_HAS_EFR2))
 888                         omap_8250_rx_dma(p);
 889         }
 890
 891         spin_unlock_irqrestore(&p->port.lock, flags);
 892 }
 893
 894 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
 895 {
 896         struct omap8250_priv    *priv = p->port.private_data;
 897         struct uart_8250_dma    *dma = p->dma;
 898         struct dma_tx_state     state;
 899         unsigned long           flags;
 900         int ret;
 901
 902         spin_lock_irqsave(&priv->rx_dma_lock, flags);
 903
 904         if (!dma->rx_running) {
 905                 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 906                 return;
 907         }
 908
 909         ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
 910         if (ret == DMA_IN_PROGRESS) {
 911                 ret = dmaengine_pause(dma->rxchan);
 912                 if (WARN_ON_ONCE(ret))
 913                         priv->rx_dma_broken = true;
 914         }
 915         __dma_rx_do_complete(p);
 916         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 917 }
 918
 919 static int omap_8250_rx_dma(struct uart_8250_port *p)
 920 {
 921         struct omap8250_priv            *priv = p->port.private_data;
 922         struct uart_8250_dma            *dma = p->dma;
 923         int                             err = 0;
 924         struct dma_async_tx_descriptor  *desc;
 925         unsigned long                   flags;
 926         u32                             reg;
 927
 928         if (priv->rx_dma_broken)
 929                 return -EINVAL;
 930
 931         spin_lock_irqsave(&priv->rx_dma_lock, flags);
 932
 933         if (dma->rx_running) {
 934                 enum dma_status state;
 935
 936                 state = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, NULL);
 937                 if (state == DMA_COMPLETE) {
 938                         /*
 939                          * Disable RX interrupts to allow RX DMA completion
 940                          * callback to run.
 941                          */
 942                         p->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 943                         serial_out(p, UART_IER, p->ier);
 944                 }
 945                 goto out;
 946         }
 947
 948         desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
 949                                            dma->rx_size, DMA_DEV_TO_MEM,
 950                                            DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 951         if (!desc) {
 952                 err = -EBUSY;
 953                 goto out;
 954         }
 955
 956         dma->rx_running = 1;
 957         desc->callback = __dma_rx_complete;
 958         desc->callback_param = p;
 959
 960         dma->rx_cookie = dmaengine_submit(desc);
 961
 962         /*
 963          * Disable RX FIFO interrupt while RX DMA is enabled, else
 964          * spurious interrupt may be raised when data is in the RX FIFO
 965          * but is yet to be drained by DMA.
 966          */
 967         if (priv->habit & UART_HAS_RHR_IT_DIS) {
 968                 reg = serial_in(p, UART_OMAP_IER2);
 969                 reg |= UART_OMAP_IER2_RHR_IT_DIS;
 970                 serial_out(p, UART_OMAP_IER2, reg);
 971         }
 972
 973         dma_async_issue_pending(dma->rxchan);
 974 out:
 975         spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
 976         return err;
 977 }
 978
 979 static int omap_8250_tx_dma(struct uart_8250_port *p);
 980
 981 static void omap_8250_dma_tx_complete(void *param)
 982 {
 983         struct uart_8250_port   *p = param;
 984         struct uart_8250_dma    *dma = p->dma;
 985         struct circ_buf         *xmit = &p->port.state->xmit;
 986         unsigned long           flags;
 987         bool                    en_thri = false;
 988         struct omap8250_priv    *priv = p->port.private_data;
 989
 990         dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
 991                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 992
 993         spin_lock_irqsave(&p->port.lock, flags);
 994
 995         dma->tx_running = 0;
 996
 997         uart_xmit_advance(&p->port, dma->tx_size);
 998
 999         if (priv->delayed_restore) {
1000                 priv->delayed_restore = 0;
1001                 omap8250_restore_regs(p);
1002         }
1003
1004         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1005                 uart_write_wakeup(&p->port);
1006
1007         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
1008                 int ret;
1009
1010                 ret = omap_8250_tx_dma(p);
1011                 if (ret)
1012                         en_thri = true;
1013         } else if (p->capabilities & UART_CAP_RPM) {
1014                 en_thri = true;
1015         }
1016
1017         if (en_thri) {
1018                 dma->tx_err = 1;
1019                 serial8250_set_THRI(p);
1020         }
1021
1022         spin_unlock_irqrestore(&p->port.lock, flags);
1023 }
1024
1025 static int omap_8250_tx_dma(struct uart_8250_port *p)
1026 {
1027         struct uart_8250_dma            *dma = p->dma;
1028         struct omap8250_priv            *priv = p->port.private_data;
1029         struct circ_buf                 *xmit = &p->port.state->xmit;
1030         struct dma_async_tx_descriptor  *desc;
1031         unsigned int    skip_byte = 0;
1032         int ret;
1033
1034         if (dma->tx_running)
1035                 return 0;
1036         if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
1037
1038                 /*
1039                  * Even if no data, we need to return an error for the two cases
1040                  * below so serial8250_tx_chars() is invoked and properly clears
1041                  * THRI and/or runtime suspend.
1042                  */
1043                 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
1044                         ret = -EBUSY;
1045                         goto err;
1046                 }
1047                 serial8250_clear_THRI(p);
1048                 return 0;
1049         }
1050
1051         dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
1052         if (priv->habit & OMAP_DMA_TX_KICK) {
1053                 u8 tx_lvl;
1054
1055                 /*
1056                  * We need to put the first byte into the FIFO in order to start
1057                  * the DMA transfer. For transfers smaller than four bytes we
1058                  * don't bother doing DMA at all. It seem not matter if there
1059                  * are still bytes in the FIFO from the last transfer (in case
1060                  * we got here directly from omap_8250_dma_tx_complete()). Bytes
1061                  * leaving the FIFO seem not to trigger the DMA transfer. It is
1062                  * really the byte that we put into the FIFO.
1063                  * If the FIFO is already full then we most likely got here from
1064                  * omap_8250_dma_tx_complete(). And this means the DMA engine
1065                  * just completed its work. We don't have to wait the complete
1066                  * 86us at 115200,8n1 but around 60us (not to mention lower
1067                  * baudrates). So in that case we take the interrupt and try
1068                  * again with an empty FIFO.
1069                  */
1070                 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
1071                 if (tx_lvl == p->tx_loadsz) {
1072                         ret = -EBUSY;
1073                         goto err;
1074                 }
1075                 if (dma->tx_size < 4) {
1076                         ret = -EINVAL;
1077                         goto err;
1078                 }
1079                 skip_byte = 1;
1080         }
1081
1082         desc = dmaengine_prep_slave_single(dma->txchan,
1083                         dma->tx_addr + xmit->tail + skip_byte,
1084                         dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
1085                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1086         if (!desc) {
1087                 ret = -EBUSY;
1088                 goto err;
1089         }
1090
1091         dma->tx_running = 1;
1092
1093         desc->callback = omap_8250_dma_tx_complete;
1094         desc->callback_param = p;
1095
1096         dma->tx_cookie = dmaengine_submit(desc);
1097
1098         dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1099                                    UART_XMIT_SIZE, DMA_TO_DEVICE);
1100
1101         dma_async_issue_pending(dma->txchan);
1102         if (dma->tx_err)
1103                 dma->tx_err = 0;
1104
1105         serial8250_clear_THRI(p);
1106         if (skip_byte)
1107                 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1108         return 0;
1109 err:
1110         dma->tx_err = 1;
1111         return ret;
1112 }
1113
1114 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1115 {
1116         switch (iir & 0x3f) {
1117         case UART_IIR_RLSI:
1118         case UART_IIR_RX_TIMEOUT:
1119         case UART_IIR_RDI:
1120                 omap_8250_rx_dma_flush(up);
1121                 return true;
1122         }
1123         return omap_8250_rx_dma(up);
1124 }
1125
1126 static u16 omap_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir, u16 status)
1127 {
1128         if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1129             (iir & UART_IIR_RDI)) {
1130                 if (handle_rx_dma(up, iir)) {
1131                         status = serial8250_rx_chars(up, status);
1132                         omap_8250_rx_dma(up);
1133                 }
1134         }
1135
1136         return status;
1137 }
1138
1139 static void am654_8250_handle_rx_dma(struct uart_8250_port *up, u8 iir,
1140                                      u16 status)
1141 {
1142         /*
1143          * Queue a new transfer if FIFO has data.
1144          */
1145         if ((status & (UART_LSR_DR | UART_LSR_BI)) &&
1146             (up->ier & UART_IER_RDI)) {
1147                 omap_8250_rx_dma(up);
1148                 serial_out(up, UART_OMAP_EFR2, UART_OMAP_EFR2_TIMEOUT_BEHAVE);
1149         } else if ((iir & 0x3f) == UART_IIR_RX_TIMEOUT) {
1150                 /*
1151                  * Disable RX timeout, read IIR to clear
1152                  * current timeout condition, clear EFR2 to
1153                  * periodic timeouts, re-enable interrupts.
1154                  */
1155                 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
1156                 serial_out(up, UART_IER, up->ier);
1157                 omap_8250_rx_dma_flush(up);
1158                 serial_in(up, UART_IIR);
1159                 serial_out(up, UART_OMAP_EFR2, 0x0);
1160                 up->ier |= UART_IER_RLSI | UART_IER_RDI;
1161                 serial_out(up, UART_IER, up->ier);
1162         }
1163 }
1164
1165 /*
1166  * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1167  * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1168  * use the default routine in the non-DMA case and this one for with DMA.
1169  */
1170 static int omap_8250_dma_handle_irq(struct uart_port *port)
1171 {
1172         struct uart_8250_port *up = up_to_u8250p(port);
1173         struct omap8250_priv *priv = up->port.private_data;
1174         u16 status;
1175         u8 iir;
1176
1177         serial8250_rpm_get(up);
1178
1179         iir = serial_port_in(port, UART_IIR);
1180         if (iir & UART_IIR_NO_INT) {
1181                 serial8250_rpm_put(up);
1182                 return IRQ_HANDLED;
1183         }
1184
1185         spin_lock(&port->lock);
1186
1187         status = serial_port_in(port, UART_LSR);
1188
1189         if ((iir & 0x3f) != UART_IIR_THRI) {
1190                 if (priv->habit & UART_HAS_EFR2)
1191                         am654_8250_handle_rx_dma(up, iir, status);
1192                 else
1193                         status = omap_8250_handle_rx_dma(up, iir, status);
1194         }
1195
1196         serial8250_modem_status(up);
1197         if (status & UART_LSR_THRE && up->dma->tx_err) {
1198                 if (uart_tx_stopped(&up->port) ||
1199                     uart_circ_empty(&up->port.state->xmit)) {
1200                         up->dma->tx_err = 0;
1201                         serial8250_tx_chars(up);
1202                 } else  {
1203                         /*
1204                          * try again due to an earlier failer which
1205                          * might have been resolved by now.
1206                          */
1207                         if (omap_8250_tx_dma(up))
1208                                 serial8250_tx_chars(up);
1209                 }
1210         }
1211
1212         uart_unlock_and_check_sysrq(port);
1213
1214         serial8250_rpm_put(up);
1215         return 1;
1216 }
1217
1218 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1219 {
1220         return false;
1221 }
1222
1223 #else
1224
1225 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1226 {
1227         return -EINVAL;
1228 }
1229 #endif
1230
1231 static int omap8250_no_handle_irq(struct uart_port *port)
1232 {
1233         /* IRQ has not been requested but handling irq? */
1234         WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1235         return 0;
1236 }
1237
1238 static struct omap8250_dma_params am654_dma = {
1239         .rx_size = SZ_2K,
1240         .rx_trigger = 1,
1241         .tx_trigger = TX_TRIGGER,
1242 };
1243
1244 static struct omap8250_dma_params am33xx_dma = {
1245         .rx_size = RX_TRIGGER,
1246         .rx_trigger = RX_TRIGGER,
1247         .tx_trigger = TX_TRIGGER,
1248 };
1249
1250 static struct omap8250_platdata am654_platdata = {
1251         .dma_params     = &am654_dma,
1252         .habit          = UART_HAS_EFR2 | UART_HAS_RHR_IT_DIS |
1253                           UART_RX_TIMEOUT_QUIRK,
1254 };
1255
1256 static struct omap8250_platdata am33xx_platdata = {
1257         .dma_params     = &am33xx_dma,
1258         .habit          = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE,
1259 };
1260
1261 static struct omap8250_platdata omap4_platdata = {
1262         .dma_params     = &am33xx_dma,
1263         .habit          = UART_ERRATA_CLOCK_DISABLE,
1264 };
1265
1266 static const struct of_device_id omap8250_dt_ids[] = {
1267         { .compatible = "ti,am654-uart", .data = &am654_platdata, },
1268         { .compatible = "ti,omap2-uart" },
1269         { .compatible = "ti,omap3-uart" },
1270         { .compatible = "ti,omap4-uart", .data = &omap4_platdata, },
1271         { .compatible = "ti,am3352-uart", .data = &am33xx_platdata, },
1272         { .compatible = "ti,am4372-uart", .data = &am33xx_platdata, },
1273         { .compatible = "ti,dra742-uart", .data = &omap4_platdata, },
1274         {},
1275 };
1276 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1277
1278 static int omap8250_probe(struct platform_device *pdev)
1279 {
1280         struct device_node *np = pdev->dev.of_node;
1281         struct omap8250_priv *priv;
1282         const struct omap8250_platdata *pdata;
1283         struct uart_8250_port up;
1284         struct resource *regs;
1285         void __iomem *membase;
1286         int irq, ret;
1287
1288         irq = platform_get_irq(pdev, 0);
1289         if (irq < 0)
1290                 return irq;
1291
1292         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1293         if (!regs) {
1294                 dev_err(&pdev->dev, "missing registers\n");
1295                 return -EINVAL;
1296         }
1297
1298         priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1299         if (!priv)
1300                 return -ENOMEM;
1301
1302         membase = devm_ioremap(&pdev->dev, regs->start,
1303                                        resource_size(regs));
1304         if (!membase)
1305                 return -ENODEV;
1306
1307         memset(&up, 0, sizeof(up));
1308         up.port.dev = &pdev->dev;
1309         up.port.mapbase = regs->start;
1310         up.port.membase = membase;
1311         up.port.irq = irq;
1312         /*
1313          * It claims to be 16C750 compatible however it is a little different.
1314          * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1315          * have) is enabled via EFR instead of MCR. The type is set here 8250
1316          * just to get things going. UNKNOWN does not work for a few reasons and
1317          * we don't need our own type since we don't use 8250's set_termios()
1318          * or pm callback.
1319          */
1320         up.port.type = PORT_8250;
1321         up.port.iotype = UPIO_MEM;
1322         up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1323                 UPF_HARD_FLOW;
1324         up.port.private_data = priv;
1325
1326         up.port.regshift = OMAP_UART_REGSHIFT;
1327         up.port.fifosize = 64;
1328         up.tx_loadsz = 64;
1329         up.capabilities = UART_CAP_FIFO;
1330 #ifdef CONFIG_PM
1331         /*
1332          * Runtime PM is mostly transparent. However to do it right we need to a
1333          * TX empty interrupt before we can put the device to auto idle. So if
1334          * PM is not enabled we don't add that flag and can spare that one extra
1335          * interrupt in the TX path.
1336          */
1337         up.capabilities |= UART_CAP_RPM;
1338 #endif
1339         up.port.set_termios = omap_8250_set_termios;
1340         up.port.set_mctrl = omap8250_set_mctrl;
1341         up.port.pm = omap_8250_pm;
1342         up.port.startup = omap_8250_startup;
1343         up.port.shutdown = omap_8250_shutdown;
1344         up.port.throttle = omap_8250_throttle;
1345         up.port.unthrottle = omap_8250_unthrottle;
1346         up.port.rs485_config = serial8250_em485_config;
1347         up.port.rs485_supported = serial8250_em485_supported;
1348         up.rs485_start_tx = serial8250_em485_start_tx;
1349         up.rs485_stop_tx = serial8250_em485_stop_tx;
1350         up.port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_8250_CONSOLE);
1351
1352         ret = of_alias_get_id(np, "serial");
1353         if (ret < 0) {
1354                 dev_err(&pdev->dev, "failed to get alias\n");
1355                 return ret;
1356         }
1357         up.port.line = ret;
1358
1359         if (of_property_read_u32(np, "clock-frequency", &up.port.uartclk)) {
1360                 struct clk *clk;
1361
1362                 clk = devm_clk_get(&pdev->dev, NULL);
1363                 if (IS_ERR(clk)) {
1364                         if (PTR_ERR(clk) == -EPROBE_DEFER)
1365                                 return -EPROBE_DEFER;
1366                 } else {
1367                         up.port.uartclk = clk_get_rate(clk);
1368                 }
1369         }
1370
1371         if (of_property_read_u32(np, "overrun-throttle-ms",
1372                                  &up.overrun_backoff_time_ms) != 0)
1373                 up.overrun_backoff_time_ms = 0;
1374
1375         priv->wakeirq = irq_of_parse_and_map(np, 1);
1376
1377         pdata = of_device_get_match_data(&pdev->dev);
1378         if (pdata)
1379                 priv->habit |= pdata->habit;
1380
1381         if (!up.port.uartclk) {
1382                 up.port.uartclk = DEFAULT_CLK_SPEED;
1383                 dev_warn(&pdev->dev,
1384                          "No clock speed specified: using default: %d\n",
1385                          DEFAULT_CLK_SPEED);
1386         }
1387
1388         priv->membase = membase;
1389         priv->line = -ENODEV;
1390         priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1391         priv->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1392         cpu_latency_qos_add_request(&priv->pm_qos_request, priv->latency);
1393         INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1394
1395         spin_lock_init(&priv->rx_dma_lock);
1396
1397         platform_set_drvdata(pdev, priv);
1398
1399         device_init_wakeup(&pdev->dev, true);
1400         pm_runtime_enable(&pdev->dev);
1401         pm_runtime_use_autosuspend(&pdev->dev);
1402
1403         /*
1404          * Disable runtime PM until autosuspend delay unless specifically
1405          * enabled by the user via sysfs. This is the historic way to
1406          * prevent an unsafe default policy with lossy characters on wake-up.
1407          * For serdev devices this is not needed, the policy can be managed by
1408          * the serdev driver.
1409          */
1410         if (!of_get_available_child_count(pdev->dev.of_node))
1411                 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1412
1413         pm_runtime_irq_safe(&pdev->dev);
1414
1415         pm_runtime_get_sync(&pdev->dev);
1416
1417         omap_serial_fill_features_erratas(&up, priv);
1418         up.port.handle_irq = omap8250_no_handle_irq;
1419         priv->rx_trigger = RX_TRIGGER;
1420         priv->tx_trigger = TX_TRIGGER;
1421 #ifdef CONFIG_SERIAL_8250_DMA
1422         /*
1423          * Oh DMA support. If there are no DMA properties in the DT then
1424          * we will fall back to a generic DMA channel which does not
1425          * really work here. To ensure that we do not get a generic DMA
1426          * channel assigned, we have the the_no_dma_filter_fn() here.
1427          * To avoid "failed to request DMA" messages we check for DMA
1428          * properties in DT.
1429          */
1430         ret = of_property_count_strings(np, "dma-names");
1431         if (ret == 2) {
1432                 struct omap8250_dma_params *dma_params = NULL;
1433
1434                 up.dma = &priv->omap8250_dma;
1435                 up.dma->fn = the_no_dma_filter_fn;
1436                 up.dma->tx_dma = omap_8250_tx_dma;
1437                 up.dma->rx_dma = omap_8250_rx_dma;
1438                 if (pdata)
1439                         dma_params = pdata->dma_params;
1440
1441                 if (dma_params) {
1442                         up.dma->rx_size = dma_params->rx_size;
1443                         up.dma->rxconf.src_maxburst = dma_params->rx_trigger;
1444                         up.dma->txconf.dst_maxburst = dma_params->tx_trigger;
1445                         priv->rx_trigger = dma_params->rx_trigger;
1446                         priv->tx_trigger = dma_params->tx_trigger;
1447                 } else {
1448                         up.dma->rx_size = RX_TRIGGER;
1449                         up.dma->rxconf.src_maxburst = RX_TRIGGER;
1450                         up.dma->txconf.dst_maxburst = TX_TRIGGER;
1451                 }
1452         }
1453 #endif
1454         ret = serial8250_register_8250_port(&up);
1455         if (ret < 0) {
1456                 dev_err(&pdev->dev, "unable to register 8250 port\n");
1457                 goto err;
1458         }
1459         priv->line = ret;
1460         pm_runtime_mark_last_busy(&pdev->dev);
1461         pm_runtime_put_autosuspend(&pdev->dev);
1462         return 0;
1463 err:
1464         pm_runtime_dont_use_autosuspend(&pdev->dev);
1465         pm_runtime_put_sync(&pdev->dev);
1466         flush_work(&priv->qos_work);
1467         pm_runtime_disable(&pdev->dev);
1468         cpu_latency_qos_remove_request(&priv->pm_qos_request);
1469         return ret;
1470 }
1471
1472 static int omap8250_remove(struct platform_device *pdev)
1473 {
1474         struct omap8250_priv *priv = platform_get_drvdata(pdev);
1475         int err;
1476
1477         err = pm_runtime_resume_and_get(&pdev->dev);
1478         if (err)
1479                 return err;
1480
1481         serial8250_unregister_port(priv->line);
1482         priv->line = -ENODEV;
1483         pm_runtime_dont_use_autosuspend(&pdev->dev);
1484         pm_runtime_put_sync(&pdev->dev);
1485         flush_work(&priv->qos_work);
1486         pm_runtime_disable(&pdev->dev);
1487         cpu_latency_qos_remove_request(&priv->pm_qos_request);
1488         device_init_wakeup(&pdev->dev, false);
1489         return 0;
1490 }
1491
1492 static int omap8250_prepare(struct device *dev)
1493 {
1494         struct omap8250_priv *priv = dev_get_drvdata(dev);
1495
1496         if (!priv)
1497                 return 0;
1498         priv->is_suspending = true;
1499         return 0;
1500 }
1501
1502 static void omap8250_complete(struct device *dev)
1503 {
1504         struct omap8250_priv *priv = dev_get_drvdata(dev);
1505
1506         if (!priv)
1507                 return;
1508         priv->is_suspending = false;
1509 }
1510
1511 static int omap8250_suspend(struct device *dev)
1512 {
1513         struct omap8250_priv *priv = dev_get_drvdata(dev);
1514         struct uart_8250_port *up = serial8250_get_port(priv->line);
1515         int err = 0;
1516
1517         serial8250_suspend_port(priv->line);
1518
1519         err = pm_runtime_resume_and_get(dev);
1520         if (err)
1521                 return err;
1522         if (!device_may_wakeup(dev))
1523                 priv->wer = 0;
1524         serial_out(up, UART_OMAP_WER, priv->wer);
1525         if (uart_console(&up->port) && console_suspend_enabled)
1526                 err = pm_runtime_force_suspend(dev);
1527         flush_work(&priv->qos_work);
1528
1529         return err;
1530 }
1531
1532 static int omap8250_resume(struct device *dev)
1533 {
1534         struct omap8250_priv *priv = dev_get_drvdata(dev);
1535         struct uart_8250_port *up = serial8250_get_port(priv->line);
1536         int err;
1537
1538         if (uart_console(&up->port) && console_suspend_enabled) {
1539                 err = pm_runtime_force_resume(dev);
1540                 if (err)
1541                         return err;
1542         }
1543
1544         serial8250_resume_port(priv->line);
1545         /* Paired with pm_runtime_resume_and_get() in omap8250_suspend() */
1546         pm_runtime_mark_last_busy(dev);
1547         pm_runtime_put_autosuspend(dev);
1548
1549         return 0;
1550 }
1551
1552 static int omap8250_lost_context(struct uart_8250_port *up)
1553 {
1554         u32 val;
1555
1556         val = serial_in(up, UART_OMAP_SCR);
1557         /*
1558          * If we lose context, then SCR is set to its reset value of zero.
1559          * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1560          * among other bits, to never set the register back to zero again.
1561          */
1562         if (!val)
1563                 return 1;
1564         return 0;
1565 }
1566
1567 static void uart_write(struct omap8250_priv *priv, u32 reg, u32 val)
1568 {
1569         writel(val, priv->membase + (reg << OMAP_UART_REGSHIFT));
1570 }
1571
1572 /* TODO: in future, this should happen via API in drivers/reset/ */
1573 static int omap8250_soft_reset(struct device *dev)
1574 {
1575         struct omap8250_priv *priv = dev_get_drvdata(dev);
1576         int timeout = 100;
1577         int sysc;
1578         int syss;
1579
1580         /*
1581          * At least on omap4, unused uarts may not idle after reset without
1582          * a basic scr dma configuration even with no dma in use. The
1583          * module clkctrl status bits will be 1 instead of 3 blocking idle
1584          * for the whole clockdomain. The softreset below will clear scr,
1585          * and we restore it on resume so this is safe to do on all SoCs
1586          * needing omap8250_soft_reset() quirk. Do it in two writes as
1587          * recommended in the comment for omap8250_update_scr().
1588          */
1589         uart_write(priv, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1590         uart_write(priv, UART_OMAP_SCR,
1591                    OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1592
1593         sysc = uart_read(priv, UART_OMAP_SYSC);
1594
1595         /* softreset the UART */
1596         sysc |= OMAP_UART_SYSC_SOFTRESET;
1597         uart_write(priv, UART_OMAP_SYSC, sysc);
1598
1599         /* By experiments, 1us enough for reset complete on AM335x */
1600         do {
1601                 udelay(1);
1602                 syss = uart_read(priv, UART_OMAP_SYSS);
1603         } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1604
1605         if (!timeout) {
1606                 dev_err(dev, "timed out waiting for reset done\n");
1607                 return -ETIMEDOUT;
1608         }
1609
1610         return 0;
1611 }
1612
1613 static int omap8250_runtime_suspend(struct device *dev)
1614 {
1615         struct omap8250_priv *priv = dev_get_drvdata(dev);
1616         struct uart_8250_port *up = NULL;
1617
1618         if (priv->line >= 0)
1619                 up = serial8250_get_port(priv->line);
1620
1621         if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1622                 int ret;
1623
1624                 ret = omap8250_soft_reset(dev);
1625                 if (ret)
1626                         return ret;
1627
1628                 if (up) {
1629                         /* Restore to UART mode after reset (for wakeup) */
1630                         omap8250_update_mdr1(up, priv);
1631                         /* Restore wakeup enable register */
1632                         serial_out(up, UART_OMAP_WER, priv->wer);
1633                 }
1634         }
1635
1636         if (up && up->dma && up->dma->rxchan)
1637                 omap_8250_rx_dma_flush(up);
1638
1639         priv->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1640         schedule_work(&priv->qos_work);
1641
1642         return 0;
1643 }
1644
1645 static int omap8250_runtime_resume(struct device *dev)
1646 {
1647         struct omap8250_priv *priv = dev_get_drvdata(dev);
1648         struct uart_8250_port *up = NULL;
1649
1650         if (priv->line >= 0)
1651                 up = serial8250_get_port(priv->line);
1652
1653         if (up && omap8250_lost_context(up))
1654                 omap8250_restore_regs(up);
1655
1656         if (up && up->dma && up->dma->rxchan && !(priv->habit & UART_HAS_EFR2))
1657                 omap_8250_rx_dma(up);
1658
1659         priv->latency = priv->calc_latency;
1660         schedule_work(&priv->qos_work);
1661         return 0;
1662 }
1663
1664 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1665 static int __init omap8250_console_fixup(void)
1666 {
1667         char *omap_str;
1668         char *options;
1669         u8 idx;
1670
1671         if (strstr(boot_command_line, "console=ttyS"))
1672                 /* user set a ttyS based name for the console */
1673                 return 0;
1674
1675         omap_str = strstr(boot_command_line, "console=ttyO");
1676         if (!omap_str)
1677                 /* user did not set ttyO based console, so we don't care */
1678                 return 0;
1679
1680         omap_str += 12;
1681         if ('0' <= *omap_str && *omap_str <= '9')
1682                 idx = *omap_str - '0';
1683         else
1684                 return 0;
1685
1686         omap_str++;
1687         if (omap_str[0] == ',') {
1688                 omap_str++;
1689                 options = omap_str;
1690         } else {
1691                 options = NULL;
1692         }
1693
1694         add_preferred_console("ttyS", idx, options);
1695         pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1696                idx, idx);
1697         pr_err("This ensures that you still see kernel messages. Please\n");
1698         pr_err("update your kernel commandline.\n");
1699         return 0;
1700 }
1701 console_initcall(omap8250_console_fixup);
1702 #endif
1703
1704 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1705         SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1706         RUNTIME_PM_OPS(omap8250_runtime_suspend,
1707                            omap8250_runtime_resume, NULL)
1708         .prepare        = pm_sleep_ptr(omap8250_prepare),
1709         .complete       = pm_sleep_ptr(omap8250_complete),
1710 };
1711
1712 static struct platform_driver omap8250_platform_driver = {
1713         .driver = {
1714                 .name           = "omap8250",
1715                 .pm             = pm_ptr(&omap8250_dev_pm_ops),
1716                 .of_match_table = omap8250_dt_ids,
1717         },
1718         .probe                  = omap8250_probe,
1719         .remove                 = omap8250_remove,
1720 };
1721 module_platform_driver(omap8250_platform_driver);
1722
1723 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1724 MODULE_DESCRIPTION("OMAP 8250 Driver");
1725 MODULE_LICENSE("GPL v2");