2 * Synopsys DesignWare 8250 driver.
4 * Copyright 2011 Picochip, Jamie Iles.
5 * Copyright 2013 Intel Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
13 * LCR is written whilst busy. If it is, then a busy detect interrupt is
14 * raised, the LCR needs to be rewritten and the uart status register read.
16 #include <linux/device.h>
17 #include <linux/init.h>
19 #include <linux/module.h>
20 #include <linux/serial_8250.h>
21 #include <linux/serial_core.h>
22 #include <linux/serial_reg.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
27 #include <linux/slab.h>
28 #include <linux/acpi.h>
29 #include <linux/clk.h>
30 #include <linux/pm_runtime.h>
34 /* Offsets for the DesignWare specific registers */
35 #define DW_UART_USR 0x1f /* UART Status Register */
36 #define DW_UART_CPR 0xf4 /* Component Parameter Register */
37 #define DW_UART_UCV 0xf8 /* UART Component Version */
39 /* Component Parameter Register bits */
40 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0)
41 #define DW_UART_CPR_AFCE_MODE (1 << 4)
42 #define DW_UART_CPR_THRE_MODE (1 << 5)
43 #define DW_UART_CPR_SIR_MODE (1 << 6)
44 #define DW_UART_CPR_SIR_LP_MODE (1 << 7)
45 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8)
46 #define DW_UART_CPR_FIFO_ACCESS (1 << 9)
47 #define DW_UART_CPR_FIFO_STAT (1 << 10)
48 #define DW_UART_CPR_SHADOW (1 << 11)
49 #define DW_UART_CPR_ENCODED_PARMS (1 << 12)
50 #define DW_UART_CPR_DMA_EXTRA (1 << 13)
51 #define DW_UART_CPR_FIFO_MODE (0xff << 16)
52 /* Helper for fifo size calculation */
53 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16)
62 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
64 struct dw8250_data *d = p->private_data;
66 /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */
67 if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) {
68 value |= UART_MSR_CTS;
69 value &= ~UART_MSR_DCTS;
75 static void dw8250_force_idle(struct uart_port *p)
77 serial8250_clear_and_reinit_fifos(container_of
78 (p, struct uart_8250_port, port));
79 (void)p->serial_in(p, UART_RX);
82 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
84 struct dw8250_data *d = p->private_data;
86 if (offset == UART_MCR)
89 writeb(value, p->membase + (offset << p->regshift));
91 /* Make sure LCR write wasn't ignored */
92 if (offset == UART_LCR) {
95 unsigned int lcr = p->serial_in(p, UART_LCR);
96 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
99 writeb(value, p->membase + (UART_LCR << p->regshift));
101 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
105 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
107 unsigned int value = readb(p->membase + (offset << p->regshift));
109 return dw8250_modify_msr(p, offset, value);
112 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
114 struct dw8250_data *d = p->private_data;
116 if (offset == UART_MCR)
119 writel(value, p->membase + (offset << p->regshift));
121 /* Make sure LCR write wasn't ignored */
122 if (offset == UART_LCR) {
125 unsigned int lcr = p->serial_in(p, UART_LCR);
126 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
128 dw8250_force_idle(p);
129 writel(value, p->membase + (UART_LCR << p->regshift));
131 dev_err(p->dev, "Couldn't set LCR to %d\n", value);
135 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
137 unsigned int value = readl(p->membase + (offset << p->regshift));
139 return dw8250_modify_msr(p, offset, value);
142 static int dw8250_handle_irq(struct uart_port *p)
144 unsigned int iir = p->serial_in(p, UART_IIR);
146 if (serial8250_handle_irq(p, iir)) {
148 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
150 (void)p->serial_in(p, DW_UART_USR);
159 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
162 pm_runtime_get_sync(port->dev);
164 serial8250_do_pm(port, state, old);
167 pm_runtime_put_sync_suspend(port->dev);
170 static int dw8250_probe_of(struct uart_port *p)
172 struct device_node *np = p->dev->of_node;
175 if (!of_property_read_u32(np, "reg-io-width", &val)) {
180 p->iotype = UPIO_MEM32;
181 p->serial_in = dw8250_serial_in32;
182 p->serial_out = dw8250_serial_out32;
185 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val);
190 if (!of_property_read_u32(np, "reg-shift", &val))
193 /* clock got configured through clk api, all done */
197 /* try to find out clock frequency from DT as fallback */
198 if (of_property_read_u32(np, "clock-frequency", &val)) {
199 dev_err(p->dev, "clk or clock-frequency not defined\n");
208 static int dw8250_probe_acpi(struct uart_8250_port *up)
210 const struct acpi_device_id *id;
211 struct uart_port *p = &up->port;
213 id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
217 p->iotype = UPIO_MEM32;
218 p->serial_in = dw8250_serial_in32;
219 p->serial_out = dw8250_serial_out32;
223 p->uartclk = (unsigned int)id->driver_data;
225 up->dma = devm_kzalloc(p->dev, sizeof(*up->dma), GFP_KERNEL);
229 up->dma->rxconf.src_maxburst = p->fifosize / 4;
230 up->dma->txconf.dst_maxburst = p->fifosize / 4;
235 static inline int dw8250_probe_acpi(struct uart_8250_port *up)
239 #endif /* CONFIG_ACPI */
241 static void dw8250_setup_port(struct uart_8250_port *up)
243 struct uart_port *p = &up->port;
244 u32 reg = readl(p->membase + DW_UART_UCV);
247 * If the Component Version Register returns zero, we know that
248 * ADDITIONAL_FEATURES are not enabled. No need to go any further.
253 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n",
254 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff);
256 reg = readl(p->membase + DW_UART_CPR);
260 /* Select the type based on fifo */
261 if (reg & DW_UART_CPR_FIFO_MODE) {
262 p->type = PORT_16550A;
263 p->flags |= UPF_FIXED_TYPE;
264 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg);
265 up->tx_loadsz = p->fifosize;
266 up->capabilities = UART_CAP_FIFO;
269 if (reg & DW_UART_CPR_AFCE_MODE)
270 up->capabilities |= UART_CAP_AFE;
273 static int dw8250_probe(struct platform_device *pdev)
275 struct uart_8250_port uart = {};
276 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
277 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
278 struct dw8250_data *data;
282 dev_err(&pdev->dev, "no registers/irq defined\n");
286 spin_lock_init(&uart.port.lock);
287 uart.port.mapbase = regs->start;
288 uart.port.irq = irq->start;
289 uart.port.handle_irq = dw8250_handle_irq;
290 uart.port.pm = dw8250_do_pm;
291 uart.port.type = PORT_8250;
292 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT;
293 uart.port.dev = &pdev->dev;
295 uart.port.membase = devm_ioremap(&pdev->dev, regs->start,
296 resource_size(regs));
297 if (!uart.port.membase)
300 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
304 data->clk = devm_clk_get(&pdev->dev, NULL);
305 if (!IS_ERR(data->clk)) {
306 clk_prepare_enable(data->clk);
307 uart.port.uartclk = clk_get_rate(data->clk);
310 uart.port.iotype = UPIO_MEM;
311 uart.port.serial_in = dw8250_serial_in;
312 uart.port.serial_out = dw8250_serial_out;
313 uart.port.private_data = data;
315 dw8250_setup_port(&uart);
317 if (pdev->dev.of_node) {
318 err = dw8250_probe_of(&uart.port);
321 } else if (ACPI_HANDLE(&pdev->dev)) {
322 err = dw8250_probe_acpi(&uart);
329 data->line = serial8250_register_8250_port(&uart);
333 platform_set_drvdata(pdev, data);
335 pm_runtime_set_active(&pdev->dev);
336 pm_runtime_enable(&pdev->dev);
341 static int dw8250_remove(struct platform_device *pdev)
343 struct dw8250_data *data = platform_get_drvdata(pdev);
345 pm_runtime_get_sync(&pdev->dev);
347 serial8250_unregister_port(data->line);
349 if (!IS_ERR(data->clk))
350 clk_disable_unprepare(data->clk);
352 pm_runtime_disable(&pdev->dev);
353 pm_runtime_put_noidle(&pdev->dev);
359 static int dw8250_suspend(struct device *dev)
361 struct dw8250_data *data = dev_get_drvdata(dev);
363 serial8250_suspend_port(data->line);
368 static int dw8250_resume(struct device *dev)
370 struct dw8250_data *data = dev_get_drvdata(dev);
372 serial8250_resume_port(data->line);
376 #endif /* CONFIG_PM */
378 #ifdef CONFIG_PM_RUNTIME
379 static int dw8250_runtime_suspend(struct device *dev)
381 struct dw8250_data *data = dev_get_drvdata(dev);
383 if (!IS_ERR(data->clk))
384 clk_disable_unprepare(data->clk);
389 static int dw8250_runtime_resume(struct device *dev)
391 struct dw8250_data *data = dev_get_drvdata(dev);
393 if (!IS_ERR(data->clk))
394 clk_prepare_enable(data->clk);
400 static const struct dev_pm_ops dw8250_pm_ops = {
401 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
402 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
405 static const struct of_device_id dw8250_of_match[] = {
406 { .compatible = "snps,dw-apb-uart" },
409 MODULE_DEVICE_TABLE(of, dw8250_of_match);
411 static const struct acpi_device_id dw8250_acpi_match[] = {
419 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
421 static struct platform_driver dw8250_platform_driver = {
423 .name = "dw-apb-uart",
424 .owner = THIS_MODULE,
425 .pm = &dw8250_pm_ops,
426 .of_match_table = dw8250_of_match,
427 .acpi_match_table = ACPI_PTR(dw8250_acpi_match),
429 .probe = dw8250_probe,
430 .remove = dw8250_remove,
433 module_platform_driver(dw8250_platform_driver);
435 MODULE_AUTHOR("Jamie Iles");
436 MODULE_LICENSE("GPL");
437 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");