4 * Driver for the Motorola Triple Speed Ethernet Controller
6 * This software may be used and distributed according to the
7 * terms of the GNU Public License, Version 2, incorporated
10 * Copyright 2004 Freescale Semiconductor.
11 * (C) Copyright 2003, Motorola, Inc.
12 * maintained by Xianghua Xiao (x.xiao@motorola.com)
23 #ifndef CFG_TSEC1_OFFSET
24 #define CFG_TSEC1_OFFSET (0x24000)
27 #define TSEC_SIZE 0x01000
29 /* FIXME: Should these be pushed back to 83xx and 85xx config files? */
30 #if defined(CONFIG_MPC85xx)
31 #define TSEC_BASE_ADDR (CFG_IMMR + CFG_TSEC1_OFFSET)
32 #elif defined(CONFIG_MPC83XX)
33 #define TSEC_BASE_ADDR (CFG_IMMRBAR + CFG_TSEC1_OFFSET)
37 #define MAC_ADDR_LEN 6
39 /* #define TSEC_TIMEOUT 1000000 */
40 #define TSEC_TIMEOUT 1000
41 #define TOUT_LOOP 1000000
43 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* in ms */
45 /* MAC register bits */
46 #define MACCFG1_SOFT_RESET 0x80000000
47 #define MACCFG1_RESET_RX_MC 0x00080000
48 #define MACCFG1_RESET_TX_MC 0x00040000
49 #define MACCFG1_RESET_RX_FUN 0x00020000
50 #define MACCFG1_RESET_TX_FUN 0x00010000
51 #define MACCFG1_LOOPBACK 0x00000100
52 #define MACCFG1_RX_FLOW 0x00000020
53 #define MACCFG1_TX_FLOW 0x00000010
54 #define MACCFG1_SYNCD_RX_EN 0x00000008
55 #define MACCFG1_RX_EN 0x00000004
56 #define MACCFG1_SYNCD_TX_EN 0x00000002
57 #define MACCFG1_TX_EN 0x00000001
59 #define MACCFG2_INIT_SETTINGS 0x00007205
60 #define MACCFG2_FULL_DUPLEX 0x00000001
61 #define MACCFG2_IF 0x00000300
62 #define MACCFG2_GMII 0x00000200
63 #define MACCFG2_MII 0x00000100
65 #define ECNTRL_INIT_SETTINGS 0x00001000
66 #define ECNTRL_TBI_MODE 0x00000020
67 #define ECNTRL_R100 0x00000008
72 #define TBIPA_VALUE 0x1f
73 #define MIIMCFG_INIT_VALUE 0x00000003
74 #define MIIMCFG_RESET 0x80000000
76 #define MIIMIND_BUSY 0x00000001
77 #define MIIMIND_NOTVALID 0x00000004
79 #define MIIM_CONTROL 0x00
80 #define MIIM_CONTROL_RESET 0x00009140
81 #define MIIM_CONTROL_INIT 0x00001140
82 #define MIIM_CONTROL_RESTART 0x00001340
83 #define MIIM_ANEN 0x00001000
86 #define MIIM_CR_RST 0x00008000
87 #define MIIM_CR_INIT 0x00001000
89 #define MIIM_STATUS 0x1
90 #define MIIM_STATUS_AN_DONE 0x00000020
91 #define MIIM_STATUS_LINK 0x0004
92 #define PHY_BMSR_AUTN_ABLE 0x0008
93 #define PHY_BMSR_AUTN_COMP 0x0020
95 #define MIIM_PHYIR1 0x2
96 #define MIIM_PHYIR2 0x3
99 #define MIIM_ANAR_INIT 0x1e1
101 #define MIIM_TBI_ANLPBPA 0x5
102 #define MIIM_TBI_ANLPBPA_HALF 0x00000040
103 #define MIIM_TBI_ANLPBPA_FULL 0x00000020
105 #define MIIM_TBI_ANEX 0x6
106 #define MIIM_TBI_ANEX_NP 0x00000004
107 #define MIIM_TBI_ANEX_PRX 0x00000002
109 #define MIIM_GBIT_CONTROL 0x9
110 #define MIIM_GBIT_CONTROL_INIT 0xe00
112 /* Cicada Auxiliary Control/Status Register */
113 #define MIIM_CIS8201_AUX_CONSTAT 0x1c
114 #define MIIM_CIS8201_AUXCONSTAT_INIT 0x0004
115 #define MIIM_CIS8201_AUXCONSTAT_DUPLEX 0x0020
116 #define MIIM_CIS8201_AUXCONSTAT_SPEED 0x0018
117 #define MIIM_CIS8201_AUXCONSTAT_GBIT 0x0010
118 #define MIIM_CIS8201_AUXCONSTAT_100 0x0008
120 /* Cicada Extended Control Register 1 */
121 #define MIIM_CIS8201_EXT_CON1 0x17
122 #define MIIM_CIS8201_EXTCON1_INIT 0x0000
124 /* Cicada 8204 Extended PHY Control Register 1 */
125 #define MIIM_CIS8204_EPHY_CON 0x17
126 #define MIIM_CIS8204_EPHYCON_INIT 0x0006
127 #define MIIM_CIS8204_EPHYCON_RGMII 0x1100
129 /* Cicada 8204 Serial LED Control Register */
130 #define MIIM_CIS8204_SLED_CON 0x1b
131 #define MIIM_CIS8204_SLEDCON_INIT 0x1115
133 #define MIIM_GBIT_CON 0x09
134 #define MIIM_GBIT_CON_ADVERT 0x0e00
136 /* 88E1011 PHY Status Register */
137 #define MIIM_88E1011_PHY_STATUS 0x11
138 #define MIIM_88E1011_PHYSTAT_SPEED 0xc000
139 #define MIIM_88E1011_PHYSTAT_GBIT 0x8000
140 #define MIIM_88E1011_PHYSTAT_100 0x4000
141 #define MIIM_88E1011_PHYSTAT_DUPLEX 0x2000
142 #define MIIM_88E1011_PHYSTAT_SPDDONE 0x0800
143 #define MIIM_88E1011_PHYSTAT_LINK 0x0400
145 #define MIIM_88E1011_PHY_SCR 0x10
146 #define MIIM_88E1011_PHY_MDI_X_AUTO 0x0060
148 /* 88E1111 PHY LED Control Register */
149 #define MIIM_88E1111_PHY_LED_CONTROL 24
150 #define MIIM_88E1111_PHY_LED_DIRECT 0x4100
151 #define MIIM_88E1111_PHY_LED_COMBINE 0x411C
153 /* 88E1145 Extended PHY Specific Control Register */
154 #define MIIM_88E1145_PHY_EXT_CR 20
155 #define MIIM_M88E1145_RGMII_RX_DELAY 0x0080
156 #define MIIM_M88E1145_RGMII_TX_DELAY 0x0002
158 #define MIIM_88E1145_PHY_PAGE 29
159 #define MIIM_88E1145_PHY_CAL_OV 30
162 /* DM9161 Control register values */
163 #define MIIM_DM9161_CR_STOP 0x0400
164 #define MIIM_DM9161_CR_RSTAN 0x1200
166 #define MIIM_DM9161_SCR 0x10
167 #define MIIM_DM9161_SCR_INIT 0x0610
169 /* DM9161 Specified Configuration and Status Register */
170 #define MIIM_DM9161_SCSR 0x11
171 #define MIIM_DM9161_SCSR_100F 0x8000
172 #define MIIM_DM9161_SCSR_100H 0x4000
173 #define MIIM_DM9161_SCSR_10F 0x2000
174 #define MIIM_DM9161_SCSR_10H 0x1000
176 /* DM9161 10BT Configuration/Status */
177 #define MIIM_DM9161_10BTCSR 0x12
178 #define MIIM_DM9161_10BTCSR_INIT 0x7800
180 /* LXT971 Status 2 registers */
181 #define MIIM_LXT971_SR2 0x11 /* Status Register 2 */
182 #define MIIM_LXT971_SR2_SPEED_MASK 0x4200
183 #define MIIM_LXT971_SR2_10HDX 0x0000 /* 10 Mbit half duplex selected */
184 #define MIIM_LXT971_SR2_10FDX 0x0200 /* 10 Mbit full duplex selected */
185 #define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
186 #define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
188 /* DP83865 Control register values */
189 #define MIIM_DP83865_CR_INIT 0x9200
191 /* DP83865 Link and Auto-Neg Status Register */
192 #define MIIM_DP83865_LANR 0x11
193 #define MIIM_DP83865_SPD_MASK 0x0018
194 #define MIIM_DP83865_SPD_1000 0x0010
195 #define MIIM_DP83865_SPD_100 0x0008
196 #define MIIM_DP83865_DPX_FULL 0x0002
198 #define MIIM_READ_COMMAND 0x00000001
200 #define MRBLR_INIT_SETTINGS PKTSIZE_ALIGN
202 #define MINFLR_INIT_SETTINGS 0x00000040
204 #define DMACTRL_INIT_SETTINGS 0x000000c3
205 #define DMACTRL_GRS 0x00000010
206 #define DMACTRL_GTS 0x00000008
208 #define TSTAT_CLEAR_THALT 0x80000000
209 #define RSTAT_CLEAR_RHALT 0x00800000
212 #define IEVENT_INIT_CLEAR 0xffffffff
213 #define IEVENT_BABR 0x80000000
214 #define IEVENT_RXC 0x40000000
215 #define IEVENT_BSY 0x20000000
216 #define IEVENT_EBERR 0x10000000
217 #define IEVENT_MSRO 0x04000000
218 #define IEVENT_GTSC 0x02000000
219 #define IEVENT_BABT 0x01000000
220 #define IEVENT_TXC 0x00800000
221 #define IEVENT_TXE 0x00400000
222 #define IEVENT_TXB 0x00200000
223 #define IEVENT_TXF 0x00100000
224 #define IEVENT_IE 0x00080000
225 #define IEVENT_LC 0x00040000
226 #define IEVENT_CRL 0x00020000
227 #define IEVENT_XFUN 0x00010000
228 #define IEVENT_RXB0 0x00008000
229 #define IEVENT_GRSC 0x00000100
230 #define IEVENT_RXF0 0x00000080
232 #define IMASK_INIT_CLEAR 0x00000000
233 #define IMASK_TXEEN 0x00400000
234 #define IMASK_TXBEN 0x00200000
235 #define IMASK_TXFEN 0x00100000
236 #define IMASK_RXFEN0 0x00000080
239 /* Default Attribute fields */
240 #define ATTR_INIT_SETTINGS 0x000000c0
241 #define ATTRELI_INIT_SETTINGS 0x00000000
244 /* TxBD status field bits */
245 #define TXBD_READY 0x8000
246 #define TXBD_PADCRC 0x4000
247 #define TXBD_WRAP 0x2000
248 #define TXBD_INTERRUPT 0x1000
249 #define TXBD_LAST 0x0800
250 #define TXBD_CRC 0x0400
251 #define TXBD_DEF 0x0200
252 #define TXBD_HUGEFRAME 0x0080
253 #define TXBD_LATECOLLISION 0x0080
254 #define TXBD_RETRYLIMIT 0x0040
255 #define TXBD_RETRYCOUNTMASK 0x003c
256 #define TXBD_UNDERRUN 0x0002
257 #define TXBD_STATS 0x03ff
259 /* RxBD status field bits */
260 #define RXBD_EMPTY 0x8000
261 #define RXBD_RO1 0x4000
262 #define RXBD_WRAP 0x2000
263 #define RXBD_INTERRUPT 0x1000
264 #define RXBD_LAST 0x0800
265 #define RXBD_FIRST 0x0400
266 #define RXBD_MISS 0x0100
267 #define RXBD_BROADCAST 0x0080
268 #define RXBD_MULTICAST 0x0040
269 #define RXBD_LARGE 0x0020
270 #define RXBD_NONOCTET 0x0010
271 #define RXBD_SHORT 0x0008
272 #define RXBD_CRCERR 0x0004
273 #define RXBD_OVERRUN 0x0002
274 #define RXBD_TRUNCATED 0x0001
275 #define RXBD_STATS 0x003f
279 ushort status; /* Status Fields */
280 ushort length; /* Buffer length */
281 uint bufPtr; /* Buffer Pointer */
286 ushort status; /* Status Fields */
287 ushort length; /* Buffer Length */
288 uint bufPtr; /* Buffer Pointer */
291 typedef struct rmon_mib
293 /* Transmit and Receive Counters */
294 uint tr64; /* Transmit and Receive 64-byte Frame Counter */
295 uint tr127; /* Transmit and Receive 65-127 byte Frame Counter */
296 uint tr255; /* Transmit and Receive 128-255 byte Frame Counter */
297 uint tr511; /* Transmit and Receive 256-511 byte Frame Counter */
298 uint tr1k; /* Transmit and Receive 512-1023 byte Frame Counter */
299 uint trmax; /* Transmit and Receive 1024-1518 byte Frame Counter */
300 uint trmgv; /* Transmit and Receive 1519-1522 byte Good VLAN Frame */
301 /* Receive Counters */
302 uint rbyt; /* Receive Byte Counter */
303 uint rpkt; /* Receive Packet Counter */
304 uint rfcs; /* Receive FCS Error Counter */
305 uint rmca; /* Receive Multicast Packet (Counter) */
306 uint rbca; /* Receive Broadcast Packet */
307 uint rxcf; /* Receive Control Frame Packet */
308 uint rxpf; /* Receive Pause Frame Packet */
309 uint rxuo; /* Receive Unknown OP Code */
310 uint raln; /* Receive Alignment Error */
311 uint rflr; /* Receive Frame Length Error */
312 uint rcde; /* Receive Code Error */
313 uint rcse; /* Receive Carrier Sense Error */
314 uint rund; /* Receive Undersize Packet */
315 uint rovr; /* Receive Oversize Packet */
316 uint rfrg; /* Receive Fragments */
317 uint rjbr; /* Receive Jabber */
318 uint rdrp; /* Receive Drop */
319 /* Transmit Counters */
320 uint tbyt; /* Transmit Byte Counter */
321 uint tpkt; /* Transmit Packet */
322 uint tmca; /* Transmit Multicast Packet */
323 uint tbca; /* Transmit Broadcast Packet */
324 uint txpf; /* Transmit Pause Control Frame */
325 uint tdfr; /* Transmit Deferral Packet */
326 uint tedf; /* Transmit Excessive Deferral Packet */
327 uint tscl; /* Transmit Single Collision Packet */
329 uint tmcl; /* Transmit Multiple Collision Packet */
330 uint tlcl; /* Transmit Late Collision Packet */
331 uint txcl; /* Transmit Excessive Collision Packet */
332 uint tncl; /* Transmit Total Collision */
336 uint tdrp; /* Transmit Drop Frame */
337 uint tjbr; /* Transmit Jabber Frame */
338 uint tfcs; /* Transmit FCS Error */
339 uint txcf; /* Transmit Control Frame */
340 uint tovr; /* Transmit Oversize Frame */
341 uint tund; /* Transmit Undersize Frame */
342 uint tfrg; /* Transmit Fragments Frame */
343 /* General Registers */
344 uint car1; /* Carry Register One */
345 uint car2; /* Carry Register Two */
346 uint cam1; /* Carry Register One Mask */
347 uint cam2; /* Carry Register Two Mask */
350 typedef struct tsec_hash_regs
352 uint iaddr0; /* Individual Address Register 0 */
353 uint iaddr1; /* Individual Address Register 1 */
354 uint iaddr2; /* Individual Address Register 2 */
355 uint iaddr3; /* Individual Address Register 3 */
356 uint iaddr4; /* Individual Address Register 4 */
357 uint iaddr5; /* Individual Address Register 5 */
358 uint iaddr6; /* Individual Address Register 6 */
359 uint iaddr7; /* Individual Address Register 7 */
361 uint gaddr0; /* Group Address Register 0 */
362 uint gaddr1; /* Group Address Register 1 */
363 uint gaddr2; /* Group Address Register 2 */
364 uint gaddr3; /* Group Address Register 3 */
365 uint gaddr4; /* Group Address Register 4 */
366 uint gaddr5; /* Group Address Register 5 */
367 uint gaddr6; /* Group Address Register 6 */
368 uint gaddr7; /* Group Address Register 7 */
374 /* General Control and Status Registers (0x2_n000) */
377 uint ievent; /* Interrupt Event */
378 uint imask; /* Interrupt Mask */
379 uint edis; /* Error Disabled */
381 uint ecntrl; /* Ethernet Control */
382 uint minflr; /* Minimum Frame Length */
383 uint ptv; /* Pause Time Value */
384 uint dmactrl; /* DMA Control */
385 uint tbipa; /* TBI PHY Address */
390 /* Transmit Control and Status Registers (0x2_n100) */
391 uint tctrl; /* Transmit Control */
392 uint tstat; /* Transmit Status */
394 uint tbdlen; /* Tx BD Data Length */
396 uint ctbptr; /* Current TxBD Pointer */
398 uint tbptr; /* TxBD Pointer */
402 uint tbase; /* TxBD Base Address */
404 uint ostbd; /* Out of Sequence TxBD */
405 uint ostbdp; /* Out of Sequence Tx Data Buffer Pointer */
408 /* Receive Control and Status Registers (0x2_n300) */
409 uint rctrl; /* Receive Control */
410 uint rstat; /* Receive Status */
412 uint rbdlen; /* RxBD Data Length */
415 uint crbptr; /* Current Receive Buffer Pointer */
417 uint mrblr; /* Maximum Receive Buffer Length */
419 uint rbptr; /* RxBD Pointer */
423 uint rbase; /* RxBD Base Address */
426 /* MAC Registers (0x2_n500) */
427 uint maccfg1; /* MAC Configuration #1 */
428 uint maccfg2; /* MAC Configuration #2 */
429 uint ipgifg; /* Inter Packet Gap/Inter Frame Gap */
430 uint hafdup; /* Half-duplex */
431 uint maxfrm; /* Maximum Frame */
437 uint miimcfg; /* MII Management: Configuration */
438 uint miimcom; /* MII Management: Command */
439 uint miimadd; /* MII Management: Address */
440 uint miimcon; /* MII Management: Control */
441 uint miimstat; /* MII Management: Status */
442 uint miimind; /* MII Management: Indicators */
446 uint ifstat; /* Interface Status */
447 uint macstnaddr1; /* Station Address, part 1 */
448 uint macstnaddr2; /* Station Address, part 2 */
454 /* RMON MIB Registers (0x2_n680-0x2_n73c) */
458 /* Hash Function Registers (0x2_n800) */
463 /* Pattern Registers (0x2_nb00) */
465 uint attr; /* Default Attribute Register */
466 uint attreli; /* Default Attribute Extract Length and Index */
468 /* TSEC Future Expansion Space (0x2_nc00-0x2_nffc) */
472 #define TSEC_GIGABIT (1)
474 /* This flag currently only has
475 * meaning if we're using the eTSEC */
476 #define TSEC_REDUCED (1 << 1)
478 struct tsec_private {
479 volatile tsec_t *regs;
480 volatile tsec_t *phyregs;
481 struct phy_info *phyinfo;
491 * struct phy_cmd: A command for reading or writing a PHY register
493 * mii_reg: The register to read or write
495 * mii_data: For writes, the value to put in the register.
496 * A value of -1 indicates this is a read.
498 * funct: A function pointer which is invoked for each command.
499 * For reads, this function will be passed the value read
500 * from the PHY, and process it.
501 * For writes, the result of this function will be written
502 * to the PHY register
507 uint (*funct) (uint mii_reg, struct tsec_private* priv);
510 /* struct phy_info: a structure which defines attributes for a PHY
512 * id will contain a number which represents the PHY. During
513 * startup, the driver will poll the PHY to find out what its
514 * UID--as defined by registers 2 and 3--is. The 32-bit result
515 * gotten from the PHY will be shifted right by "shift" bits to
516 * discard any bits which may change based on revision numbers
517 * unimportant to functionality
519 * The struct phy_cmd entries represent pointers to an arrays of
520 * commands which tell the driver what to do to the PHY.
526 /* Called to configure the PHY, and modify the controller
527 * based on the results */
528 struct phy_cmd *config;
530 /* Called when starting up the controller */
531 struct phy_cmd *startup;
533 /* Called when bringing down the controller */
534 struct phy_cmd *shutdown;
537 #endif /* __TSEC_H */