Merge branch 'master' of http://www.denx.de/git/u-boot
[platform/kernel/u-boot.git] / drivers / tsec.c
1 /*
2  * Freescale Three Speed Ethernet Controller driver
3  *
4  * This software may be used and distributed according to the
5  * terms of the GNU Public License, Version 2, incorporated
6  * herein by reference.
7  *
8  * Copyright 2004 Freescale Semiconductor.
9  * (C) Copyright 2003, Motorola, Inc.
10  * author Andy Fleming
11  *
12  */
13
14 #include <config.h>
15 #include <mpc85xx.h>
16 #include <mpc86xx.h>
17 #include <common.h>
18 #include <malloc.h>
19 #include <net.h>
20 #include <command.h>
21
22 #if defined(CONFIG_TSEC_ENET)
23 #include "tsec.h"
24 #include "miiphy.h"
25
26 DECLARE_GLOBAL_DATA_PTR;
27
28 #define TX_BUF_CNT              2
29
30 static uint rxIdx;              /* index of the current RX buffer */
31 static uint txIdx;              /* index of the current TX buffer */
32
33 typedef volatile struct rtxbd {
34         txbd8_t txbd[TX_BUF_CNT];
35         rxbd8_t rxbd[PKTBUFSRX];
36 } RTXBD;
37
38 struct tsec_info_struct {
39         unsigned int phyaddr;
40         u32 flags;
41         unsigned int phyregidx;
42 };
43
44 /* The tsec_info structure contains 3 values which the
45  * driver uses to determine how to operate a given ethernet
46  * device. The information needed is:
47  *  phyaddr - The address of the PHY which is attached to
48  *      the given device.
49  *
50  *  flags - This variable indicates whether the device
51  *      supports gigabit speed ethernet, and whether it should be
52  *      in reduced mode.
53  *
54  *  phyregidx - This variable specifies which ethernet device
55  *      controls the MII Management registers which are connected
56  *      to the PHY.  For now, only TSEC1 (index 0) has
57  *      access to the PHYs, so all of the entries have "0".
58  *
59  * The values specified in the table are taken from the board's
60  * config file in include/configs/.  When implementing a new
61  * board with ethernet capability, it is necessary to define:
62  *   TSECn_PHY_ADDR
63  *   TSECn_PHYIDX
64  *
65  * for n = 1,2,3, etc.  And for FEC:
66  *   FEC_PHY_ADDR
67  *   FEC_PHYIDX
68  */
69 static struct tsec_info_struct tsec_info[] = {
70 #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
71         {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
72 #elif defined(CONFIG_MPC86XX_TSEC1)
73         {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
74 #else
75         {0, 0, 0},
76 #endif
77 #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
78         {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
79 #elif defined(CONFIG_MPC86XX_TSEC2)
80         {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
81 #else
82         {0, 0, 0},
83 #endif
84 #ifdef CONFIG_MPC85XX_FEC
85         {FEC_PHY_ADDR, 0, FEC_PHYIDX},
86 #else
87 #if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
88         {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
89 #else
90         {0, 0, 0},
91 #endif
92 #if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
93         {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
94 #else
95         {0, 0, 0},
96 #endif
97 #endif
98 };
99
100 #define MAXCONTROLLERS  (4)
101
102 static int relocated = 0;
103
104 static struct tsec_private *privlist[MAXCONTROLLERS];
105
106 #ifdef __GNUC__
107 static RTXBD rtx __attribute__ ((aligned(8)));
108 #else
109 #error "rtx must be 64-bit aligned"
110 #endif
111
112 static int tsec_send(struct eth_device *dev,
113                      volatile void *packet, int length);
114 static int tsec_recv(struct eth_device *dev);
115 static int tsec_init(struct eth_device *dev, bd_t * bd);
116 static void tsec_halt(struct eth_device *dev);
117 static void init_registers(volatile tsec_t * regs);
118 static void startup_tsec(struct eth_device *dev);
119 static int init_phy(struct eth_device *dev);
120 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
121 uint read_phy_reg(struct tsec_private *priv, uint regnum);
122 struct phy_info *get_phy_info(struct eth_device *dev);
123 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
124 static void adjust_link(struct eth_device *dev);
125 static void relocate_cmds(void);
126 static int tsec_miiphy_write(char *devname, unsigned char addr,
127                              unsigned char reg, unsigned short value);
128 static int tsec_miiphy_read(char *devname, unsigned char addr,
129                             unsigned char reg, unsigned short *value);
130
131 /* Initialize device structure. Returns success if PHY
132  * initialization succeeded (i.e. if it recognizes the PHY)
133  */
134 int tsec_initialize(bd_t * bis, int index, char *devname)
135 {
136         struct eth_device *dev;
137         int i;
138         struct tsec_private *priv;
139
140         dev = (struct eth_device *)malloc(sizeof *dev);
141
142         if (NULL == dev)
143                 return 0;
144
145         memset(dev, 0, sizeof *dev);
146
147         priv = (struct tsec_private *)malloc(sizeof(*priv));
148
149         if (NULL == priv)
150                 return 0;
151
152         privlist[index] = priv;
153         priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
154         priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
155                                             tsec_info[index].phyregidx *
156                                             TSEC_SIZE);
157
158         priv->phyaddr = tsec_info[index].phyaddr;
159         priv->flags = tsec_info[index].flags;
160
161         sprintf(dev->name, devname);
162         dev->iobase = 0;
163         dev->priv = priv;
164         dev->init = tsec_init;
165         dev->halt = tsec_halt;
166         dev->send = tsec_send;
167         dev->recv = tsec_recv;
168
169         /* Tell u-boot to get the addr from the env */
170         for (i = 0; i < 6; i++)
171                 dev->enetaddr[i] = 0;
172
173         eth_register(dev);
174
175         /* Reset the MAC */
176         priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
177         priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
178
179 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
180         && !defined(BITBANGMII)
181         miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
182 #endif
183
184         /* Try to initialize PHY here, and return */
185         return init_phy(dev);
186 }
187
188 /* Initializes data structures and registers for the controller,
189  * and brings the interface up.  Returns the link status, meaning
190  * that it returns success if the link is up, failure otherwise.
191  * This allows u-boot to find the first active controller.
192  */
193 int tsec_init(struct eth_device *dev, bd_t * bd)
194 {
195         uint tempval;
196         char tmpbuf[MAC_ADDR_LEN];
197         int i;
198         struct tsec_private *priv = (struct tsec_private *)dev->priv;
199         volatile tsec_t *regs = priv->regs;
200
201         /* Make sure the controller is stopped */
202         tsec_halt(dev);
203
204         /* Init MACCFG2.  Defaults to GMII */
205         regs->maccfg2 = MACCFG2_INIT_SETTINGS;
206
207         /* Init ECNTRL */
208         regs->ecntrl = ECNTRL_INIT_SETTINGS;
209
210         /* Copy the station address into the address registers.
211          * Backwards, because little endian MACS are dumb */
212         for (i = 0; i < MAC_ADDR_LEN; i++) {
213                 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
214         }
215         regs->macstnaddr1 = *((uint *) (tmpbuf));
216
217         tempval = *((uint *) (tmpbuf + 4));
218
219         regs->macstnaddr2 = tempval;
220
221         /* reset the indices to zero */
222         rxIdx = 0;
223         txIdx = 0;
224
225         /* Clear out (for the most part) the other registers */
226         init_registers(regs);
227
228         /* Ready the device for tx/rx */
229         startup_tsec(dev);
230
231         /* If there's no link, fail */
232         return priv->link;
233
234 }
235
236 /* Write value to the device's PHY through the registers
237  * specified in priv, modifying the register specified in regnum.
238  * It will wait for the write to be done (or for a timeout to
239  * expire) before exiting
240  */
241 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
242 {
243         volatile tsec_t *regbase = priv->phyregs;
244         uint phyid = priv->phyaddr;
245         int timeout = 1000000;
246
247         regbase->miimadd = (phyid << 8) | regnum;
248         regbase->miimcon = value;
249         asm("sync");
250
251         timeout = 1000000;
252         while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
253 }
254
255 /* Reads register regnum on the device's PHY through the
256  * registers specified in priv.  It lowers and raises the read
257  * command, and waits for the data to become valid (miimind
258  * notvalid bit cleared), and the bus to cease activity (miimind
259  * busy bit cleared), and then returns the value
260  */
261 uint read_phy_reg(struct tsec_private *priv, uint regnum)
262 {
263         uint value;
264         volatile tsec_t *regbase = priv->phyregs;
265         uint phyid = priv->phyaddr;
266
267         /* Put the address of the phy, and the register
268          * number into MIIMADD */
269         regbase->miimadd = (phyid << 8) | regnum;
270
271         /* Clear the command register, and wait */
272         regbase->miimcom = 0;
273         asm("sync");
274
275         /* Initiate a read command, and wait */
276         regbase->miimcom = MIIM_READ_COMMAND;
277         asm("sync");
278
279         /* Wait for the the indication that the read is done */
280         while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
281
282         /* Grab the value read from the PHY */
283         value = regbase->miimstat;
284
285         return value;
286 }
287
288 /* Discover which PHY is attached to the device, and configure it
289  * properly.  If the PHY is not recognized, then return 0
290  * (failure).  Otherwise, return 1
291  */
292 static int init_phy(struct eth_device *dev)
293 {
294         struct tsec_private *priv = (struct tsec_private *)dev->priv;
295         struct phy_info *curphy;
296         volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
297
298         /* Assign a Physical address to the TBI */
299         regs->tbipa = TBIPA_VALUE;
300         regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
301         regs->tbipa = TBIPA_VALUE;
302         asm("sync");
303
304         /* Reset MII (due to new addresses) */
305         priv->phyregs->miimcfg = MIIMCFG_RESET;
306         asm("sync");
307         priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
308         asm("sync");
309         while (priv->phyregs->miimind & MIIMIND_BUSY) ;
310
311         if (0 == relocated)
312                 relocate_cmds();
313
314         /* Get the cmd structure corresponding to the attached
315          * PHY */
316         curphy = get_phy_info(dev);
317
318         if (NULL == curphy) {
319                 printf("%s: No PHY found\n", dev->name);
320
321                 return 0;
322         }
323
324         priv->phyinfo = curphy;
325
326         phy_run_commands(priv, priv->phyinfo->config);
327
328         return 1;
329 }
330
331 /*
332  * Returns which value to write to the control register.
333  * For 10/100, the value is slightly different
334  */
335 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
336 {
337         if (priv->flags & TSEC_GIGABIT)
338                 return MIIM_CONTROL_INIT;
339         else
340                 return MIIM_CR_INIT;
341 }
342
343 /* Parse the status register for link, and then do
344  * auto-negotiation
345  */
346 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
347 {
348         /*
349          * Wait if PHY is capable of autonegotiation and autonegotiation
350          * is not complete.
351          */
352         mii_reg = read_phy_reg(priv, MIIM_STATUS);
353         if ((mii_reg & PHY_BMSR_AUTN_ABLE)
354             && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
355                 int i = 0;
356
357                 puts("Waiting for PHY auto negotiation to complete");
358                 while (!((mii_reg & PHY_BMSR_AUTN_COMP)
359                          && (mii_reg & MIIM_STATUS_LINK))) {
360                         /*
361                          * Timeout reached ?
362                          */
363                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
364                                 puts(" TIMEOUT !\n");
365                                 priv->link = 0;
366                                 return 0;
367                         }
368
369                         if ((i++ % 1000) == 0) {
370                                 putc('.');
371                         }
372                         udelay(1000);   /* 1 ms */
373                         mii_reg = read_phy_reg(priv, MIIM_STATUS);
374                 }
375                 puts(" done\n");
376                 priv->link = 1;
377                 udelay(500000); /* another 500 ms (results in faster booting) */
378         } else {
379                 priv->link = 1;
380         }
381
382         return 0;
383 }
384
385 /* Parse the 88E1011's status register for speed and duplex
386  * information
387  */
388 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
389 {
390         uint speed;
391
392         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
393
394         if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
395               (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
396                 int i = 0;
397
398                 puts("Waiting for PHY realtime link");
399                 while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
400                          (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
401                         /*
402                          * Timeout reached ?
403                          */
404                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
405                                 puts(" TIMEOUT !\n");
406                                 priv->link = 0;
407                                 break;
408                         }
409
410                         if ((i++ % 1000) == 0) {
411                                 putc('.');
412                         }
413                         udelay(1000);   /* 1 ms */
414                         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
415                 }
416                 puts(" done\n");
417                 udelay(500000); /* another 500 ms (results in faster booting) */
418         }
419
420         if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
421                 priv->duplexity = 1;
422         else
423                 priv->duplexity = 0;
424
425         speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
426
427         switch (speed) {
428         case MIIM_88E1011_PHYSTAT_GBIT:
429                 priv->speed = 1000;
430                 break;
431         case MIIM_88E1011_PHYSTAT_100:
432                 priv->speed = 100;
433                 break;
434         default:
435                 priv->speed = 10;
436         }
437
438         return 0;
439 }
440
441 /* Parse the cis8201's status register for speed and duplex
442  * information
443  */
444 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
445 {
446         uint speed;
447
448         if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
449                 priv->duplexity = 1;
450         else
451                 priv->duplexity = 0;
452
453         speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
454         switch (speed) {
455         case MIIM_CIS8201_AUXCONSTAT_GBIT:
456                 priv->speed = 1000;
457                 break;
458         case MIIM_CIS8201_AUXCONSTAT_100:
459                 priv->speed = 100;
460                 break;
461         default:
462                 priv->speed = 10;
463                 break;
464         }
465
466         return 0;
467 }
468
469 /* Parse the vsc8244's status register for speed and duplex
470  * information
471  */
472 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
473 {
474         uint speed;
475
476         if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
477                 priv->duplexity = 1;
478         else
479                 priv->duplexity = 0;
480
481         speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
482         switch (speed) {
483         case MIIM_VSC8244_AUXCONSTAT_GBIT:
484                 priv->speed = 1000;
485                 break;
486         case MIIM_VSC8244_AUXCONSTAT_100:
487                 priv->speed = 100;
488                 break;
489         default:
490                 priv->speed = 10;
491                 break;
492         }
493
494         return 0;
495 }
496
497 /* Parse the DM9161's status register for speed and duplex
498  * information
499  */
500 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
501 {
502         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
503                 priv->speed = 100;
504         else
505                 priv->speed = 10;
506
507         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
508                 priv->duplexity = 1;
509         else
510                 priv->duplexity = 0;
511
512         return 0;
513 }
514
515 /*
516  * Hack to write all 4 PHYs with the LED values
517  */
518 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
519 {
520         uint phyid;
521         volatile tsec_t *regbase = priv->phyregs;
522         int timeout = 1000000;
523
524         for (phyid = 0; phyid < 4; phyid++) {
525                 regbase->miimadd = (phyid << 8) | mii_reg;
526                 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
527                 asm("sync");
528
529                 timeout = 1000000;
530                 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
531         }
532
533         return MIIM_CIS8204_SLEDCON_INIT;
534 }
535
536 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
537 {
538         if (priv->flags & TSEC_REDUCED)
539                 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
540         else
541                 return MIIM_CIS8204_EPHYCON_INIT;
542 }
543
544 /* Initialized required registers to appropriate values, zeroing
545  * those we don't care about (unless zero is bad, in which case,
546  * choose a more appropriate value)
547  */
548 static void init_registers(volatile tsec_t * regs)
549 {
550         /* Clear IEVENT */
551         regs->ievent = IEVENT_INIT_CLEAR;
552
553         regs->imask = IMASK_INIT_CLEAR;
554
555         regs->hash.iaddr0 = 0;
556         regs->hash.iaddr1 = 0;
557         regs->hash.iaddr2 = 0;
558         regs->hash.iaddr3 = 0;
559         regs->hash.iaddr4 = 0;
560         regs->hash.iaddr5 = 0;
561         regs->hash.iaddr6 = 0;
562         regs->hash.iaddr7 = 0;
563
564         regs->hash.gaddr0 = 0;
565         regs->hash.gaddr1 = 0;
566         regs->hash.gaddr2 = 0;
567         regs->hash.gaddr3 = 0;
568         regs->hash.gaddr4 = 0;
569         regs->hash.gaddr5 = 0;
570         regs->hash.gaddr6 = 0;
571         regs->hash.gaddr7 = 0;
572
573         regs->rctrl = 0x00000000;
574
575         /* Init RMON mib registers */
576         memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
577
578         regs->rmon.cam1 = 0xffffffff;
579         regs->rmon.cam2 = 0xffffffff;
580
581         regs->mrblr = MRBLR_INIT_SETTINGS;
582
583         regs->minflr = MINFLR_INIT_SETTINGS;
584
585         regs->attr = ATTR_INIT_SETTINGS;
586         regs->attreli = ATTRELI_INIT_SETTINGS;
587
588 }
589
590 /* Configure maccfg2 based on negotiated speed and duplex
591  * reported by PHY handling code
592  */
593 static void adjust_link(struct eth_device *dev)
594 {
595         struct tsec_private *priv = (struct tsec_private *)dev->priv;
596         volatile tsec_t *regs = priv->regs;
597
598         if (priv->link) {
599                 if (priv->duplexity != 0)
600                         regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
601                 else
602                         regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
603
604                 switch (priv->speed) {
605                 case 1000:
606                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
607                                          | MACCFG2_GMII);
608                         break;
609                 case 100:
610                 case 10:
611                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
612                                          | MACCFG2_MII);
613
614                         /* If We're in reduced mode, we need
615                          * to say whether we're 10 or 100 MB.
616                          */
617                         if ((priv->speed == 100)
618                             && (priv->flags & TSEC_REDUCED))
619                                 regs->ecntrl |= ECNTRL_R100;
620                         else
621                                 regs->ecntrl &= ~(ECNTRL_R100);
622                         break;
623                 default:
624                         printf("%s: Speed was bad\n", dev->name);
625                         break;
626                 }
627
628                 printf("Speed: %d, %s duplex\n", priv->speed,
629                        (priv->duplexity) ? "full" : "half");
630
631         } else {
632                 printf("%s: No link.\n", dev->name);
633         }
634 }
635
636 /* Set up the buffers and their descriptors, and bring up the
637  * interface
638  */
639 static void startup_tsec(struct eth_device *dev)
640 {
641         int i;
642         struct tsec_private *priv = (struct tsec_private *)dev->priv;
643         volatile tsec_t *regs = priv->regs;
644
645         /* Point to the buffer descriptors */
646         regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
647         regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
648
649         /* Initialize the Rx Buffer descriptors */
650         for (i = 0; i < PKTBUFSRX; i++) {
651                 rtx.rxbd[i].status = RXBD_EMPTY;
652                 rtx.rxbd[i].length = 0;
653                 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
654         }
655         rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
656
657         /* Initialize the TX Buffer Descriptors */
658         for (i = 0; i < TX_BUF_CNT; i++) {
659                 rtx.txbd[i].status = 0;
660                 rtx.txbd[i].length = 0;
661                 rtx.txbd[i].bufPtr = 0;
662         }
663         rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
664
665         /* Start up the PHY */
666         phy_run_commands(priv, priv->phyinfo->startup);
667         adjust_link(dev);
668
669         /* Enable Transmit and Receive */
670         regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
671
672         /* Tell the DMA it is clear to go */
673         regs->dmactrl |= DMACTRL_INIT_SETTINGS;
674         regs->tstat = TSTAT_CLEAR_THALT;
675         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
676 }
677
678 /* This returns the status bits of the device.  The return value
679  * is never checked, and this is what the 8260 driver did, so we
680  * do the same.  Presumably, this would be zero if there were no
681  * errors
682  */
683 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
684 {
685         int i;
686         int result = 0;
687         struct tsec_private *priv = (struct tsec_private *)dev->priv;
688         volatile tsec_t *regs = priv->regs;
689
690         /* Find an empty buffer descriptor */
691         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
692                 if (i >= TOUT_LOOP) {
693                         debug("%s: tsec: tx buffers full\n", dev->name);
694                         return result;
695                 }
696         }
697
698         rtx.txbd[txIdx].bufPtr = (uint) packet;
699         rtx.txbd[txIdx].length = length;
700         rtx.txbd[txIdx].status |=
701             (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
702
703         /* Tell the DMA to go */
704         regs->tstat = TSTAT_CLEAR_THALT;
705
706         /* Wait for buffer to be transmitted */
707         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
708                 if (i >= TOUT_LOOP) {
709                         debug("%s: tsec: tx error\n", dev->name);
710                         return result;
711                 }
712         }
713
714         txIdx = (txIdx + 1) % TX_BUF_CNT;
715         result = rtx.txbd[txIdx].status & TXBD_STATS;
716
717         return result;
718 }
719
720 static int tsec_recv(struct eth_device *dev)
721 {
722         int length;
723         struct tsec_private *priv = (struct tsec_private *)dev->priv;
724         volatile tsec_t *regs = priv->regs;
725
726         while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
727
728                 length = rtx.rxbd[rxIdx].length;
729
730                 /* Send the packet up if there were no errors */
731                 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
732                         NetReceive(NetRxPackets[rxIdx], length - 4);
733                 } else {
734                         printf("Got error %x\n",
735                                (rtx.rxbd[rxIdx].status & RXBD_STATS));
736                 }
737
738                 rtx.rxbd[rxIdx].length = 0;
739
740                 /* Set the wrap bit if this is the last element in the list */
741                 rtx.rxbd[rxIdx].status =
742                     RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
743
744                 rxIdx = (rxIdx + 1) % PKTBUFSRX;
745         }
746
747         if (regs->ievent & IEVENT_BSY) {
748                 regs->ievent = IEVENT_BSY;
749                 regs->rstat = RSTAT_CLEAR_RHALT;
750         }
751
752         return -1;
753
754 }
755
756 /* Stop the interface */
757 static void tsec_halt(struct eth_device *dev)
758 {
759         struct tsec_private *priv = (struct tsec_private *)dev->priv;
760         volatile tsec_t *regs = priv->regs;
761
762         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
763         regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
764
765         while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
766
767         regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
768
769         /* Shut down the PHY, as needed */
770         phy_run_commands(priv, priv->phyinfo->shutdown);
771 }
772
773 struct phy_info phy_info_M88E1011S = {
774         0x01410c6,
775         "Marvell 88E1011S",
776         4,
777         (struct phy_cmd[]){     /* config */
778                            /* Reset and configure the PHY */
779                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
780                            {0x1d, 0x1f, NULL},
781                            {0x1e, 0x200c, NULL},
782                            {0x1d, 0x5, NULL},
783                            {0x1e, 0x0, NULL},
784                            {0x1e, 0x100, NULL},
785                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
786                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
787                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
788                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
789                            {miim_end,}
790                            },
791         (struct phy_cmd[]){     /* startup */
792                            /* Status is read once to clear old link state */
793                            {MIIM_STATUS, miim_read, NULL},
794                            /* Auto-negotiate */
795                            {MIIM_STATUS, miim_read, &mii_parse_sr},
796                            /* Read the status */
797                            {MIIM_88E1011_PHY_STATUS, miim_read,
798                             &mii_parse_88E1011_psr},
799                            {miim_end,}
800                            },
801         (struct phy_cmd[]){     /* shutdown */
802                            {miim_end,}
803                            },
804 };
805
806 struct phy_info phy_info_M88E1111S = {
807         0x01410cc,
808         "Marvell 88E1111S",
809         4,
810         (struct phy_cmd[]){     /* config */
811                            /* Reset and configure the PHY */
812                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
813                            {0x1d, 0x1f, NULL},
814                            {0x1e, 0x200c, NULL},
815                            {0x1d, 0x5, NULL},
816                            {0x1e, 0x0, NULL},
817                            {0x1e, 0x100, NULL},
818                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
819                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
820                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
821                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
822                            {miim_end,}
823                            },
824         (struct phy_cmd[]){     /* startup */
825                            /* Status is read once to clear old link state */
826                            {MIIM_STATUS, miim_read, NULL},
827                            /* Auto-negotiate */
828                            {MIIM_STATUS, miim_read, &mii_parse_sr},
829                            /* Read the status */
830                            {MIIM_88E1011_PHY_STATUS, miim_read,
831                             &mii_parse_88E1011_psr},
832                            {miim_end,}
833                            },
834         (struct phy_cmd[]){     /* shutdown */
835                            {miim_end,}
836                            },
837 };
838
839 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
840 {
841         unsigned int temp;
842         uint mii_data = read_phy_reg(priv, mii_reg);
843
844         /* Setting MIIM_88E1145_PHY_EXT_CR */
845         if (priv->flags & TSEC_REDUCED)
846                 return mii_data |
847                     MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
848         else
849                 return mii_data;
850 }
851
852 static struct phy_info phy_info_M88E1145 = {
853         0x01410cd,
854         "Marvell 88E1145",
855         4,
856         (struct phy_cmd[]){     /* config */
857                            /* Errata E0, E1 */
858                            {29, 0x001b, NULL},
859                            {30, 0x418f, NULL},
860                            {29, 0x0016, NULL},
861                            {30, 0xa2da, NULL},
862
863                            /* Reset and configure the PHY */
864                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
865                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
866                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
867                            {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
868                             NULL},
869                            {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
870                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
871                            {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
872                            {miim_end,}
873                            },
874         (struct phy_cmd[]){     /* startup */
875                            /* Status is read once to clear old link state */
876                            {MIIM_STATUS, miim_read, NULL},
877                            /* Auto-negotiate */
878                            {MIIM_STATUS, miim_read, &mii_parse_sr},
879                            {MIIM_88E1111_PHY_LED_CONTROL,
880                             MIIM_88E1111_PHY_LED_DIRECT, NULL},
881                            /* Read the Status */
882                            {MIIM_88E1011_PHY_STATUS, miim_read,
883                             &mii_parse_88E1011_psr},
884                            {miim_end,}
885                            },
886         (struct phy_cmd[]){     /* shutdown */
887                            {miim_end,}
888                            },
889 };
890
891 struct phy_info phy_info_cis8204 = {
892         0x3f11,
893         "Cicada Cis8204",
894         6,
895         (struct phy_cmd[]){     /* config */
896                            /* Override PHY config settings */
897                            {MIIM_CIS8201_AUX_CONSTAT,
898                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
899                            /* Configure some basic stuff */
900                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
901                            {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
902                             &mii_cis8204_fixled},
903                            {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
904                             &mii_cis8204_setmode},
905                            {miim_end,}
906                            },
907         (struct phy_cmd[]){     /* startup */
908                            /* Read the Status (2x to make sure link is right) */
909                            {MIIM_STATUS, miim_read, NULL},
910                            /* Auto-negotiate */
911                            {MIIM_STATUS, miim_read, &mii_parse_sr},
912                            /* Read the status */
913                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
914                             &mii_parse_cis8201},
915                            {miim_end,}
916                            },
917         (struct phy_cmd[]){     /* shutdown */
918                            {miim_end,}
919                            },
920 };
921
922 /* Cicada 8201 */
923 struct phy_info phy_info_cis8201 = {
924         0xfc41,
925         "CIS8201",
926         4,
927         (struct phy_cmd[]){     /* config */
928                            /* Override PHY config settings */
929                            {MIIM_CIS8201_AUX_CONSTAT,
930                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
931                            /* Set up the interface mode */
932                            {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
933                             NULL},
934                            /* Configure some basic stuff */
935                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
936                            {miim_end,}
937                            },
938         (struct phy_cmd[]){     /* startup */
939                            /* Read the Status (2x to make sure link is right) */
940                            {MIIM_STATUS, miim_read, NULL},
941                            /* Auto-negotiate */
942                            {MIIM_STATUS, miim_read, &mii_parse_sr},
943                            /* Read the status */
944                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
945                             &mii_parse_cis8201},
946                            {miim_end,}
947                            },
948         (struct phy_cmd[]){     /* shutdown */
949                            {miim_end,}
950                            },
951 };
952 struct phy_info phy_info_VSC8244 = {
953         0x3f1b,
954         "Vitesse VSC8244",
955         6,
956         (struct phy_cmd[]){     /* config */
957                            /* Override PHY config settings */
958                            /* Configure some basic stuff */
959                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
960                            {miim_end,}
961                            },
962         (struct phy_cmd[]){     /* startup */
963                            /* Read the Status (2x to make sure link is right) */
964                            {MIIM_STATUS, miim_read, NULL},
965                            /* Auto-negotiate */
966                            {MIIM_STATUS, miim_read, &mii_parse_sr},
967                            /* Read the status */
968                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
969                             &mii_parse_vsc8244},
970                            {miim_end,}
971                            },
972         (struct phy_cmd[]){     /* shutdown */
973                            {miim_end,}
974                            },
975 };
976
977 struct phy_info phy_info_dm9161 = {
978         0x0181b88,
979         "Davicom DM9161E",
980         4,
981         (struct phy_cmd[]){     /* config */
982                            {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
983                            /* Do not bypass the scrambler/descrambler */
984                            {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
985                            /* Clear 10BTCSR to default */
986                            {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
987                             NULL},
988                            /* Configure some basic stuff */
989                            {MIIM_CONTROL, MIIM_CR_INIT, NULL},
990                            /* Restart Auto Negotiation */
991                            {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
992                            {miim_end,}
993                            },
994         (struct phy_cmd[]){     /* startup */
995                            /* Status is read once to clear old link state */
996                            {MIIM_STATUS, miim_read, NULL},
997                            /* Auto-negotiate */
998                            {MIIM_STATUS, miim_read, &mii_parse_sr},
999                            /* Read the status */
1000                            {MIIM_DM9161_SCSR, miim_read,
1001                             &mii_parse_dm9161_scsr},
1002                            {miim_end,}
1003                            },
1004         (struct phy_cmd[]){     /* shutdown */
1005                            {miim_end,}
1006                            },
1007 };
1008
1009 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1010 {
1011         unsigned int speed;
1012         if (priv->link) {
1013                 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1014
1015                 switch (speed) {
1016                 case MIIM_LXT971_SR2_10HDX:
1017                         priv->speed = 10;
1018                         priv->duplexity = 0;
1019                         break;
1020                 case MIIM_LXT971_SR2_10FDX:
1021                         priv->speed = 10;
1022                         priv->duplexity = 1;
1023                         break;
1024                 case MIIM_LXT971_SR2_100HDX:
1025                         priv->speed = 100;
1026                         priv->duplexity = 0;
1027                 default:
1028                         priv->speed = 100;
1029                         priv->duplexity = 1;
1030                         break;
1031                 }
1032         } else {
1033                 priv->speed = 0;
1034                 priv->duplexity = 0;
1035         }
1036
1037         return 0;
1038 }
1039
1040 static struct phy_info phy_info_lxt971 = {
1041         0x0001378e,
1042         "LXT971",
1043         4,
1044         (struct phy_cmd[]){     /* config */
1045                            {MIIM_CR, MIIM_CR_INIT, mii_cr_init},        /* autonegotiate */
1046                            {miim_end,}
1047                            },
1048         (struct phy_cmd[]){     /* startup - enable interrupts */
1049                            /* { 0x12, 0x00f2, NULL }, */
1050                            {MIIM_STATUS, miim_read, NULL},
1051                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1052                            {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1053                            {miim_end,}
1054                            },
1055         (struct phy_cmd[]){     /* shutdown - disable interrupts */
1056                            {miim_end,}
1057                            },
1058 };
1059
1060 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1061  * information
1062  */
1063 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1064 {
1065         switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1066
1067         case MIIM_DP83865_SPD_1000:
1068                 priv->speed = 1000;
1069                 break;
1070
1071         case MIIM_DP83865_SPD_100:
1072                 priv->speed = 100;
1073                 break;
1074
1075         default:
1076                 priv->speed = 10;
1077                 break;
1078
1079         }
1080
1081         if (mii_reg & MIIM_DP83865_DPX_FULL)
1082                 priv->duplexity = 1;
1083         else
1084                 priv->duplexity = 0;
1085
1086         return 0;
1087 }
1088
1089 struct phy_info phy_info_dp83865 = {
1090         0x20005c7,
1091         "NatSemi DP83865",
1092         4,
1093         (struct phy_cmd[]){     /* config */
1094                            {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1095                            {miim_end,}
1096                            },
1097         (struct phy_cmd[]){     /* startup */
1098                            /* Status is read once to clear old link state */
1099                            {MIIM_STATUS, miim_read, NULL},
1100                            /* Auto-negotiate */
1101                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1102                            /* Read the link and auto-neg status */
1103                            {MIIM_DP83865_LANR, miim_read,
1104                             &mii_parse_dp83865_lanr},
1105                            {miim_end,}
1106                            },
1107         (struct phy_cmd[]){     /* shutdown */
1108                            {miim_end,}
1109                            },
1110 };
1111
1112 struct phy_info *phy_info[] = {
1113 #if 0
1114         &phy_info_cis8201,
1115 #endif
1116         &phy_info_cis8204,
1117         &phy_info_M88E1011S,
1118         &phy_info_M88E1111S,
1119         &phy_info_M88E1145,
1120         &phy_info_dm9161,
1121         &phy_info_lxt971,
1122         &phy_info_VSC8244,
1123         &phy_info_dp83865,
1124         NULL
1125 };
1126
1127 /* Grab the identifier of the device's PHY, and search through
1128  * all of the known PHYs to see if one matches.  If so, return
1129  * it, if not, return NULL
1130  */
1131 struct phy_info *get_phy_info(struct eth_device *dev)
1132 {
1133         struct tsec_private *priv = (struct tsec_private *)dev->priv;
1134         uint phy_reg, phy_ID;
1135         int i;
1136         struct phy_info *theInfo = NULL;
1137
1138         /* Grab the bits from PHYIR1, and put them in the upper half */
1139         phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1140         phy_ID = (phy_reg & 0xffff) << 16;
1141
1142         /* Grab the bits from PHYIR2, and put them in the lower half */
1143         phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1144         phy_ID |= (phy_reg & 0xffff);
1145
1146         /* loop through all the known PHY types, and find one that */
1147         /* matches the ID we read from the PHY. */
1148         for (i = 0; phy_info[i]; i++) {
1149                 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
1150                         theInfo = phy_info[i];
1151         }
1152
1153         if (theInfo == NULL) {
1154                 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1155                 return NULL;
1156         } else {
1157                 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1158         }
1159
1160         return theInfo;
1161 }
1162
1163 /* Execute the given series of commands on the given device's
1164  * PHY, running functions as necessary
1165  */
1166 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1167 {
1168         int i;
1169         uint result;
1170         volatile tsec_t *phyregs = priv->phyregs;
1171
1172         phyregs->miimcfg = MIIMCFG_RESET;
1173
1174         phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1175
1176         while (phyregs->miimind & MIIMIND_BUSY) ;
1177
1178         for (i = 0; cmd->mii_reg != miim_end; i++) {
1179                 if (cmd->mii_data == miim_read) {
1180                         result = read_phy_reg(priv, cmd->mii_reg);
1181
1182                         if (cmd->funct != NULL)
1183                                 (*(cmd->funct)) (result, priv);
1184
1185                 } else {
1186                         if (cmd->funct != NULL)
1187                                 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1188                         else
1189                                 result = cmd->mii_data;
1190
1191                         write_phy_reg(priv, cmd->mii_reg, result);
1192
1193                 }
1194                 cmd++;
1195         }
1196 }
1197
1198 /* Relocate the function pointers in the phy cmd lists */
1199 static void relocate_cmds(void)
1200 {
1201         struct phy_cmd **cmdlistptr;
1202         struct phy_cmd *cmd;
1203         int i, j, k;
1204
1205         for (i = 0; phy_info[i]; i++) {
1206                 /* First thing's first: relocate the pointers to the
1207                  * PHY command structures (the structs were done) */
1208                 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1209                                                   + gd->reloc_off);
1210                 phy_info[i]->name += gd->reloc_off;
1211                 phy_info[i]->config =
1212                     (struct phy_cmd *)((uint) phy_info[i]->config
1213                                        + gd->reloc_off);
1214                 phy_info[i]->startup =
1215                     (struct phy_cmd *)((uint) phy_info[i]->startup
1216                                        + gd->reloc_off);
1217                 phy_info[i]->shutdown =
1218                     (struct phy_cmd *)((uint) phy_info[i]->shutdown
1219                                        + gd->reloc_off);
1220
1221                 cmdlistptr = &phy_info[i]->config;
1222                 j = 0;
1223                 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1224                         k = 0;
1225                         for (cmd = *cmdlistptr;
1226                              cmd->mii_reg != miim_end;
1227                              cmd++) {
1228                                 /* Only relocate non-NULL pointers */
1229                                 if (cmd->funct)
1230                                         cmd->funct += gd->reloc_off;
1231
1232                                 k++;
1233                         }
1234                         j++;
1235                 }
1236         }
1237
1238         relocated = 1;
1239 }
1240
1241 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
1242         && !defined(BITBANGMII)
1243
1244 struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
1245 {
1246         int i;
1247
1248         for (i = 0; i < MAXCONTROLLERS; i++) {
1249                 if (privlist[i]->phyaddr == phyaddr)
1250                         return privlist[i];
1251         }
1252
1253         return NULL;
1254 }
1255
1256 /*
1257  * Read a MII PHY register.
1258  *
1259  * Returns:
1260  *  0 on success
1261  */
1262 static int tsec_miiphy_read(char *devname, unsigned char addr,
1263                             unsigned char reg, unsigned short *value)
1264 {
1265         unsigned short ret;
1266         struct tsec_private *priv = get_priv_for_phy(addr);
1267
1268         if (NULL == priv) {
1269                 printf("Can't read PHY at address %d\n", addr);
1270                 return -1;
1271         }
1272
1273         ret = (unsigned short)read_phy_reg(priv, reg);
1274         *value = ret;
1275
1276         return 0;
1277 }
1278
1279 /*
1280  * Write a MII PHY register.
1281  *
1282  * Returns:
1283  *  0 on success
1284  */
1285 static int tsec_miiphy_write(char *devname, unsigned char addr,
1286                              unsigned char reg, unsigned short value)
1287 {
1288         struct tsec_private *priv = get_priv_for_phy(addr);
1289
1290         if (NULL == priv) {
1291                 printf("Can't write PHY at address %d\n", addr);
1292                 return -1;
1293         }
1294
1295         write_phy_reg(priv, reg, value);
1296
1297         return 0;
1298 }
1299
1300 #endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1301                 && !defined(BITBANGMII) */
1302
1303 #endif /* CONFIG_TSEC_ENET */