Merge branch 'mpc8641'
[platform/kernel/u-boot.git] / drivers / tsec.c
1 /*
2  * Freescale Three Speed Ethernet Controller driver
3  *
4  * This software may be used and distributed according to the
5  * terms of the GNU Public License, Version 2, incorporated
6  * herein by reference.
7  *
8  * Copyright 2004, 2007 Freescale Semiconductor, Inc.
9  * (C) Copyright 2003, Motorola, Inc.
10  * author Andy Fleming
11  *
12  */
13
14 #include <config.h>
15 #include <common.h>
16 #include <malloc.h>
17 #include <net.h>
18 #include <command.h>
19
20 #if defined(CONFIG_TSEC_ENET)
21 #include "tsec.h"
22 #include "miiphy.h"
23
24 DECLARE_GLOBAL_DATA_PTR;
25
26 #define TX_BUF_CNT              2
27
28 static uint rxIdx;              /* index of the current RX buffer */
29 static uint txIdx;              /* index of the current TX buffer */
30
31 typedef volatile struct rtxbd {
32         txbd8_t txbd[TX_BUF_CNT];
33         rxbd8_t rxbd[PKTBUFSRX];
34 } RTXBD;
35
36 struct tsec_info_struct {
37         unsigned int phyaddr;
38         u32 flags;
39         unsigned int phyregidx;
40 };
41
42 /* The tsec_info structure contains 3 values which the
43  * driver uses to determine how to operate a given ethernet
44  * device. The information needed is:
45  *  phyaddr - The address of the PHY which is attached to
46  *      the given device.
47  *
48  *  flags - This variable indicates whether the device
49  *      supports gigabit speed ethernet, and whether it should be
50  *      in reduced mode.
51  *
52  *  phyregidx - This variable specifies which ethernet device
53  *      controls the MII Management registers which are connected
54  *      to the PHY.  For now, only TSEC1 (index 0) has
55  *      access to the PHYs, so all of the entries have "0".
56  *
57  * The values specified in the table are taken from the board's
58  * config file in include/configs/.  When implementing a new
59  * board with ethernet capability, it is necessary to define:
60  *   TSECn_PHY_ADDR
61  *   TSECn_PHYIDX
62  *
63  * for n = 1,2,3, etc.  And for FEC:
64  *   FEC_PHY_ADDR
65  *   FEC_PHYIDX
66  */
67 static struct tsec_info_struct tsec_info[] = {
68 #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
69 #if defined(CONFIG_MPC8544DS)
70         {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
71 #else
72         {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
73 #endif
74 #elif defined(CONFIG_MPC86XX_TSEC1)
75         {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
76 #else
77         {0, 0, 0},
78 #endif
79 #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
80         {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
81 #elif defined(CONFIG_MPC86XX_TSEC2)
82         {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
83 #else
84         {0, 0, 0},
85 #endif
86 #ifdef CONFIG_MPC85XX_FEC
87         {FEC_PHY_ADDR, 0, FEC_PHYIDX},
88 #else
89 #if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
90         {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
91 #else
92         {0, 0, 0},
93 #endif
94 #if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
95         {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
96 #else
97         {0, 0, 0},
98 #endif
99 #endif
100 };
101
102 #define MAXCONTROLLERS  (4)
103
104 static int relocated = 0;
105
106 static struct tsec_private *privlist[MAXCONTROLLERS];
107
108 #ifdef __GNUC__
109 static RTXBD rtx __attribute__ ((aligned(8)));
110 #else
111 #error "rtx must be 64-bit aligned"
112 #endif
113
114 static int tsec_send(struct eth_device *dev,
115                      volatile void *packet, int length);
116 static int tsec_recv(struct eth_device *dev);
117 static int tsec_init(struct eth_device *dev, bd_t * bd);
118 static void tsec_halt(struct eth_device *dev);
119 static void init_registers(volatile tsec_t * regs);
120 static void startup_tsec(struct eth_device *dev);
121 static int init_phy(struct eth_device *dev);
122 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
123 uint read_phy_reg(struct tsec_private *priv, uint regnum);
124 struct phy_info *get_phy_info(struct eth_device *dev);
125 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
126 static void adjust_link(struct eth_device *dev);
127 static void relocate_cmds(void);
128 static int tsec_miiphy_write(char *devname, unsigned char addr,
129                              unsigned char reg, unsigned short value);
130 static int tsec_miiphy_read(char *devname, unsigned char addr,
131                             unsigned char reg, unsigned short *value);
132
133 /* Initialize device structure. Returns success if PHY
134  * initialization succeeded (i.e. if it recognizes the PHY)
135  */
136 int tsec_initialize(bd_t * bis, int index, char *devname)
137 {
138         struct eth_device *dev;
139         int i;
140         struct tsec_private *priv;
141
142         dev = (struct eth_device *)malloc(sizeof *dev);
143
144         if (NULL == dev)
145                 return 0;
146
147         memset(dev, 0, sizeof *dev);
148
149         priv = (struct tsec_private *)malloc(sizeof(*priv));
150
151         if (NULL == priv)
152                 return 0;
153
154         privlist[index] = priv;
155         priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
156         priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
157                                             tsec_info[index].phyregidx *
158                                             TSEC_SIZE);
159
160         priv->phyaddr = tsec_info[index].phyaddr;
161         priv->flags = tsec_info[index].flags;
162
163         sprintf(dev->name, devname);
164         dev->iobase = 0;
165         dev->priv = priv;
166         dev->init = tsec_init;
167         dev->halt = tsec_halt;
168         dev->send = tsec_send;
169         dev->recv = tsec_recv;
170
171         /* Tell u-boot to get the addr from the env */
172         for (i = 0; i < 6; i++)
173                 dev->enetaddr[i] = 0;
174
175         eth_register(dev);
176
177         /* Reset the MAC */
178         priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
179         priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
180
181 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
182         && !defined(BITBANGMII)
183         miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
184 #endif
185
186         /* Try to initialize PHY here, and return */
187         return init_phy(dev);
188 }
189
190 /* Initializes data structures and registers for the controller,
191  * and brings the interface up.  Returns the link status, meaning
192  * that it returns success if the link is up, failure otherwise.
193  * This allows u-boot to find the first active controller.
194  */
195 int tsec_init(struct eth_device *dev, bd_t * bd)
196 {
197         uint tempval;
198         char tmpbuf[MAC_ADDR_LEN];
199         int i;
200         struct tsec_private *priv = (struct tsec_private *)dev->priv;
201         volatile tsec_t *regs = priv->regs;
202
203         /* Make sure the controller is stopped */
204         tsec_halt(dev);
205
206         /* Init MACCFG2.  Defaults to GMII */
207         regs->maccfg2 = MACCFG2_INIT_SETTINGS;
208
209         /* Init ECNTRL */
210         regs->ecntrl = ECNTRL_INIT_SETTINGS;
211
212         /* Copy the station address into the address registers.
213          * Backwards, because little endian MACS are dumb */
214         for (i = 0; i < MAC_ADDR_LEN; i++) {
215                 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
216         }
217         regs->macstnaddr1 = *((uint *) (tmpbuf));
218
219         tempval = *((uint *) (tmpbuf + 4));
220
221         regs->macstnaddr2 = tempval;
222
223         /* reset the indices to zero */
224         rxIdx = 0;
225         txIdx = 0;
226
227         /* Clear out (for the most part) the other registers */
228         init_registers(regs);
229
230         /* Ready the device for tx/rx */
231         startup_tsec(dev);
232
233         /* If there's no link, fail */
234         return priv->link;
235
236 }
237
238 /* Write value to the device's PHY through the registers
239  * specified in priv, modifying the register specified in regnum.
240  * It will wait for the write to be done (or for a timeout to
241  * expire) before exiting
242  */
243 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
244 {
245         volatile tsec_t *regbase = priv->phyregs;
246         uint phyid = priv->phyaddr;
247         int timeout = 1000000;
248
249         regbase->miimadd = (phyid << 8) | regnum;
250         regbase->miimcon = value;
251         asm("sync");
252
253         timeout = 1000000;
254         while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
255 }
256
257 /* Reads register regnum on the device's PHY through the
258  * registers specified in priv.  It lowers and raises the read
259  * command, and waits for the data to become valid (miimind
260  * notvalid bit cleared), and the bus to cease activity (miimind
261  * busy bit cleared), and then returns the value
262  */
263 uint read_phy_reg(struct tsec_private *priv, uint regnum)
264 {
265         uint value;
266         volatile tsec_t *regbase = priv->phyregs;
267         uint phyid = priv->phyaddr;
268
269         /* Put the address of the phy, and the register
270          * number into MIIMADD */
271         regbase->miimadd = (phyid << 8) | regnum;
272
273         /* Clear the command register, and wait */
274         regbase->miimcom = 0;
275         asm("sync");
276
277         /* Initiate a read command, and wait */
278         regbase->miimcom = MIIM_READ_COMMAND;
279         asm("sync");
280
281         /* Wait for the the indication that the read is done */
282         while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
283
284         /* Grab the value read from the PHY */
285         value = regbase->miimstat;
286
287         return value;
288 }
289
290 /* Discover which PHY is attached to the device, and configure it
291  * properly.  If the PHY is not recognized, then return 0
292  * (failure).  Otherwise, return 1
293  */
294 static int init_phy(struct eth_device *dev)
295 {
296         struct tsec_private *priv = (struct tsec_private *)dev->priv;
297         struct phy_info *curphy;
298         volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
299
300         /* Assign a Physical address to the TBI */
301         regs->tbipa = TBIPA_VALUE;
302         regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
303         regs->tbipa = TBIPA_VALUE;
304         asm("sync");
305
306         /* Reset MII (due to new addresses) */
307         priv->phyregs->miimcfg = MIIMCFG_RESET;
308         asm("sync");
309         priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
310         asm("sync");
311         while (priv->phyregs->miimind & MIIMIND_BUSY) ;
312
313         if (0 == relocated)
314                 relocate_cmds();
315
316         /* Get the cmd structure corresponding to the attached
317          * PHY */
318         curphy = get_phy_info(dev);
319
320         if (curphy == NULL) {
321                 priv->phyinfo = NULL;
322                 printf("%s: No PHY found\n", dev->name);
323
324                 return 0;
325         }
326
327         priv->phyinfo = curphy;
328
329         phy_run_commands(priv, priv->phyinfo->config);
330
331         return 1;
332 }
333
334 /*
335  * Returns which value to write to the control register.
336  * For 10/100, the value is slightly different
337  */
338 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
339 {
340         if (priv->flags & TSEC_GIGABIT)
341                 return MIIM_CONTROL_INIT;
342         else
343                 return MIIM_CR_INIT;
344 }
345
346 /* Parse the status register for link, and then do
347  * auto-negotiation
348  */
349 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
350 {
351         /*
352          * Wait if PHY is capable of autonegotiation and autonegotiation
353          * is not complete.
354          */
355         mii_reg = read_phy_reg(priv, MIIM_STATUS);
356         if ((mii_reg & PHY_BMSR_AUTN_ABLE)
357             && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
358                 int i = 0;
359
360                 puts("Waiting for PHY auto negotiation to complete");
361                 while (!((mii_reg & PHY_BMSR_AUTN_COMP)
362                          && (mii_reg & MIIM_STATUS_LINK))) {
363                         /*
364                          * Timeout reached ?
365                          */
366                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
367                                 puts(" TIMEOUT !\n");
368                                 priv->link = 0;
369                                 return 0;
370                         }
371
372                         if ((i++ % 1000) == 0) {
373                                 putc('.');
374                         }
375                         udelay(1000);   /* 1 ms */
376                         mii_reg = read_phy_reg(priv, MIIM_STATUS);
377                 }
378                 puts(" done\n");
379                 priv->link = 1;
380                 udelay(500000); /* another 500 ms (results in faster booting) */
381         } else {
382                 priv->link = 1;
383         }
384
385         return 0;
386 }
387
388 /* Generic function which updates the speed and duplex.  If
389  * autonegotiation is enabled, it uses the AND of the link
390  * partner's advertised capabilities and our advertised
391  * capabilities.  If autonegotiation is disabled, we use the
392  * appropriate bits in the control register.
393  *
394  * Stolen from Linux's mii.c and phy_device.c
395  */
396 uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
397 {
398         /* We're using autonegotiation */
399         if (mii_reg & PHY_BMSR_AUTN_ABLE) {
400                 uint lpa = 0;
401                 uint gblpa = 0;
402
403                 /* Check for gigabit capability */
404                 if (mii_reg & PHY_BMSR_EXT) {
405                         /* We want a list of states supported by
406                          * both PHYs in the link
407                          */
408                         gblpa = read_phy_reg(priv, PHY_1000BTSR);
409                         gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
410                 }
411
412                 /* Set the baseline so we only have to set them
413                  * if they're different
414                  */
415                 priv->speed = 10;
416                 priv->duplexity = 0;
417
418                 /* Check the gigabit fields */
419                 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
420                         priv->speed = 1000;
421
422                         if (gblpa & PHY_1000BTSR_1000FD)
423                                 priv->duplexity = 1;
424
425                         /* We're done! */
426                         return 0;
427                 }
428
429                 lpa = read_phy_reg(priv, PHY_ANAR);
430                 lpa &= read_phy_reg(priv, PHY_ANLPAR);
431
432                 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
433                         priv->speed = 100;
434
435                         if (lpa & PHY_ANLPAR_TXFD)
436                                 priv->duplexity = 1;
437
438                 } else if (lpa & PHY_ANLPAR_10FD)
439                         priv->duplexity = 1;
440         } else {
441                 uint bmcr = read_phy_reg(priv, PHY_BMCR);
442
443                 priv->speed = 10;
444                 priv->duplexity = 0;
445
446                 if (bmcr & PHY_BMCR_DPLX)
447                         priv->duplexity = 1;
448
449                 if (bmcr & PHY_BMCR_1000_MBPS)
450                         priv->speed = 1000;
451                 else if (bmcr & PHY_BMCR_100_MBPS)
452                         priv->speed = 100;
453         }
454
455         return 0;
456 }
457
458 /*
459  * Parse the BCM54xx status register for speed and duplex information.
460  * The linux sungem_phy has this information, but in a table format.
461  */
462 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
463 {
464
465         switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
466
467                 case 1:
468                         printf("Enet starting in 10BT/HD\n");
469                         priv->duplexity = 0;
470                         priv->speed = 10;
471                         break;
472
473                 case 2:
474                         printf("Enet starting in 10BT/FD\n");
475                         priv->duplexity = 1;
476                         priv->speed = 10;
477                         break;
478
479                 case 3:
480                         printf("Enet starting in 100BT/HD\n");
481                         priv->duplexity = 0;
482                         priv->speed = 100;
483                         break;
484
485                 case 5:
486                         printf("Enet starting in 100BT/FD\n");
487                         priv->duplexity = 1;
488                         priv->speed = 100;
489                         break;
490
491                 case 6:
492                         printf("Enet starting in 1000BT/HD\n");
493                         priv->duplexity = 0;
494                         priv->speed = 1000;
495                         break;
496
497                 case 7:
498                         printf("Enet starting in 1000BT/FD\n");
499                         priv->duplexity = 1;
500                         priv->speed = 1000;
501                         break;
502
503                 default:
504                         printf("Auto-neg error, defaulting to 10BT/HD\n");
505                         priv->duplexity = 0;
506                         priv->speed = 10;
507                         break;
508         }
509
510         return 0;
511
512 }
513 /* Parse the 88E1011's status register for speed and duplex
514  * information
515  */
516 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
517 {
518         uint speed;
519
520         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
521
522         if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
523               (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
524                 int i = 0;
525
526                 puts("Waiting for PHY realtime link");
527                 while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
528                          (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
529                         /*
530                          * Timeout reached ?
531                          */
532                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
533                                 puts(" TIMEOUT !\n");
534                                 priv->link = 0;
535                                 break;
536                         }
537
538                         if ((i++ % 1000) == 0) {
539                                 putc('.');
540                         }
541                         udelay(1000);   /* 1 ms */
542                         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
543                 }
544                 puts(" done\n");
545                 udelay(500000); /* another 500 ms (results in faster booting) */
546         }
547
548         if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
549                 priv->duplexity = 1;
550         else
551                 priv->duplexity = 0;
552
553         speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
554
555         switch (speed) {
556         case MIIM_88E1011_PHYSTAT_GBIT:
557                 priv->speed = 1000;
558                 break;
559         case MIIM_88E1011_PHYSTAT_100:
560                 priv->speed = 100;
561                 break;
562         default:
563                 priv->speed = 10;
564         }
565
566         return 0;
567 }
568
569 /* Parse the cis8201's status register for speed and duplex
570  * information
571  */
572 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
573 {
574         uint speed;
575
576         if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
577                 priv->duplexity = 1;
578         else
579                 priv->duplexity = 0;
580
581         speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
582         switch (speed) {
583         case MIIM_CIS8201_AUXCONSTAT_GBIT:
584                 priv->speed = 1000;
585                 break;
586         case MIIM_CIS8201_AUXCONSTAT_100:
587                 priv->speed = 100;
588                 break;
589         default:
590                 priv->speed = 10;
591                 break;
592         }
593
594         return 0;
595 }
596
597 /* Parse the vsc8244's status register for speed and duplex
598  * information
599  */
600 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
601 {
602         uint speed;
603
604         if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
605                 priv->duplexity = 1;
606         else
607                 priv->duplexity = 0;
608
609         speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
610         switch (speed) {
611         case MIIM_VSC8244_AUXCONSTAT_GBIT:
612                 priv->speed = 1000;
613                 break;
614         case MIIM_VSC8244_AUXCONSTAT_100:
615                 priv->speed = 100;
616                 break;
617         default:
618                 priv->speed = 10;
619                 break;
620         }
621
622         return 0;
623 }
624
625 /* Parse the DM9161's status register for speed and duplex
626  * information
627  */
628 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
629 {
630         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
631                 priv->speed = 100;
632         else
633                 priv->speed = 10;
634
635         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
636                 priv->duplexity = 1;
637         else
638                 priv->duplexity = 0;
639
640         return 0;
641 }
642
643 /*
644  * Hack to write all 4 PHYs with the LED values
645  */
646 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
647 {
648         uint phyid;
649         volatile tsec_t *regbase = priv->phyregs;
650         int timeout = 1000000;
651
652         for (phyid = 0; phyid < 4; phyid++) {
653                 regbase->miimadd = (phyid << 8) | mii_reg;
654                 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
655                 asm("sync");
656
657                 timeout = 1000000;
658                 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
659         }
660
661         return MIIM_CIS8204_SLEDCON_INIT;
662 }
663
664 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
665 {
666         if (priv->flags & TSEC_REDUCED)
667                 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
668         else
669                 return MIIM_CIS8204_EPHYCON_INIT;
670 }
671
672 /* Initialized required registers to appropriate values, zeroing
673  * those we don't care about (unless zero is bad, in which case,
674  * choose a more appropriate value)
675  */
676 static void init_registers(volatile tsec_t * regs)
677 {
678         /* Clear IEVENT */
679         regs->ievent = IEVENT_INIT_CLEAR;
680
681         regs->imask = IMASK_INIT_CLEAR;
682
683         regs->hash.iaddr0 = 0;
684         regs->hash.iaddr1 = 0;
685         regs->hash.iaddr2 = 0;
686         regs->hash.iaddr3 = 0;
687         regs->hash.iaddr4 = 0;
688         regs->hash.iaddr5 = 0;
689         regs->hash.iaddr6 = 0;
690         regs->hash.iaddr7 = 0;
691
692         regs->hash.gaddr0 = 0;
693         regs->hash.gaddr1 = 0;
694         regs->hash.gaddr2 = 0;
695         regs->hash.gaddr3 = 0;
696         regs->hash.gaddr4 = 0;
697         regs->hash.gaddr5 = 0;
698         regs->hash.gaddr6 = 0;
699         regs->hash.gaddr7 = 0;
700
701         regs->rctrl = 0x00000000;
702
703         /* Init RMON mib registers */
704         memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
705
706         regs->rmon.cam1 = 0xffffffff;
707         regs->rmon.cam2 = 0xffffffff;
708
709         regs->mrblr = MRBLR_INIT_SETTINGS;
710
711         regs->minflr = MINFLR_INIT_SETTINGS;
712
713         regs->attr = ATTR_INIT_SETTINGS;
714         regs->attreli = ATTRELI_INIT_SETTINGS;
715
716 }
717
718 /* Configure maccfg2 based on negotiated speed and duplex
719  * reported by PHY handling code
720  */
721 static void adjust_link(struct eth_device *dev)
722 {
723         struct tsec_private *priv = (struct tsec_private *)dev->priv;
724         volatile tsec_t *regs = priv->regs;
725
726         if (priv->link) {
727                 if (priv->duplexity != 0)
728                         regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
729                 else
730                         regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
731
732                 switch (priv->speed) {
733                 case 1000:
734                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
735                                          | MACCFG2_GMII);
736                         break;
737                 case 100:
738                 case 10:
739                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
740                                          | MACCFG2_MII);
741
742                         /* Set R100 bit in all modes although
743                          * it is only used in RGMII mode
744                          */
745                         if (priv->speed == 100)
746                                 regs->ecntrl |= ECNTRL_R100;
747                         else
748                                 regs->ecntrl &= ~(ECNTRL_R100);
749                         break;
750                 default:
751                         printf("%s: Speed was bad\n", dev->name);
752                         break;
753                 }
754
755                 printf("Speed: %d, %s duplex\n", priv->speed,
756                        (priv->duplexity) ? "full" : "half");
757
758         } else {
759                 printf("%s: No link.\n", dev->name);
760         }
761 }
762
763 /* Set up the buffers and their descriptors, and bring up the
764  * interface
765  */
766 static void startup_tsec(struct eth_device *dev)
767 {
768         int i;
769         struct tsec_private *priv = (struct tsec_private *)dev->priv;
770         volatile tsec_t *regs = priv->regs;
771
772         /* Point to the buffer descriptors */
773         regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
774         regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
775
776         /* Initialize the Rx Buffer descriptors */
777         for (i = 0; i < PKTBUFSRX; i++) {
778                 rtx.rxbd[i].status = RXBD_EMPTY;
779                 rtx.rxbd[i].length = 0;
780                 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
781         }
782         rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
783
784         /* Initialize the TX Buffer Descriptors */
785         for (i = 0; i < TX_BUF_CNT; i++) {
786                 rtx.txbd[i].status = 0;
787                 rtx.txbd[i].length = 0;
788                 rtx.txbd[i].bufPtr = 0;
789         }
790         rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
791
792         /* Start up the PHY */
793         if(priv->phyinfo)
794                 phy_run_commands(priv, priv->phyinfo->startup);
795
796         adjust_link(dev);
797
798         /* Enable Transmit and Receive */
799         regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
800
801         /* Tell the DMA it is clear to go */
802         regs->dmactrl |= DMACTRL_INIT_SETTINGS;
803         regs->tstat = TSTAT_CLEAR_THALT;
804         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
805 }
806
807 /* This returns the status bits of the device.  The return value
808  * is never checked, and this is what the 8260 driver did, so we
809  * do the same.  Presumably, this would be zero if there were no
810  * errors
811  */
812 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
813 {
814         int i;
815         int result = 0;
816         struct tsec_private *priv = (struct tsec_private *)dev->priv;
817         volatile tsec_t *regs = priv->regs;
818
819         /* Find an empty buffer descriptor */
820         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
821                 if (i >= TOUT_LOOP) {
822                         debug("%s: tsec: tx buffers full\n", dev->name);
823                         return result;
824                 }
825         }
826
827         rtx.txbd[txIdx].bufPtr = (uint) packet;
828         rtx.txbd[txIdx].length = length;
829         rtx.txbd[txIdx].status |=
830             (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
831
832         /* Tell the DMA to go */
833         regs->tstat = TSTAT_CLEAR_THALT;
834
835         /* Wait for buffer to be transmitted */
836         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
837                 if (i >= TOUT_LOOP) {
838                         debug("%s: tsec: tx error\n", dev->name);
839                         return result;
840                 }
841         }
842
843         txIdx = (txIdx + 1) % TX_BUF_CNT;
844         result = rtx.txbd[txIdx].status & TXBD_STATS;
845
846         return result;
847 }
848
849 static int tsec_recv(struct eth_device *dev)
850 {
851         int length;
852         struct tsec_private *priv = (struct tsec_private *)dev->priv;
853         volatile tsec_t *regs = priv->regs;
854
855         while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
856
857                 length = rtx.rxbd[rxIdx].length;
858
859                 /* Send the packet up if there were no errors */
860                 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
861                         NetReceive(NetRxPackets[rxIdx], length - 4);
862                 } else {
863                         printf("Got error %x\n",
864                                (rtx.rxbd[rxIdx].status & RXBD_STATS));
865                 }
866
867                 rtx.rxbd[rxIdx].length = 0;
868
869                 /* Set the wrap bit if this is the last element in the list */
870                 rtx.rxbd[rxIdx].status =
871                     RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
872
873                 rxIdx = (rxIdx + 1) % PKTBUFSRX;
874         }
875
876         if (regs->ievent & IEVENT_BSY) {
877                 regs->ievent = IEVENT_BSY;
878                 regs->rstat = RSTAT_CLEAR_RHALT;
879         }
880
881         return -1;
882
883 }
884
885 /* Stop the interface */
886 static void tsec_halt(struct eth_device *dev)
887 {
888         struct tsec_private *priv = (struct tsec_private *)dev->priv;
889         volatile tsec_t *regs = priv->regs;
890
891         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
892         regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
893
894         while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
895
896         regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
897
898         /* Shut down the PHY, as needed */
899         if(priv->phyinfo)
900                 phy_run_commands(priv, priv->phyinfo->shutdown);
901 }
902
903 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
904 struct phy_info phy_info_BCM5461S = {
905         0x02060c1,      /* 5461 ID */
906         "Broadcom BCM5461S",
907         0, /* not clear to me what minor revisions we can shift away */
908         (struct phy_cmd[]) { /* config */
909                 /* Reset and configure the PHY */
910                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
911                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
912                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
913                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
914                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
915                 {miim_end,}
916         },
917         (struct phy_cmd[]) { /* startup */
918                 /* Status is read once to clear old link state */
919                 {MIIM_STATUS, miim_read, NULL},
920                 /* Auto-negotiate */
921                 {MIIM_STATUS, miim_read, &mii_parse_sr},
922                 /* Read the status */
923                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
924                 {miim_end,}
925         },
926         (struct phy_cmd[]) { /* shutdown */
927                 {miim_end,}
928         },
929 };
930
931 struct phy_info phy_info_M88E1011S = {
932         0x01410c6,
933         "Marvell 88E1011S",
934         4,
935         (struct phy_cmd[]){     /* config */
936                            /* Reset and configure the PHY */
937                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
938                            {0x1d, 0x1f, NULL},
939                            {0x1e, 0x200c, NULL},
940                            {0x1d, 0x5, NULL},
941                            {0x1e, 0x0, NULL},
942                            {0x1e, 0x100, NULL},
943                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
944                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
945                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
946                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
947                            {miim_end,}
948                            },
949         (struct phy_cmd[]){     /* startup */
950                            /* Status is read once to clear old link state */
951                            {MIIM_STATUS, miim_read, NULL},
952                            /* Auto-negotiate */
953                            {MIIM_STATUS, miim_read, &mii_parse_sr},
954                            /* Read the status */
955                            {MIIM_88E1011_PHY_STATUS, miim_read,
956                             &mii_parse_88E1011_psr},
957                            {miim_end,}
958                            },
959         (struct phy_cmd[]){     /* shutdown */
960                            {miim_end,}
961                            },
962 };
963
964 struct phy_info phy_info_M88E1111S = {
965         0x01410cc,
966         "Marvell 88E1111S",
967         4,
968         (struct phy_cmd[]){     /* config */
969                            /* Reset and configure the PHY */
970                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
971                            {0x1d, 0x1f, NULL},
972                            {0x1e, 0x200c, NULL},
973                            {0x1d, 0x5, NULL},
974                            {0x1e, 0x0, NULL},
975                            {0x1e, 0x100, NULL},
976                            {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
977                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
978                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
979                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
980                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
981                            {miim_end,}
982                            },
983         (struct phy_cmd[]){     /* startup */
984                            /* Status is read once to clear old link state */
985                            {MIIM_STATUS, miim_read, NULL},
986                            /* Auto-negotiate */
987                            {MIIM_STATUS, miim_read, &mii_parse_sr},
988                            /* Read the status */
989                            {MIIM_88E1011_PHY_STATUS, miim_read,
990                             &mii_parse_88E1011_psr},
991                            {miim_end,}
992                            },
993         (struct phy_cmd[]){     /* shutdown */
994                            {miim_end,}
995                            },
996 };
997
998 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
999 {
1000         uint mii_data = read_phy_reg(priv, mii_reg);
1001
1002         /* Setting MIIM_88E1145_PHY_EXT_CR */
1003         if (priv->flags & TSEC_REDUCED)
1004                 return mii_data |
1005                     MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1006         else
1007                 return mii_data;
1008 }
1009
1010 static struct phy_info phy_info_M88E1145 = {
1011         0x01410cd,
1012         "Marvell 88E1145",
1013         4,
1014         (struct phy_cmd[]){     /* config */
1015                            /* Errata E0, E1 */
1016                            {29, 0x001b, NULL},
1017                            {30, 0x418f, NULL},
1018                            {29, 0x0016, NULL},
1019                            {30, 0xa2da, NULL},
1020
1021                            /* Reset and configure the PHY */
1022                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1023                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1024                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1025                            {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
1026                             NULL},
1027                            {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1028                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1029                            {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1030                            {miim_end,}
1031                            },
1032         (struct phy_cmd[]){     /* startup */
1033                            /* Status is read once to clear old link state */
1034                            {MIIM_STATUS, miim_read, NULL},
1035                            /* Auto-negotiate */
1036                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1037                            {MIIM_88E1111_PHY_LED_CONTROL,
1038                             MIIM_88E1111_PHY_LED_DIRECT, NULL},
1039                            /* Read the Status */
1040                            {MIIM_88E1011_PHY_STATUS, miim_read,
1041                             &mii_parse_88E1011_psr},
1042                            {miim_end,}
1043                            },
1044         (struct phy_cmd[]){     /* shutdown */
1045                            {miim_end,}
1046                            },
1047 };
1048
1049 struct phy_info phy_info_cis8204 = {
1050         0x3f11,
1051         "Cicada Cis8204",
1052         6,
1053         (struct phy_cmd[]){     /* config */
1054                            /* Override PHY config settings */
1055                            {MIIM_CIS8201_AUX_CONSTAT,
1056                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1057                            /* Configure some basic stuff */
1058                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1059                            {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1060                             &mii_cis8204_fixled},
1061                            {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1062                             &mii_cis8204_setmode},
1063                            {miim_end,}
1064                            },
1065         (struct phy_cmd[]){     /* startup */
1066                            /* Read the Status (2x to make sure link is right) */
1067                            {MIIM_STATUS, miim_read, NULL},
1068                            /* Auto-negotiate */
1069                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1070                            /* Read the status */
1071                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1072                             &mii_parse_cis8201},
1073                            {miim_end,}
1074                            },
1075         (struct phy_cmd[]){     /* shutdown */
1076                            {miim_end,}
1077                            },
1078 };
1079
1080 /* Cicada 8201 */
1081 struct phy_info phy_info_cis8201 = {
1082         0xfc41,
1083         "CIS8201",
1084         4,
1085         (struct phy_cmd[]){     /* config */
1086                            /* Override PHY config settings */
1087                            {MIIM_CIS8201_AUX_CONSTAT,
1088                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1089                            /* Set up the interface mode */
1090                            {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1091                             NULL},
1092                            /* Configure some basic stuff */
1093                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1094                            {miim_end,}
1095                            },
1096         (struct phy_cmd[]){     /* startup */
1097                            /* Read the Status (2x to make sure link is right) */
1098                            {MIIM_STATUS, miim_read, NULL},
1099                            /* Auto-negotiate */
1100                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1101                            /* Read the status */
1102                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1103                             &mii_parse_cis8201},
1104                            {miim_end,}
1105                            },
1106         (struct phy_cmd[]){     /* shutdown */
1107                            {miim_end,}
1108                            },
1109 };
1110 struct phy_info phy_info_VSC8244 = {
1111         0x3f1b,
1112         "Vitesse VSC8244",
1113         6,
1114         (struct phy_cmd[]){     /* config */
1115                            /* Override PHY config settings */
1116                            /* Configure some basic stuff */
1117                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1118                            {miim_end,}
1119                            },
1120         (struct phy_cmd[]){     /* startup */
1121                            /* Read the Status (2x to make sure link is right) */
1122                            {MIIM_STATUS, miim_read, NULL},
1123                            /* Auto-negotiate */
1124                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1125                            /* Read the status */
1126                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1127                             &mii_parse_vsc8244},
1128                            {miim_end,}
1129                            },
1130         (struct phy_cmd[]){     /* shutdown */
1131                            {miim_end,}
1132                            },
1133 };
1134
1135 struct phy_info phy_info_dm9161 = {
1136         0x0181b88,
1137         "Davicom DM9161E",
1138         4,
1139         (struct phy_cmd[]){     /* config */
1140                            {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1141                            /* Do not bypass the scrambler/descrambler */
1142                            {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1143                            /* Clear 10BTCSR to default */
1144                            {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1145                             NULL},
1146                            /* Configure some basic stuff */
1147                            {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1148                            /* Restart Auto Negotiation */
1149                            {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1150                            {miim_end,}
1151                            },
1152         (struct phy_cmd[]){     /* startup */
1153                            /* Status is read once to clear old link state */
1154                            {MIIM_STATUS, miim_read, NULL},
1155                            /* Auto-negotiate */
1156                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1157                            /* Read the status */
1158                            {MIIM_DM9161_SCSR, miim_read,
1159                             &mii_parse_dm9161_scsr},
1160                            {miim_end,}
1161                            },
1162         (struct phy_cmd[]){     /* shutdown */
1163                            {miim_end,}
1164                            },
1165 };
1166 /* a generic flavor.  */
1167 struct phy_info phy_info_generic =  {
1168         0,
1169         "Unknown/Generic PHY",
1170         32,
1171         (struct phy_cmd[]) { /* config */
1172                 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1173                 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1174                 {miim_end,}
1175         },
1176         (struct phy_cmd[]) { /* startup */
1177                 {PHY_BMSR, miim_read, NULL},
1178                 {PHY_BMSR, miim_read, &mii_parse_sr},
1179                 {PHY_BMSR, miim_read, &mii_parse_link},
1180                 {miim_end,}
1181         },
1182         (struct phy_cmd[]) { /* shutdown */
1183                 {miim_end,}
1184         }
1185 };
1186
1187
1188 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1189 {
1190         unsigned int speed;
1191         if (priv->link) {
1192                 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1193
1194                 switch (speed) {
1195                 case MIIM_LXT971_SR2_10HDX:
1196                         priv->speed = 10;
1197                         priv->duplexity = 0;
1198                         break;
1199                 case MIIM_LXT971_SR2_10FDX:
1200                         priv->speed = 10;
1201                         priv->duplexity = 1;
1202                         break;
1203                 case MIIM_LXT971_SR2_100HDX:
1204                         priv->speed = 100;
1205                         priv->duplexity = 0;
1206                 default:
1207                         priv->speed = 100;
1208                         priv->duplexity = 1;
1209                         break;
1210                 }
1211         } else {
1212                 priv->speed = 0;
1213                 priv->duplexity = 0;
1214         }
1215
1216         return 0;
1217 }
1218
1219 static struct phy_info phy_info_lxt971 = {
1220         0x0001378e,
1221         "LXT971",
1222         4,
1223         (struct phy_cmd[]){     /* config */
1224                            {MIIM_CR, MIIM_CR_INIT, mii_cr_init},        /* autonegotiate */
1225                            {miim_end,}
1226                            },
1227         (struct phy_cmd[]){     /* startup - enable interrupts */
1228                            /* { 0x12, 0x00f2, NULL }, */
1229                            {MIIM_STATUS, miim_read, NULL},
1230                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1231                            {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1232                            {miim_end,}
1233                            },
1234         (struct phy_cmd[]){     /* shutdown - disable interrupts */
1235                            {miim_end,}
1236                            },
1237 };
1238
1239 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1240  * information
1241  */
1242 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1243 {
1244         switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1245
1246         case MIIM_DP83865_SPD_1000:
1247                 priv->speed = 1000;
1248                 break;
1249
1250         case MIIM_DP83865_SPD_100:
1251                 priv->speed = 100;
1252                 break;
1253
1254         default:
1255                 priv->speed = 10;
1256                 break;
1257
1258         }
1259
1260         if (mii_reg & MIIM_DP83865_DPX_FULL)
1261                 priv->duplexity = 1;
1262         else
1263                 priv->duplexity = 0;
1264
1265         return 0;
1266 }
1267
1268 struct phy_info phy_info_dp83865 = {
1269         0x20005c7,
1270         "NatSemi DP83865",
1271         4,
1272         (struct phy_cmd[]){     /* config */
1273                            {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1274                            {miim_end,}
1275                            },
1276         (struct phy_cmd[]){     /* startup */
1277                            /* Status is read once to clear old link state */
1278                            {MIIM_STATUS, miim_read, NULL},
1279                            /* Auto-negotiate */
1280                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1281                            /* Read the link and auto-neg status */
1282                            {MIIM_DP83865_LANR, miim_read,
1283                             &mii_parse_dp83865_lanr},
1284                            {miim_end,}
1285                            },
1286         (struct phy_cmd[]){     /* shutdown */
1287                            {miim_end,}
1288                            },
1289 };
1290
1291 struct phy_info *phy_info[] = {
1292         &phy_info_cis8204,
1293         &phy_info_cis8201,
1294         &phy_info_BCM5461S,
1295         &phy_info_M88E1011S,
1296         &phy_info_M88E1111S,
1297         &phy_info_M88E1145,
1298         &phy_info_dm9161,
1299         &phy_info_lxt971,
1300         &phy_info_VSC8244,
1301         &phy_info_dp83865,
1302         &phy_info_generic,
1303         NULL
1304 };
1305
1306 /* Grab the identifier of the device's PHY, and search through
1307  * all of the known PHYs to see if one matches.  If so, return
1308  * it, if not, return NULL
1309  */
1310 struct phy_info *get_phy_info(struct eth_device *dev)
1311 {
1312         struct tsec_private *priv = (struct tsec_private *)dev->priv;
1313         uint phy_reg, phy_ID;
1314         int i;
1315         struct phy_info *theInfo = NULL;
1316
1317         /* Grab the bits from PHYIR1, and put them in the upper half */
1318         phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1319         phy_ID = (phy_reg & 0xffff) << 16;
1320
1321         /* Grab the bits from PHYIR2, and put them in the lower half */
1322         phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1323         phy_ID |= (phy_reg & 0xffff);
1324
1325         /* loop through all the known PHY types, and find one that */
1326         /* matches the ID we read from the PHY. */
1327         for (i = 0; phy_info[i]; i++) {
1328                 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
1329                         theInfo = phy_info[i];
1330         }
1331
1332         if (theInfo == NULL) {
1333                 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1334                 return NULL;
1335         } else {
1336                 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1337         }
1338
1339         return theInfo;
1340 }
1341
1342 /* Execute the given series of commands on the given device's
1343  * PHY, running functions as necessary
1344  */
1345 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1346 {
1347         int i;
1348         uint result;
1349         volatile tsec_t *phyregs = priv->phyregs;
1350
1351         phyregs->miimcfg = MIIMCFG_RESET;
1352
1353         phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1354
1355         while (phyregs->miimind & MIIMIND_BUSY) ;
1356
1357         for (i = 0; cmd->mii_reg != miim_end; i++) {
1358                 if (cmd->mii_data == miim_read) {
1359                         result = read_phy_reg(priv, cmd->mii_reg);
1360
1361                         if (cmd->funct != NULL)
1362                                 (*(cmd->funct)) (result, priv);
1363
1364                 } else {
1365                         if (cmd->funct != NULL)
1366                                 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1367                         else
1368                                 result = cmd->mii_data;
1369
1370                         write_phy_reg(priv, cmd->mii_reg, result);
1371
1372                 }
1373                 cmd++;
1374         }
1375 }
1376
1377 /* Relocate the function pointers in the phy cmd lists */
1378 static void relocate_cmds(void)
1379 {
1380         struct phy_cmd **cmdlistptr;
1381         struct phy_cmd *cmd;
1382         int i, j, k;
1383
1384         for (i = 0; phy_info[i]; i++) {
1385                 /* First thing's first: relocate the pointers to the
1386                  * PHY command structures (the structs were done) */
1387                 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1388                                                   + gd->reloc_off);
1389                 phy_info[i]->name += gd->reloc_off;
1390                 phy_info[i]->config =
1391                     (struct phy_cmd *)((uint) phy_info[i]->config
1392                                        + gd->reloc_off);
1393                 phy_info[i]->startup =
1394                     (struct phy_cmd *)((uint) phy_info[i]->startup
1395                                        + gd->reloc_off);
1396                 phy_info[i]->shutdown =
1397                     (struct phy_cmd *)((uint) phy_info[i]->shutdown
1398                                        + gd->reloc_off);
1399
1400                 cmdlistptr = &phy_info[i]->config;
1401                 j = 0;
1402                 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1403                         k = 0;
1404                         for (cmd = *cmdlistptr;
1405                              cmd->mii_reg != miim_end;
1406                              cmd++) {
1407                                 /* Only relocate non-NULL pointers */
1408                                 if (cmd->funct)
1409                                         cmd->funct += gd->reloc_off;
1410
1411                                 k++;
1412                         }
1413                         j++;
1414                 }
1415         }
1416
1417         relocated = 1;
1418 }
1419
1420 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
1421         && !defined(BITBANGMII)
1422
1423 struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
1424 {
1425         int i;
1426
1427         for (i = 0; i < MAXCONTROLLERS; i++) {
1428                 if (privlist[i]->phyaddr == phyaddr)
1429                         return privlist[i];
1430         }
1431
1432         return NULL;
1433 }
1434
1435 /*
1436  * Read a MII PHY register.
1437  *
1438  * Returns:
1439  *  0 on success
1440  */
1441 static int tsec_miiphy_read(char *devname, unsigned char addr,
1442                             unsigned char reg, unsigned short *value)
1443 {
1444         unsigned short ret;
1445         struct tsec_private *priv = get_priv_for_phy(addr);
1446
1447         if (NULL == priv) {
1448                 printf("Can't read PHY at address %d\n", addr);
1449                 return -1;
1450         }
1451
1452         ret = (unsigned short)read_phy_reg(priv, reg);
1453         *value = ret;
1454
1455         return 0;
1456 }
1457
1458 /*
1459  * Write a MII PHY register.
1460  *
1461  * Returns:
1462  *  0 on success
1463  */
1464 static int tsec_miiphy_write(char *devname, unsigned char addr,
1465                              unsigned char reg, unsigned short value)
1466 {
1467         struct tsec_private *priv = get_priv_for_phy(addr);
1468
1469         if (NULL == priv) {
1470                 printf("Can't write PHY at address %d\n", addr);
1471                 return -1;
1472         }
1473
1474         write_phy_reg(priv, reg, value);
1475
1476         return 0;
1477 }
1478
1479 #endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1480                 && !defined(BITBANGMII) */
1481
1482 #endif /* CONFIG_TSEC_ENET */