drivers/tsec.c

   1 /*
   2  * Freescale Three Speed Ethernet Controller driver
   3  *
   4  * This software may be used and distributed according to the
   5  * terms of the GNU Public License, Version 2, incorporated
   6  * herein by reference.
   7  *
   8  * Copyright 2004, 2007 Freescale Semiconductor, Inc.
   9  * (C) Copyright 2003, Motorola, Inc.
  10  * author Andy Fleming
  11  *
  12  */
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <command.h>
  19
  20 #if defined(CONFIG_TSEC_ENET)
  21 #include "tsec.h"
  22 #include "miiphy.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define TX_BUF_CNT              2
  27
  28 static uint rxIdx;              /* index of the current RX buffer */
  29 static uint txIdx;              /* index of the current TX buffer */
  30
  31 typedef volatile struct rtxbd {
  32         txbd8_t txbd[TX_BUF_CNT];
  33         rxbd8_t rxbd[PKTBUFSRX];
  34 } RTXBD;
  35
  36 struct tsec_info_struct {
  37         unsigned int phyaddr;
  38         u32 flags;
  39         unsigned int phyregidx;
  40 };
  41
  42 /* The tsec_info structure contains 3 values which the
  43  * driver uses to determine how to operate a given ethernet
  44  * device. The information needed is:
  45  *  phyaddr - The address of the PHY which is attached to
  46  *      the given device.
  47  *
  48  *  flags - This variable indicates whether the device
  49  *      supports gigabit speed ethernet, and whether it should be
  50  *      in reduced mode.
  51  *
  52  *  phyregidx - This variable specifies which ethernet device
  53  *      controls the MII Management registers which are connected
  54  *      to the PHY.  For now, only TSEC1 (index 0) has
  55  *      access to the PHYs, so all of the entries have "0".
  56  *
  57  * The values specified in the table are taken from the board's
  58  * config file in include/configs/.  When implementing a new
  59  * board with ethernet capability, it is necessary to define:
  60  *   TSECn_PHY_ADDR
  61  *   TSECn_PHYIDX
  62  *
  63  * for n = 1,2,3, etc.  And for FEC:
  64  *   FEC_PHY_ADDR
  65  *   FEC_PHYIDX
  66  */
  67 static struct tsec_info_struct tsec_info[] = {
  68 #if defined(CONFIG_TSEC1)
  69 #if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN)
  70         {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
  71 #else
  72         {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
  73 #endif
  74 #else
  75         {0, 0, 0},
  76 #endif
  77 #if defined(CONFIG_TSEC2)
  78 #if defined(CONFIG_MPC8641HPCN)
  79         {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
  80 #else
  81         {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
  82 #endif
  83 #else
  84         {0, 0, 0},
  85 #endif
  86 #ifdef CONFIG_MPC85XX_FEC
  87         {FEC_PHY_ADDR, 0, FEC_PHYIDX},
  88 #else
  89 #if defined(CONFIG_TSEC3)
  90         {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
  91 #else
  92         {0, 0, 0},
  93 #endif
  94 #if defined(CONFIG_TSEC4)
  95         {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
  96 #else
  97         {0, 0, 0},
  98 #endif
  99 #endif
 100 };
 101
 102 #define MAXCONTROLLERS  (4)
 103
 104 static int relocated = 0;
 105
 106 static struct tsec_private *privlist[MAXCONTROLLERS];
 107
 108 #ifdef __GNUC__
 109 static RTXBD rtx __attribute__ ((aligned(8)));
 110 #else
 111 #error "rtx must be 64-bit aligned"
 112 #endif
 113
 114 static int tsec_send(struct eth_device *dev,
 115                      volatile void *packet, int length);
 116 static int tsec_recv(struct eth_device *dev);
 117 static int tsec_init(struct eth_device *dev, bd_t * bd);
 118 static void tsec_halt(struct eth_device *dev);
 119 static void init_registers(volatile tsec_t * regs);
 120 static void startup_tsec(struct eth_device *dev);
 121 static int init_phy(struct eth_device *dev);
 122 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
 123 uint read_phy_reg(struct tsec_private *priv, uint regnum);
 124 struct phy_info *get_phy_info(struct eth_device *dev);
 125 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
 126 static void adjust_link(struct eth_device *dev);
 127 static void relocate_cmds(void);
 128 static int tsec_miiphy_write(char *devname, unsigned char addr,
 129                              unsigned char reg, unsigned short value);
 130 static int tsec_miiphy_read(char *devname, unsigned char addr,
 131                             unsigned char reg, unsigned short *value);
 132
 133 /* Initialize device structure. Returns success if PHY
 134  * initialization succeeded (i.e. if it recognizes the PHY)
 135  */
 136 int tsec_initialize(bd_t * bis, int index, char *devname)
 137 {
 138         struct eth_device *dev;
 139         int i;
 140         struct tsec_private *priv;
 141
 142         dev = (struct eth_device *)malloc(sizeof *dev);
 143
 144         if (NULL == dev)
 145                 return 0;
 146
 147         memset(dev, 0, sizeof *dev);
 148
 149         priv = (struct tsec_private *)malloc(sizeof(*priv));
 150
 151         if (NULL == priv)
 152                 return 0;
 153
 154         privlist[index] = priv;
 155         priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
 156         priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
 157                                             tsec_info[index].phyregidx *
 158                                             TSEC_SIZE);
 159
 160         priv->phyaddr = tsec_info[index].phyaddr;
 161         priv->flags = tsec_info[index].flags;
 162
 163         sprintf(dev->name, devname);
 164         dev->iobase = 0;
 165         dev->priv = priv;
 166         dev->init = tsec_init;
 167         dev->halt = tsec_halt;
 168         dev->send = tsec_send;
 169         dev->recv = tsec_recv;
 170
 171         /* Tell u-boot to get the addr from the env */
 172         for (i = 0; i < 6; i++)
 173                 dev->enetaddr[i] = 0;
 174
 175         eth_register(dev);
 176
 177         /* Reset the MAC */
 178         priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
 179         priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
 180
 181 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
 182         && !defined(BITBANGMII)
 183         miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
 184 #endif
 185
 186         /* Try to initialize PHY here, and return */
 187         return init_phy(dev);
 188 }
 189
 190 /* Initializes data structures and registers for the controller,
 191  * and brings the interface up.  Returns the link status, meaning
 192  * that it returns success if the link is up, failure otherwise.
 193  * This allows u-boot to find the first active controller.
 194  */
 195 int tsec_init(struct eth_device *dev, bd_t * bd)
 196 {
 197         uint tempval;
 198         char tmpbuf[MAC_ADDR_LEN];
 199         int i;
 200         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 201         volatile tsec_t *regs = priv->regs;
 202
 203         /* Make sure the controller is stopped */
 204         tsec_halt(dev);
 205
 206         /* Init MACCFG2.  Defaults to GMII */
 207         regs->maccfg2 = MACCFG2_INIT_SETTINGS;
 208
 209         /* Init ECNTRL */
 210         regs->ecntrl = ECNTRL_INIT_SETTINGS;
 211
 212         /* Copy the station address into the address registers.
 213          * Backwards, because little endian MACS are dumb */
 214         for (i = 0; i < MAC_ADDR_LEN; i++) {
 215                 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
 216         }
 217         regs->macstnaddr1 = *((uint *) (tmpbuf));
 218
 219         tempval = *((uint *) (tmpbuf + 4));
 220
 221         regs->macstnaddr2 = tempval;
 222
 223         /* reset the indices to zero */
 224         rxIdx = 0;
 225         txIdx = 0;
 226
 227         /* Clear out (for the most part) the other registers */
 228         init_registers(regs);
 229
 230         /* Ready the device for tx/rx */
 231         startup_tsec(dev);
 232
 233         /* If there's no link, fail */
 234         return priv->link;
 235
 236 }
 237
 238 /* Write value to the device's PHY through the registers
 239  * specified in priv, modifying the register specified in regnum.
 240  * It will wait for the write to be done (or for a timeout to
 241  * expire) before exiting
 242  */
 243 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
 244 {
 245         volatile tsec_t *regbase = priv->phyregs;
 246         uint phyid = priv->phyaddr;
 247         int timeout = 1000000;
 248
 249         regbase->miimadd = (phyid << 8) | regnum;
 250         regbase->miimcon = value;
 251         asm("sync");
 252
 253         timeout = 1000000;
 254         while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 255 }
 256
 257 /* Reads register regnum on the device's PHY through the
 258  * registers specified in priv.  It lowers and raises the read
 259  * command, and waits for the data to become valid (miimind
 260  * notvalid bit cleared), and the bus to cease activity (miimind
 261  * busy bit cleared), and then returns the value
 262  */
 263 uint read_phy_reg(struct tsec_private *priv, uint regnum)
 264 {
 265         uint value;
 266         volatile tsec_t *regbase = priv->phyregs;
 267         uint phyid = priv->phyaddr;
 268
 269         /* Put the address of the phy, and the register
 270          * number into MIIMADD */
 271         regbase->miimadd = (phyid << 8) | regnum;
 272
 273         /* Clear the command register, and wait */
 274         regbase->miimcom = 0;
 275         asm("sync");
 276
 277         /* Initiate a read command, and wait */
 278         regbase->miimcom = MIIM_READ_COMMAND;
 279         asm("sync");
 280
 281         /* Wait for the the indication that the read is done */
 282         while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
 283
 284         /* Grab the value read from the PHY */
 285         value = regbase->miimstat;
 286
 287         return value;
 288 }
 289
 290 /* Discover which PHY is attached to the device, and configure it
 291  * properly.  If the PHY is not recognized, then return 0
 292  * (failure).  Otherwise, return 1
 293  */
 294 static int init_phy(struct eth_device *dev)
 295 {
 296         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 297         struct phy_info *curphy;
 298         volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
 299
 300         /* Assign a Physical address to the TBI */
 301         regs->tbipa = CFG_TBIPA_VALUE;
 302         regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
 303         regs->tbipa = CFG_TBIPA_VALUE;
 304         asm("sync");
 305
 306         /* Reset MII (due to new addresses) */
 307         priv->phyregs->miimcfg = MIIMCFG_RESET;
 308         asm("sync");
 309         priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
 310         asm("sync");
 311         while (priv->phyregs->miimind & MIIMIND_BUSY) ;
 312
 313         if (0 == relocated)
 314                 relocate_cmds();
 315
 316         /* Get the cmd structure corresponding to the attached
 317          * PHY */
 318         curphy = get_phy_info(dev);
 319
 320         if (curphy == NULL) {
 321                 priv->phyinfo = NULL;
 322                 printf("%s: No PHY found\n", dev->name);
 323
 324                 return 0;
 325         }
 326
 327         priv->phyinfo = curphy;
 328
 329         phy_run_commands(priv, priv->phyinfo->config);
 330
 331         return 1;
 332 }
 333
 334 /*
 335  * Returns which value to write to the control register.
 336  * For 10/100, the value is slightly different
 337  */
 338 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
 339 {
 340         if (priv->flags & TSEC_GIGABIT)
 341                 return MIIM_CONTROL_INIT;
 342         else
 343                 return MIIM_CR_INIT;
 344 }
 345
 346 /* Parse the status register for link, and then do
 347  * auto-negotiation
 348  */
 349 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 350 {
 351         /*
 352          * Wait if PHY is capable of autonegotiation and autonegotiation
 353          * is not complete.
 354          */
 355         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 356         if ((mii_reg & PHY_BMSR_AUTN_ABLE)
 357             && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
 358                 int i = 0;
 359
 360                 puts("Waiting for PHY auto negotiation to complete");
 361                 while (!((mii_reg & PHY_BMSR_AUTN_COMP)
 362                          && (mii_reg & MIIM_STATUS_LINK))) {
 363                         /*
 364                          * Timeout reached ?
 365                          */
 366                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 367                                 puts(" TIMEOUT !\n");
 368                                 priv->link = 0;
 369                                 return 0;
 370                         }
 371
 372                         if ((i++ % 1000) == 0) {
 373                                 putc('.');
 374                         }
 375                         udelay(1000);   /* 1 ms */
 376                         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 377                 }
 378                 puts(" done\n");
 379                 priv->link = 1;
 380                 udelay(500000); /* another 500 ms (results in faster booting) */
 381         } else {
 382                 priv->link = 1;
 383         }
 384
 385         return 0;
 386 }
 387
 388 /* Generic function which updates the speed and duplex.  If
 389  * autonegotiation is enabled, it uses the AND of the link
 390  * partner's advertised capabilities and our advertised
 391  * capabilities.  If autonegotiation is disabled, we use the
 392  * appropriate bits in the control register.
 393  *
 394  * Stolen from Linux's mii.c and phy_device.c
 395  */
 396 uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
 397 {
 398         /* We're using autonegotiation */
 399         if (mii_reg & PHY_BMSR_AUTN_ABLE) {
 400                 uint lpa = 0;
 401                 uint gblpa = 0;
 402
 403                 /* Check for gigabit capability */
 404                 if (mii_reg & PHY_BMSR_EXT) {
 405                         /* We want a list of states supported by
 406                          * both PHYs in the link
 407                          */
 408                         gblpa = read_phy_reg(priv, PHY_1000BTSR);
 409                         gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
 410                 }
 411
 412                 /* Set the baseline so we only have to set them
 413                  * if they're different
 414                  */
 415                 priv->speed = 10;
 416                 priv->duplexity = 0;
 417
 418                 /* Check the gigabit fields */
 419                 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
 420                         priv->speed = 1000;
 421
 422                         if (gblpa & PHY_1000BTSR_1000FD)
 423                                 priv->duplexity = 1;
 424
 425                         /* We're done! */
 426                         return 0;
 427                 }
 428
 429                 lpa = read_phy_reg(priv, PHY_ANAR);
 430                 lpa &= read_phy_reg(priv, PHY_ANLPAR);
 431
 432                 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
 433                         priv->speed = 100;
 434
 435                         if (lpa & PHY_ANLPAR_TXFD)
 436                                 priv->duplexity = 1;
 437
 438                 } else if (lpa & PHY_ANLPAR_10FD)
 439                         priv->duplexity = 1;
 440         } else {
 441                 uint bmcr = read_phy_reg(priv, PHY_BMCR);
 442
 443                 priv->speed = 10;
 444                 priv->duplexity = 0;
 445
 446                 if (bmcr & PHY_BMCR_DPLX)
 447                         priv->duplexity = 1;
 448
 449                 if (bmcr & PHY_BMCR_1000_MBPS)
 450                         priv->speed = 1000;
 451                 else if (bmcr & PHY_BMCR_100_MBPS)
 452                         priv->speed = 100;
 453         }
 454
 455         return 0;
 456 }
 457
 458 /*
 459  * Parse the BCM54xx status register for speed and duplex information.
 460  * The linux sungem_phy has this information, but in a table format.
 461  */
 462 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
 463 {
 464
 465         switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
 466
 467                 case 1:
 468                         printf("Enet starting in 10BT/HD\n");
 469                         priv->duplexity = 0;
 470                         priv->speed = 10;
 471                         break;
 472
 473                 case 2:
 474                         printf("Enet starting in 10BT/FD\n");
 475                         priv->duplexity = 1;
 476                         priv->speed = 10;
 477                         break;
 478
 479                 case 3:
 480                         printf("Enet starting in 100BT/HD\n");
 481                         priv->duplexity = 0;
 482                         priv->speed = 100;
 483                         break;
 484
 485                 case 5:
 486                         printf("Enet starting in 100BT/FD\n");
 487                         priv->duplexity = 1;
 488                         priv->speed = 100;
 489                         break;
 490
 491                 case 6:
 492                         printf("Enet starting in 1000BT/HD\n");
 493                         priv->duplexity = 0;
 494                         priv->speed = 1000;
 495                         break;
 496
 497                 case 7:
 498                         printf("Enet starting in 1000BT/FD\n");
 499                         priv->duplexity = 1;
 500                         priv->speed = 1000;
 501                         break;
 502
 503                 default:
 504                         printf("Auto-neg error, defaulting to 10BT/HD\n");
 505                         priv->duplexity = 0;
 506                         priv->speed = 10;
 507                         break;
 508         }
 509
 510         return 0;
 511
 512 }
 513 /* Parse the 88E1011's status register for speed and duplex
 514  * information
 515  */
 516 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
 517 {
 518         uint speed;
 519
 520         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 521
 522         if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
 523               (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
 524                 int i = 0;
 525
 526                 puts("Waiting for PHY realtime link");
 527                 while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
 528                          (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
 529                         /*
 530                          * Timeout reached ?
 531                          */
 532                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 533                                 puts(" TIMEOUT !\n");
 534                                 priv->link = 0;
 535                                 break;
 536                         }
 537
 538                         if ((i++ % 1000) == 0) {
 539                                 putc('.');
 540                         }
 541                         udelay(1000);   /* 1 ms */
 542                         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 543                 }
 544                 puts(" done\n");
 545                 udelay(500000); /* another 500 ms (results in faster booting) */
 546         }
 547
 548         if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
 549                 priv->duplexity = 1;
 550         else
 551                 priv->duplexity = 0;
 552
 553         speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
 554
 555         switch (speed) {
 556         case MIIM_88E1011_PHYSTAT_GBIT:
 557                 priv->speed = 1000;
 558                 break;
 559         case MIIM_88E1011_PHYSTAT_100:
 560                 priv->speed = 100;
 561                 break;
 562         default:
 563                 priv->speed = 10;
 564         }
 565
 566         return 0;
 567 }
 568
 569 /* Parse the cis8201's status register for speed and duplex
 570  * information
 571  */
 572 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
 573 {
 574         uint speed;
 575
 576         if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
 577                 priv->duplexity = 1;
 578         else
 579                 priv->duplexity = 0;
 580
 581         speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
 582         switch (speed) {
 583         case MIIM_CIS8201_AUXCONSTAT_GBIT:
 584                 priv->speed = 1000;
 585                 break;
 586         case MIIM_CIS8201_AUXCONSTAT_100:
 587                 priv->speed = 100;
 588                 break;
 589         default:
 590                 priv->speed = 10;
 591                 break;
 592         }
 593
 594         return 0;
 595 }
 596
 597 /* Parse the vsc8244's status register for speed and duplex
 598  * information
 599  */
 600 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
 601 {
 602         uint speed;
 603
 604         if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
 605                 priv->duplexity = 1;
 606         else
 607                 priv->duplexity = 0;
 608
 609         speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
 610         switch (speed) {
 611         case MIIM_VSC8244_AUXCONSTAT_GBIT:
 612                 priv->speed = 1000;
 613                 break;
 614         case MIIM_VSC8244_AUXCONSTAT_100:
 615                 priv->speed = 100;
 616                 break;
 617         default:
 618                 priv->speed = 10;
 619                 break;
 620         }
 621
 622         return 0;
 623 }
 624
 625 /* Parse the DM9161's status register for speed and duplex
 626  * information
 627  */
 628 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
 629 {
 630         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
 631                 priv->speed = 100;
 632         else
 633                 priv->speed = 10;
 634
 635         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
 636                 priv->duplexity = 1;
 637         else
 638                 priv->duplexity = 0;
 639
 640         return 0;
 641 }
 642
 643 /*
 644  * Hack to write all 4 PHYs with the LED values
 645  */
 646 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
 647 {
 648         uint phyid;
 649         volatile tsec_t *regbase = priv->phyregs;
 650         int timeout = 1000000;
 651
 652         for (phyid = 0; phyid < 4; phyid++) {
 653                 regbase->miimadd = (phyid << 8) | mii_reg;
 654                 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
 655                 asm("sync");
 656
 657                 timeout = 1000000;
 658                 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 659         }
 660
 661         return MIIM_CIS8204_SLEDCON_INIT;
 662 }
 663
 664 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
 665 {
 666         if (priv->flags & TSEC_REDUCED)
 667                 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
 668         else
 669                 return MIIM_CIS8204_EPHYCON_INIT;
 670 }
 671
 672 /* Initialized required registers to appropriate values, zeroing
 673  * those we don't care about (unless zero is bad, in which case,
 674  * choose a more appropriate value)
 675  */
 676 static void init_registers(volatile tsec_t * regs)
 677 {
 678         /* Clear IEVENT */
 679         regs->ievent = IEVENT_INIT_CLEAR;
 680
 681         regs->imask = IMASK_INIT_CLEAR;
 682
 683         regs->hash.iaddr0 = 0;
 684         regs->hash.iaddr1 = 0;
 685         regs->hash.iaddr2 = 0;
 686         regs->hash.iaddr3 = 0;
 687         regs->hash.iaddr4 = 0;
 688         regs->hash.iaddr5 = 0;
 689         regs->hash.iaddr6 = 0;
 690         regs->hash.iaddr7 = 0;
 691
 692         regs->hash.gaddr0 = 0;
 693         regs->hash.gaddr1 = 0;
 694         regs->hash.gaddr2 = 0;
 695         regs->hash.gaddr3 = 0;
 696         regs->hash.gaddr4 = 0;
 697         regs->hash.gaddr5 = 0;
 698         regs->hash.gaddr6 = 0;
 699         regs->hash.gaddr7 = 0;
 700
 701         regs->rctrl = 0x00000000;
 702
 703         /* Init RMON mib registers */
 704         memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
 705
 706         regs->rmon.cam1 = 0xffffffff;
 707         regs->rmon.cam2 = 0xffffffff;
 708
 709         regs->mrblr = MRBLR_INIT_SETTINGS;
 710
 711         regs->minflr = MINFLR_INIT_SETTINGS;
 712
 713         regs->attr = ATTR_INIT_SETTINGS;
 714         regs->attreli = ATTRELI_INIT_SETTINGS;
 715
 716 }
 717
 718 /* Configure maccfg2 based on negotiated speed and duplex
 719  * reported by PHY handling code
 720  */
 721 static void adjust_link(struct eth_device *dev)
 722 {
 723         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 724         volatile tsec_t *regs = priv->regs;
 725
 726         if (priv->link) {
 727                 if (priv->duplexity != 0)
 728                         regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
 729                 else
 730                         regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
 731
 732                 switch (priv->speed) {
 733                 case 1000:
 734                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 735                                          | MACCFG2_GMII);
 736                         break;
 737                 case 100:
 738                 case 10:
 739                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 740                                          | MACCFG2_MII);
 741
 742                         /* Set R100 bit in all modes although
 743                          * it is only used in RGMII mode
 744                          */
 745                         if (priv->speed == 100)
 746                                 regs->ecntrl |= ECNTRL_R100;
 747                         else
 748                                 regs->ecntrl &= ~(ECNTRL_R100);
 749                         break;
 750                 default:
 751                         printf("%s: Speed was bad\n", dev->name);
 752                         break;
 753                 }
 754
 755                 printf("Speed: %d, %s duplex\n", priv->speed,
 756                        (priv->duplexity) ? "full" : "half");
 757
 758         } else {
 759                 printf("%s: No link.\n", dev->name);
 760         }
 761 }
 762
 763 /* Set up the buffers and their descriptors, and bring up the
 764  * interface
 765  */
 766 static void startup_tsec(struct eth_device *dev)
 767 {
 768         int i;
 769         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 770         volatile tsec_t *regs = priv->regs;
 771
 772         /* Point to the buffer descriptors */
 773         regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
 774         regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
 775
 776         /* Initialize the Rx Buffer descriptors */
 777         for (i = 0; i < PKTBUFSRX; i++) {
 778                 rtx.rxbd[i].status = RXBD_EMPTY;
 779                 rtx.rxbd[i].length = 0;
 780                 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
 781         }
 782         rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
 783
 784         /* Initialize the TX Buffer Descriptors */
 785         for (i = 0; i < TX_BUF_CNT; i++) {
 786                 rtx.txbd[i].status = 0;
 787                 rtx.txbd[i].length = 0;
 788                 rtx.txbd[i].bufPtr = 0;
 789         }
 790         rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
 791
 792         /* Start up the PHY */
 793         if(priv->phyinfo)
 794                 phy_run_commands(priv, priv->phyinfo->startup);
 795
 796         adjust_link(dev);
 797
 798         /* Enable Transmit and Receive */
 799         regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 800
 801         /* Tell the DMA it is clear to go */
 802         regs->dmactrl |= DMACTRL_INIT_SETTINGS;
 803         regs->tstat = TSTAT_CLEAR_THALT;
 804         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 805 }
 806
 807 /* This returns the status bits of the device.  The return value
 808  * is never checked, and this is what the 8260 driver did, so we
 809  * do the same.  Presumably, this would be zero if there were no
 810  * errors
 811  */
 812 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
 813 {
 814         int i;
 815         int result = 0;
 816         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 817         volatile tsec_t *regs = priv->regs;
 818
 819         /* Find an empty buffer descriptor */
 820         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 821                 if (i >= TOUT_LOOP) {
 822                         debug("%s: tsec: tx buffers full\n", dev->name);
 823                         return result;
 824                 }
 825         }
 826
 827         rtx.txbd[txIdx].bufPtr = (uint) packet;
 828         rtx.txbd[txIdx].length = length;
 829         rtx.txbd[txIdx].status |=
 830             (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
 831
 832         /* Tell the DMA to go */
 833         regs->tstat = TSTAT_CLEAR_THALT;
 834
 835         /* Wait for buffer to be transmitted */
 836         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 837                 if (i >= TOUT_LOOP) {
 838                         debug("%s: tsec: tx error\n", dev->name);
 839                         return result;
 840                 }
 841         }
 842
 843         txIdx = (txIdx + 1) % TX_BUF_CNT;
 844         result = rtx.txbd[txIdx].status & TXBD_STATS;
 845
 846         return result;
 847 }
 848
 849 static int tsec_recv(struct eth_device *dev)
 850 {
 851         int length;
 852         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 853         volatile tsec_t *regs = priv->regs;
 854
 855         while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
 856
 857                 length = rtx.rxbd[rxIdx].length;
 858
 859                 /* Send the packet up if there were no errors */
 860                 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
 861                         NetReceive(NetRxPackets[rxIdx], length - 4);
 862                 } else {
 863                         printf("Got error %x\n",
 864                                (rtx.rxbd[rxIdx].status & RXBD_STATS));
 865                 }
 866
 867                 rtx.rxbd[rxIdx].length = 0;
 868
 869                 /* Set the wrap bit if this is the last element in the list */
 870                 rtx.rxbd[rxIdx].status =
 871                     RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
 872
 873                 rxIdx = (rxIdx + 1) % PKTBUFSRX;
 874         }
 875
 876         if (regs->ievent & IEVENT_BSY) {
 877                 regs->ievent = IEVENT_BSY;
 878                 regs->rstat = RSTAT_CLEAR_RHALT;
 879         }
 880
 881         return -1;
 882
 883 }
 884
 885 /* Stop the interface */
 886 static void tsec_halt(struct eth_device *dev)
 887 {
 888         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 889         volatile tsec_t *regs = priv->regs;
 890
 891         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 892         regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
 893
 894         while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
 895
 896         regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
 897
 898         /* Shut down the PHY, as needed */
 899         if(priv->phyinfo)
 900                 phy_run_commands(priv, priv->phyinfo->shutdown);
 901 }
 902
 903 struct phy_info phy_info_M88E1149S = {
 904         0x1410ca,
 905         "Marvell 88E1149S",
 906         4,
 907         (struct phy_cmd[]){     /* config */
 908                 /* Reset and configure the PHY */
 909                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 910                 {0x1d, 0x1f, NULL},
 911                 {0x1e, 0x200c, NULL},
 912                 {0x1d, 0x5, NULL},
 913                 {0x1e, 0x0, NULL},
 914                 {0x1e, 0x100, NULL},
 915                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 916                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 917                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 918                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 919                 {miim_end,}
 920         },
 921         (struct phy_cmd[]){     /* startup */
 922                 /* Status is read once to clear old link state */
 923                 {MIIM_STATUS, miim_read, NULL},
 924                 /* Auto-negotiate */
 925                 {MIIM_STATUS, miim_read, &mii_parse_sr},
 926                 /* Read the status */
 927                 {MIIM_88E1011_PHY_STATUS, miim_read,
 928                  &mii_parse_88E1011_psr},
 929                 {miim_end,}
 930         },
 931         (struct phy_cmd[]){     /* shutdown */
 932                 {miim_end,}
 933         },
 934 };
 935
 936 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
 937 struct phy_info phy_info_BCM5461S = {
 938         0x02060c1,      /* 5461 ID */
 939         "Broadcom BCM5461S",
 940         0, /* not clear to me what minor revisions we can shift away */
 941         (struct phy_cmd[]) { /* config */
 942                 /* Reset and configure the PHY */
 943                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 944                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 945                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 946                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 947                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 948                 {miim_end,}
 949         },
 950         (struct phy_cmd[]) { /* startup */
 951                 /* Status is read once to clear old link state */
 952                 {MIIM_STATUS, miim_read, NULL},
 953                 /* Auto-negotiate */
 954                 {MIIM_STATUS, miim_read, &mii_parse_sr},
 955                 /* Read the status */
 956                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
 957                 {miim_end,}
 958         },
 959         (struct phy_cmd[]) { /* shutdown */
 960                 {miim_end,}
 961         },
 962 };
 963
 964 struct phy_info phy_info_BCM5464S = {
 965         0x02060b1,      /* 5464 ID */
 966         "Broadcom BCM5464S",
 967         0, /* not clear to me what minor revisions we can shift away */
 968         (struct phy_cmd[]) { /* config */
 969                 /* Reset and configure the PHY */
 970                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 971                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 972                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 973                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 974                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 975                 {miim_end,}
 976         },
 977         (struct phy_cmd[]) { /* startup */
 978                 /* Status is read once to clear old link state */
 979                 {MIIM_STATUS, miim_read, NULL},
 980                 /* Auto-negotiate */
 981                 {MIIM_STATUS, miim_read, &mii_parse_sr},
 982                 /* Read the status */
 983                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
 984                 {miim_end,}
 985         },
 986         (struct phy_cmd[]) { /* shutdown */
 987                 {miim_end,}
 988         },
 989 };
 990
 991 struct phy_info phy_info_M88E1011S = {
 992         0x01410c6,
 993         "Marvell 88E1011S",
 994         4,
 995         (struct phy_cmd[]){     /* config */
 996                            /* Reset and configure the PHY */
 997                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 998                            {0x1d, 0x1f, NULL},
 999                            {0x1e, 0x200c, NULL},
1000                            {0x1d, 0x5, NULL},
1001                            {0x1e, 0x0, NULL},
1002                            {0x1e, 0x100, NULL},
1003                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1004                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1005                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1006                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1007                            {miim_end,}
1008                            },
1009         (struct phy_cmd[]){     /* startup */
1010                            /* Status is read once to clear old link state */
1011                            {MIIM_STATUS, miim_read, NULL},
1012                            /* Auto-negotiate */
1013                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1014                            /* Read the status */
1015                            {MIIM_88E1011_PHY_STATUS, miim_read,
1016                             &mii_parse_88E1011_psr},
1017                            {miim_end,}
1018                            },
1019         (struct phy_cmd[]){     /* shutdown */
1020                            {miim_end,}
1021                            },
1022 };
1023
1024 struct phy_info phy_info_M88E1111S = {
1025         0x01410cc,
1026         "Marvell 88E1111S",
1027         4,
1028         (struct phy_cmd[]){     /* config */
1029                            /* Reset and configure the PHY */
1030                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1031                            {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
1032                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1033                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1034                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1035                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1036                            {miim_end,}
1037                            },
1038         (struct phy_cmd[]){     /* startup */
1039                            /* Status is read once to clear old link state */
1040                            {MIIM_STATUS, miim_read, NULL},
1041                            /* Auto-negotiate */
1042                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1043                            /* Read the status */
1044                            {MIIM_88E1011_PHY_STATUS, miim_read,
1045                             &mii_parse_88E1011_psr},
1046                            {miim_end,}
1047                            },
1048         (struct phy_cmd[]){     /* shutdown */
1049                            {miim_end,}
1050                            },
1051 };
1052
1053 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1054 {
1055         uint mii_data = read_phy_reg(priv, mii_reg);
1056
1057         /* Setting MIIM_88E1145_PHY_EXT_CR */
1058         if (priv->flags & TSEC_REDUCED)
1059                 return mii_data |
1060                     MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1061         else
1062                 return mii_data;
1063 }
1064
1065 static struct phy_info phy_info_M88E1145 = {
1066         0x01410cd,
1067         "Marvell 88E1145",
1068         4,
1069         (struct phy_cmd[]){     /* config */
1070                            /* Reset the PHY */
1071                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1072
1073                            /* Errata E0, E1 */
1074                            {29, 0x001b, NULL},
1075                            {30, 0x418f, NULL},
1076                            {29, 0x0016, NULL},
1077                            {30, 0xa2da, NULL},
1078
1079                            /* Configure the PHY */
1080                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1081                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1082                            {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
1083                             NULL},
1084                            {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1085                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1086                            {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1087                            {miim_end,}
1088                            },
1089         (struct phy_cmd[]){     /* startup */
1090                            /* Status is read once to clear old link state */
1091                            {MIIM_STATUS, miim_read, NULL},
1092                            /* Auto-negotiate */
1093                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1094                            {MIIM_88E1111_PHY_LED_CONTROL,
1095                             MIIM_88E1111_PHY_LED_DIRECT, NULL},
1096                            /* Read the Status */
1097                            {MIIM_88E1011_PHY_STATUS, miim_read,
1098                             &mii_parse_88E1011_psr},
1099                            {miim_end,}
1100                            },
1101         (struct phy_cmd[]){     /* shutdown */
1102                            {miim_end,}
1103                            },
1104 };
1105
1106 struct phy_info phy_info_cis8204 = {
1107         0x3f11,
1108         "Cicada Cis8204",
1109         6,
1110         (struct phy_cmd[]){     /* config */
1111                            /* Override PHY config settings */
1112                            {MIIM_CIS8201_AUX_CONSTAT,
1113                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1114                            /* Configure some basic stuff */
1115                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1116                            {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1117                             &mii_cis8204_fixled},
1118                            {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1119                             &mii_cis8204_setmode},
1120                            {miim_end,}
1121                            },
1122         (struct phy_cmd[]){     /* startup */
1123                            /* Read the Status (2x to make sure link is right) */
1124                            {MIIM_STATUS, miim_read, NULL},
1125                            /* Auto-negotiate */
1126                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1127                            /* Read the status */
1128                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1129                             &mii_parse_cis8201},
1130                            {miim_end,}
1131                            },
1132         (struct phy_cmd[]){     /* shutdown */
1133                            {miim_end,}
1134                            },
1135 };
1136
1137 /* Cicada 8201 */
1138 struct phy_info phy_info_cis8201 = {
1139         0xfc41,
1140         "CIS8201",
1141         4,
1142         (struct phy_cmd[]){     /* config */
1143                            /* Override PHY config settings */
1144                            {MIIM_CIS8201_AUX_CONSTAT,
1145                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1146                            /* Set up the interface mode */
1147                            {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1148                             NULL},
1149                            /* Configure some basic stuff */
1150                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1151                            {miim_end,}
1152                            },
1153         (struct phy_cmd[]){     /* startup */
1154                            /* Read the Status (2x to make sure link is right) */
1155                            {MIIM_STATUS, miim_read, NULL},
1156                            /* Auto-negotiate */
1157                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1158                            /* Read the status */
1159                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1160                             &mii_parse_cis8201},
1161                            {miim_end,}
1162                            },
1163         (struct phy_cmd[]){     /* shutdown */
1164                            {miim_end,}
1165                            },
1166 };
1167 struct phy_info phy_info_VSC8244 = {
1168         0x3f1b,
1169         "Vitesse VSC8244",
1170         6,
1171         (struct phy_cmd[]){     /* config */
1172                            /* Override PHY config settings */
1173                            /* Configure some basic stuff */
1174                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1175                            {miim_end,}
1176                            },
1177         (struct phy_cmd[]){     /* startup */
1178                            /* Read the Status (2x to make sure link is right) */
1179                            {MIIM_STATUS, miim_read, NULL},
1180                            /* Auto-negotiate */
1181                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1182                            /* Read the status */
1183                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1184                             &mii_parse_vsc8244},
1185                            {miim_end,}
1186                            },
1187         (struct phy_cmd[]){     /* shutdown */
1188                            {miim_end,}
1189                            },
1190 };
1191
1192 struct phy_info phy_info_dm9161 = {
1193         0x0181b88,
1194         "Davicom DM9161E",
1195         4,
1196         (struct phy_cmd[]){     /* config */
1197                            {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1198                            /* Do not bypass the scrambler/descrambler */
1199                            {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1200                            /* Clear 10BTCSR to default */
1201                            {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1202                             NULL},
1203                            /* Configure some basic stuff */
1204                            {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1205                            /* Restart Auto Negotiation */
1206                            {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1207                            {miim_end,}
1208                            },
1209         (struct phy_cmd[]){     /* startup */
1210                            /* Status is read once to clear old link state */
1211                            {MIIM_STATUS, miim_read, NULL},
1212                            /* Auto-negotiate */
1213                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1214                            /* Read the status */
1215                            {MIIM_DM9161_SCSR, miim_read,
1216                             &mii_parse_dm9161_scsr},
1217                            {miim_end,}
1218                            },
1219         (struct phy_cmd[]){     /* shutdown */
1220                            {miim_end,}
1221                            },
1222 };
1223 /* a generic flavor.  */
1224 struct phy_info phy_info_generic =  {
1225         0,
1226         "Unknown/Generic PHY",
1227         32,
1228         (struct phy_cmd[]) { /* config */
1229                 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1230                 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1231                 {miim_end,}
1232         },
1233         (struct phy_cmd[]) { /* startup */
1234                 {PHY_BMSR, miim_read, NULL},
1235                 {PHY_BMSR, miim_read, &mii_parse_sr},
1236                 {PHY_BMSR, miim_read, &mii_parse_link},
1237                 {miim_end,}
1238         },
1239         (struct phy_cmd[]) { /* shutdown */
1240                 {miim_end,}
1241         }
1242 };
1243
1244
1245 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1246 {
1247         unsigned int speed;
1248         if (priv->link) {
1249                 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1250
1251                 switch (speed) {
1252                 case MIIM_LXT971_SR2_10HDX:
1253                         priv->speed = 10;
1254                         priv->duplexity = 0;
1255                         break;
1256                 case MIIM_LXT971_SR2_10FDX:
1257                         priv->speed = 10;
1258                         priv->duplexity = 1;
1259                         break;
1260                 case MIIM_LXT971_SR2_100HDX:
1261                         priv->speed = 100;
1262                         priv->duplexity = 0;
1263                 default:
1264                         priv->speed = 100;
1265                         priv->duplexity = 1;
1266                         break;
1267                 }
1268         } else {
1269                 priv->speed = 0;
1270                 priv->duplexity = 0;
1271         }
1272
1273         return 0;
1274 }
1275
1276 static struct phy_info phy_info_lxt971 = {
1277         0x0001378e,
1278         "LXT971",
1279         4,
1280         (struct phy_cmd[]){     /* config */
1281                            {MIIM_CR, MIIM_CR_INIT, mii_cr_init},        /* autonegotiate */
1282                            {miim_end,}
1283                            },
1284         (struct phy_cmd[]){     /* startup - enable interrupts */
1285                            /* { 0x12, 0x00f2, NULL }, */
1286                            {MIIM_STATUS, miim_read, NULL},
1287                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1288                            {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1289                            {miim_end,}
1290                            },
1291         (struct phy_cmd[]){     /* shutdown - disable interrupts */
1292                            {miim_end,}
1293                            },
1294 };
1295
1296 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1297  * information
1298  */
1299 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1300 {
1301         switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1302
1303         case MIIM_DP83865_SPD_1000:
1304                 priv->speed = 1000;
1305                 break;
1306
1307         case MIIM_DP83865_SPD_100:
1308                 priv->speed = 100;
1309                 break;
1310
1311         default:
1312                 priv->speed = 10;
1313                 break;
1314
1315         }
1316
1317         if (mii_reg & MIIM_DP83865_DPX_FULL)
1318                 priv->duplexity = 1;
1319         else
1320                 priv->duplexity = 0;
1321
1322         return 0;
1323 }
1324
1325 struct phy_info phy_info_dp83865 = {
1326         0x20005c7,
1327         "NatSemi DP83865",
1328         4,
1329         (struct phy_cmd[]){     /* config */
1330                            {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1331                            {miim_end,}
1332                            },
1333         (struct phy_cmd[]){     /* startup */
1334                            /* Status is read once to clear old link state */
1335                            {MIIM_STATUS, miim_read, NULL},
1336                            /* Auto-negotiate */
1337                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1338                            /* Read the link and auto-neg status */
1339                            {MIIM_DP83865_LANR, miim_read,
1340                             &mii_parse_dp83865_lanr},
1341                            {miim_end,}
1342                            },
1343         (struct phy_cmd[]){     /* shutdown */
1344                            {miim_end,}
1345                            },
1346 };
1347
1348 struct phy_info *phy_info[] = {
1349         &phy_info_cis8204,
1350         &phy_info_cis8201,
1351         &phy_info_BCM5461S,
1352         &phy_info_BCM5464S,
1353         &phy_info_M88E1011S,
1354         &phy_info_M88E1111S,
1355         &phy_info_M88E1145,
1356         &phy_info_M88E1149S,
1357         &phy_info_dm9161,
1358         &phy_info_lxt971,
1359         &phy_info_VSC8244,
1360         &phy_info_dp83865,
1361         &phy_info_generic,
1362         NULL
1363 };
1364
1365 /* Grab the identifier of the device's PHY, and search through
1366  * all of the known PHYs to see if one matches.  If so, return
1367  * it, if not, return NULL
1368  */
1369 struct phy_info *get_phy_info(struct eth_device *dev)
1370 {
1371         struct tsec_private *priv = (struct tsec_private *)dev->priv;
1372         uint phy_reg, phy_ID;
1373         int i;
1374         struct phy_info *theInfo = NULL;
1375
1376         /* Grab the bits from PHYIR1, and put them in the upper half */
1377         phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1378         phy_ID = (phy_reg & 0xffff) << 16;
1379
1380         /* Grab the bits from PHYIR2, and put them in the lower half */
1381         phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1382         phy_ID |= (phy_reg & 0xffff);
1383
1384         /* loop through all the known PHY types, and find one that */
1385         /* matches the ID we read from the PHY. */
1386         for (i = 0; phy_info[i]; i++) {
1387                 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
1388                         theInfo = phy_info[i];
1389                         break;
1390                 }
1391         }
1392
1393         if (theInfo == NULL) {
1394                 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1395                 return NULL;
1396         } else {
1397                 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1398         }
1399
1400         return theInfo;
1401 }
1402
1403 /* Execute the given series of commands on the given device's
1404  * PHY, running functions as necessary
1405  */
1406 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1407 {
1408         int i;
1409         uint result;
1410         volatile tsec_t *phyregs = priv->phyregs;
1411
1412         phyregs->miimcfg = MIIMCFG_RESET;
1413
1414         phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1415
1416         while (phyregs->miimind & MIIMIND_BUSY) ;
1417
1418         for (i = 0; cmd->mii_reg != miim_end; i++) {
1419                 if (cmd->mii_data == miim_read) {
1420                         result = read_phy_reg(priv, cmd->mii_reg);
1421
1422                         if (cmd->funct != NULL)
1423                                 (*(cmd->funct)) (result, priv);
1424
1425                 } else {
1426                         if (cmd->funct != NULL)
1427                                 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1428                         else
1429                                 result = cmd->mii_data;
1430
1431                         write_phy_reg(priv, cmd->mii_reg, result);
1432
1433                 }
1434                 cmd++;
1435         }
1436 }
1437
1438 /* Relocate the function pointers in the phy cmd lists */
1439 static void relocate_cmds(void)
1440 {
1441         struct phy_cmd **cmdlistptr;
1442         struct phy_cmd *cmd;
1443         int i, j, k;
1444
1445         for (i = 0; phy_info[i]; i++) {
1446                 /* First thing's first: relocate the pointers to the
1447                  * PHY command structures (the structs were done) */
1448                 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1449                                                   + gd->reloc_off);
1450                 phy_info[i]->name += gd->reloc_off;
1451                 phy_info[i]->config =
1452                     (struct phy_cmd *)((uint) phy_info[i]->config
1453                                        + gd->reloc_off);
1454                 phy_info[i]->startup =
1455                     (struct phy_cmd *)((uint) phy_info[i]->startup
1456                                        + gd->reloc_off);
1457                 phy_info[i]->shutdown =
1458                     (struct phy_cmd *)((uint) phy_info[i]->shutdown
1459                                        + gd->reloc_off);
1460
1461                 cmdlistptr = &phy_info[i]->config;
1462                 j = 0;
1463                 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1464                         k = 0;
1465                         for (cmd = *cmdlistptr;
1466                              cmd->mii_reg != miim_end;
1467                              cmd++) {
1468                                 /* Only relocate non-NULL pointers */
1469                                 if (cmd->funct)
1470                                         cmd->funct += gd->reloc_off;
1471
1472                                 k++;
1473                         }
1474                         j++;
1475                 }
1476         }
1477
1478         relocated = 1;
1479 }
1480
1481 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1482         && !defined(BITBANGMII)
1483
1484 struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
1485 {
1486         int i;
1487
1488         for (i = 0; i < MAXCONTROLLERS; i++) {
1489                 if (privlist[i]->phyaddr == phyaddr)
1490                         return privlist[i];
1491         }
1492
1493         return NULL;
1494 }
1495
1496 /*
1497  * Read a MII PHY register.
1498  *
1499  * Returns:
1500  *  0 on success
1501  */
1502 static int tsec_miiphy_read(char *devname, unsigned char addr,
1503                             unsigned char reg, unsigned short *value)
1504 {
1505         unsigned short ret;
1506         struct tsec_private *priv = get_priv_for_phy(addr);
1507
1508         if (NULL == priv) {
1509                 printf("Can't read PHY at address %d\n", addr);
1510                 return -1;
1511         }
1512
1513         ret = (unsigned short)read_phy_reg(priv, reg);
1514         *value = ret;
1515
1516         return 0;
1517 }
1518
1519 /*
1520  * Write a MII PHY register.
1521  *
1522  * Returns:
1523  *  0 on success
1524  */
1525 static int tsec_miiphy_write(char *devname, unsigned char addr,
1526                              unsigned char reg, unsigned short value)
1527 {
1528         struct tsec_private *priv = get_priv_for_phy(addr);
1529
1530         if (NULL == priv) {
1531                 printf("Can't write PHY at address %d\n", addr);
1532                 return -1;
1533         }
1534
1535         write_phy_reg(priv, reg, value);
1536
1537         return 0;
1538 }
1539
1540 #endif
1541
1542 #endif /* CONFIG_TSEC_ENET */