3 * Freescale Three Speed Ethernet Controller driver
5 * This software may be used and distributed according to the
6 * terms of the GNU Public License, Version 2, incorporated
9 * Copyright 2004 Freescale Semiconductor.
10 * (C) Copyright 2003, Motorola, Inc.
22 #if defined(CONFIG_TSEC_ENET)
26 DECLARE_GLOBAL_DATA_PTR;
30 static uint rxIdx; /* index of the current RX buffer */
31 static uint txIdx; /* index of the current TX buffer */
33 typedef volatile struct rtxbd {
34 txbd8_t txbd[TX_BUF_CNT];
35 rxbd8_t rxbd[PKTBUFSRX];
38 struct tsec_info_struct {
41 unsigned int phyregidx;
45 /* The tsec_info structure contains 3 values which the
46 * driver uses to determine how to operate a given ethernet
47 * device. The information needed is:
48 * phyaddr - The address of the PHY which is attached to
51 * flags - This variable indicates whether the device
52 * supports gigabit speed ethernet, and whether it should be
55 * phyregidx - This variable specifies which ethernet device
56 * controls the MII Management registers which are connected
57 * to the PHY. For now, only TSEC1 (index 0) has
58 * access to the PHYs, so all of the entries have "0".
60 * The values specified in the table are taken from the board's
61 * config file in include/configs/. When implementing a new
62 * board with ethernet capability, it is necessary to define:
66 * for n = 1,2,3, etc. And for FEC:
70 static struct tsec_info_struct tsec_info[] = {
71 #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
72 {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
76 #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
77 {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
81 #ifdef CONFIG_MPC85XX_FEC
82 {FEC_PHY_ADDR, 0, FEC_PHYIDX},
84 # if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3)
85 {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
89 # if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4)
90 {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
97 #define MAXCONTROLLERS (4)
99 static int relocated = 0;
101 static struct tsec_private *privlist[MAXCONTROLLERS];
104 static RTXBD rtx __attribute__ ((aligned(8)));
106 #error "rtx must be 64-bit aligned"
109 static int tsec_send(struct eth_device* dev, volatile void *packet, int length);
110 static int tsec_recv(struct eth_device* dev);
111 static int tsec_init(struct eth_device* dev, bd_t * bd);
112 static void tsec_halt(struct eth_device* dev);
113 static void init_registers(volatile tsec_t *regs);
114 static void startup_tsec(struct eth_device *dev);
115 static int init_phy(struct eth_device *dev);
116 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
117 uint read_phy_reg(struct tsec_private *priv, uint regnum);
118 struct phy_info * get_phy_info(struct eth_device *dev);
119 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
120 static void adjust_link(struct eth_device *dev);
121 static void relocate_cmds(void);
122 static int tsec_miiphy_write(char *devname, unsigned char addr,
123 unsigned char reg, unsigned short value);
124 static int tsec_miiphy_read(char *devname, unsigned char addr,
125 unsigned char reg, unsigned short *value);
127 /* Initialize device structure. Returns success if PHY
128 * initialization succeeded (i.e. if it recognizes the PHY)
130 int tsec_initialize(bd_t *bis, int index, char *devname)
132 struct eth_device* dev;
134 struct tsec_private *priv;
136 dev = (struct eth_device*) malloc(sizeof *dev);
141 memset(dev, 0, sizeof *dev);
143 priv = (struct tsec_private *) malloc(sizeof(*priv));
148 privlist[index] = priv;
149 priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index*TSEC_SIZE);
150 priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
151 tsec_info[index].phyregidx*TSEC_SIZE);
153 priv->phyaddr = tsec_info[index].phyaddr;
154 priv->flags = tsec_info[index].flags;
156 sprintf(dev->name, devname);
159 dev->init = tsec_init;
160 dev->halt = tsec_halt;
161 dev->send = tsec_send;
162 dev->recv = tsec_recv;
164 /* Tell u-boot to get the addr from the env */
166 dev->enetaddr[i] = 0;
172 priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
173 priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
175 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
176 && !defined(BITBANGMII)
177 miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
180 /* Try to initialize PHY here, and return */
181 return init_phy(dev);
185 /* Initializes data structures and registers for the controller,
186 * and brings the interface up. Returns the link status, meaning
187 * that it returns success if the link is up, failure otherwise.
188 * This allows u-boot to find the first active controller. */
189 int tsec_init(struct eth_device* dev, bd_t * bd)
192 char tmpbuf[MAC_ADDR_LEN];
194 struct tsec_private *priv = (struct tsec_private *)dev->priv;
195 volatile tsec_t *regs = priv->regs;
197 /* Make sure the controller is stopped */
200 /* Init MACCFG2. Defaults to GMII */
201 regs->maccfg2 = MACCFG2_INIT_SETTINGS;
204 regs->ecntrl = ECNTRL_INIT_SETTINGS;
206 /* Copy the station address into the address registers.
207 * Backwards, because little endian MACS are dumb */
208 for(i=0;i<MAC_ADDR_LEN;i++) {
209 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
211 regs->macstnaddr1 = *((uint *)(tmpbuf));
213 tempval = *((uint *)(tmpbuf +4));
215 regs->macstnaddr2 = tempval;
217 /* reset the indices to zero */
221 /* Clear out (for the most part) the other registers */
222 init_registers(regs);
224 /* Ready the device for tx/rx */
227 /* If there's no link, fail */
233 /* Write value to the device's PHY through the registers
234 * specified in priv, modifying the register specified in regnum.
235 * It will wait for the write to be done (or for a timeout to
236 * expire) before exiting
238 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
240 volatile tsec_t *regbase = priv->phyregs;
241 uint phyid = priv->phyaddr;
244 regbase->miimadd = (phyid << 8) | regnum;
245 regbase->miimcon = value;
249 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
253 /* Reads register regnum on the device's PHY through the
254 * registers specified in priv. It lowers and raises the read
255 * command, and waits for the data to become valid (miimind
256 * notvalid bit cleared), and the bus to cease activity (miimind
257 * busy bit cleared), and then returns the value
259 uint read_phy_reg(struct tsec_private *priv, uint regnum)
262 volatile tsec_t *regbase = priv->phyregs;
263 uint phyid = priv->phyaddr;
265 /* Put the address of the phy, and the register
266 * number into MIIMADD */
267 regbase->miimadd = (phyid << 8) | regnum;
269 /* Clear the command register, and wait */
270 regbase->miimcom = 0;
273 /* Initiate a read command, and wait */
274 regbase->miimcom = MIIM_READ_COMMAND;
277 /* Wait for the the indication that the read is done */
278 while((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY)));
280 /* Grab the value read from the PHY */
281 value = regbase->miimstat;
287 /* Discover which PHY is attached to the device, and configure it
288 * properly. If the PHY is not recognized, then return 0
289 * (failure). Otherwise, return 1
291 static int init_phy(struct eth_device *dev)
293 struct tsec_private *priv = (struct tsec_private *)dev->priv;
294 struct phy_info *curphy;
296 /* Assign a Physical address to the TBI */
299 volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
300 regs->tbipa = TBIPA_VALUE;
301 regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
302 regs->tbipa = TBIPA_VALUE;
306 /* Reset MII (due to new addresses) */
307 priv->phyregs->miimcfg = MIIMCFG_RESET;
309 priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
311 while(priv->phyregs->miimind & MIIMIND_BUSY);
316 /* Get the cmd structure corresponding to the attached
318 curphy = get_phy_info(dev);
321 printf("%s: No PHY found\n", dev->name);
326 priv->phyinfo = curphy;
328 phy_run_commands(priv, priv->phyinfo->config);
334 /* Returns which value to write to the control register. */
335 /* For 10/100, the value is slightly different */
336 uint mii_cr_init(uint mii_reg, struct tsec_private *priv)
338 if(priv->flags & TSEC_GIGABIT)
339 return MIIM_CONTROL_INIT;
345 /* Parse the status register for link, and then do
346 * auto-negotiation */
347 uint mii_parse_sr(uint mii_reg, struct tsec_private *priv)
350 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
352 mii_reg = read_phy_reg(priv, MIIM_STATUS);
353 if ((mii_reg & PHY_BMSR_AUTN_ABLE) && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
356 puts ("Waiting for PHY auto negotiation to complete");
357 while (!((mii_reg & PHY_BMSR_AUTN_COMP) && (mii_reg & MIIM_STATUS_LINK))) {
361 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
362 puts (" TIMEOUT !\n");
367 if ((i++ % 1000) == 0) {
370 udelay (1000); /* 1 ms */
371 mii_reg = read_phy_reg(priv, MIIM_STATUS);
375 udelay (500000); /* another 500 ms (results in faster booting) */
384 /* Parse the 88E1011's status register for speed and duplex
386 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private *priv)
390 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
392 if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
393 (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
396 puts ("Waiting for PHY realtime link");
397 while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
398 (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
402 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
403 puts (" TIMEOUT !\n");
408 if ((i++ % 1000) == 0) {
411 udelay (1000); /* 1 ms */
412 mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
415 udelay (500000); /* another 500 ms (results in faster booting) */
418 if(mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
423 speed = (mii_reg &MIIM_88E1011_PHYSTAT_SPEED);
426 case MIIM_88E1011_PHYSTAT_GBIT:
429 case MIIM_88E1011_PHYSTAT_100:
440 /* Parse the cis8201's status register for speed and duplex
442 uint mii_parse_cis8201(uint mii_reg, struct tsec_private *priv)
446 if(mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
451 speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
453 case MIIM_CIS8201_AUXCONSTAT_GBIT:
456 case MIIM_CIS8201_AUXCONSTAT_100:
468 /* Parse the DM9161's status register for speed and duplex
470 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private *priv)
472 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
477 if(mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
486 /* Hack to write all 4 PHYs with the LED values */
487 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private *priv)
490 volatile tsec_t *regbase = priv->phyregs;
493 for(phyid=0;phyid<4;phyid++) {
494 regbase->miimadd = (phyid << 8) | mii_reg;
495 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
499 while((regbase->miimind & MIIMIND_BUSY) && timeout--);
502 return MIIM_CIS8204_SLEDCON_INIT;
505 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private *priv)
507 if (priv->flags & TSEC_REDUCED)
508 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
510 return MIIM_CIS8204_EPHYCON_INIT;
513 /* Initialized required registers to appropriate values, zeroing
514 * those we don't care about (unless zero is bad, in which case,
515 * choose a more appropriate value) */
516 static void init_registers(volatile tsec_t *regs)
519 regs->ievent = IEVENT_INIT_CLEAR;
521 regs->imask = IMASK_INIT_CLEAR;
523 regs->hash.iaddr0 = 0;
524 regs->hash.iaddr1 = 0;
525 regs->hash.iaddr2 = 0;
526 regs->hash.iaddr3 = 0;
527 regs->hash.iaddr4 = 0;
528 regs->hash.iaddr5 = 0;
529 regs->hash.iaddr6 = 0;
530 regs->hash.iaddr7 = 0;
532 regs->hash.gaddr0 = 0;
533 regs->hash.gaddr1 = 0;
534 regs->hash.gaddr2 = 0;
535 regs->hash.gaddr3 = 0;
536 regs->hash.gaddr4 = 0;
537 regs->hash.gaddr5 = 0;
538 regs->hash.gaddr6 = 0;
539 regs->hash.gaddr7 = 0;
541 regs->rctrl = 0x00000000;
543 /* Init RMON mib registers */
544 memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
546 regs->rmon.cam1 = 0xffffffff;
547 regs->rmon.cam2 = 0xffffffff;
549 regs->mrblr = MRBLR_INIT_SETTINGS;
551 regs->minflr = MINFLR_INIT_SETTINGS;
553 regs->attr = ATTR_INIT_SETTINGS;
554 regs->attreli = ATTRELI_INIT_SETTINGS;
559 /* Configure maccfg2 based on negotiated speed and duplex
560 * reported by PHY handling code */
561 static void adjust_link(struct eth_device *dev)
563 struct tsec_private *priv = (struct tsec_private *)dev->priv;
564 volatile tsec_t *regs = priv->regs;
567 if(priv->duplexity != 0)
568 regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
570 regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
572 switch(priv->speed) {
574 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
579 regs->maccfg2 = ((regs->maccfg2&~(MACCFG2_IF))
582 /* If We're in reduced mode, we need
583 * to say whether we're 10 or 100 MB.
585 if ((priv->speed == 100)
586 && (priv->flags & TSEC_REDUCED))
587 regs->ecntrl |= ECNTRL_R100;
589 regs->ecntrl &= ~(ECNTRL_R100);
592 printf("%s: Speed was bad\n", dev->name);
596 printf("Speed: %d, %s duplex\n", priv->speed,
597 (priv->duplexity) ? "full" : "half");
600 printf("%s: No link.\n", dev->name);
605 /* Set up the buffers and their descriptors, and bring up the
607 static void startup_tsec(struct eth_device *dev)
610 struct tsec_private *priv = (struct tsec_private *)dev->priv;
611 volatile tsec_t *regs = priv->regs;
613 /* Point to the buffer descriptors */
614 regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
615 regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
617 /* Initialize the Rx Buffer descriptors */
618 for (i = 0; i < PKTBUFSRX; i++) {
619 rtx.rxbd[i].status = RXBD_EMPTY;
620 rtx.rxbd[i].length = 0;
621 rtx.rxbd[i].bufPtr = (uint)NetRxPackets[i];
623 rtx.rxbd[PKTBUFSRX -1].status |= RXBD_WRAP;
625 /* Initialize the TX Buffer Descriptors */
626 for(i=0; i<TX_BUF_CNT; i++) {
627 rtx.txbd[i].status = 0;
628 rtx.txbd[i].length = 0;
629 rtx.txbd[i].bufPtr = 0;
631 rtx.txbd[TX_BUF_CNT -1].status |= TXBD_WRAP;
633 /* Start up the PHY */
634 phy_run_commands(priv, priv->phyinfo->startup);
637 /* Enable Transmit and Receive */
638 regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
640 /* Tell the DMA it is clear to go */
641 regs->dmactrl |= DMACTRL_INIT_SETTINGS;
642 regs->tstat = TSTAT_CLEAR_THALT;
643 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
646 /* This returns the status bits of the device. The return value
647 * is never checked, and this is what the 8260 driver did, so we
648 * do the same. Presumably, this would be zero if there were no
650 static int tsec_send(struct eth_device* dev, volatile void *packet, int length)
654 struct tsec_private *priv = (struct tsec_private *)dev->priv;
655 volatile tsec_t *regs = priv->regs;
657 /* Find an empty buffer descriptor */
658 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
659 if (i >= TOUT_LOOP) {
660 debug ("%s: tsec: tx buffers full\n", dev->name);
665 rtx.txbd[txIdx].bufPtr = (uint)packet;
666 rtx.txbd[txIdx].length = length;
667 rtx.txbd[txIdx].status |= (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
669 /* Tell the DMA to go */
670 regs->tstat = TSTAT_CLEAR_THALT;
672 /* Wait for buffer to be transmitted */
673 for(i=0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
674 if (i >= TOUT_LOOP) {
675 debug ("%s: tsec: tx error\n", dev->name);
680 txIdx = (txIdx + 1) % TX_BUF_CNT;
681 result = rtx.txbd[txIdx].status & TXBD_STATS;
686 static int tsec_recv(struct eth_device* dev)
689 struct tsec_private *priv = (struct tsec_private *)dev->priv;
690 volatile tsec_t *regs = priv->regs;
692 while(!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
694 length = rtx.rxbd[rxIdx].length;
696 /* Send the packet up if there were no errors */
697 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
698 NetReceive(NetRxPackets[rxIdx], length - 4);
700 printf("Got error %x\n",
701 (rtx.rxbd[rxIdx].status & RXBD_STATS));
704 rtx.rxbd[rxIdx].length = 0;
706 /* Set the wrap bit if this is the last element in the list */
707 rtx.rxbd[rxIdx].status = RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
709 rxIdx = (rxIdx + 1) % PKTBUFSRX;
712 if(regs->ievent&IEVENT_BSY) {
713 regs->ievent = IEVENT_BSY;
714 regs->rstat = RSTAT_CLEAR_RHALT;
722 /* Stop the interface */
723 static void tsec_halt(struct eth_device* dev)
725 struct tsec_private *priv = (struct tsec_private *)dev->priv;
726 volatile tsec_t *regs = priv->regs;
728 regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
729 regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
731 while(!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC)));
733 regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
735 /* Shut down the PHY, as needed */
736 phy_run_commands(priv, priv->phyinfo->shutdown);
740 struct phy_info phy_info_M88E1011S = {
744 (struct phy_cmd[]) { /* config */
745 /* Reset and configure the PHY */
746 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
748 {0x1e, 0x200c, NULL},
752 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
753 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
754 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
755 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
758 (struct phy_cmd[]) { /* startup */
759 /* Status is read once to clear old link state */
760 {MIIM_STATUS, miim_read, NULL},
762 {MIIM_STATUS, miim_read, &mii_parse_sr},
763 /* Read the status */
764 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
767 (struct phy_cmd[]) { /* shutdown */
772 struct phy_info phy_info_M88E1111S = {
776 (struct phy_cmd[]) { /* config */
777 /* Reset and configure the PHY */
778 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
780 {0x1e, 0x200c, NULL},
784 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
785 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
786 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
787 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
790 (struct phy_cmd[]) { /* startup */
791 /* Status is read once to clear old link state */
792 {MIIM_STATUS, miim_read, NULL},
794 {MIIM_STATUS, miim_read, &mii_parse_sr},
795 /* Read the status */
796 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
799 (struct phy_cmd[]) { /* shutdown */
804 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
807 uint mii_data = read_phy_reg(priv, mii_reg);
810 /* Setting MIIM_88E1145_PHY_EXT_CR */
811 if (priv->flags & TSEC_REDUCED)
813 MIIM_M88E1145_RGMII_RX_DELAY |
814 MIIM_M88E1145_RGMII_TX_DELAY;
819 static struct phy_info phy_info_M88E1145 = {
823 (struct phy_cmd[]) { /* config */
830 /* Reset and configure the PHY */
831 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
832 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
833 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
834 {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO, NULL},
835 {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
836 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
837 {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
840 (struct phy_cmd[]) { /* startup */
841 /* Status is read once to clear old link state */
842 {MIIM_STATUS, miim_read, NULL},
844 {MIIM_STATUS, miim_read, &mii_parse_sr},
845 {MIIM_88E1111_PHY_LED_CONTROL, MIIM_88E1111_PHY_LED_DIRECT, NULL},
846 /* Read the Status */
847 {MIIM_88E1011_PHY_STATUS, miim_read, &mii_parse_88E1011_psr},
850 (struct phy_cmd[]) { /* shutdown */
856 struct phy_info phy_info_cis8204 = {
860 (struct phy_cmd[]) { /* config */
861 /* Override PHY config settings */
862 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
863 /* Configure some basic stuff */
864 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
865 {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT, &mii_cis8204_fixled},
866 {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT, &mii_cis8204_setmode},
869 (struct phy_cmd[]) { /* startup */
870 /* Read the Status (2x to make sure link is right) */
871 {MIIM_STATUS, miim_read, NULL},
873 {MIIM_STATUS, miim_read, &mii_parse_sr},
874 /* Read the status */
875 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
878 (struct phy_cmd[]) { /* shutdown */
884 struct phy_info phy_info_cis8201 = {
888 (struct phy_cmd[]) { /* config */
889 /* Override PHY config settings */
890 {MIIM_CIS8201_AUX_CONSTAT, MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
891 /* Set up the interface mode */
892 {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT, NULL},
893 /* Configure some basic stuff */
894 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
897 (struct phy_cmd[]) { /* startup */
898 /* Read the Status (2x to make sure link is right) */
899 {MIIM_STATUS, miim_read, NULL},
901 {MIIM_STATUS, miim_read, &mii_parse_sr},
902 /* Read the status */
903 {MIIM_CIS8201_AUX_CONSTAT, miim_read, &mii_parse_cis8201},
906 (struct phy_cmd[]) { /* shutdown */
912 struct phy_info phy_info_dm9161 = {
916 (struct phy_cmd[]) { /* config */
917 {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
918 /* Do not bypass the scrambler/descrambler */
919 {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
920 /* Clear 10BTCSR to default */
921 {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT, NULL},
922 /* Configure some basic stuff */
923 {MIIM_CONTROL, MIIM_CR_INIT, NULL},
924 /* Restart Auto Negotiation */
925 {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
928 (struct phy_cmd[]) { /* startup */
929 /* Status is read once to clear old link state */
930 {MIIM_STATUS, miim_read, NULL},
932 {MIIM_STATUS, miim_read, &mii_parse_sr},
933 /* Read the status */
934 {MIIM_DM9161_SCSR, miim_read, &mii_parse_dm9161_scsr},
937 (struct phy_cmd[]) { /* shutdown */
942 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
946 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
949 case MIIM_LXT971_SR2_10HDX:
953 case MIIM_LXT971_SR2_10FDX:
957 case MIIM_LXT971_SR2_100HDX:
973 static struct phy_info phy_info_lxt971 = {
977 (struct phy_cmd []) { /* config */
978 { MIIM_CR, MIIM_CR_INIT, mii_cr_init }, /* autonegotiate */
981 (struct phy_cmd []) { /* startup - enable interrupts */
982 /* { 0x12, 0x00f2, NULL }, */
983 { MIIM_STATUS, miim_read, NULL },
984 { MIIM_STATUS, miim_read, &mii_parse_sr },
985 { MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2 },
988 (struct phy_cmd []) { /* shutdown - disable interrupts */
993 /* Parse the DP83865's link and auto-neg status register for speed and duplex
995 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
997 switch (mii_reg & MIIM_DP83865_SPD_MASK) {
999 case MIIM_DP83865_SPD_1000:
1003 case MIIM_DP83865_SPD_100:
1013 if (mii_reg & MIIM_DP83865_DPX_FULL)
1014 priv->duplexity = 1;
1016 priv->duplexity = 0;
1021 struct phy_info phy_info_dp83865 = {
1025 (struct phy_cmd[]) { /* config */
1026 {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1029 (struct phy_cmd[]) { /* startup */
1030 /* Status is read once to clear old link state */
1031 {MIIM_STATUS, miim_read, NULL},
1032 /* Auto-negotiate */
1033 {MIIM_STATUS, miim_read, &mii_parse_sr},
1034 /* Read the link and auto-neg status */
1035 {MIIM_DP83865_LANR, miim_read, &mii_parse_dp83865_lanr},
1038 (struct phy_cmd[]) { /* shutdown */
1043 struct phy_info *phy_info[] = {
1048 &phy_info_M88E1011S,
1049 &phy_info_M88E1111S,
1058 /* Grab the identifier of the device's PHY, and search through
1059 * all of the known PHYs to see if one matches. If so, return
1060 * it, if not, return NULL */
1061 struct phy_info * get_phy_info(struct eth_device *dev)
1063 struct tsec_private *priv = (struct tsec_private *)dev->priv;
1064 uint phy_reg, phy_ID;
1066 struct phy_info *theInfo = NULL;
1068 /* Grab the bits from PHYIR1, and put them in the upper half */
1069 phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1070 phy_ID = (phy_reg & 0xffff) << 16;
1072 /* Grab the bits from PHYIR2, and put them in the lower half */
1073 phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1074 phy_ID |= (phy_reg & 0xffff);
1076 /* loop through all the known PHY types, and find one that */
1077 /* matches the ID we read from the PHY. */
1078 for(i=0; phy_info[i]; i++) {
1079 if(phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
1080 theInfo = phy_info[i];
1085 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1088 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1095 /* Execute the given series of commands on the given device's
1096 * PHY, running functions as necessary*/
1097 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1101 volatile tsec_t *phyregs = priv->phyregs;
1103 phyregs->miimcfg = MIIMCFG_RESET;
1105 phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1107 while(phyregs->miimind & MIIMIND_BUSY);
1109 for(i=0;cmd->mii_reg != miim_end;i++) {
1110 if(cmd->mii_data == miim_read) {
1111 result = read_phy_reg(priv, cmd->mii_reg);
1113 if(cmd->funct != NULL)
1114 (*(cmd->funct))(result, priv);
1117 if(cmd->funct != NULL)
1118 result = (*(cmd->funct))(cmd->mii_reg, priv);
1120 result = cmd->mii_data;
1122 write_phy_reg(priv, cmd->mii_reg, result);
1130 /* Relocate the function pointers in the phy cmd lists */
1131 static void relocate_cmds(void)
1133 struct phy_cmd **cmdlistptr;
1134 struct phy_cmd *cmd;
1137 for(i=0; phy_info[i]; i++) {
1138 /* First thing's first: relocate the pointers to the
1139 * PHY command structures (the structs were done) */
1140 phy_info[i] = (struct phy_info *) ((uint)phy_info[i]
1142 phy_info[i]->name += gd->reloc_off;
1143 phy_info[i]->config =
1144 (struct phy_cmd *)((uint)phy_info[i]->config
1146 phy_info[i]->startup =
1147 (struct phy_cmd *)((uint)phy_info[i]->startup
1149 phy_info[i]->shutdown =
1150 (struct phy_cmd *)((uint)phy_info[i]->shutdown
1153 cmdlistptr = &phy_info[i]->config;
1155 for(;cmdlistptr <= &phy_info[i]->shutdown;cmdlistptr++) {
1157 for(cmd=*cmdlistptr;cmd->mii_reg != miim_end;cmd++) {
1158 /* Only relocate non-NULL pointers */
1160 cmd->funct += gd->reloc_off;
1172 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
1173 && !defined(BITBANGMII)
1175 struct tsec_private * get_priv_for_phy(unsigned char phyaddr)
1179 for(i=0;i<MAXCONTROLLERS;i++) {
1180 if(privlist[i]->phyaddr == phyaddr)
1188 * Read a MII PHY register.
1193 static int tsec_miiphy_read(char *devname, unsigned char addr,
1194 unsigned char reg, unsigned short *value)
1197 struct tsec_private *priv = get_priv_for_phy(addr);
1200 printf("Can't read PHY at address %d\n", addr);
1204 ret = (unsigned short)read_phy_reg(priv, reg);
1211 * Write a MII PHY register.
1216 static int tsec_miiphy_write(char *devname, unsigned char addr,
1217 unsigned char reg, unsigned short value)
1219 struct tsec_private *priv = get_priv_for_phy(addr);
1222 printf("Can't write PHY at address %d\n", addr);
1226 write_phy_reg(priv, reg, value);
1231 #endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1232 && !defined(BITBANGMII) */
1234 #endif /* CONFIG_TSEC_ENET */