drivers/tsec.c

   1 /*
   2  * Freescale Three Speed Ethernet Controller driver
   3  *
   4  * This software may be used and distributed according to the
   5  * terms of the GNU Public License, Version 2, incorporated
   6  * herein by reference.
   7  *
   8  * Copyright 2004, 2007 Freescale Semiconductor, Inc.
   9  * (C) Copyright 2003, Motorola, Inc.
  10  * author Andy Fleming
  11  *
  12  */
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <command.h>
  19
  20 #if defined(CONFIG_TSEC_ENET)
  21 #include "tsec.h"
  22 #include "miiphy.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define TX_BUF_CNT              2
  27
  28 static uint rxIdx;              /* index of the current RX buffer */
  29 static uint txIdx;              /* index of the current TX buffer */
  30
  31 typedef volatile struct rtxbd {
  32         txbd8_t txbd[TX_BUF_CNT];
  33         rxbd8_t rxbd[PKTBUFSRX];
  34 } RTXBD;
  35
  36 struct tsec_info_struct {
  37         unsigned int phyaddr;
  38         u32 flags;
  39         unsigned int phyregidx;
  40 };
  41
  42 /* The tsec_info structure contains 3 values which the
  43  * driver uses to determine how to operate a given ethernet
  44  * device. The information needed is:
  45  *  phyaddr - The address of the PHY which is attached to
  46  *      the given device.
  47  *
  48  *  flags - This variable indicates whether the device
  49  *      supports gigabit speed ethernet, and whether it should be
  50  *      in reduced mode.
  51  *
  52  *  phyregidx - This variable specifies which ethernet device
  53  *      controls the MII Management registers which are connected
  54  *      to the PHY.  For now, only TSEC1 (index 0) has
  55  *      access to the PHYs, so all of the entries have "0".
  56  *
  57  * The values specified in the table are taken from the board's
  58  * config file in include/configs/.  When implementing a new
  59  * board with ethernet capability, it is necessary to define:
  60  *   TSECn_PHY_ADDR
  61  *   TSECn_PHYIDX
  62  *
  63  * for n = 1,2,3, etc.  And for FEC:
  64  *   FEC_PHY_ADDR
  65  *   FEC_PHYIDX
  66  */
  67 static struct tsec_info_struct tsec_info[] = {
  68 #if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
  69 #if defined(CONFIG_MPC8544DS)
  70         {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
  71 #else
  72         {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
  73 #endif
  74 #elif defined(CONFIG_MPC86XX_TSEC1)
  75         {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
  76 #else
  77         {0, 0, 0},
  78 #endif
  79 #if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
  80         {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
  81 #elif defined(CONFIG_MPC86XX_TSEC2)
  82         {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
  83 #else
  84         {0, 0, 0},
  85 #endif
  86 #ifdef CONFIG_MPC85XX_FEC
  87         {FEC_PHY_ADDR, 0, FEC_PHYIDX},
  88 #else
  89 #if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
  90         {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
  91 #else
  92         {0, 0, 0},
  93 #endif
  94 #if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
  95         {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
  96 #else
  97         {0, 0, 0},
  98 #endif
  99 #endif
 100 };
 101
 102 #define MAXCONTROLLERS  (4)
 103
 104 static int relocated = 0;
 105
 106 static struct tsec_private *privlist[MAXCONTROLLERS];
 107
 108 #ifdef __GNUC__
 109 static RTXBD rtx __attribute__ ((aligned(8)));
 110 #else
 111 #error "rtx must be 64-bit aligned"
 112 #endif
 113
 114 static int tsec_send(struct eth_device *dev,
 115                      volatile void *packet, int length);
 116 static int tsec_recv(struct eth_device *dev);
 117 static int tsec_init(struct eth_device *dev, bd_t * bd);
 118 static void tsec_halt(struct eth_device *dev);
 119 static void init_registers(volatile tsec_t * regs);
 120 static void startup_tsec(struct eth_device *dev);
 121 static int init_phy(struct eth_device *dev);
 122 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
 123 uint read_phy_reg(struct tsec_private *priv, uint regnum);
 124 struct phy_info *get_phy_info(struct eth_device *dev);
 125 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
 126 static void adjust_link(struct eth_device *dev);
 127 static void relocate_cmds(void);
 128 static int tsec_miiphy_write(char *devname, unsigned char addr,
 129                              unsigned char reg, unsigned short value);
 130 static int tsec_miiphy_read(char *devname, unsigned char addr,
 131                             unsigned char reg, unsigned short *value);
 132
 133 /* Initialize device structure. Returns success if PHY
 134  * initialization succeeded (i.e. if it recognizes the PHY)
 135  */
 136 int tsec_initialize(bd_t * bis, int index, char *devname)
 137 {
 138         struct eth_device *dev;
 139         int i;
 140         struct tsec_private *priv;
 141
 142         dev = (struct eth_device *)malloc(sizeof *dev);
 143
 144         if (NULL == dev)
 145                 return 0;
 146
 147         memset(dev, 0, sizeof *dev);
 148
 149         priv = (struct tsec_private *)malloc(sizeof(*priv));
 150
 151         if (NULL == priv)
 152                 return 0;
 153
 154         privlist[index] = priv;
 155         priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
 156         priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
 157                                             tsec_info[index].phyregidx *
 158                                             TSEC_SIZE);
 159
 160         priv->phyaddr = tsec_info[index].phyaddr;
 161         priv->flags = tsec_info[index].flags;
 162
 163         sprintf(dev->name, devname);
 164         dev->iobase = 0;
 165         dev->priv = priv;
 166         dev->init = tsec_init;
 167         dev->halt = tsec_halt;
 168         dev->send = tsec_send;
 169         dev->recv = tsec_recv;
 170
 171         /* Tell u-boot to get the addr from the env */
 172         for (i = 0; i < 6; i++)
 173                 dev->enetaddr[i] = 0;
 174
 175         eth_register(dev);
 176
 177         /* Reset the MAC */
 178         priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
 179         priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
 180
 181 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
 182         && !defined(BITBANGMII)
 183         miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
 184 #endif
 185
 186         /* Try to initialize PHY here, and return */
 187         return init_phy(dev);
 188 }
 189
 190 /* Initializes data structures and registers for the controller,
 191  * and brings the interface up.  Returns the link status, meaning
 192  * that it returns success if the link is up, failure otherwise.
 193  * This allows u-boot to find the first active controller.
 194  */
 195 int tsec_init(struct eth_device *dev, bd_t * bd)
 196 {
 197         uint tempval;
 198         char tmpbuf[MAC_ADDR_LEN];
 199         int i;
 200         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 201         volatile tsec_t *regs = priv->regs;
 202
 203         /* Make sure the controller is stopped */
 204         tsec_halt(dev);
 205
 206         /* Init MACCFG2.  Defaults to GMII */
 207         regs->maccfg2 = MACCFG2_INIT_SETTINGS;
 208
 209         /* Init ECNTRL */
 210         regs->ecntrl = ECNTRL_INIT_SETTINGS;
 211
 212         /* Copy the station address into the address registers.
 213          * Backwards, because little endian MACS are dumb */
 214         for (i = 0; i < MAC_ADDR_LEN; i++) {
 215                 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
 216         }
 217         regs->macstnaddr1 = *((uint *) (tmpbuf));
 218
 219         tempval = *((uint *) (tmpbuf + 4));
 220
 221         regs->macstnaddr2 = tempval;
 222
 223         /* reset the indices to zero */
 224         rxIdx = 0;
 225         txIdx = 0;
 226
 227         /* Clear out (for the most part) the other registers */
 228         init_registers(regs);
 229
 230         /* Ready the device for tx/rx */
 231         startup_tsec(dev);
 232
 233         /* If there's no link, fail */
 234         return priv->link;
 235
 236 }
 237
 238 /* Write value to the device's PHY through the registers
 239  * specified in priv, modifying the register specified in regnum.
 240  * It will wait for the write to be done (or for a timeout to
 241  * expire) before exiting
 242  */
 243 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
 244 {
 245         volatile tsec_t *regbase = priv->phyregs;
 246         uint phyid = priv->phyaddr;
 247         int timeout = 1000000;
 248
 249         regbase->miimadd = (phyid << 8) | regnum;
 250         regbase->miimcon = value;
 251         asm("sync");
 252
 253         timeout = 1000000;
 254         while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 255 }
 256
 257 /* Reads register regnum on the device's PHY through the
 258  * registers specified in priv.  It lowers and raises the read
 259  * command, and waits for the data to become valid (miimind
 260  * notvalid bit cleared), and the bus to cease activity (miimind
 261  * busy bit cleared), and then returns the value
 262  */
 263 uint read_phy_reg(struct tsec_private *priv, uint regnum)
 264 {
 265         uint value;
 266         volatile tsec_t *regbase = priv->phyregs;
 267         uint phyid = priv->phyaddr;
 268
 269         /* Put the address of the phy, and the register
 270          * number into MIIMADD */
 271         regbase->miimadd = (phyid << 8) | regnum;
 272
 273         /* Clear the command register, and wait */
 274         regbase->miimcom = 0;
 275         asm("sync");
 276
 277         /* Initiate a read command, and wait */
 278         regbase->miimcom = MIIM_READ_COMMAND;
 279         asm("sync");
 280
 281         /* Wait for the the indication that the read is done */
 282         while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
 283
 284         /* Grab the value read from the PHY */
 285         value = regbase->miimstat;
 286
 287         return value;
 288 }
 289
 290 /* Discover which PHY is attached to the device, and configure it
 291  * properly.  If the PHY is not recognized, then return 0
 292  * (failure).  Otherwise, return 1
 293  */
 294 static int init_phy(struct eth_device *dev)
 295 {
 296         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 297         struct phy_info *curphy;
 298         volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
 299
 300         /* Assign a Physical address to the TBI */
 301         regs->tbipa = TBIPA_VALUE;
 302         regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
 303         regs->tbipa = TBIPA_VALUE;
 304         asm("sync");
 305
 306         /* Reset MII (due to new addresses) */
 307         priv->phyregs->miimcfg = MIIMCFG_RESET;
 308         asm("sync");
 309         priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
 310         asm("sync");
 311         while (priv->phyregs->miimind & MIIMIND_BUSY) ;
 312
 313         if (0 == relocated)
 314                 relocate_cmds();
 315
 316         /* Get the cmd structure corresponding to the attached
 317          * PHY */
 318         curphy = get_phy_info(dev);
 319
 320         if (curphy == NULL) {
 321                 priv->phyinfo = NULL;
 322                 printf("%s: No PHY found\n", dev->name);
 323
 324                 return 0;
 325         }
 326
 327         priv->phyinfo = curphy;
 328
 329         phy_run_commands(priv, priv->phyinfo->config);
 330
 331         return 1;
 332 }
 333
 334 /*
 335  * Returns which value to write to the control register.
 336  * For 10/100, the value is slightly different
 337  */
 338 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
 339 {
 340         if (priv->flags & TSEC_GIGABIT)
 341                 return MIIM_CONTROL_INIT;
 342         else
 343                 return MIIM_CR_INIT;
 344 }
 345
 346 /* Parse the status register for link, and then do
 347  * auto-negotiation
 348  */
 349 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 350 {
 351         /*
 352          * Wait if PHY is capable of autonegotiation and autonegotiation
 353          * is not complete.
 354          */
 355         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 356         if ((mii_reg & PHY_BMSR_AUTN_ABLE)
 357             && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
 358                 int i = 0;
 359
 360                 puts("Waiting for PHY auto negotiation to complete");
 361                 while (!((mii_reg & PHY_BMSR_AUTN_COMP)
 362                          && (mii_reg & MIIM_STATUS_LINK))) {
 363                         /*
 364                          * Timeout reached ?
 365                          */
 366                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 367                                 puts(" TIMEOUT !\n");
 368                                 priv->link = 0;
 369                                 return 0;
 370                         }
 371
 372                         if ((i++ % 1000) == 0) {
 373                                 putc('.');
 374                         }
 375                         udelay(1000);   /* 1 ms */
 376                         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 377                 }
 378                 puts(" done\n");
 379                 priv->link = 1;
 380                 udelay(500000); /* another 500 ms (results in faster booting) */
 381         } else {
 382                 priv->link = 1;
 383         }
 384
 385         return 0;
 386 }
 387
 388 /*
 389  * Parse the BCM54xx status register for speed and duplex information.
 390  * The linux sungem_phy has this information, but in a table format.
 391  */
 392 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
 393 {
 394
 395         switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
 396
 397                 case 1:
 398                         printf("Enet starting in 10BT/HD\n");
 399                         priv->duplexity = 0;
 400                         priv->speed = 10;
 401                         break;
 402
 403                 case 2:
 404                         printf("Enet starting in 10BT/FD\n");
 405                         priv->duplexity = 1;
 406                         priv->speed = 10;
 407                         break;
 408
 409                 case 3:
 410                         printf("Enet starting in 100BT/HD\n");
 411                         priv->duplexity = 0;
 412                         priv->speed = 100;
 413                         break;
 414
 415                 case 5:
 416                         printf("Enet starting in 100BT/FD\n");
 417                         priv->duplexity = 1;
 418                         priv->speed = 100;
 419                         break;
 420
 421                 case 6:
 422                         printf("Enet starting in 1000BT/HD\n");
 423                         priv->duplexity = 0;
 424                         priv->speed = 1000;
 425                         break;
 426
 427                 case 7:
 428                         printf("Enet starting in 1000BT/FD\n");
 429                         priv->duplexity = 1;
 430                         priv->speed = 1000;
 431                         break;
 432
 433                 default:
 434                         printf("Auto-neg error, defaulting to 10BT/HD\n");
 435                         priv->duplexity = 0;
 436                         priv->speed = 10;
 437                         break;
 438         }
 439
 440         return 0;
 441
 442 }
 443 /* Parse the 88E1011's status register for speed and duplex
 444  * information
 445  */
 446 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
 447 {
 448         uint speed;
 449
 450         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 451
 452         if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
 453               (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
 454                 int i = 0;
 455
 456                 puts("Waiting for PHY realtime link");
 457                 while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
 458                          (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
 459                         /*
 460                          * Timeout reached ?
 461                          */
 462                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 463                                 puts(" TIMEOUT !\n");
 464                                 priv->link = 0;
 465                                 break;
 466                         }
 467
 468                         if ((i++ % 1000) == 0) {
 469                                 putc('.');
 470                         }
 471                         udelay(1000);   /* 1 ms */
 472                         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 473                 }
 474                 puts(" done\n");
 475                 udelay(500000); /* another 500 ms (results in faster booting) */
 476         }
 477
 478         if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
 479                 priv->duplexity = 1;
 480         else
 481                 priv->duplexity = 0;
 482
 483         speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
 484
 485         switch (speed) {
 486         case MIIM_88E1011_PHYSTAT_GBIT:
 487                 priv->speed = 1000;
 488                 break;
 489         case MIIM_88E1011_PHYSTAT_100:
 490                 priv->speed = 100;
 491                 break;
 492         default:
 493                 priv->speed = 10;
 494         }
 495
 496         return 0;
 497 }
 498
 499 /* Parse the cis8201's status register for speed and duplex
 500  * information
 501  */
 502 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
 503 {
 504         uint speed;
 505
 506         if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
 507                 priv->duplexity = 1;
 508         else
 509                 priv->duplexity = 0;
 510
 511         speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
 512         switch (speed) {
 513         case MIIM_CIS8201_AUXCONSTAT_GBIT:
 514                 priv->speed = 1000;
 515                 break;
 516         case MIIM_CIS8201_AUXCONSTAT_100:
 517                 priv->speed = 100;
 518                 break;
 519         default:
 520                 priv->speed = 10;
 521                 break;
 522         }
 523
 524         return 0;
 525 }
 526
 527 /* Parse the vsc8244's status register for speed and duplex
 528  * information
 529  */
 530 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
 531 {
 532         uint speed;
 533
 534         if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
 535                 priv->duplexity = 1;
 536         else
 537                 priv->duplexity = 0;
 538
 539         speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
 540         switch (speed) {
 541         case MIIM_VSC8244_AUXCONSTAT_GBIT:
 542                 priv->speed = 1000;
 543                 break;
 544         case MIIM_VSC8244_AUXCONSTAT_100:
 545                 priv->speed = 100;
 546                 break;
 547         default:
 548                 priv->speed = 10;
 549                 break;
 550         }
 551
 552         return 0;
 553 }
 554
 555 /* Parse the DM9161's status register for speed and duplex
 556  * information
 557  */
 558 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
 559 {
 560         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
 561                 priv->speed = 100;
 562         else
 563                 priv->speed = 10;
 564
 565         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
 566                 priv->duplexity = 1;
 567         else
 568                 priv->duplexity = 0;
 569
 570         return 0;
 571 }
 572
 573 /*
 574  * Hack to write all 4 PHYs with the LED values
 575  */
 576 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
 577 {
 578         uint phyid;
 579         volatile tsec_t *regbase = priv->phyregs;
 580         int timeout = 1000000;
 581
 582         for (phyid = 0; phyid < 4; phyid++) {
 583                 regbase->miimadd = (phyid << 8) | mii_reg;
 584                 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
 585                 asm("sync");
 586
 587                 timeout = 1000000;
 588                 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 589         }
 590
 591         return MIIM_CIS8204_SLEDCON_INIT;
 592 }
 593
 594 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
 595 {
 596         if (priv->flags & TSEC_REDUCED)
 597                 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
 598         else
 599                 return MIIM_CIS8204_EPHYCON_INIT;
 600 }
 601
 602 /* Initialized required registers to appropriate values, zeroing
 603  * those we don't care about (unless zero is bad, in which case,
 604  * choose a more appropriate value)
 605  */
 606 static void init_registers(volatile tsec_t * regs)
 607 {
 608         /* Clear IEVENT */
 609         regs->ievent = IEVENT_INIT_CLEAR;
 610
 611         regs->imask = IMASK_INIT_CLEAR;
 612
 613         regs->hash.iaddr0 = 0;
 614         regs->hash.iaddr1 = 0;
 615         regs->hash.iaddr2 = 0;
 616         regs->hash.iaddr3 = 0;
 617         regs->hash.iaddr4 = 0;
 618         regs->hash.iaddr5 = 0;
 619         regs->hash.iaddr6 = 0;
 620         regs->hash.iaddr7 = 0;
 621
 622         regs->hash.gaddr0 = 0;
 623         regs->hash.gaddr1 = 0;
 624         regs->hash.gaddr2 = 0;
 625         regs->hash.gaddr3 = 0;
 626         regs->hash.gaddr4 = 0;
 627         regs->hash.gaddr5 = 0;
 628         regs->hash.gaddr6 = 0;
 629         regs->hash.gaddr7 = 0;
 630
 631         regs->rctrl = 0x00000000;
 632
 633         /* Init RMON mib registers */
 634         memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
 635
 636         regs->rmon.cam1 = 0xffffffff;
 637         regs->rmon.cam2 = 0xffffffff;
 638
 639         regs->mrblr = MRBLR_INIT_SETTINGS;
 640
 641         regs->minflr = MINFLR_INIT_SETTINGS;
 642
 643         regs->attr = ATTR_INIT_SETTINGS;
 644         regs->attreli = ATTRELI_INIT_SETTINGS;
 645
 646 }
 647
 648 /* Configure maccfg2 based on negotiated speed and duplex
 649  * reported by PHY handling code
 650  */
 651 static void adjust_link(struct eth_device *dev)
 652 {
 653         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 654         volatile tsec_t *regs = priv->regs;
 655
 656         if (priv->link) {
 657                 if (priv->duplexity != 0)
 658                         regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
 659                 else
 660                         regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
 661
 662                 switch (priv->speed) {
 663                 case 1000:
 664                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 665                                          | MACCFG2_GMII);
 666                         break;
 667                 case 100:
 668                 case 10:
 669                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 670                                          | MACCFG2_MII);
 671
 672                         /* Set R100 bit in all modes although
 673                          * it is only used in RGMII mode
 674                          */
 675                         if (priv->speed == 100)
 676                                 regs->ecntrl |= ECNTRL_R100;
 677                         else
 678                                 regs->ecntrl &= ~(ECNTRL_R100);
 679                         break;
 680                 default:
 681                         printf("%s: Speed was bad\n", dev->name);
 682                         break;
 683                 }
 684
 685                 printf("Speed: %d, %s duplex\n", priv->speed,
 686                        (priv->duplexity) ? "full" : "half");
 687
 688         } else {
 689                 printf("%s: No link.\n", dev->name);
 690         }
 691 }
 692
 693 /* Set up the buffers and their descriptors, and bring up the
 694  * interface
 695  */
 696 static void startup_tsec(struct eth_device *dev)
 697 {
 698         int i;
 699         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 700         volatile tsec_t *regs = priv->regs;
 701
 702         /* Point to the buffer descriptors */
 703         regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
 704         regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
 705
 706         /* Initialize the Rx Buffer descriptors */
 707         for (i = 0; i < PKTBUFSRX; i++) {
 708                 rtx.rxbd[i].status = RXBD_EMPTY;
 709                 rtx.rxbd[i].length = 0;
 710                 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
 711         }
 712         rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
 713
 714         /* Initialize the TX Buffer Descriptors */
 715         for (i = 0; i < TX_BUF_CNT; i++) {
 716                 rtx.txbd[i].status = 0;
 717                 rtx.txbd[i].length = 0;
 718                 rtx.txbd[i].bufPtr = 0;
 719         }
 720         rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
 721
 722         /* Start up the PHY */
 723         if(priv->phyinfo)
 724                 phy_run_commands(priv, priv->phyinfo->startup);
 725         adjust_link(dev);
 726
 727         /* Enable Transmit and Receive */
 728         regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 729
 730         /* Tell the DMA it is clear to go */
 731         regs->dmactrl |= DMACTRL_INIT_SETTINGS;
 732         regs->tstat = TSTAT_CLEAR_THALT;
 733         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 734 }
 735
 736 /* This returns the status bits of the device.  The return value
 737  * is never checked, and this is what the 8260 driver did, so we
 738  * do the same.  Presumably, this would be zero if there were no
 739  * errors
 740  */
 741 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
 742 {
 743         int i;
 744         int result = 0;
 745         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 746         volatile tsec_t *regs = priv->regs;
 747
 748         /* Find an empty buffer descriptor */
 749         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 750                 if (i >= TOUT_LOOP) {
 751                         debug("%s: tsec: tx buffers full\n", dev->name);
 752                         return result;
 753                 }
 754         }
 755
 756         rtx.txbd[txIdx].bufPtr = (uint) packet;
 757         rtx.txbd[txIdx].length = length;
 758         rtx.txbd[txIdx].status |=
 759             (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
 760
 761         /* Tell the DMA to go */
 762         regs->tstat = TSTAT_CLEAR_THALT;
 763
 764         /* Wait for buffer to be transmitted */
 765         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 766                 if (i >= TOUT_LOOP) {
 767                         debug("%s: tsec: tx error\n", dev->name);
 768                         return result;
 769                 }
 770         }
 771
 772         txIdx = (txIdx + 1) % TX_BUF_CNT;
 773         result = rtx.txbd[txIdx].status & TXBD_STATS;
 774
 775         return result;
 776 }
 777
 778 static int tsec_recv(struct eth_device *dev)
 779 {
 780         int length;
 781         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 782         volatile tsec_t *regs = priv->regs;
 783
 784         while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
 785
 786                 length = rtx.rxbd[rxIdx].length;
 787
 788                 /* Send the packet up if there were no errors */
 789                 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
 790                         NetReceive(NetRxPackets[rxIdx], length - 4);
 791                 } else {
 792                         printf("Got error %x\n",
 793                                (rtx.rxbd[rxIdx].status & RXBD_STATS));
 794                 }
 795
 796                 rtx.rxbd[rxIdx].length = 0;
 797
 798                 /* Set the wrap bit if this is the last element in the list */
 799                 rtx.rxbd[rxIdx].status =
 800                     RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
 801
 802                 rxIdx = (rxIdx + 1) % PKTBUFSRX;
 803         }
 804
 805         if (regs->ievent & IEVENT_BSY) {
 806                 regs->ievent = IEVENT_BSY;
 807                 regs->rstat = RSTAT_CLEAR_RHALT;
 808         }
 809
 810         return -1;
 811
 812 }
 813
 814 /* Stop the interface */
 815 static void tsec_halt(struct eth_device *dev)
 816 {
 817         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 818         volatile tsec_t *regs = priv->regs;
 819
 820         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 821         regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
 822
 823         while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
 824
 825         regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
 826
 827         /* Shut down the PHY, as needed */
 828         if(priv->phyinfo)
 829                 phy_run_commands(priv, priv->phyinfo->shutdown);
 830 }
 831
 832 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
 833 struct phy_info phy_info_BCM5461S = {
 834         0x02060c1,      /* 5461 ID */
 835         "Broadcom BCM5461S",
 836         0, /* not clear to me what minor revisions we can shift away */
 837         (struct phy_cmd[]) { /* config */
 838                 /* Reset and configure the PHY */
 839                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 840                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 841                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 842                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 843                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 844                 {miim_end,}
 845         },
 846         (struct phy_cmd[]) { /* startup */
 847                 /* Status is read once to clear old link state */
 848                 {MIIM_STATUS, miim_read, NULL},
 849                 /* Auto-negotiate */
 850                 {MIIM_STATUS, miim_read, &mii_parse_sr},
 851                 /* Read the status */
 852                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
 853                 {miim_end,}
 854         },
 855         (struct phy_cmd[]) { /* shutdown */
 856                 {miim_end,}
 857         },
 858 };
 859
 860 struct phy_info phy_info_M88E1011S = {
 861         0x01410c6,
 862         "Marvell 88E1011S",
 863         4,
 864         (struct phy_cmd[]){     /* config */
 865                            /* Reset and configure the PHY */
 866                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 867                            {0x1d, 0x1f, NULL},
 868                            {0x1e, 0x200c, NULL},
 869                            {0x1d, 0x5, NULL},
 870                            {0x1e, 0x0, NULL},
 871                            {0x1e, 0x100, NULL},
 872                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 873                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 874                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 875                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 876                            {miim_end,}
 877                            },
 878         (struct phy_cmd[]){     /* startup */
 879                            /* Status is read once to clear old link state */
 880                            {MIIM_STATUS, miim_read, NULL},
 881                            /* Auto-negotiate */
 882                            {MIIM_STATUS, miim_read, &mii_parse_sr},
 883                            /* Read the status */
 884                            {MIIM_88E1011_PHY_STATUS, miim_read,
 885                             &mii_parse_88E1011_psr},
 886                            {miim_end,}
 887                            },
 888         (struct phy_cmd[]){     /* shutdown */
 889                            {miim_end,}
 890                            },
 891 };
 892
 893 struct phy_info phy_info_M88E1111S = {
 894         0x01410cc,
 895         "Marvell 88E1111S",
 896         4,
 897         (struct phy_cmd[]){     /* config */
 898                            /* Reset and configure the PHY */
 899                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 900                            {0x1d, 0x1f, NULL},
 901                            {0x1e, 0x200c, NULL},
 902                            {0x1d, 0x5, NULL},
 903                            {0x1e, 0x0, NULL},
 904                            {0x1e, 0x100, NULL},
 905                            {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
 906                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 907                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 908                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 909                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 910                            {miim_end,}
 911                            },
 912         (struct phy_cmd[]){     /* startup */
 913                            /* Status is read once to clear old link state */
 914                            {MIIM_STATUS, miim_read, NULL},
 915                            /* Auto-negotiate */
 916                            {MIIM_STATUS, miim_read, &mii_parse_sr},
 917                            /* Read the status */
 918                            {MIIM_88E1011_PHY_STATUS, miim_read,
 919                             &mii_parse_88E1011_psr},
 920                            {miim_end,}
 921                            },
 922         (struct phy_cmd[]){     /* shutdown */
 923                            {miim_end,}
 924                            },
 925 };
 926
 927 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
 928 {
 929         uint mii_data = read_phy_reg(priv, mii_reg);
 930
 931         /* Setting MIIM_88E1145_PHY_EXT_CR */
 932         if (priv->flags & TSEC_REDUCED)
 933                 return mii_data |
 934                     MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
 935         else
 936                 return mii_data;
 937 }
 938
 939 static struct phy_info phy_info_M88E1145 = {
 940         0x01410cd,
 941         "Marvell 88E1145",
 942         4,
 943         (struct phy_cmd[]){     /* config */
 944                            /* Errata E0, E1 */
 945                            {29, 0x001b, NULL},
 946                            {30, 0x418f, NULL},
 947                            {29, 0x0016, NULL},
 948                            {30, 0xa2da, NULL},
 949
 950                            /* Reset and configure the PHY */
 951                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 952                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 953                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 954                            {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
 955                             NULL},
 956                            {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
 957                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 958                            {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
 959                            {miim_end,}
 960                            },
 961         (struct phy_cmd[]){     /* startup */
 962                            /* Status is read once to clear old link state */
 963                            {MIIM_STATUS, miim_read, NULL},
 964                            /* Auto-negotiate */
 965                            {MIIM_STATUS, miim_read, &mii_parse_sr},
 966                            {MIIM_88E1111_PHY_LED_CONTROL,
 967                             MIIM_88E1111_PHY_LED_DIRECT, NULL},
 968                            /* Read the Status */
 969                            {MIIM_88E1011_PHY_STATUS, miim_read,
 970                             &mii_parse_88E1011_psr},
 971                            {miim_end,}
 972                            },
 973         (struct phy_cmd[]){     /* shutdown */
 974                            {miim_end,}
 975                            },
 976 };
 977
 978 struct phy_info phy_info_cis8204 = {
 979         0x3f11,
 980         "Cicada Cis8204",
 981         6,
 982         (struct phy_cmd[]){     /* config */
 983                            /* Override PHY config settings */
 984                            {MIIM_CIS8201_AUX_CONSTAT,
 985                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
 986                            /* Configure some basic stuff */
 987                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 988                            {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
 989                             &mii_cis8204_fixled},
 990                            {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
 991                             &mii_cis8204_setmode},
 992                            {miim_end,}
 993                            },
 994         (struct phy_cmd[]){     /* startup */
 995                            /* Read the Status (2x to make sure link is right) */
 996                            {MIIM_STATUS, miim_read, NULL},
 997                            /* Auto-negotiate */
 998                            {MIIM_STATUS, miim_read, &mii_parse_sr},
 999                            /* Read the status */
1000                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1001                             &mii_parse_cis8201},
1002                            {miim_end,}
1003                            },
1004         (struct phy_cmd[]){     /* shutdown */
1005                            {miim_end,}
1006                            },
1007 };
1008
1009 /* Cicada 8201 */
1010 struct phy_info phy_info_cis8201 = {
1011         0xfc41,
1012         "CIS8201",
1013         4,
1014         (struct phy_cmd[]){     /* config */
1015                            /* Override PHY config settings */
1016                            {MIIM_CIS8201_AUX_CONSTAT,
1017                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1018                            /* Set up the interface mode */
1019                            {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1020                             NULL},
1021                            /* Configure some basic stuff */
1022                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1023                            {miim_end,}
1024                            },
1025         (struct phy_cmd[]){     /* startup */
1026                            /* Read the Status (2x to make sure link is right) */
1027                            {MIIM_STATUS, miim_read, NULL},
1028                            /* Auto-negotiate */
1029                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1030                            /* Read the status */
1031                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1032                             &mii_parse_cis8201},
1033                            {miim_end,}
1034                            },
1035         (struct phy_cmd[]){     /* shutdown */
1036                            {miim_end,}
1037                            },
1038 };
1039 struct phy_info phy_info_VSC8244 = {
1040         0x3f1b,
1041         "Vitesse VSC8244",
1042         6,
1043         (struct phy_cmd[]){     /* config */
1044                            /* Override PHY config settings */
1045                            /* Configure some basic stuff */
1046                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1047                            {miim_end,}
1048                            },
1049         (struct phy_cmd[]){     /* startup */
1050                            /* Read the Status (2x to make sure link is right) */
1051                            {MIIM_STATUS, miim_read, NULL},
1052                            /* Auto-negotiate */
1053                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1054                            /* Read the status */
1055                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1056                             &mii_parse_vsc8244},
1057                            {miim_end,}
1058                            },
1059         (struct phy_cmd[]){     /* shutdown */
1060                            {miim_end,}
1061                            },
1062 };
1063
1064 struct phy_info phy_info_dm9161 = {
1065         0x0181b88,
1066         "Davicom DM9161E",
1067         4,
1068         (struct phy_cmd[]){     /* config */
1069                            {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1070                            /* Do not bypass the scrambler/descrambler */
1071                            {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1072                            /* Clear 10BTCSR to default */
1073                            {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1074                             NULL},
1075                            /* Configure some basic stuff */
1076                            {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1077                            /* Restart Auto Negotiation */
1078                            {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1079                            {miim_end,}
1080                            },
1081         (struct phy_cmd[]){     /* startup */
1082                            /* Status is read once to clear old link state */
1083                            {MIIM_STATUS, miim_read, NULL},
1084                            /* Auto-negotiate */
1085                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1086                            /* Read the status */
1087                            {MIIM_DM9161_SCSR, miim_read,
1088                             &mii_parse_dm9161_scsr},
1089                            {miim_end,}
1090                            },
1091         (struct phy_cmd[]){     /* shutdown */
1092                            {miim_end,}
1093                            },
1094 };
1095
1096 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1097 {
1098         unsigned int speed;
1099         if (priv->link) {
1100                 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1101
1102                 switch (speed) {
1103                 case MIIM_LXT971_SR2_10HDX:
1104                         priv->speed = 10;
1105                         priv->duplexity = 0;
1106                         break;
1107                 case MIIM_LXT971_SR2_10FDX:
1108                         priv->speed = 10;
1109                         priv->duplexity = 1;
1110                         break;
1111                 case MIIM_LXT971_SR2_100HDX:
1112                         priv->speed = 100;
1113                         priv->duplexity = 0;
1114                 default:
1115                         priv->speed = 100;
1116                         priv->duplexity = 1;
1117                         break;
1118                 }
1119         } else {
1120                 priv->speed = 0;
1121                 priv->duplexity = 0;
1122         }
1123
1124         return 0;
1125 }
1126
1127 static struct phy_info phy_info_lxt971 = {
1128         0x0001378e,
1129         "LXT971",
1130         4,
1131         (struct phy_cmd[]){     /* config */
1132                            {MIIM_CR, MIIM_CR_INIT, mii_cr_init},        /* autonegotiate */
1133                            {miim_end,}
1134                            },
1135         (struct phy_cmd[]){     /* startup - enable interrupts */
1136                            /* { 0x12, 0x00f2, NULL }, */
1137                            {MIIM_STATUS, miim_read, NULL},
1138                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1139                            {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1140                            {miim_end,}
1141                            },
1142         (struct phy_cmd[]){     /* shutdown - disable interrupts */
1143                            {miim_end,}
1144                            },
1145 };
1146
1147 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1148  * information
1149  */
1150 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1151 {
1152         switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1153
1154         case MIIM_DP83865_SPD_1000:
1155                 priv->speed = 1000;
1156                 break;
1157
1158         case MIIM_DP83865_SPD_100:
1159                 priv->speed = 100;
1160                 break;
1161
1162         default:
1163                 priv->speed = 10;
1164                 break;
1165
1166         }
1167
1168         if (mii_reg & MIIM_DP83865_DPX_FULL)
1169                 priv->duplexity = 1;
1170         else
1171                 priv->duplexity = 0;
1172
1173         return 0;
1174 }
1175
1176 struct phy_info phy_info_dp83865 = {
1177         0x20005c7,
1178         "NatSemi DP83865",
1179         4,
1180         (struct phy_cmd[]){     /* config */
1181                            {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1182                            {miim_end,}
1183                            },
1184         (struct phy_cmd[]){     /* startup */
1185                            /* Status is read once to clear old link state */
1186                            {MIIM_STATUS, miim_read, NULL},
1187                            /* Auto-negotiate */
1188                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1189                            /* Read the link and auto-neg status */
1190                            {MIIM_DP83865_LANR, miim_read,
1191                             &mii_parse_dp83865_lanr},
1192                            {miim_end,}
1193                            },
1194         (struct phy_cmd[]){     /* shutdown */
1195                            {miim_end,}
1196                            },
1197 };
1198
1199 struct phy_info *phy_info[] = {
1200         &phy_info_cis8204,
1201         &phy_info_cis8201,
1202         &phy_info_BCM5461S,
1203         &phy_info_M88E1011S,
1204         &phy_info_M88E1111S,
1205         &phy_info_M88E1145,
1206         &phy_info_dm9161,
1207         &phy_info_lxt971,
1208         &phy_info_VSC8244,
1209         &phy_info_dp83865,
1210         NULL
1211 };
1212
1213 /* Grab the identifier of the device's PHY, and search through
1214  * all of the known PHYs to see if one matches.  If so, return
1215  * it, if not, return NULL
1216  */
1217 struct phy_info *get_phy_info(struct eth_device *dev)
1218 {
1219         struct tsec_private *priv = (struct tsec_private *)dev->priv;
1220         uint phy_reg, phy_ID;
1221         int i;
1222         struct phy_info *theInfo = NULL;
1223
1224         /* Grab the bits from PHYIR1, and put them in the upper half */
1225         phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1226         phy_ID = (phy_reg & 0xffff) << 16;
1227
1228         /* Grab the bits from PHYIR2, and put them in the lower half */
1229         phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1230         phy_ID |= (phy_reg & 0xffff);
1231
1232         /* loop through all the known PHY types, and find one that */
1233         /* matches the ID we read from the PHY. */
1234         for (i = 0; phy_info[i]; i++) {
1235                 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift))
1236                         theInfo = phy_info[i];
1237         }
1238
1239         if (theInfo == NULL) {
1240                 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1241                 return NULL;
1242         } else {
1243                 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1244         }
1245
1246         return theInfo;
1247 }
1248
1249 /* Execute the given series of commands on the given device's
1250  * PHY, running functions as necessary
1251  */
1252 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1253 {
1254         int i;
1255         uint result;
1256         volatile tsec_t *phyregs = priv->phyregs;
1257
1258         phyregs->miimcfg = MIIMCFG_RESET;
1259
1260         phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1261
1262         while (phyregs->miimind & MIIMIND_BUSY) ;
1263
1264         for (i = 0; cmd->mii_reg != miim_end; i++) {
1265                 if (cmd->mii_data == miim_read) {
1266                         result = read_phy_reg(priv, cmd->mii_reg);
1267
1268                         if (cmd->funct != NULL)
1269                                 (*(cmd->funct)) (result, priv);
1270
1271                 } else {
1272                         if (cmd->funct != NULL)
1273                                 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1274                         else
1275                                 result = cmd->mii_data;
1276
1277                         write_phy_reg(priv, cmd->mii_reg, result);
1278
1279                 }
1280                 cmd++;
1281         }
1282 }
1283
1284 /* Relocate the function pointers in the phy cmd lists */
1285 static void relocate_cmds(void)
1286 {
1287         struct phy_cmd **cmdlistptr;
1288         struct phy_cmd *cmd;
1289         int i, j, k;
1290
1291         for (i = 0; phy_info[i]; i++) {
1292                 /* First thing's first: relocate the pointers to the
1293                  * PHY command structures (the structs were done) */
1294                 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1295                                                   + gd->reloc_off);
1296                 phy_info[i]->name += gd->reloc_off;
1297                 phy_info[i]->config =
1298                     (struct phy_cmd *)((uint) phy_info[i]->config
1299                                        + gd->reloc_off);
1300                 phy_info[i]->startup =
1301                     (struct phy_cmd *)((uint) phy_info[i]->startup
1302                                        + gd->reloc_off);
1303                 phy_info[i]->shutdown =
1304                     (struct phy_cmd *)((uint) phy_info[i]->shutdown
1305                                        + gd->reloc_off);
1306
1307                 cmdlistptr = &phy_info[i]->config;
1308                 j = 0;
1309                 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1310                         k = 0;
1311                         for (cmd = *cmdlistptr;
1312                              cmd->mii_reg != miim_end;
1313                              cmd++) {
1314                                 /* Only relocate non-NULL pointers */
1315                                 if (cmd->funct)
1316                                         cmd->funct += gd->reloc_off;
1317
1318                                 k++;
1319                         }
1320                         j++;
1321                 }
1322         }
1323
1324         relocated = 1;
1325 }
1326
1327 #if defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII) \
1328         && !defined(BITBANGMII)
1329
1330 struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
1331 {
1332         int i;
1333
1334         for (i = 0; i < MAXCONTROLLERS; i++) {
1335                 if (privlist[i]->phyaddr == phyaddr)
1336                         return privlist[i];
1337         }
1338
1339         return NULL;
1340 }
1341
1342 /*
1343  * Read a MII PHY register.
1344  *
1345  * Returns:
1346  *  0 on success
1347  */
1348 static int tsec_miiphy_read(char *devname, unsigned char addr,
1349                             unsigned char reg, unsigned short *value)
1350 {
1351         unsigned short ret;
1352         struct tsec_private *priv = get_priv_for_phy(addr);
1353
1354         if (NULL == priv) {
1355                 printf("Can't read PHY at address %d\n", addr);
1356                 return -1;
1357         }
1358
1359         ret = (unsigned short)read_phy_reg(priv, reg);
1360         *value = ret;
1361
1362         return 0;
1363 }
1364
1365 /*
1366  * Write a MII PHY register.
1367  *
1368  * Returns:
1369  *  0 on success
1370  */
1371 static int tsec_miiphy_write(char *devname, unsigned char addr,
1372                              unsigned char reg, unsigned short value)
1373 {
1374         struct tsec_private *priv = get_priv_for_phy(addr);
1375
1376         if (NULL == priv) {
1377                 printf("Can't write PHY at address %d\n", addr);
1378                 return -1;
1379         }
1380
1381         write_phy_reg(priv, reg, value);
1382
1383         return 0;
1384 }
1385
1386 #endif /* defined(CONFIG_MII) || (CONFIG_COMMANDS & CFG_CMD_MII)
1387                 && !defined(BITBANGMII) */
1388
1389 #endif /* CONFIG_TSEC_ENET */