drivers/tsec.c

   1 /*
   2  * Freescale Three Speed Ethernet Controller driver
   3  *
   4  * This software may be used and distributed according to the
   5  * terms of the GNU Public License, Version 2, incorporated
   6  * herein by reference.
   7  *
   8  * Copyright 2004, 2007 Freescale Semiconductor, Inc.
   9  * (C) Copyright 2003, Motorola, Inc.
  10  * author Andy Fleming
  11  *
  12  */
  13
  14 #include <config.h>
  15 #include <common.h>
  16 #include <malloc.h>
  17 #include <net.h>
  18 #include <command.h>
  19
  20 #if defined(CONFIG_TSEC_ENET)
  21 #include "tsec.h"
  22 #include "miiphy.h"
  23
  24 DECLARE_GLOBAL_DATA_PTR;
  25
  26 #define TX_BUF_CNT              2
  27
  28 static uint rxIdx;              /* index of the current RX buffer */
  29 static uint txIdx;              /* index of the current TX buffer */
  30
  31 typedef volatile struct rtxbd {
  32         txbd8_t txbd[TX_BUF_CNT];
  33         rxbd8_t rxbd[PKTBUFSRX];
  34 } RTXBD;
  35
  36 struct tsec_info_struct {
  37         unsigned int phyaddr;
  38         u32 flags;
  39         unsigned int phyregidx;
  40 };
  41
  42 /* The tsec_info structure contains 3 values which the
  43  * driver uses to determine how to operate a given ethernet
  44  * device. The information needed is:
  45  *  phyaddr - The address of the PHY which is attached to
  46  *      the given device.
  47  *
  48  *  flags - This variable indicates whether the device
  49  *      supports gigabit speed ethernet, and whether it should be
  50  *      in reduced mode.
  51  *
  52  *  phyregidx - This variable specifies which ethernet device
  53  *      controls the MII Management registers which are connected
  54  *      to the PHY.  For now, only TSEC1 (index 0) has
  55  *      access to the PHYs, so all of the entries have "0".
  56  *
  57  * The values specified in the table are taken from the board's
  58  * config file in include/configs/.  When implementing a new
  59  * board with ethernet capability, it is necessary to define:
  60  *   TSECn_PHY_ADDR
  61  *   TSECn_PHYIDX
  62  *
  63  * for n = 1,2,3, etc.  And for FEC:
  64  *   FEC_PHY_ADDR
  65  *   FEC_PHYIDX
  66  */
  67 static struct tsec_info_struct tsec_info[] = {
  68 #if defined(CONFIG_TSEC1)
  69 #if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN)
  70         {TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
  71 #else
  72         {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
  73 #endif
  74         {0, 0, 0},
  75 #endif
  76 #if defined(CONFIG_TSEC2)
  77 #if defined(CONFIG_MPC8641HPCN)
  78         {TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
  79 #else
  80         {TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
  81 #endif
  82         {0, 0, 0},
  83 #endif
  84 #ifdef CONFIG_MPC85XX_FEC
  85         {FEC_PHY_ADDR, 0, FEC_PHYIDX},
  86 #else
  87 #if defined(CONFIG_TSEC3)
  88         {TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
  89 #else
  90         {0, 0, 0},
  91 #endif
  92 #if defined(CONFIG_TSEC4)
  93         {TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
  94 #else
  95         {0, 0, 0},
  96 #endif
  97 #endif
  98 };
  99
 100 #define MAXCONTROLLERS  (4)
 101
 102 static int relocated = 0;
 103
 104 static struct tsec_private *privlist[MAXCONTROLLERS];
 105
 106 #ifdef __GNUC__
 107 static RTXBD rtx __attribute__ ((aligned(8)));
 108 #else
 109 #error "rtx must be 64-bit aligned"
 110 #endif
 111
 112 static int tsec_send(struct eth_device *dev,
 113                      volatile void *packet, int length);
 114 static int tsec_recv(struct eth_device *dev);
 115 static int tsec_init(struct eth_device *dev, bd_t * bd);
 116 static void tsec_halt(struct eth_device *dev);
 117 static void init_registers(volatile tsec_t * regs);
 118 static void startup_tsec(struct eth_device *dev);
 119 static int init_phy(struct eth_device *dev);
 120 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value);
 121 uint read_phy_reg(struct tsec_private *priv, uint regnum);
 122 struct phy_info *get_phy_info(struct eth_device *dev);
 123 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd);
 124 static void adjust_link(struct eth_device *dev);
 125 static void relocate_cmds(void);
 126 static int tsec_miiphy_write(char *devname, unsigned char addr,
 127                              unsigned char reg, unsigned short value);
 128 static int tsec_miiphy_read(char *devname, unsigned char addr,
 129                             unsigned char reg, unsigned short *value);
 130
 131 /* Initialize device structure. Returns success if PHY
 132  * initialization succeeded (i.e. if it recognizes the PHY)
 133  */
 134 int tsec_initialize(bd_t * bis, int index, char *devname)
 135 {
 136         struct eth_device *dev;
 137         int i;
 138         struct tsec_private *priv;
 139
 140         dev = (struct eth_device *)malloc(sizeof *dev);
 141
 142         if (NULL == dev)
 143                 return 0;
 144
 145         memset(dev, 0, sizeof *dev);
 146
 147         priv = (struct tsec_private *)malloc(sizeof(*priv));
 148
 149         if (NULL == priv)
 150                 return 0;
 151
 152         privlist[index] = priv;
 153         priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
 154         priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
 155                                             tsec_info[index].phyregidx *
 156                                             TSEC_SIZE);
 157
 158         priv->phyaddr = tsec_info[index].phyaddr;
 159         priv->flags = tsec_info[index].flags;
 160
 161         sprintf(dev->name, devname);
 162         dev->iobase = 0;
 163         dev->priv = priv;
 164         dev->init = tsec_init;
 165         dev->halt = tsec_halt;
 166         dev->send = tsec_send;
 167         dev->recv = tsec_recv;
 168
 169         /* Tell u-boot to get the addr from the env */
 170         for (i = 0; i < 6; i++)
 171                 dev->enetaddr[i] = 0;
 172
 173         eth_register(dev);
 174
 175         /* Reset the MAC */
 176         priv->regs->maccfg1 |= MACCFG1_SOFT_RESET;
 177         priv->regs->maccfg1 &= ~(MACCFG1_SOFT_RESET);
 178
 179 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
 180         && !defined(BITBANGMII)
 181         miiphy_register(dev->name, tsec_miiphy_read, tsec_miiphy_write);
 182 #endif
 183
 184         /* Try to initialize PHY here, and return */
 185         return init_phy(dev);
 186 }
 187
 188 /* Initializes data structures and registers for the controller,
 189  * and brings the interface up.  Returns the link status, meaning
 190  * that it returns success if the link is up, failure otherwise.
 191  * This allows u-boot to find the first active controller.
 192  */
 193 int tsec_init(struct eth_device *dev, bd_t * bd)
 194 {
 195         uint tempval;
 196         char tmpbuf[MAC_ADDR_LEN];
 197         int i;
 198         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 199         volatile tsec_t *regs = priv->regs;
 200
 201         /* Make sure the controller is stopped */
 202         tsec_halt(dev);
 203
 204         /* Init MACCFG2.  Defaults to GMII */
 205         regs->maccfg2 = MACCFG2_INIT_SETTINGS;
 206
 207         /* Init ECNTRL */
 208         regs->ecntrl = ECNTRL_INIT_SETTINGS;
 209
 210         /* Copy the station address into the address registers.
 211          * Backwards, because little endian MACS are dumb */
 212         for (i = 0; i < MAC_ADDR_LEN; i++) {
 213                 tmpbuf[MAC_ADDR_LEN - 1 - i] = dev->enetaddr[i];
 214         }
 215         regs->macstnaddr1 = *((uint *) (tmpbuf));
 216
 217         tempval = *((uint *) (tmpbuf + 4));
 218
 219         regs->macstnaddr2 = tempval;
 220
 221         /* reset the indices to zero */
 222         rxIdx = 0;
 223         txIdx = 0;
 224
 225         /* Clear out (for the most part) the other registers */
 226         init_registers(regs);
 227
 228         /* Ready the device for tx/rx */
 229         startup_tsec(dev);
 230
 231         /* If there's no link, fail */
 232         return priv->link;
 233
 234 }
 235
 236 /* Write value to the device's PHY through the registers
 237  * specified in priv, modifying the register specified in regnum.
 238  * It will wait for the write to be done (or for a timeout to
 239  * expire) before exiting
 240  */
 241 void write_phy_reg(struct tsec_private *priv, uint regnum, uint value)
 242 {
 243         volatile tsec_t *regbase = priv->phyregs;
 244         uint phyid = priv->phyaddr;
 245         int timeout = 1000000;
 246
 247         regbase->miimadd = (phyid << 8) | regnum;
 248         regbase->miimcon = value;
 249         asm("sync");
 250
 251         timeout = 1000000;
 252         while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 253 }
 254
 255 /* Reads register regnum on the device's PHY through the
 256  * registers specified in priv.  It lowers and raises the read
 257  * command, and waits for the data to become valid (miimind
 258  * notvalid bit cleared), and the bus to cease activity (miimind
 259  * busy bit cleared), and then returns the value
 260  */
 261 uint read_phy_reg(struct tsec_private *priv, uint regnum)
 262 {
 263         uint value;
 264         volatile tsec_t *regbase = priv->phyregs;
 265         uint phyid = priv->phyaddr;
 266
 267         /* Put the address of the phy, and the register
 268          * number into MIIMADD */
 269         regbase->miimadd = (phyid << 8) | regnum;
 270
 271         /* Clear the command register, and wait */
 272         regbase->miimcom = 0;
 273         asm("sync");
 274
 275         /* Initiate a read command, and wait */
 276         regbase->miimcom = MIIM_READ_COMMAND;
 277         asm("sync");
 278
 279         /* Wait for the the indication that the read is done */
 280         while ((regbase->miimind & (MIIMIND_NOTVALID | MIIMIND_BUSY))) ;
 281
 282         /* Grab the value read from the PHY */
 283         value = regbase->miimstat;
 284
 285         return value;
 286 }
 287
 288 /* Discover which PHY is attached to the device, and configure it
 289  * properly.  If the PHY is not recognized, then return 0
 290  * (failure).  Otherwise, return 1
 291  */
 292 static int init_phy(struct eth_device *dev)
 293 {
 294         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 295         struct phy_info *curphy;
 296         volatile tsec_t *regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
 297
 298         /* Assign a Physical address to the TBI */
 299         regs->tbipa = TBIPA_VALUE;
 300         regs = (volatile tsec_t *)(TSEC_BASE_ADDR + TSEC_SIZE);
 301         regs->tbipa = TBIPA_VALUE;
 302         asm("sync");
 303
 304         /* Reset MII (due to new addresses) */
 305         priv->phyregs->miimcfg = MIIMCFG_RESET;
 306         asm("sync");
 307         priv->phyregs->miimcfg = MIIMCFG_INIT_VALUE;
 308         asm("sync");
 309         while (priv->phyregs->miimind & MIIMIND_BUSY) ;
 310
 311         if (0 == relocated)
 312                 relocate_cmds();
 313
 314         /* Get the cmd structure corresponding to the attached
 315          * PHY */
 316         curphy = get_phy_info(dev);
 317
 318         if (curphy == NULL) {
 319                 priv->phyinfo = NULL;
 320                 printf("%s: No PHY found\n", dev->name);
 321
 322                 return 0;
 323         }
 324
 325         priv->phyinfo = curphy;
 326
 327         phy_run_commands(priv, priv->phyinfo->config);
 328
 329         return 1;
 330 }
 331
 332 /*
 333  * Returns which value to write to the control register.
 334  * For 10/100, the value is slightly different
 335  */
 336 uint mii_cr_init(uint mii_reg, struct tsec_private * priv)
 337 {
 338         if (priv->flags & TSEC_GIGABIT)
 339                 return MIIM_CONTROL_INIT;
 340         else
 341                 return MIIM_CR_INIT;
 342 }
 343
 344 /* Parse the status register for link, and then do
 345  * auto-negotiation
 346  */
 347 uint mii_parse_sr(uint mii_reg, struct tsec_private * priv)
 348 {
 349         /*
 350          * Wait if PHY is capable of autonegotiation and autonegotiation
 351          * is not complete.
 352          */
 353         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 354         if ((mii_reg & PHY_BMSR_AUTN_ABLE)
 355             && !(mii_reg & PHY_BMSR_AUTN_COMP)) {
 356                 int i = 0;
 357
 358                 puts("Waiting for PHY auto negotiation to complete");
 359                 while (!((mii_reg & PHY_BMSR_AUTN_COMP)
 360                          && (mii_reg & MIIM_STATUS_LINK))) {
 361                         /*
 362                          * Timeout reached ?
 363                          */
 364                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 365                                 puts(" TIMEOUT !\n");
 366                                 priv->link = 0;
 367                                 return 0;
 368                         }
 369
 370                         if ((i++ % 1000) == 0) {
 371                                 putc('.');
 372                         }
 373                         udelay(1000);   /* 1 ms */
 374                         mii_reg = read_phy_reg(priv, MIIM_STATUS);
 375                 }
 376                 puts(" done\n");
 377                 priv->link = 1;
 378                 udelay(500000); /* another 500 ms (results in faster booting) */
 379         } else {
 380                 priv->link = 1;
 381         }
 382
 383         return 0;
 384 }
 385
 386 /* Generic function which updates the speed and duplex.  If
 387  * autonegotiation is enabled, it uses the AND of the link
 388  * partner's advertised capabilities and our advertised
 389  * capabilities.  If autonegotiation is disabled, we use the
 390  * appropriate bits in the control register.
 391  *
 392  * Stolen from Linux's mii.c and phy_device.c
 393  */
 394 uint mii_parse_link(uint mii_reg, struct tsec_private *priv)
 395 {
 396         /* We're using autonegotiation */
 397         if (mii_reg & PHY_BMSR_AUTN_ABLE) {
 398                 uint lpa = 0;
 399                 uint gblpa = 0;
 400
 401                 /* Check for gigabit capability */
 402                 if (mii_reg & PHY_BMSR_EXT) {
 403                         /* We want a list of states supported by
 404                          * both PHYs in the link
 405                          */
 406                         gblpa = read_phy_reg(priv, PHY_1000BTSR);
 407                         gblpa &= read_phy_reg(priv, PHY_1000BTCR) << 2;
 408                 }
 409
 410                 /* Set the baseline so we only have to set them
 411                  * if they're different
 412                  */
 413                 priv->speed = 10;
 414                 priv->duplexity = 0;
 415
 416                 /* Check the gigabit fields */
 417                 if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
 418                         priv->speed = 1000;
 419
 420                         if (gblpa & PHY_1000BTSR_1000FD)
 421                                 priv->duplexity = 1;
 422
 423                         /* We're done! */
 424                         return 0;
 425                 }
 426
 427                 lpa = read_phy_reg(priv, PHY_ANAR);
 428                 lpa &= read_phy_reg(priv, PHY_ANLPAR);
 429
 430                 if (lpa & (PHY_ANLPAR_TXFD | PHY_ANLPAR_TX)) {
 431                         priv->speed = 100;
 432
 433                         if (lpa & PHY_ANLPAR_TXFD)
 434                                 priv->duplexity = 1;
 435
 436                 } else if (lpa & PHY_ANLPAR_10FD)
 437                         priv->duplexity = 1;
 438         } else {
 439                 uint bmcr = read_phy_reg(priv, PHY_BMCR);
 440
 441                 priv->speed = 10;
 442                 priv->duplexity = 0;
 443
 444                 if (bmcr & PHY_BMCR_DPLX)
 445                         priv->duplexity = 1;
 446
 447                 if (bmcr & PHY_BMCR_1000_MBPS)
 448                         priv->speed = 1000;
 449                 else if (bmcr & PHY_BMCR_100_MBPS)
 450                         priv->speed = 100;
 451         }
 452
 453         return 0;
 454 }
 455
 456 /*
 457  * Parse the BCM54xx status register for speed and duplex information.
 458  * The linux sungem_phy has this information, but in a table format.
 459  */
 460 uint mii_parse_BCM54xx_sr(uint mii_reg, struct tsec_private *priv)
 461 {
 462
 463         switch((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >> MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT){
 464
 465                 case 1:
 466                         printf("Enet starting in 10BT/HD\n");
 467                         priv->duplexity = 0;
 468                         priv->speed = 10;
 469                         break;
 470
 471                 case 2:
 472                         printf("Enet starting in 10BT/FD\n");
 473                         priv->duplexity = 1;
 474                         priv->speed = 10;
 475                         break;
 476
 477                 case 3:
 478                         printf("Enet starting in 100BT/HD\n");
 479                         priv->duplexity = 0;
 480                         priv->speed = 100;
 481                         break;
 482
 483                 case 5:
 484                         printf("Enet starting in 100BT/FD\n");
 485                         priv->duplexity = 1;
 486                         priv->speed = 100;
 487                         break;
 488
 489                 case 6:
 490                         printf("Enet starting in 1000BT/HD\n");
 491                         priv->duplexity = 0;
 492                         priv->speed = 1000;
 493                         break;
 494
 495                 case 7:
 496                         printf("Enet starting in 1000BT/FD\n");
 497                         priv->duplexity = 1;
 498                         priv->speed = 1000;
 499                         break;
 500
 501                 default:
 502                         printf("Auto-neg error, defaulting to 10BT/HD\n");
 503                         priv->duplexity = 0;
 504                         priv->speed = 10;
 505                         break;
 506         }
 507
 508         return 0;
 509
 510 }
 511 /* Parse the 88E1011's status register for speed and duplex
 512  * information
 513  */
 514 uint mii_parse_88E1011_psr(uint mii_reg, struct tsec_private * priv)
 515 {
 516         uint speed;
 517
 518         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 519
 520         if (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
 521               (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
 522                 int i = 0;
 523
 524                 puts("Waiting for PHY realtime link");
 525                 while (!((mii_reg & MIIM_88E1011_PHYSTAT_SPDDONE) &&
 526                          (mii_reg & MIIM_88E1011_PHYSTAT_LINK))) {
 527                         /*
 528                          * Timeout reached ?
 529                          */
 530                         if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
 531                                 puts(" TIMEOUT !\n");
 532                                 priv->link = 0;
 533                                 break;
 534                         }
 535
 536                         if ((i++ % 1000) == 0) {
 537                                 putc('.');
 538                         }
 539                         udelay(1000);   /* 1 ms */
 540                         mii_reg = read_phy_reg(priv, MIIM_88E1011_PHY_STATUS);
 541                 }
 542                 puts(" done\n");
 543                 udelay(500000); /* another 500 ms (results in faster booting) */
 544         }
 545
 546         if (mii_reg & MIIM_88E1011_PHYSTAT_DUPLEX)
 547                 priv->duplexity = 1;
 548         else
 549                 priv->duplexity = 0;
 550
 551         speed = (mii_reg & MIIM_88E1011_PHYSTAT_SPEED);
 552
 553         switch (speed) {
 554         case MIIM_88E1011_PHYSTAT_GBIT:
 555                 priv->speed = 1000;
 556                 break;
 557         case MIIM_88E1011_PHYSTAT_100:
 558                 priv->speed = 100;
 559                 break;
 560         default:
 561                 priv->speed = 10;
 562         }
 563
 564         return 0;
 565 }
 566
 567 /* Parse the cis8201's status register for speed and duplex
 568  * information
 569  */
 570 uint mii_parse_cis8201(uint mii_reg, struct tsec_private * priv)
 571 {
 572         uint speed;
 573
 574         if (mii_reg & MIIM_CIS8201_AUXCONSTAT_DUPLEX)
 575                 priv->duplexity = 1;
 576         else
 577                 priv->duplexity = 0;
 578
 579         speed = mii_reg & MIIM_CIS8201_AUXCONSTAT_SPEED;
 580         switch (speed) {
 581         case MIIM_CIS8201_AUXCONSTAT_GBIT:
 582                 priv->speed = 1000;
 583                 break;
 584         case MIIM_CIS8201_AUXCONSTAT_100:
 585                 priv->speed = 100;
 586                 break;
 587         default:
 588                 priv->speed = 10;
 589                 break;
 590         }
 591
 592         return 0;
 593 }
 594
 595 /* Parse the vsc8244's status register for speed and duplex
 596  * information
 597  */
 598 uint mii_parse_vsc8244(uint mii_reg, struct tsec_private * priv)
 599 {
 600         uint speed;
 601
 602         if (mii_reg & MIIM_VSC8244_AUXCONSTAT_DUPLEX)
 603                 priv->duplexity = 1;
 604         else
 605                 priv->duplexity = 0;
 606
 607         speed = mii_reg & MIIM_VSC8244_AUXCONSTAT_SPEED;
 608         switch (speed) {
 609         case MIIM_VSC8244_AUXCONSTAT_GBIT:
 610                 priv->speed = 1000;
 611                 break;
 612         case MIIM_VSC8244_AUXCONSTAT_100:
 613                 priv->speed = 100;
 614                 break;
 615         default:
 616                 priv->speed = 10;
 617                 break;
 618         }
 619
 620         return 0;
 621 }
 622
 623 /* Parse the DM9161's status register for speed and duplex
 624  * information
 625  */
 626 uint mii_parse_dm9161_scsr(uint mii_reg, struct tsec_private * priv)
 627 {
 628         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_100H))
 629                 priv->speed = 100;
 630         else
 631                 priv->speed = 10;
 632
 633         if (mii_reg & (MIIM_DM9161_SCSR_100F | MIIM_DM9161_SCSR_10F))
 634                 priv->duplexity = 1;
 635         else
 636                 priv->duplexity = 0;
 637
 638         return 0;
 639 }
 640
 641 /*
 642  * Hack to write all 4 PHYs with the LED values
 643  */
 644 uint mii_cis8204_fixled(uint mii_reg, struct tsec_private * priv)
 645 {
 646         uint phyid;
 647         volatile tsec_t *regbase = priv->phyregs;
 648         int timeout = 1000000;
 649
 650         for (phyid = 0; phyid < 4; phyid++) {
 651                 regbase->miimadd = (phyid << 8) | mii_reg;
 652                 regbase->miimcon = MIIM_CIS8204_SLEDCON_INIT;
 653                 asm("sync");
 654
 655                 timeout = 1000000;
 656                 while ((regbase->miimind & MIIMIND_BUSY) && timeout--) ;
 657         }
 658
 659         return MIIM_CIS8204_SLEDCON_INIT;
 660 }
 661
 662 uint mii_cis8204_setmode(uint mii_reg, struct tsec_private * priv)
 663 {
 664         if (priv->flags & TSEC_REDUCED)
 665                 return MIIM_CIS8204_EPHYCON_INIT | MIIM_CIS8204_EPHYCON_RGMII;
 666         else
 667                 return MIIM_CIS8204_EPHYCON_INIT;
 668 }
 669
 670 /* Initialized required registers to appropriate values, zeroing
 671  * those we don't care about (unless zero is bad, in which case,
 672  * choose a more appropriate value)
 673  */
 674 static void init_registers(volatile tsec_t * regs)
 675 {
 676         /* Clear IEVENT */
 677         regs->ievent = IEVENT_INIT_CLEAR;
 678
 679         regs->imask = IMASK_INIT_CLEAR;
 680
 681         regs->hash.iaddr0 = 0;
 682         regs->hash.iaddr1 = 0;
 683         regs->hash.iaddr2 = 0;
 684         regs->hash.iaddr3 = 0;
 685         regs->hash.iaddr4 = 0;
 686         regs->hash.iaddr5 = 0;
 687         regs->hash.iaddr6 = 0;
 688         regs->hash.iaddr7 = 0;
 689
 690         regs->hash.gaddr0 = 0;
 691         regs->hash.gaddr1 = 0;
 692         regs->hash.gaddr2 = 0;
 693         regs->hash.gaddr3 = 0;
 694         regs->hash.gaddr4 = 0;
 695         regs->hash.gaddr5 = 0;
 696         regs->hash.gaddr6 = 0;
 697         regs->hash.gaddr7 = 0;
 698
 699         regs->rctrl = 0x00000000;
 700
 701         /* Init RMON mib registers */
 702         memset((void *)&(regs->rmon), 0, sizeof(rmon_mib_t));
 703
 704         regs->rmon.cam1 = 0xffffffff;
 705         regs->rmon.cam2 = 0xffffffff;
 706
 707         regs->mrblr = MRBLR_INIT_SETTINGS;
 708
 709         regs->minflr = MINFLR_INIT_SETTINGS;
 710
 711         regs->attr = ATTR_INIT_SETTINGS;
 712         regs->attreli = ATTRELI_INIT_SETTINGS;
 713
 714 }
 715
 716 /* Configure maccfg2 based on negotiated speed and duplex
 717  * reported by PHY handling code
 718  */
 719 static void adjust_link(struct eth_device *dev)
 720 {
 721         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 722         volatile tsec_t *regs = priv->regs;
 723
 724         if (priv->link) {
 725                 if (priv->duplexity != 0)
 726                         regs->maccfg2 |= MACCFG2_FULL_DUPLEX;
 727                 else
 728                         regs->maccfg2 &= ~(MACCFG2_FULL_DUPLEX);
 729
 730                 switch (priv->speed) {
 731                 case 1000:
 732                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 733                                          | MACCFG2_GMII);
 734                         break;
 735                 case 100:
 736                 case 10:
 737                         regs->maccfg2 = ((regs->maccfg2 & ~(MACCFG2_IF))
 738                                          | MACCFG2_MII);
 739
 740                         /* Set R100 bit in all modes although
 741                          * it is only used in RGMII mode
 742                          */
 743                         if (priv->speed == 100)
 744                                 regs->ecntrl |= ECNTRL_R100;
 745                         else
 746                                 regs->ecntrl &= ~(ECNTRL_R100);
 747                         break;
 748                 default:
 749                         printf("%s: Speed was bad\n", dev->name);
 750                         break;
 751                 }
 752
 753                 printf("Speed: %d, %s duplex\n", priv->speed,
 754                        (priv->duplexity) ? "full" : "half");
 755
 756         } else {
 757                 printf("%s: No link.\n", dev->name);
 758         }
 759 }
 760
 761 /* Set up the buffers and their descriptors, and bring up the
 762  * interface
 763  */
 764 static void startup_tsec(struct eth_device *dev)
 765 {
 766         int i;
 767         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 768         volatile tsec_t *regs = priv->regs;
 769
 770         /* Point to the buffer descriptors */
 771         regs->tbase = (unsigned int)(&rtx.txbd[txIdx]);
 772         regs->rbase = (unsigned int)(&rtx.rxbd[rxIdx]);
 773
 774         /* Initialize the Rx Buffer descriptors */
 775         for (i = 0; i < PKTBUFSRX; i++) {
 776                 rtx.rxbd[i].status = RXBD_EMPTY;
 777                 rtx.rxbd[i].length = 0;
 778                 rtx.rxbd[i].bufPtr = (uint) NetRxPackets[i];
 779         }
 780         rtx.rxbd[PKTBUFSRX - 1].status |= RXBD_WRAP;
 781
 782         /* Initialize the TX Buffer Descriptors */
 783         for (i = 0; i < TX_BUF_CNT; i++) {
 784                 rtx.txbd[i].status = 0;
 785                 rtx.txbd[i].length = 0;
 786                 rtx.txbd[i].bufPtr = 0;
 787         }
 788         rtx.txbd[TX_BUF_CNT - 1].status |= TXBD_WRAP;
 789
 790         /* Start up the PHY */
 791         if(priv->phyinfo)
 792                 phy_run_commands(priv, priv->phyinfo->startup);
 793
 794         adjust_link(dev);
 795
 796         /* Enable Transmit and Receive */
 797         regs->maccfg1 |= (MACCFG1_RX_EN | MACCFG1_TX_EN);
 798
 799         /* Tell the DMA it is clear to go */
 800         regs->dmactrl |= DMACTRL_INIT_SETTINGS;
 801         regs->tstat = TSTAT_CLEAR_THALT;
 802         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 803 }
 804
 805 /* This returns the status bits of the device.  The return value
 806  * is never checked, and this is what the 8260 driver did, so we
 807  * do the same.  Presumably, this would be zero if there were no
 808  * errors
 809  */
 810 static int tsec_send(struct eth_device *dev, volatile void *packet, int length)
 811 {
 812         int i;
 813         int result = 0;
 814         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 815         volatile tsec_t *regs = priv->regs;
 816
 817         /* Find an empty buffer descriptor */
 818         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 819                 if (i >= TOUT_LOOP) {
 820                         debug("%s: tsec: tx buffers full\n", dev->name);
 821                         return result;
 822                 }
 823         }
 824
 825         rtx.txbd[txIdx].bufPtr = (uint) packet;
 826         rtx.txbd[txIdx].length = length;
 827         rtx.txbd[txIdx].status |=
 828             (TXBD_READY | TXBD_LAST | TXBD_CRC | TXBD_INTERRUPT);
 829
 830         /* Tell the DMA to go */
 831         regs->tstat = TSTAT_CLEAR_THALT;
 832
 833         /* Wait for buffer to be transmitted */
 834         for (i = 0; rtx.txbd[txIdx].status & TXBD_READY; i++) {
 835                 if (i >= TOUT_LOOP) {
 836                         debug("%s: tsec: tx error\n", dev->name);
 837                         return result;
 838                 }
 839         }
 840
 841         txIdx = (txIdx + 1) % TX_BUF_CNT;
 842         result = rtx.txbd[txIdx].status & TXBD_STATS;
 843
 844         return result;
 845 }
 846
 847 static int tsec_recv(struct eth_device *dev)
 848 {
 849         int length;
 850         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 851         volatile tsec_t *regs = priv->regs;
 852
 853         while (!(rtx.rxbd[rxIdx].status & RXBD_EMPTY)) {
 854
 855                 length = rtx.rxbd[rxIdx].length;
 856
 857                 /* Send the packet up if there were no errors */
 858                 if (!(rtx.rxbd[rxIdx].status & RXBD_STATS)) {
 859                         NetReceive(NetRxPackets[rxIdx], length - 4);
 860                 } else {
 861                         printf("Got error %x\n",
 862                                (rtx.rxbd[rxIdx].status & RXBD_STATS));
 863                 }
 864
 865                 rtx.rxbd[rxIdx].length = 0;
 866
 867                 /* Set the wrap bit if this is the last element in the list */
 868                 rtx.rxbd[rxIdx].status =
 869                     RXBD_EMPTY | (((rxIdx + 1) == PKTBUFSRX) ? RXBD_WRAP : 0);
 870
 871                 rxIdx = (rxIdx + 1) % PKTBUFSRX;
 872         }
 873
 874         if (regs->ievent & IEVENT_BSY) {
 875                 regs->ievent = IEVENT_BSY;
 876                 regs->rstat = RSTAT_CLEAR_RHALT;
 877         }
 878
 879         return -1;
 880
 881 }
 882
 883 /* Stop the interface */
 884 static void tsec_halt(struct eth_device *dev)
 885 {
 886         struct tsec_private *priv = (struct tsec_private *)dev->priv;
 887         volatile tsec_t *regs = priv->regs;
 888
 889         regs->dmactrl &= ~(DMACTRL_GRS | DMACTRL_GTS);
 890         regs->dmactrl |= (DMACTRL_GRS | DMACTRL_GTS);
 891
 892         while (!(regs->ievent & (IEVENT_GRSC | IEVENT_GTSC))) ;
 893
 894         regs->maccfg1 &= ~(MACCFG1_TX_EN | MACCFG1_RX_EN);
 895
 896         /* Shut down the PHY, as needed */
 897         if(priv->phyinfo)
 898                 phy_run_commands(priv, priv->phyinfo->shutdown);
 899 }
 900
 901 struct phy_info phy_info_M88E1149S = {
 902         0x1410ca,
 903         "Marvell 88E1149S",
 904         4,
 905         (struct phy_cmd[]){     /* config */
 906                 /* Reset and configure the PHY */
 907                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 908                 {0x1d, 0x1f, NULL},
 909                 {0x1e, 0x200c, NULL},
 910                 {0x1d, 0x5, NULL},
 911                 {0x1e, 0x0, NULL},
 912                 {0x1e, 0x100, NULL},
 913                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 914                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 915                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 916                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 917                 {miim_end,}
 918         },
 919         (struct phy_cmd[]){     /* startup */
 920                 /* Status is read once to clear old link state */
 921                 {MIIM_STATUS, miim_read, NULL},
 922                 /* Auto-negotiate */
 923                 {MIIM_STATUS, miim_read, &mii_parse_sr},
 924                 /* Read the status */
 925                 {MIIM_88E1011_PHY_STATUS, miim_read,
 926                  &mii_parse_88E1011_psr},
 927                 {miim_end,}
 928         },
 929         (struct phy_cmd[]){     /* shutdown */
 930                 {miim_end,}
 931         },
 932 };
 933
 934 /* The 5411 id is 0x206070, the 5421 is 0x2060e0 */
 935 struct phy_info phy_info_BCM5461S = {
 936         0x02060c1,      /* 5461 ID */
 937         "Broadcom BCM5461S",
 938         0, /* not clear to me what minor revisions we can shift away */
 939         (struct phy_cmd[]) { /* config */
 940                 /* Reset and configure the PHY */
 941                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 942                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 943                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 944                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 945                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 946                 {miim_end,}
 947         },
 948         (struct phy_cmd[]) { /* startup */
 949                 /* Status is read once to clear old link state */
 950                 {MIIM_STATUS, miim_read, NULL},
 951                 /* Auto-negotiate */
 952                 {MIIM_STATUS, miim_read, &mii_parse_sr},
 953                 /* Read the status */
 954                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
 955                 {miim_end,}
 956         },
 957         (struct phy_cmd[]) { /* shutdown */
 958                 {miim_end,}
 959         },
 960 };
 961
 962 struct phy_info phy_info_BCM5464S = {
 963         0x02060b1,      /* 5464 ID */
 964         "Broadcom BCM5464S",
 965         0, /* not clear to me what minor revisions we can shift away */
 966         (struct phy_cmd[]) { /* config */
 967                 /* Reset and configure the PHY */
 968                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 969                 {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
 970                 {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
 971                 {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 972                 {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
 973                 {miim_end,}
 974         },
 975         (struct phy_cmd[]) { /* startup */
 976                 /* Status is read once to clear old link state */
 977                 {MIIM_STATUS, miim_read, NULL},
 978                 /* Auto-negotiate */
 979                 {MIIM_STATUS, miim_read, &mii_parse_sr},
 980                 /* Read the status */
 981                 {MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
 982                 {miim_end,}
 983         },
 984         (struct phy_cmd[]) { /* shutdown */
 985                 {miim_end,}
 986         },
 987 };
 988
 989 struct phy_info phy_info_M88E1011S = {
 990         0x01410c6,
 991         "Marvell 88E1011S",
 992         4,
 993         (struct phy_cmd[]){     /* config */
 994                            /* Reset and configure the PHY */
 995                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
 996                            {0x1d, 0x1f, NULL},
 997                            {0x1e, 0x200c, NULL},
 998                            {0x1d, 0x5, NULL},
 999                            {0x1e, 0x0, NULL},
1000                            {0x1e, 0x100, NULL},
1001                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1002                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1003                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1004                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1005                            {miim_end,}
1006                            },
1007         (struct phy_cmd[]){     /* startup */
1008                            /* Status is read once to clear old link state */
1009                            {MIIM_STATUS, miim_read, NULL},
1010                            /* Auto-negotiate */
1011                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1012                            /* Read the status */
1013                            {MIIM_88E1011_PHY_STATUS, miim_read,
1014                             &mii_parse_88E1011_psr},
1015                            {miim_end,}
1016                            },
1017         (struct phy_cmd[]){     /* shutdown */
1018                            {miim_end,}
1019                            },
1020 };
1021
1022 struct phy_info phy_info_M88E1111S = {
1023         0x01410cc,
1024         "Marvell 88E1111S",
1025         4,
1026         (struct phy_cmd[]){     /* config */
1027                            /* Reset and configure the PHY */
1028                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1029                            {0x14, 0x0cd2, NULL}, /* Delay RGMII TX and RX */
1030                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1031                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1032                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1033                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1034                            {miim_end,}
1035                            },
1036         (struct phy_cmd[]){     /* startup */
1037                            /* Status is read once to clear old link state */
1038                            {MIIM_STATUS, miim_read, NULL},
1039                            /* Auto-negotiate */
1040                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1041                            /* Read the status */
1042                            {MIIM_88E1011_PHY_STATUS, miim_read,
1043                             &mii_parse_88E1011_psr},
1044                            {miim_end,}
1045                            },
1046         (struct phy_cmd[]){     /* shutdown */
1047                            {miim_end,}
1048                            },
1049 };
1050
1051 static unsigned int m88e1145_setmode(uint mii_reg, struct tsec_private *priv)
1052 {
1053         uint mii_data = read_phy_reg(priv, mii_reg);
1054
1055         /* Setting MIIM_88E1145_PHY_EXT_CR */
1056         if (priv->flags & TSEC_REDUCED)
1057                 return mii_data |
1058                     MIIM_M88E1145_RGMII_RX_DELAY | MIIM_M88E1145_RGMII_TX_DELAY;
1059         else
1060                 return mii_data;
1061 }
1062
1063 static struct phy_info phy_info_M88E1145 = {
1064         0x01410cd,
1065         "Marvell 88E1145",
1066         4,
1067         (struct phy_cmd[]){     /* config */
1068                            /* Reset the PHY */
1069                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1070
1071                            /* Errata E0, E1 */
1072                            {29, 0x001b, NULL},
1073                            {30, 0x418f, NULL},
1074                            {29, 0x0016, NULL},
1075                            {30, 0xa2da, NULL},
1076
1077                            /* Configure the PHY */
1078                            {MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
1079                            {MIIM_ANAR, MIIM_ANAR_INIT, NULL},
1080                            {MIIM_88E1011_PHY_SCR, MIIM_88E1011_PHY_MDI_X_AUTO,
1081                             NULL},
1082                            {MIIM_88E1145_PHY_EXT_CR, 0, &m88e1145_setmode},
1083                            {MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
1084                            {MIIM_CONTROL, MIIM_CONTROL_INIT, NULL},
1085                            {miim_end,}
1086                            },
1087         (struct phy_cmd[]){     /* startup */
1088                            /* Status is read once to clear old link state */
1089                            {MIIM_STATUS, miim_read, NULL},
1090                            /* Auto-negotiate */
1091                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1092                            {MIIM_88E1111_PHY_LED_CONTROL,
1093                             MIIM_88E1111_PHY_LED_DIRECT, NULL},
1094                            /* Read the Status */
1095                            {MIIM_88E1011_PHY_STATUS, miim_read,
1096                             &mii_parse_88E1011_psr},
1097                            {miim_end,}
1098                            },
1099         (struct phy_cmd[]){     /* shutdown */
1100                            {miim_end,}
1101                            },
1102 };
1103
1104 struct phy_info phy_info_cis8204 = {
1105         0x3f11,
1106         "Cicada Cis8204",
1107         6,
1108         (struct phy_cmd[]){     /* config */
1109                            /* Override PHY config settings */
1110                            {MIIM_CIS8201_AUX_CONSTAT,
1111                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1112                            /* Configure some basic stuff */
1113                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1114                            {MIIM_CIS8204_SLED_CON, MIIM_CIS8204_SLEDCON_INIT,
1115                             &mii_cis8204_fixled},
1116                            {MIIM_CIS8204_EPHY_CON, MIIM_CIS8204_EPHYCON_INIT,
1117                             &mii_cis8204_setmode},
1118                            {miim_end,}
1119                            },
1120         (struct phy_cmd[]){     /* startup */
1121                            /* Read the Status (2x to make sure link is right) */
1122                            {MIIM_STATUS, miim_read, NULL},
1123                            /* Auto-negotiate */
1124                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1125                            /* Read the status */
1126                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1127                             &mii_parse_cis8201},
1128                            {miim_end,}
1129                            },
1130         (struct phy_cmd[]){     /* shutdown */
1131                            {miim_end,}
1132                            },
1133 };
1134
1135 /* Cicada 8201 */
1136 struct phy_info phy_info_cis8201 = {
1137         0xfc41,
1138         "CIS8201",
1139         4,
1140         (struct phy_cmd[]){     /* config */
1141                            /* Override PHY config settings */
1142                            {MIIM_CIS8201_AUX_CONSTAT,
1143                             MIIM_CIS8201_AUXCONSTAT_INIT, NULL},
1144                            /* Set up the interface mode */
1145                            {MIIM_CIS8201_EXT_CON1, MIIM_CIS8201_EXTCON1_INIT,
1146                             NULL},
1147                            /* Configure some basic stuff */
1148                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1149                            {miim_end,}
1150                            },
1151         (struct phy_cmd[]){     /* startup */
1152                            /* Read the Status (2x to make sure link is right) */
1153                            {MIIM_STATUS, miim_read, NULL},
1154                            /* Auto-negotiate */
1155                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1156                            /* Read the status */
1157                            {MIIM_CIS8201_AUX_CONSTAT, miim_read,
1158                             &mii_parse_cis8201},
1159                            {miim_end,}
1160                            },
1161         (struct phy_cmd[]){     /* shutdown */
1162                            {miim_end,}
1163                            },
1164 };
1165 struct phy_info phy_info_VSC8244 = {
1166         0x3f1b,
1167         "Vitesse VSC8244",
1168         6,
1169         (struct phy_cmd[]){     /* config */
1170                            /* Override PHY config settings */
1171                            /* Configure some basic stuff */
1172                            {MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
1173                            {miim_end,}
1174                            },
1175         (struct phy_cmd[]){     /* startup */
1176                            /* Read the Status (2x to make sure link is right) */
1177                            {MIIM_STATUS, miim_read, NULL},
1178                            /* Auto-negotiate */
1179                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1180                            /* Read the status */
1181                            {MIIM_VSC8244_AUX_CONSTAT, miim_read,
1182                             &mii_parse_vsc8244},
1183                            {miim_end,}
1184                            },
1185         (struct phy_cmd[]){     /* shutdown */
1186                            {miim_end,}
1187                            },
1188 };
1189
1190 struct phy_info phy_info_dm9161 = {
1191         0x0181b88,
1192         "Davicom DM9161E",
1193         4,
1194         (struct phy_cmd[]){     /* config */
1195                            {MIIM_CONTROL, MIIM_DM9161_CR_STOP, NULL},
1196                            /* Do not bypass the scrambler/descrambler */
1197                            {MIIM_DM9161_SCR, MIIM_DM9161_SCR_INIT, NULL},
1198                            /* Clear 10BTCSR to default */
1199                            {MIIM_DM9161_10BTCSR, MIIM_DM9161_10BTCSR_INIT,
1200                             NULL},
1201                            /* Configure some basic stuff */
1202                            {MIIM_CONTROL, MIIM_CR_INIT, NULL},
1203                            /* Restart Auto Negotiation */
1204                            {MIIM_CONTROL, MIIM_DM9161_CR_RSTAN, NULL},
1205                            {miim_end,}
1206                            },
1207         (struct phy_cmd[]){     /* startup */
1208                            /* Status is read once to clear old link state */
1209                            {MIIM_STATUS, miim_read, NULL},
1210                            /* Auto-negotiate */
1211                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1212                            /* Read the status */
1213                            {MIIM_DM9161_SCSR, miim_read,
1214                             &mii_parse_dm9161_scsr},
1215                            {miim_end,}
1216                            },
1217         (struct phy_cmd[]){     /* shutdown */
1218                            {miim_end,}
1219                            },
1220 };
1221 /* a generic flavor.  */
1222 struct phy_info phy_info_generic =  {
1223         0,
1224         "Unknown/Generic PHY",
1225         32,
1226         (struct phy_cmd[]) { /* config */
1227                 {PHY_BMCR, PHY_BMCR_RESET, NULL},
1228                 {PHY_BMCR, PHY_BMCR_AUTON|PHY_BMCR_RST_NEG, NULL},
1229                 {miim_end,}
1230         },
1231         (struct phy_cmd[]) { /* startup */
1232                 {PHY_BMSR, miim_read, NULL},
1233                 {PHY_BMSR, miim_read, &mii_parse_sr},
1234                 {PHY_BMSR, miim_read, &mii_parse_link},
1235                 {miim_end,}
1236         },
1237         (struct phy_cmd[]) { /* shutdown */
1238                 {miim_end,}
1239         }
1240 };
1241
1242
1243 uint mii_parse_lxt971_sr2(uint mii_reg, struct tsec_private *priv)
1244 {
1245         unsigned int speed;
1246         if (priv->link) {
1247                 speed = mii_reg & MIIM_LXT971_SR2_SPEED_MASK;
1248
1249                 switch (speed) {
1250                 case MIIM_LXT971_SR2_10HDX:
1251                         priv->speed = 10;
1252                         priv->duplexity = 0;
1253                         break;
1254                 case MIIM_LXT971_SR2_10FDX:
1255                         priv->speed = 10;
1256                         priv->duplexity = 1;
1257                         break;
1258                 case MIIM_LXT971_SR2_100HDX:
1259                         priv->speed = 100;
1260                         priv->duplexity = 0;
1261                 default:
1262                         priv->speed = 100;
1263                         priv->duplexity = 1;
1264                         break;
1265                 }
1266         } else {
1267                 priv->speed = 0;
1268                 priv->duplexity = 0;
1269         }
1270
1271         return 0;
1272 }
1273
1274 static struct phy_info phy_info_lxt971 = {
1275         0x0001378e,
1276         "LXT971",
1277         4,
1278         (struct phy_cmd[]){     /* config */
1279                            {MIIM_CR, MIIM_CR_INIT, mii_cr_init},        /* autonegotiate */
1280                            {miim_end,}
1281                            },
1282         (struct phy_cmd[]){     /* startup - enable interrupts */
1283                            /* { 0x12, 0x00f2, NULL }, */
1284                            {MIIM_STATUS, miim_read, NULL},
1285                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1286                            {MIIM_LXT971_SR2, miim_read, &mii_parse_lxt971_sr2},
1287                            {miim_end,}
1288                            },
1289         (struct phy_cmd[]){     /* shutdown - disable interrupts */
1290                            {miim_end,}
1291                            },
1292 };
1293
1294 /* Parse the DP83865's link and auto-neg status register for speed and duplex
1295  * information
1296  */
1297 uint mii_parse_dp83865_lanr(uint mii_reg, struct tsec_private *priv)
1298 {
1299         switch (mii_reg & MIIM_DP83865_SPD_MASK) {
1300
1301         case MIIM_DP83865_SPD_1000:
1302                 priv->speed = 1000;
1303                 break;
1304
1305         case MIIM_DP83865_SPD_100:
1306                 priv->speed = 100;
1307                 break;
1308
1309         default:
1310                 priv->speed = 10;
1311                 break;
1312
1313         }
1314
1315         if (mii_reg & MIIM_DP83865_DPX_FULL)
1316                 priv->duplexity = 1;
1317         else
1318                 priv->duplexity = 0;
1319
1320         return 0;
1321 }
1322
1323 struct phy_info phy_info_dp83865 = {
1324         0x20005c7,
1325         "NatSemi DP83865",
1326         4,
1327         (struct phy_cmd[]){     /* config */
1328                            {MIIM_CONTROL, MIIM_DP83865_CR_INIT, NULL},
1329                            {miim_end,}
1330                            },
1331         (struct phy_cmd[]){     /* startup */
1332                            /* Status is read once to clear old link state */
1333                            {MIIM_STATUS, miim_read, NULL},
1334                            /* Auto-negotiate */
1335                            {MIIM_STATUS, miim_read, &mii_parse_sr},
1336                            /* Read the link and auto-neg status */
1337                            {MIIM_DP83865_LANR, miim_read,
1338                             &mii_parse_dp83865_lanr},
1339                            {miim_end,}
1340                            },
1341         (struct phy_cmd[]){     /* shutdown */
1342                            {miim_end,}
1343                            },
1344 };
1345
1346 struct phy_info *phy_info[] = {
1347         &phy_info_cis8204,
1348         &phy_info_cis8201,
1349         &phy_info_BCM5461S,
1350         &phy_info_BCM5464S,
1351         &phy_info_M88E1011S,
1352         &phy_info_M88E1111S,
1353         &phy_info_M88E1145,
1354         &phy_info_M88E1149S,
1355         &phy_info_dm9161,
1356         &phy_info_lxt971,
1357         &phy_info_VSC8244,
1358         &phy_info_dp83865,
1359         &phy_info_generic,
1360         NULL
1361 };
1362
1363 /* Grab the identifier of the device's PHY, and search through
1364  * all of the known PHYs to see if one matches.  If so, return
1365  * it, if not, return NULL
1366  */
1367 struct phy_info *get_phy_info(struct eth_device *dev)
1368 {
1369         struct tsec_private *priv = (struct tsec_private *)dev->priv;
1370         uint phy_reg, phy_ID;
1371         int i;
1372         struct phy_info *theInfo = NULL;
1373
1374         /* Grab the bits from PHYIR1, and put them in the upper half */
1375         phy_reg = read_phy_reg(priv, MIIM_PHYIR1);
1376         phy_ID = (phy_reg & 0xffff) << 16;
1377
1378         /* Grab the bits from PHYIR2, and put them in the lower half */
1379         phy_reg = read_phy_reg(priv, MIIM_PHYIR2);
1380         phy_ID |= (phy_reg & 0xffff);
1381
1382         /* loop through all the known PHY types, and find one that */
1383         /* matches the ID we read from the PHY. */
1384         for (i = 0; phy_info[i]; i++) {
1385                 if (phy_info[i]->id == (phy_ID >> phy_info[i]->shift)) {
1386                         theInfo = phy_info[i];
1387                         break;
1388                 }
1389         }
1390
1391         if (theInfo == NULL) {
1392                 printf("%s: PHY id %x is not supported!\n", dev->name, phy_ID);
1393                 return NULL;
1394         } else {
1395                 debug("%s: PHY is %s (%x)\n", dev->name, theInfo->name, phy_ID);
1396         }
1397
1398         return theInfo;
1399 }
1400
1401 /* Execute the given series of commands on the given device's
1402  * PHY, running functions as necessary
1403  */
1404 void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd)
1405 {
1406         int i;
1407         uint result;
1408         volatile tsec_t *phyregs = priv->phyregs;
1409
1410         phyregs->miimcfg = MIIMCFG_RESET;
1411
1412         phyregs->miimcfg = MIIMCFG_INIT_VALUE;
1413
1414         while (phyregs->miimind & MIIMIND_BUSY) ;
1415
1416         for (i = 0; cmd->mii_reg != miim_end; i++) {
1417                 if (cmd->mii_data == miim_read) {
1418                         result = read_phy_reg(priv, cmd->mii_reg);
1419
1420                         if (cmd->funct != NULL)
1421                                 (*(cmd->funct)) (result, priv);
1422
1423                 } else {
1424                         if (cmd->funct != NULL)
1425                                 result = (*(cmd->funct)) (cmd->mii_reg, priv);
1426                         else
1427                                 result = cmd->mii_data;
1428
1429                         write_phy_reg(priv, cmd->mii_reg, result);
1430
1431                 }
1432                 cmd++;
1433         }
1434 }
1435
1436 /* Relocate the function pointers in the phy cmd lists */
1437 static void relocate_cmds(void)
1438 {
1439         struct phy_cmd **cmdlistptr;
1440         struct phy_cmd *cmd;
1441         int i, j, k;
1442
1443         for (i = 0; phy_info[i]; i++) {
1444                 /* First thing's first: relocate the pointers to the
1445                  * PHY command structures (the structs were done) */
1446                 phy_info[i] = (struct phy_info *)((uint) phy_info[i]
1447                                                   + gd->reloc_off);
1448                 phy_info[i]->name += gd->reloc_off;
1449                 phy_info[i]->config =
1450                     (struct phy_cmd *)((uint) phy_info[i]->config
1451                                        + gd->reloc_off);
1452                 phy_info[i]->startup =
1453                     (struct phy_cmd *)((uint) phy_info[i]->startup
1454                                        + gd->reloc_off);
1455                 phy_info[i]->shutdown =
1456                     (struct phy_cmd *)((uint) phy_info[i]->shutdown
1457                                        + gd->reloc_off);
1458
1459                 cmdlistptr = &phy_info[i]->config;
1460                 j = 0;
1461                 for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) {
1462                         k = 0;
1463                         for (cmd = *cmdlistptr;
1464                              cmd->mii_reg != miim_end;
1465                              cmd++) {
1466                                 /* Only relocate non-NULL pointers */
1467                                 if (cmd->funct)
1468                                         cmd->funct += gd->reloc_off;
1469
1470                                 k++;
1471                         }
1472                         j++;
1473                 }
1474         }
1475
1476         relocated = 1;
1477 }
1478
1479 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \
1480         && !defined(BITBANGMII)
1481
1482 struct tsec_private *get_priv_for_phy(unsigned char phyaddr)
1483 {
1484         int i;
1485
1486         for (i = 0; i < MAXCONTROLLERS; i++) {
1487                 if (privlist[i]->phyaddr == phyaddr)
1488                         return privlist[i];
1489         }
1490
1491         return NULL;
1492 }
1493
1494 /*
1495  * Read a MII PHY register.
1496  *
1497  * Returns:
1498  *  0 on success
1499  */
1500 static int tsec_miiphy_read(char *devname, unsigned char addr,
1501                             unsigned char reg, unsigned short *value)
1502 {
1503         unsigned short ret;
1504         struct tsec_private *priv = get_priv_for_phy(addr);
1505
1506         if (NULL == priv) {
1507                 printf("Can't read PHY at address %d\n", addr);
1508                 return -1;
1509         }
1510
1511         ret = (unsigned short)read_phy_reg(priv, reg);
1512         *value = ret;
1513
1514         return 0;
1515 }
1516
1517 /*
1518  * Write a MII PHY register.
1519  *
1520  * Returns:
1521  *  0 on success
1522  */
1523 static int tsec_miiphy_write(char *devname, unsigned char addr,
1524                              unsigned char reg, unsigned short value)
1525 {
1526         struct tsec_private *priv = get_priv_for_phy(addr);
1527
1528         if (NULL == priv) {
1529                 printf("Can't write PHY at address %d\n", addr);
1530                 return -1;
1531         }
1532
1533         write_phy_reg(priv, reg, value);
1534
1535         return 0;
1536 }
1537
1538 #endif
1539
1540 #endif /* CONFIG_TSEC_ENET */