drivers/timer/xilinx-timer.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * (C) Copyright 2022 Advanced Micro Devices, Inc
   4  * Michal Simek <michal.simek@amd.com>
   5  *
   6  * (C) Copyright 2007 Michal Simek
   7  * Michal SIMEK <monstr@monstr.eu>
   8  */
   9
  10 #include <common.h>
  11 #include <dm.h>
  12 #include <timer.h>
  13 #include <regmap.h>
  14 #include <dm/device_compat.h>
  15
  16 #define TIMER_ENABLE_ALL    0x400 /* ENALL */
  17 #define TIMER_PWM           0x200 /* PWMA0 */
  18 #define TIMER_INTERRUPT     0x100 /* T0INT */
  19 #define TIMER_ENABLE        0x080 /* ENT0 */
  20 #define TIMER_ENABLE_INTR   0x040 /* ENIT0 */
  21 #define TIMER_RESET         0x020 /* LOAD0 */
  22 #define TIMER_RELOAD        0x010 /* ARHT0 */
  23 #define TIMER_EXT_CAPTURE   0x008 /* CAPT0 */
  24 #define TIMER_EXT_COMPARE   0x004 /* GENT0 */
  25 #define TIMER_DOWN_COUNT    0x002 /* UDT0 */
  26 #define TIMER_CAPTURE_MODE  0x001 /* MDT0 */
  27
  28 #define TIMER_CONTROL_OFFSET    0
  29 #define TIMER_LOADREG_OFFSET    4
  30 #define TIMER_COUNTER_OFFSET    8
  31
  32 struct xilinx_timer_priv {
  33         struct regmap *regs;
  34 };
  35
  36 static u64 xilinx_timer_get_count(struct udevice *dev)
  37 {
  38         struct xilinx_timer_priv *priv = dev_get_priv(dev);
  39         u32 value;
  40
  41         regmap_read(priv->regs, TIMER_COUNTER_OFFSET, &value);
  42
  43         return timer_conv_64(value);
  44 }
  45
  46 static int xilinx_timer_probe(struct udevice *dev)
  47 {
  48         struct xilinx_timer_priv *priv = dev_get_priv(dev);
  49         int ret;
  50
  51         /* uc_priv->clock_rate has already clock rate */
  52         ret = regmap_init_mem(dev_ofnode(dev), &priv->regs);
  53         if (ret) {
  54                 dev_dbg(dev, "failed to get regbase of timer\n");
  55                 return ret;
  56         }
  57
  58         regmap_write(priv->regs, TIMER_LOADREG_OFFSET, 0);
  59         regmap_write(priv->regs, TIMER_CONTROL_OFFSET, TIMER_RESET);
  60         regmap_write(priv->regs, TIMER_CONTROL_OFFSET,
  61                      TIMER_ENABLE | TIMER_RELOAD);
  62
  63         return 0;
  64 }
  65
  66 static const struct timer_ops xilinx_timer_ops = {
  67         .get_count = xilinx_timer_get_count,
  68 };
  69
  70 static const struct udevice_id xilinx_timer_ids[] = {
  71         { .compatible = "xlnx,xps-timer-1.00.a" },
  72         {}
  73 };
  74
  75 U_BOOT_DRIVER(xilinx_timer) = {
  76         .name = "xilinx_timer",
  77         .id = UCLASS_TIMER,
  78         .of_match = xilinx_timer_ids,
  79         .priv_auto = sizeof(struct xilinx_timer_priv),
  80         .probe = xilinx_timer_probe,
  81         .ops = &xilinx_timer_ops,
  82 };