1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dm/fdtaddr.h>
9 #define TIMER_CTRL 0x00
10 #define TIMER0_EN BIT(0)
11 #define TIMER0_RELOAD_EN BIT(1)
12 #define TIMER0_RELOAD 0x10
13 #define TIMER0_VAL 0x14
15 enum input_clock_type {
16 INPUT_CLOCK_NON_FIXED,
17 INPUT_CLOCK_25MHZ, /* input clock rate is fixed to 25MHz */
20 struct orion_timer_priv {
24 #define MVEBU_TIMER_FIXED_RATE_25MHZ 25000000
26 static bool early_init_done(void *base)
28 if ((readl(base + TIMER_CTRL) & TIMER0_EN) &&
29 (readl(base + TIMER0_RELOAD) == ~0))
34 /* Common functions for early (boot) and DM based timer */
35 static void orion_timer_init(void *base, enum input_clock_type type)
37 /* Only init the timer once */
38 if (early_init_done(base))
41 writel(~0, base + TIMER0_VAL);
42 writel(~0, base + TIMER0_RELOAD);
44 if (type == INPUT_CLOCK_25MHZ) {
46 * On Armada XP / 38x ..., the 25MHz clock source needs to
49 setbits_le32(base + TIMER_CTRL, BIT(11));
53 setbits_le32(base + TIMER_CTRL, TIMER0_EN | TIMER0_RELOAD_EN);
56 static uint64_t orion_timer_get_count(void *base)
58 return timer_conv_64(~readl(base + TIMER0_VAL));
61 /* Early (e.g. bootstage etc) timer functions */
62 static void notrace timer_early_init(void)
64 if (IS_ENABLED(CONFIG_ARCH_MVEBU))
65 orion_timer_init((void *)MVEBU_TIMER_BASE, INPUT_CLOCK_25MHZ);
67 orion_timer_init((void *)MVEBU_TIMER_BASE, INPUT_CLOCK_NON_FIXED);
71 * timer_early_get_rate() - Get the timer rate before driver model
73 unsigned long notrace timer_early_get_rate(void)
77 if (IS_ENABLED(CONFIG_ARCH_MVEBU))
78 return MVEBU_TIMER_FIXED_RATE_25MHZ;
84 * timer_early_get_count() - Get the timer count before driver model
87 u64 notrace timer_early_get_count(void)
91 return orion_timer_get_count((void *)MVEBU_TIMER_BASE);
94 ulong timer_get_boot_us(void)
98 ticks = timer_early_get_count();
99 return lldiv(ticks * 1000, timer_early_get_rate());
102 /* DM timer functions */
103 static uint64_t dm_orion_timer_get_count(struct udevice *dev)
105 struct orion_timer_priv *priv = dev_get_priv(dev);
107 return orion_timer_get_count(priv->base);
110 static int orion_timer_probe(struct udevice *dev)
112 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
113 enum input_clock_type type = dev_get_driver_data(dev);
114 struct orion_timer_priv *priv = dev_get_priv(dev);
116 priv->base = devfdt_remap_addr_index(dev, 0);
118 debug("unable to map registers\n");
122 if (type == INPUT_CLOCK_25MHZ)
123 uc_priv->clock_rate = MVEBU_TIMER_FIXED_RATE_25MHZ;
125 uc_priv->clock_rate = CFG_SYS_TCLK;
126 orion_timer_init(priv->base, type);
131 static const struct timer_ops orion_timer_ops = {
132 .get_count = dm_orion_timer_get_count,
135 static const struct udevice_id orion_timer_ids[] = {
136 { .compatible = "marvell,orion-timer", .data = INPUT_CLOCK_NON_FIXED },
137 { .compatible = "marvell,armada-370-timer", .data = INPUT_CLOCK_25MHZ },
138 { .compatible = "marvell,armada-xp-timer", .data = INPUT_CLOCK_25MHZ },
142 U_BOOT_DRIVER(orion_timer) = {
143 .name = "orion_timer",
145 .of_match = orion_timer_ids,
146 .probe = orion_timer_probe,
147 .ops = &orion_timer_ops,
148 .priv_auto = sizeof(struct orion_timer_priv),