1 // SPDX-License-Identifier: GPL-2.0+
4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
12 #include <status_led.h>
17 #include <asm/ptrace.h>
18 #include <linux/bitops.h>
20 DECLARE_GLOBAL_DATA_PTR;
23 * struct mpc83xx_timer_priv - Private data structure for MPC83xx timer driver
24 * @decrementer_count: Value to which the decrementer register should be re-set
25 * to when a timer interrupt occurs, thus determines the
26 * interrupt frequency (value for 1e6/HZ microseconds)
27 * @timestamp: Counter for the number of timer interrupts that have
28 * occurred (i.e. can be used to trigger events
29 * periodically in the timer interrupt)
31 struct mpc83xx_timer_priv {
32 uint decrementer_count;
37 * Bitmask for enabling the time base in the SPCR (System Priority
38 * Configuration Register)
40 static const u32 SPCR_TBEN_MASK = BIT(31 - 9);
43 * get_dec() - Get the value of the decrementer register
45 * Return: The value of the decrementer register
47 static inline unsigned long get_dec(void)
51 asm volatile ("mfdec %0" : "=r" (val) : );
57 * set_dec() - Set the value of the decrementer register
58 * @val: The value of the decrementer register to be set
60 static inline void set_dec(unsigned long val)
63 asm volatile ("mtdec %0"::"r" (val));
67 * mftbu() - Get value of TBU (upper time base) register
69 * Return: Value of the TBU register
71 static inline u32 mftbu(void)
75 asm volatile("mftbu %0" : "=r" (rval));
80 * mftb() - Get value of TBL (lower time base) register
82 * Return: Value of the TBL register
84 static inline u32 mftb(void)
88 asm volatile("mftb %0" : "=r" (rval));
93 * TODO(mario.six@gdsys.cc): This should really be done by timer_init, and the
94 * interrupt init should go into a interrupt driver.
96 int interrupt_init(void)
98 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
100 struct udevice *sysinfo;
101 struct udevice *timer;
102 struct mpc83xx_timer_priv *timer_priv;
106 ret = uclass_first_device_err(UCLASS_TIMER, &timer);
108 debug("%s: Could not find timer device (error: %d)",
113 timer_priv = dev_get_priv(timer);
115 if (sysinfo_get(&sysinfo)) {
116 debug("%s: sysinfo device could not be fetched.\n", __func__);
120 ret = uclass_get_device_by_phandle(UCLASS_SIMPLE_BUS, sysinfo,
123 debug("%s: Could not retrieve CSB device (error: %d)",
128 ret = clk_get_by_index(csb, 0, &clock);
130 debug("%s: Could not retrieve clock (error: %d)",
135 timer_priv->decrementer_count = (clk_get_rate(&clock) / 4)
137 /* Enable e300 time base */
138 setbits_be32(&immr->sysconf.spcr, SPCR_TBEN_MASK);
140 set_dec(timer_priv->decrementer_count);
142 /* Switch on interrupts */
143 set_msr(get_msr() | MSR_EE);
149 * timer_interrupt() - Handler for the timer interrupt
150 * @regs: Array of register values
152 void timer_interrupt(struct pt_regs *regs)
154 struct udevice *timer = gd->timer;
155 struct mpc83xx_timer_priv *priv;
158 * During initialization, gd->timer might not be set yet, but the timer
159 * interrupt may already be enabled. In this case, wait for the
160 * initialization to complete
165 priv = dev_get_priv(timer);
167 /* Restore Decrementer Count */
168 set_dec(priv->decrementer_count);
172 #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
173 if ((timestamp % (CONFIG_SYS_WATCHDOG_FREQ)) == 0)
175 #endif /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
177 #ifdef CONFIG_LED_STATUS
178 status_led_tick(priv->timestamp);
179 #endif /* CONFIG_LED_STATUS */
182 void wait_ticks(ulong ticks)
184 ulong end = get_ticks() + ticks;
186 while (end > get_ticks())
190 static u64 mpc83xx_timer_get_count(struct udevice *dev)
195 * To make sure that no tbl overflow occurred between reading tbl and
196 * tbu, read tbu again, and compare it with the previously read tbu
197 * value: If they're different, a tbl overflow has occurred.
202 } while (tbu != mftbu());
204 return (tbu * 0x10000ULL) + tbl;
207 static int mpc83xx_timer_probe(struct udevice *dev)
209 struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
213 ret = interrupt_init();
215 debug("%s: interrupt_init failed (err = %d)\n",
220 ret = clk_get_by_index(dev, 0, &clock);
222 debug("%s: Could not retrieve clock (err = %d)\n",
227 uc_priv->clock_rate = (clk_get_rate(&clock) + 3L) / 4L;
232 static const struct timer_ops mpc83xx_timer_ops = {
233 .get_count = mpc83xx_timer_get_count,
236 static const struct udevice_id mpc83xx_timer_ids[] = {
237 { .compatible = "fsl,mpc83xx-timer" },
241 U_BOOT_DRIVER(mpc83xx_timer) = {
242 .name = "mpc83xx_timer",
244 .of_match = mpc83xx_timer_ids,
245 .probe = mpc83xx_timer_probe,
246 .ops = &mpc83xx_timer_ops,
247 .priv_auto = sizeof(struct mpc83xx_timer_priv),