drivers/timer/dw-apb-timer.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Designware APB Timer driver
   4  *
   5  * Copyright (C) 2018 Marek Vasut <marex@denx.de>
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <clk.h>
  11 #include <dt-structs.h>
  12 #include <malloc.h>
  13 #include <reset.h>
  14 #include <timer.h>
  15 #include <dm/device_compat.h>
  16 #include <linux/kconfig.h>
  17
  18 #include <asm/io.h>
  19 #include <asm/arch/timer.h>
  20
  21 #define DW_APB_LOAD_VAL         0x0
  22 #define DW_APB_CURR_VAL         0x4
  23 #define DW_APB_CTRL             0x8
  24
  25 struct dw_apb_timer_priv {
  26         fdt_addr_t regs;
  27         struct reset_ctl_bulk resets;
  28 };
  29
  30 struct dw_apb_timer_plat {
  31 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  32         struct dtd_snps_dw_apb_timer dtplat;
  33 #endif
  34 };
  35
  36 static u64 dw_apb_timer_get_count(struct udevice *dev)
  37 {
  38         struct dw_apb_timer_priv *priv = dev_get_priv(dev);
  39
  40         /*
  41          * The DW APB counter counts down, but this function
  42          * requires the count to be incrementing. Invert the
  43          * result.
  44          */
  45         return timer_conv_64(~readl(priv->regs + DW_APB_CURR_VAL));
  46 }
  47
  48 static int dw_apb_timer_probe(struct udevice *dev)
  49 {
  50         struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  51         struct dw_apb_timer_priv *priv = dev_get_priv(dev);
  52         struct clk clk;
  53         int ret;
  54 #if CONFIG_IS_ENABLED(OF_PLATDATA)
  55         struct dw_apb_timer_plat *plat = dev_get_plat(dev);
  56         struct dtd_snps_dw_apb_timer *dtplat = &plat->dtplat;
  57
  58         priv->regs = dtplat->reg[0];
  59
  60         ret = clk_get_by_phandle(dev, &dtplat->clocks[0], &clk);
  61         if (ret < 0)
  62                 return ret;
  63
  64         uc_priv->clock_rate = dtplat->clock_frequency;
  65 #endif
  66         if (CONFIG_IS_ENABLED(OF_REAL)) {
  67                 ret = reset_get_bulk(dev, &priv->resets);
  68                 if (ret)
  69                         dev_warn(dev, "Can't get reset: %d\n", ret);
  70                 else
  71                         reset_deassert_bulk(&priv->resets);
  72
  73                 ret = clk_get_by_index(dev, 0, &clk);
  74                 if (ret)
  75                         return ret;
  76
  77                 uc_priv->clock_rate = clk_get_rate(&clk);
  78
  79                 clk_free(&clk);
  80         }
  81
  82         /* init timer */
  83         writel(0xffffffff, priv->regs + DW_APB_LOAD_VAL);
  84         writel(0xffffffff, priv->regs + DW_APB_CURR_VAL);
  85         setbits_le32(priv->regs + DW_APB_CTRL, 0x3);
  86
  87         return 0;
  88 }
  89
  90 static int dw_apb_timer_of_to_plat(struct udevice *dev)
  91 {
  92         if (CONFIG_IS_ENABLED(OF_REAL)) {
  93                 struct dw_apb_timer_priv *priv = dev_get_priv(dev);
  94
  95                 priv->regs = dev_read_addr(dev);
  96         }
  97
  98         return 0;
  99 }
 100
 101 static int dw_apb_timer_remove(struct udevice *dev)
 102 {
 103         struct dw_apb_timer_priv *priv = dev_get_priv(dev);
 104
 105         return reset_release_bulk(&priv->resets);
 106 }
 107
 108 static const struct timer_ops dw_apb_timer_ops = {
 109         .get_count      = dw_apb_timer_get_count,
 110 };
 111
 112 static const struct udevice_id dw_apb_timer_ids[] = {
 113         { .compatible = "snps,dw-apb-timer" },
 114         {}
 115 };
 116
 117 U_BOOT_DRIVER(snps_dw_apb_timer) = {
 118         .name           = "snps_dw_apb_timer",
 119         .id             = UCLASS_TIMER,
 120         .ops            = &dw_apb_timer_ops,
 121         .probe          = dw_apb_timer_probe,
 122         .of_match       = dw_apb_timer_ids,
 123         .of_to_plat = dw_apb_timer_of_to_plat,
 124         .remove         = dw_apb_timer_remove,
 125         .priv_auto      = sizeof(struct dw_apb_timer_priv),
 126         .plat_auto      = sizeof(struct dw_apb_timer_plat),
 127 };