1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt control channel messages
5 * Copyright (C) 2014 Andreas Noever <andreas.noever@gmail.com>
6 * Copyright (C) 2017, Intel Corporation
12 #include <linux/types.h>
13 #include <linux/uuid.h>
23 TB_CFG_ERROR_PORT_NOT_CONNECTED = 0,
24 TB_CFG_ERROR_LINK_ERROR = 1,
25 TB_CFG_ERROR_INVALID_CONFIG_SPACE = 2,
26 TB_CFG_ERROR_NO_SUCH_PORT = 4,
27 TB_CFG_ERROR_ACK_PLUG_EVENT = 7, /* send as reply to TB_CFG_PKG_EVENT */
28 TB_CFG_ERROR_LOOP = 8,
29 TB_CFG_ERROR_HEC_ERROR_DETECTED = 12,
30 TB_CFG_ERROR_FLOW_CONTROL_ERROR = 13,
31 TB_CFG_ERROR_LOCK = 15,
32 TB_CFG_ERROR_DP_BW = 32,
33 TB_CFG_ERROR_ROP_CMPLT = 33,
34 TB_CFG_ERROR_POP_CMPLT = 34,
35 TB_CFG_ERROR_PCIE_WAKE = 35,
36 TB_CFG_ERROR_DP_CON_CHANGE = 36,
37 TB_CFG_ERROR_DPTX_DISCOVERY = 37,
38 TB_CFG_ERROR_LINK_RECOVERY = 38,
39 TB_CFG_ERROR_ASYM_LINK = 39,
43 struct tb_cfg_header {
45 u32 unknown:10; /* highest order bit is set on replies */
49 /* additional header for read/write packets */
50 struct tb_cfg_address {
51 u32 offset:13; /* in dwords */
52 u32 length:6; /* in dwords */
54 enum tb_cfg_space space:2;
55 u32 seq:2; /* sequence number */
59 /* TB_CFG_PKG_READ, response for TB_CFG_PKG_WRITE */
61 struct tb_cfg_header header;
62 struct tb_cfg_address addr;
65 /* TB_CFG_PKG_WRITE, response for TB_CFG_PKG_READ */
66 struct cfg_write_pkg {
67 struct tb_cfg_header header;
68 struct tb_cfg_address addr;
69 u32 data[64]; /* maximum size, tb_cfg_address.length has 6 bits */
72 /* TB_CFG_PKG_ERROR */
73 struct cfg_error_pkg {
74 struct tb_cfg_header header;
75 enum tb_cfg_error error:8;
82 struct tb_cfg_header header;
85 #define TB_CFG_ERROR_PG_HOT_PLUG 0x2
86 #define TB_CFG_ERROR_PG_HOT_UNPLUG 0x3
88 /* TB_CFG_PKG_EVENT */
89 struct cfg_event_pkg {
90 struct tb_cfg_header header;
96 /* TB_CFG_PKG_RESET */
97 struct cfg_reset_pkg {
98 struct tb_cfg_header header;
101 /* TB_CFG_PKG_PREPARE_TO_SLEEP */
103 struct tb_cfg_header header;
110 ICM_GET_TOPOLOGY = 0x1,
111 ICM_DRIVER_READY = 0x3,
112 ICM_APPROVE_DEVICE = 0x4,
113 ICM_CHALLENGE_DEVICE = 0x5,
114 ICM_ADD_DEVICE_KEY = 0x6,
116 ICM_APPROVE_XDOMAIN = 0x10,
117 ICM_DISCONNECT_XDOMAIN = 0x11,
118 ICM_PREBOOT_ACL = 0x18,
119 ICM_USB4_SWITCH_OP = 0x20,
122 enum icm_event_code {
123 ICM_EVENT_DEVICE_CONNECTED = 0x3,
124 ICM_EVENT_DEVICE_DISCONNECTED = 0x4,
125 ICM_EVENT_XDOMAIN_CONNECTED = 0x6,
126 ICM_EVENT_XDOMAIN_DISCONNECTED = 0x7,
127 ICM_EVENT_RTD3_VETO = 0xa,
130 struct icm_pkg_header {
137 #define ICM_FLAGS_ERROR BIT(0)
138 #define ICM_FLAGS_NO_KEY BIT(1)
139 #define ICM_FLAGS_SLEVEL_SHIFT 3
140 #define ICM_FLAGS_SLEVEL_MASK GENMASK(4, 3)
141 #define ICM_FLAGS_DUAL_LANE BIT(5)
142 #define ICM_FLAGS_SPEED_GEN3 BIT(7)
143 #define ICM_FLAGS_WRITE BIT(7)
145 struct icm_pkg_driver_ready {
146 struct icm_pkg_header hdr;
149 /* Falcon Ridge only messages */
151 struct icm_fr_pkg_driver_ready_response {
152 struct icm_pkg_header hdr;
158 #define ICM_FR_SLEVEL_MASK 0xf
160 /* Falcon Ridge & Alpine Ridge common messages */
162 struct icm_fr_pkg_get_topology {
163 struct icm_pkg_header hdr;
166 #define ICM_GET_TOPOLOGY_PACKETS 14
168 struct icm_fr_pkg_get_topology_response {
169 struct icm_pkg_header hdr;
174 u8 drom_i2c_address_index;
178 u32 port_hop_info[16];
181 #define ICM_SWITCH_USED BIT(0)
182 #define ICM_SWITCH_UPSTREAM_PORT_MASK GENMASK(7, 1)
183 #define ICM_SWITCH_UPSTREAM_PORT_SHIFT 1
185 #define ICM_PORT_TYPE_MASK GENMASK(23, 0)
186 #define ICM_PORT_INDEX_SHIFT 24
187 #define ICM_PORT_INDEX_MASK GENMASK(31, 24)
189 struct icm_fr_event_device_connected {
190 struct icm_pkg_header hdr;
198 #define ICM_LINK_INFO_LINK_MASK 0x7
199 #define ICM_LINK_INFO_DEPTH_SHIFT 4
200 #define ICM_LINK_INFO_DEPTH_MASK GENMASK(7, 4)
201 #define ICM_LINK_INFO_APPROVED BIT(8)
202 #define ICM_LINK_INFO_REJECTED BIT(9)
203 #define ICM_LINK_INFO_BOOT BIT(10)
205 struct icm_fr_pkg_approve_device {
206 struct icm_pkg_header hdr;
213 struct icm_fr_event_device_disconnected {
214 struct icm_pkg_header hdr;
219 struct icm_fr_event_xdomain_connected {
220 struct icm_pkg_header hdr;
231 struct icm_fr_event_xdomain_disconnected {
232 struct icm_pkg_header hdr;
238 struct icm_fr_pkg_add_device_key {
239 struct icm_pkg_header hdr;
247 struct icm_fr_pkg_add_device_key_response {
248 struct icm_pkg_header hdr;
255 struct icm_fr_pkg_challenge_device {
256 struct icm_pkg_header hdr;
264 struct icm_fr_pkg_challenge_device_response {
265 struct icm_pkg_header hdr;
274 struct icm_fr_pkg_approve_xdomain {
275 struct icm_pkg_header hdr;
285 struct icm_fr_pkg_approve_xdomain_response {
286 struct icm_pkg_header hdr;
296 /* Alpine Ridge only messages */
298 struct icm_ar_pkg_driver_ready_response {
299 struct icm_pkg_header hdr;
305 #define ICM_AR_FLAGS_RTD3 BIT(6)
307 #define ICM_AR_INFO_SLEVEL_MASK GENMASK(3, 0)
308 #define ICM_AR_INFO_BOOT_ACL_SHIFT 7
309 #define ICM_AR_INFO_BOOT_ACL_MASK GENMASK(11, 7)
310 #define ICM_AR_INFO_BOOT_ACL_SUPPORTED BIT(13)
312 struct icm_ar_pkg_get_route {
313 struct icm_pkg_header hdr;
318 struct icm_ar_pkg_get_route_response {
319 struct icm_pkg_header hdr;
326 struct icm_ar_boot_acl_entry {
331 #define ICM_AR_PREBOOT_ACL_ENTRIES 16
333 struct icm_ar_pkg_preboot_acl {
334 struct icm_pkg_header hdr;
335 struct icm_ar_boot_acl_entry acl[ICM_AR_PREBOOT_ACL_ENTRIES];
338 struct icm_ar_pkg_preboot_acl_response {
339 struct icm_pkg_header hdr;
340 struct icm_ar_boot_acl_entry acl[ICM_AR_PREBOOT_ACL_ENTRIES];
343 /* Titan Ridge messages */
345 struct icm_tr_pkg_driver_ready_response {
346 struct icm_pkg_header hdr;
354 #define ICM_TR_FLAGS_RTD3 BIT(6)
356 #define ICM_TR_INFO_SLEVEL_MASK GENMASK(2, 0)
357 #define ICM_TR_INFO_PROTO_VERSION_MASK GENMASK(6, 4)
358 #define ICM_TR_INFO_PROTO_VERSION_SHIFT 4
359 #define ICM_TR_INFO_BOOT_ACL_SHIFT 7
360 #define ICM_TR_INFO_BOOT_ACL_MASK GENMASK(12, 7)
362 struct icm_tr_event_device_connected {
363 struct icm_pkg_header hdr;
373 struct icm_tr_event_device_disconnected {
374 struct icm_pkg_header hdr;
379 struct icm_tr_event_xdomain_connected {
380 struct icm_pkg_header hdr;
391 struct icm_tr_event_xdomain_disconnected {
392 struct icm_pkg_header hdr;
398 struct icm_tr_pkg_approve_device {
399 struct icm_pkg_header hdr;
407 struct icm_tr_pkg_add_device_key {
408 struct icm_pkg_header hdr;
417 struct icm_tr_pkg_challenge_device {
418 struct icm_pkg_header hdr;
427 struct icm_tr_pkg_approve_xdomain {
428 struct icm_pkg_header hdr;
438 struct icm_tr_pkg_disconnect_xdomain {
439 struct icm_pkg_header hdr;
447 struct icm_tr_pkg_challenge_device_response {
448 struct icm_pkg_header hdr;
458 struct icm_tr_pkg_add_device_key_response {
459 struct icm_pkg_header hdr;
467 struct icm_tr_pkg_approve_xdomain_response {
468 struct icm_pkg_header hdr;
478 struct icm_tr_pkg_disconnect_xdomain_response {
479 struct icm_pkg_header hdr;
487 /* Ice Lake messages */
489 struct icm_icl_event_rtd3_veto {
490 struct icm_pkg_header hdr;
494 /* USB4 ICM messages */
496 struct icm_usb4_switch_op {
497 struct icm_pkg_header hdr;
506 #define ICM_USB4_SWITCH_DATA_LEN_MASK GENMASK(3, 0)
507 #define ICM_USB4_SWITCH_DATA_VALID BIT(4)
509 struct icm_usb4_switch_op_response {
510 struct icm_pkg_header hdr;
519 /* XDomain messages */
521 struct tb_xdomain_header {
527 #define TB_XDOMAIN_LENGTH_MASK GENMASK(5, 0)
528 #define TB_XDOMAIN_SN_MASK GENMASK(28, 27)
529 #define TB_XDOMAIN_SN_SHIFT 27
532 UUID_REQUEST_OLD = 1,
536 PROPERTIES_CHANGED_REQUEST,
537 PROPERTIES_CHANGED_RESPONSE,
540 LINK_STATE_STATUS_REQUEST = 15,
541 LINK_STATE_STATUS_RESPONSE,
542 LINK_STATE_CHANGE_REQUEST,
543 LINK_STATE_CHANGE_RESPONSE,
546 struct tb_xdp_header {
547 struct tb_xdomain_header xd_hdr;
552 struct tb_xdp_error_response {
553 struct tb_xdp_header hdr;
557 struct tb_xdp_link_state_status {
558 struct tb_xdp_header hdr;
561 struct tb_xdp_link_state_status_response {
563 struct tb_xdp_error_response err;
565 struct tb_xdp_header hdr;
575 struct tb_xdp_link_state_change {
576 struct tb_xdp_header hdr;
582 struct tb_xdp_link_state_change_response {
584 struct tb_xdp_error_response err;
586 struct tb_xdp_header hdr;
593 struct tb_xdp_header hdr;
596 struct tb_xdp_uuid_response {
598 struct tb_xdp_error_response err;
600 struct tb_xdp_header hdr;
608 struct tb_xdp_properties {
609 struct tb_xdp_header hdr;
616 struct tb_xdp_properties_response {
618 struct tb_xdp_error_response err;
620 struct tb_xdp_header hdr;
632 * Max length of data array single XDomain property response is allowed
635 #define TB_XDP_PROPERTIES_MAX_DATA_LENGTH \
636 (((256 - 4 - sizeof(struct tb_xdp_properties_response))) / 4)
638 /* Maximum size of the total property block in dwords we allow */
639 #define TB_XDP_PROPERTIES_MAX_LENGTH 500
641 struct tb_xdp_properties_changed {
642 struct tb_xdp_header hdr;
646 struct tb_xdp_properties_changed_response {
648 struct tb_xdp_error_response err;
649 struct tb_xdp_header hdr;
655 ERROR_UNKNOWN_PACKET,
656 ERROR_UNKNOWN_DOMAIN,