1 // SPDX-License-Identifier: GPL-2.0
3 * Tegra30 SoC Thermal Sensor driver
5 * Based on downstream HWMON driver from NVIDIA.
6 * Copyright (C) 2011 NVIDIA Corporation
8 * Author: Dmitry Osipenko <digetx@gmail.com>
9 * Copyright (C) 2021 GRATE-DRIVER project
12 #include <linux/bitfield.h>
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/errno.h>
16 #include <linux/interrupt.h>
18 #include <linux/iopoll.h>
19 #include <linux/math.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/platform_device.h>
24 #include <linux/reset.h>
25 #include <linux/slab.h>
26 #include <linux/thermal.h>
27 #include <linux/types.h>
29 #include <soc/tegra/fuse.h>
31 #include "../thermal_core.h"
32 #include "../thermal_hwmon.h"
34 #define TSENSOR_SENSOR0_CONFIG0 0x0
35 #define TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP BIT(0)
36 #define TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN BIT(1)
37 #define TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN BIT(2)
38 #define TSENSOR_SENSOR0_CONFIG0_DVFS_EN BIT(3)
39 #define TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN BIT(4)
40 #define TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN BIT(5)
41 #define TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN BIT(6)
42 #define TSENSOR_SENSOR0_CONFIG0_M GENMASK(23, 8)
43 #define TSENSOR_SENSOR0_CONFIG0_N GENMASK(31, 24)
45 #define TSENSOR_SENSOR0_CONFIG1 0x8
46 #define TSENSOR_SENSOR0_CONFIG1_TH1 GENMASK(15, 0)
47 #define TSENSOR_SENSOR0_CONFIG1_TH2 GENMASK(31, 16)
49 #define TSENSOR_SENSOR0_CONFIG2 0xc
50 #define TSENSOR_SENSOR0_CONFIG2_TH3 GENMASK(15, 0)
52 #define TSENSOR_SENSOR0_STATUS0 0x18
53 #define TSENSOR_SENSOR0_STATUS0_STATE GENMASK(2, 0)
54 #define TSENSOR_SENSOR0_STATUS0_INTR BIT(8)
55 #define TSENSOR_SENSOR0_STATUS0_CURRENT_VALID BIT(9)
57 #define TSENSOR_SENSOR0_TS_STATUS1 0x1c
58 #define TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT GENMASK(31, 16)
60 #define TEGRA30_FUSE_TEST_PROG_VER 0x28
62 #define TEGRA30_FUSE_TSENSOR_CALIB 0x98
63 #define TEGRA30_FUSE_TSENSOR_CALIB_LOW GENMASK(15, 0)
64 #define TEGRA30_FUSE_TSENSOR_CALIB_HIGH GENMASK(31, 16)
66 #define TEGRA30_FUSE_SPARE_BIT 0x144
70 struct tegra_tsensor_calibration_data {
74 struct tegra_tsensor_channel {
77 struct tegra_tsensor *ts;
78 struct thermal_zone_device *tzd;
81 struct tegra_tsensor {
86 struct reset_control *rst;
87 struct tegra_tsensor_channel ch[2];
88 struct tegra_tsensor_calibration_data calib;
91 static int tegra_tsensor_hw_enable(const struct tegra_tsensor *ts)
96 err = reset_control_assert(ts->rst);
98 dev_err(ts->dev, "failed to assert hardware reset: %d\n", err);
102 err = clk_prepare_enable(ts->clk);
104 dev_err(ts->dev, "failed to enable clock: %d\n", err);
110 err = reset_control_deassert(ts->rst);
112 dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err);
117 * Sensors are enabled after reset by default, but not gauging
118 * until clock counter is programmed.
120 * M: number of reference clock pulses after which every
121 * temperature / voltage measurement is made
123 * N: number of reference clock counts for which the counter runs
125 val = FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_M, 12500);
126 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_N, 255);
128 /* apply the same configuration to both channels */
129 writel_relaxed(val, ts->regs + 0x40 + TSENSOR_SENSOR0_CONFIG0);
130 writel_relaxed(val, ts->regs + 0x80 + TSENSOR_SENSOR0_CONFIG0);
135 clk_disable_unprepare(ts->clk);
140 static int tegra_tsensor_hw_disable(const struct tegra_tsensor *ts)
144 err = reset_control_assert(ts->rst);
146 dev_err(ts->dev, "failed to assert hardware reset: %d\n", err);
150 clk_disable_unprepare(ts->clk);
155 static void devm_tegra_tsensor_hw_disable(void *data)
157 const struct tegra_tsensor *ts = data;
159 tegra_tsensor_hw_disable(ts);
162 static int tegra_tsensor_get_temp(void *data, int *temp)
164 const struct tegra_tsensor_channel *tsc = data;
165 const struct tegra_tsensor *ts = tsc->ts;
166 int err, c1, c2, c3, c4, counter;
170 * Counter will be invalid if hardware is misprogrammed or not enough
171 * time passed since the time when sensor was enabled.
173 err = readl_relaxed_poll_timeout(tsc->regs + TSENSOR_SENSOR0_STATUS0, val,
174 val & TSENSOR_SENSOR0_STATUS0_CURRENT_VALID,
176 21 * USEC_PER_MSEC * 50);
178 dev_err_once(ts->dev, "ch%u: counter invalid\n", tsc->id);
182 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_TS_STATUS1);
183 counter = FIELD_GET(TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT, val);
186 * This shouldn't happen with a valid counter status, nevertheless
187 * lets verify the value since it's in a separate (from status)
190 if (counter == 0xffff) {
191 dev_err_once(ts->dev, "ch%u: counter overflow\n", tsc->id);
196 * temperature = a * counter + b
197 * temperature = m * (temperature ^ 2) + n * temperature + p
199 c1 = DIV_ROUND_CLOSEST(ts->calib.a * counter + ts->calib.b, 1000000);
201 c2 = DIV_ROUND_CLOSEST(ts->calib.p, c1);
202 c3 = c1 * ts->calib.m;
205 *temp = DIV_ROUND_CLOSEST(c1 * (c2 + c3 + c4), 1000);
210 static int tegra_tsensor_temp_to_counter(const struct tegra_tsensor *ts, int temp)
214 c1 = DIV_ROUND_CLOSEST(ts->calib.p - temp * 1000, ts->calib.m);
215 c2 = -ts->calib.r - int_sqrt(ts->calib.r * ts->calib.r - c1);
217 return DIV_ROUND_CLOSEST(c2 * 1000000 - ts->calib.b, ts->calib.a);
220 static int tegra_tsensor_set_trips(void *data, int low, int high)
222 const struct tegra_tsensor_channel *tsc = data;
223 const struct tegra_tsensor *ts = tsc->ts;
227 * TSENSOR doesn't trigger interrupt on the "low" temperature breach,
228 * hence bail out if high temperature is unspecified.
233 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1);
234 val &= ~TSENSOR_SENSOR0_CONFIG1_TH1;
236 high = tegra_tsensor_temp_to_counter(ts, high);
237 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH1, high);
238 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);
243 static const struct thermal_zone_of_device_ops ops = {
244 .get_temp = tegra_tsensor_get_temp,
245 .set_trips = tegra_tsensor_set_trips,
249 tegra_tsensor_handle_channel_interrupt(const struct tegra_tsensor *ts,
252 const struct tegra_tsensor_channel *tsc = &ts->ch[id];
255 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_STATUS0);
256 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_STATUS0);
258 if (FIELD_GET(TSENSOR_SENSOR0_STATUS0_STATE, val) == 5)
259 dev_err_ratelimited(ts->dev, "ch%u: counter overflowed\n", id);
261 if (!FIELD_GET(TSENSOR_SENSOR0_STATUS0_INTR, val))
264 thermal_zone_device_update(tsc->tzd, THERMAL_EVENT_UNSPECIFIED);
269 static irqreturn_t tegra_tsensor_isr(int irq, void *data)
271 const struct tegra_tsensor *ts = data;
272 bool handled = false;
275 for (i = 0; i < ARRAY_SIZE(ts->ch); i++)
276 handled |= tegra_tsensor_handle_channel_interrupt(ts, i);
278 return handled ? IRQ_HANDLED : IRQ_NONE;
281 static int tegra_tsensor_disable_hw_channel(const struct tegra_tsensor *ts,
284 const struct tegra_tsensor_channel *tsc = &ts->ch[id];
285 struct thermal_zone_device *tzd = tsc->tzd;
292 err = thermal_zone_device_disable(tzd);
294 dev_err(ts->dev, "ch%u: failed to disable zone: %d\n", id, err);
299 /* stop channel gracefully */
300 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);
301 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP, 1);
302 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
307 static void tegra_tsensor_get_hw_channel_trips(struct thermal_zone_device *tzd,
308 int *hot_trip, int *crit_trip)
313 * 90C is the maximal critical temperature of all Tegra30 SoC variants,
314 * use it for the default trip if unspecified in a device-tree.
319 for (i = 0; i < tzd->trips; i++) {
320 enum thermal_trip_type type;
323 tzd->ops->get_trip_temp(tzd, i, &trip_temp);
324 tzd->ops->get_trip_type(tzd, i, &type);
326 if (type == THERMAL_TRIP_HOT)
327 *hot_trip = trip_temp;
329 if (type == THERMAL_TRIP_CRITICAL)
330 *crit_trip = trip_temp;
333 /* clamp hardware trips to the calibration limits */
334 *hot_trip = clamp(*hot_trip, 25000, 90000);
337 * Kernel will perform a normal system shut down if it will
338 * see that critical temperature is breached, hence set the
339 * hardware limit by 5C higher in order to allow system to
340 * shut down gracefully before sending signal to the Power
341 * Management controller.
343 *crit_trip = clamp(*crit_trip + 5000, 25000, 90000);
346 static int tegra_tsensor_enable_hw_channel(const struct tegra_tsensor *ts,
349 const struct tegra_tsensor_channel *tsc = &ts->ch[id];
350 struct thermal_zone_device *tzd = tsc->tzd;
351 int err, hot_trip = 0, crit_trip = 0;
355 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);
356 val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP;
357 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
362 tegra_tsensor_get_hw_channel_trips(tzd, &hot_trip, &crit_trip);
364 /* prevent potential racing with tegra_tsensor_set_trips() */
365 mutex_lock(&tzd->lock);
367 dev_info_once(ts->dev, "ch%u: PMC emergency shutdown trip set to %dC\n",
368 id, DIV_ROUND_CLOSEST(crit_trip, 1000));
370 hot_trip = tegra_tsensor_temp_to_counter(ts, hot_trip);
371 crit_trip = tegra_tsensor_temp_to_counter(ts, crit_trip);
373 /* program LEVEL2 counter threshold */
374 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1);
375 val &= ~TSENSOR_SENSOR0_CONFIG1_TH2;
376 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH2, hot_trip);
377 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1);
379 /* program LEVEL3 counter threshold */
380 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG2);
381 val &= ~TSENSOR_SENSOR0_CONFIG2_TH3;
382 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG2_TH3, crit_trip);
383 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG2);
386 * Enable sensor, emergency shutdown, interrupts for level 1/2/3
387 * breaches and counter overflow condition.
389 * Disable DIV2 throttle for now since we need to figure out how
390 * to integrate it properly with the thermal framework.
392 * Thermal levels supported by hardware:
395 * Level 1 = passive cooling (cpufreq DVFS)
396 * Level 2 = passive cooling assisted by hardware (DIV2)
397 * Level 3 = emergency shutdown assisted by hardware (PMC)
399 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0);
400 val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP;
401 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_DVFS_EN, 1);
402 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN, 0);
403 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN, 1);
404 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN, 1);
405 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN, 1);
406 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN, 1);
407 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0);
409 mutex_unlock(&tzd->lock);
411 err = thermal_zone_device_enable(tzd);
413 dev_err(ts->dev, "ch%u: failed to enable zone: %d\n", id, err);
420 static bool tegra_tsensor_fuse_read_spare(unsigned int spare)
424 tegra_fuse_readl(TEGRA30_FUSE_SPARE_BIT + spare * 4, &val);
429 static int tegra_tsensor_nvmem_setup(struct tegra_tsensor *ts)
431 u32 i, ate_ver = 0, cal = 0, t1_25C = 0, t2_90C = 0;
432 int err, c1_25C, c2_90C;
434 err = tegra_fuse_readl(TEGRA30_FUSE_TEST_PROG_VER, &ate_ver);
436 dev_err_probe(ts->dev, err, "failed to get ATE version\n");
441 dev_info(ts->dev, "unsupported ATE version: %u\n", ate_ver);
446 * We have two TSENSOR channels in a two different spots on SoC.
447 * Second channel provides more accurate data on older SoC versions,
448 * use it as a primary channel.
451 dev_info_once(ts->dev,
452 "older ATE version detected, channels remapped\n");
453 ts->swap_channels = true;
456 err = tegra_fuse_readl(TEGRA30_FUSE_TSENSOR_CALIB, &cal);
458 dev_err(ts->dev, "failed to get calibration data: %d\n", err);
462 /* get calibrated counter values for 25C/90C thresholds */
463 c1_25C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_LOW, cal);
464 c2_90C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_HIGH, cal);
466 /* and calibrated temperatures corresponding to the counter values */
467 for (i = 0; i < 7; i++) {
468 t1_25C |= tegra_tsensor_fuse_read_spare(14 + i) << i;
469 t1_25C |= tegra_tsensor_fuse_read_spare(21 + i) << i;
471 t2_90C |= tegra_tsensor_fuse_read_spare(0 + i) << i;
472 t2_90C |= tegra_tsensor_fuse_read_spare(7 + i) << i;
475 if (c2_90C - c1_25C <= t2_90C - t1_25C) {
476 dev_err(ts->dev, "invalid calibration data: %d %d %u %u\n",
477 c2_90C, c1_25C, t2_90C, t1_25C);
481 /* all calibration coefficients are premultiplied by 1000000 */
483 ts->calib.a = DIV_ROUND_CLOSEST((t2_90C - t1_25C) * 1000000,
486 ts->calib.b = t1_25C * 1000000 - ts->calib.a * c1_25C;
488 if (tegra_sku_info.revision == TEGRA_REVISION_A01) {
490 ts->calib.n = 1338811;
491 ts->calib.p = -7300000;
494 ts->calib.n = 1528943;
495 ts->calib.p = -11100000;
498 /* except the coefficient of a reduced quadratic equation */
499 ts->calib.r = DIV_ROUND_CLOSEST(ts->calib.n, ts->calib.m * 2);
501 dev_info_once(ts->dev,
502 "calibration: %d %d %u %u ATE ver: %u SoC rev: %u\n",
503 c2_90C, c1_25C, t2_90C, t1_25C, ate_ver,
504 tegra_sku_info.revision);
509 static int tegra_tsensor_register_channel(struct tegra_tsensor *ts,
512 struct tegra_tsensor_channel *tsc = &ts->ch[id];
513 unsigned int hw_id = ts->swap_channels ? !id : id;
517 tsc->regs = ts->regs + 0x40 * (hw_id + 1);
519 tsc->tzd = devm_thermal_zone_of_sensor_register(ts->dev, id, tsc, &ops);
520 if (IS_ERR(tsc->tzd)) {
521 if (PTR_ERR(tsc->tzd) != -ENODEV)
522 return dev_err_probe(ts->dev, PTR_ERR(tsc->tzd),
523 "failed to register thermal zone\n");
526 * It's okay if sensor isn't assigned to any thermal zone
533 if (devm_thermal_add_hwmon_sysfs(tsc->tzd))
534 dev_warn(ts->dev, "failed to add hwmon sysfs attributes\n");
539 static int tegra_tsensor_probe(struct platform_device *pdev)
541 struct tegra_tsensor *ts;
545 ts = devm_kzalloc(&pdev->dev, sizeof(*ts), GFP_KERNEL);
549 irq = platform_get_irq(pdev, 0);
553 ts->dev = &pdev->dev;
554 platform_set_drvdata(pdev, ts);
556 ts->regs = devm_platform_ioremap_resource(pdev, 0);
557 if (IS_ERR(ts->regs))
558 return PTR_ERR(ts->regs);
560 ts->clk = devm_clk_get(&pdev->dev, NULL);
562 return dev_err_probe(&pdev->dev, PTR_ERR(ts->clk),
563 "failed to get clock\n");
565 ts->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
567 return dev_err_probe(&pdev->dev, PTR_ERR(ts->rst),
568 "failed to get reset control\n");
570 err = tegra_tsensor_nvmem_setup(ts);
574 err = tegra_tsensor_hw_enable(ts);
578 err = devm_add_action_or_reset(&pdev->dev,
579 devm_tegra_tsensor_hw_disable,
584 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
585 err = tegra_tsensor_register_channel(ts, i);
590 err = devm_request_threaded_irq(&pdev->dev, irq, NULL,
591 tegra_tsensor_isr, IRQF_ONESHOT,
592 "tegra_tsensor", ts);
594 return dev_err_probe(&pdev->dev, err,
595 "failed to request interrupt\n");
597 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
598 err = tegra_tsensor_enable_hw_channel(ts, i);
606 static int __maybe_unused tegra_tsensor_suspend(struct device *dev)
608 struct tegra_tsensor *ts = dev_get_drvdata(dev);
612 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
613 err = tegra_tsensor_disable_hw_channel(ts, i);
618 err = tegra_tsensor_hw_disable(ts);
626 tegra_tsensor_enable_hw_channel(ts, i);
631 static int __maybe_unused tegra_tsensor_resume(struct device *dev)
633 struct tegra_tsensor *ts = dev_get_drvdata(dev);
637 err = tegra_tsensor_hw_enable(ts);
641 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) {
642 err = tegra_tsensor_enable_hw_channel(ts, i);
650 static const struct dev_pm_ops tegra_tsensor_pm_ops = {
651 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_tsensor_suspend,
652 tegra_tsensor_resume)
655 static const struct of_device_id tegra_tsensor_of_match[] = {
656 { .compatible = "nvidia,tegra30-tsensor", },
659 MODULE_DEVICE_TABLE(of, tegra_tsensor_of_match);
661 static struct platform_driver tegra_tsensor_driver = {
662 .probe = tegra_tsensor_probe,
664 .name = "tegra30-tsensor",
665 .of_match_table = tegra_tsensor_of_match,
666 .pm = &tegra_tsensor_pm_ops,
669 module_platform_driver(tegra_tsensor_driver);
671 MODULE_DESCRIPTION("NVIDIA Tegra30 Thermal Sensor driver");
672 MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
673 MODULE_LICENSE("GPL");