1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2023 MediaTek Inc.
4 * Author: Balsam CHIHI <bchihi@baylibre.com>
8 #include <linux/clk-provider.h>
9 #include <linux/delay.h>
10 #include <linux/debugfs.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13 #include <linux/iopoll.h>
14 #include <linux/kernel.h>
15 #include <linux/nvmem-consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/reset.h>
19 #include <linux/thermal.h>
20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
22 #include "../thermal_hwmon.h"
24 #define LVTS_MONCTL0(__base) (__base + 0x0000)
25 #define LVTS_MONCTL1(__base) (__base + 0x0004)
26 #define LVTS_MONCTL2(__base) (__base + 0x0008)
27 #define LVTS_MONINT(__base) (__base + 0x000C)
28 #define LVTS_MONINTSTS(__base) (__base + 0x0010)
29 #define LVTS_MONIDET0(__base) (__base + 0x0014)
30 #define LVTS_MONIDET1(__base) (__base + 0x0018)
31 #define LVTS_MONIDET2(__base) (__base + 0x001C)
32 #define LVTS_MONIDET3(__base) (__base + 0x0020)
33 #define LVTS_H2NTHRE(__base) (__base + 0x0024)
34 #define LVTS_HTHRE(__base) (__base + 0x0028)
35 #define LVTS_OFFSETH(__base) (__base + 0x0030)
36 #define LVTS_OFFSETL(__base) (__base + 0x0034)
37 #define LVTS_MSRCTL0(__base) (__base + 0x0038)
38 #define LVTS_MSRCTL1(__base) (__base + 0x003C)
39 #define LVTS_TSSEL(__base) (__base + 0x0040)
40 #define LVTS_CALSCALE(__base) (__base + 0x0048)
41 #define LVTS_ID(__base) (__base + 0x004C)
42 #define LVTS_CONFIG(__base) (__base + 0x0050)
43 #define LVTS_EDATA00(__base) (__base + 0x0054)
44 #define LVTS_EDATA01(__base) (__base + 0x0058)
45 #define LVTS_EDATA02(__base) (__base + 0x005C)
46 #define LVTS_EDATA03(__base) (__base + 0x0060)
47 #define LVTS_MSR0(__base) (__base + 0x0090)
48 #define LVTS_MSR1(__base) (__base + 0x0094)
49 #define LVTS_MSR2(__base) (__base + 0x0098)
50 #define LVTS_MSR3(__base) (__base + 0x009C)
51 #define LVTS_IMMD0(__base) (__base + 0x00A0)
52 #define LVTS_IMMD1(__base) (__base + 0x00A4)
53 #define LVTS_IMMD2(__base) (__base + 0x00A8)
54 #define LVTS_IMMD3(__base) (__base + 0x00AC)
55 #define LVTS_PROTCTL(__base) (__base + 0x00C0)
56 #define LVTS_PROTTA(__base) (__base + 0x00C4)
57 #define LVTS_PROTTB(__base) (__base + 0x00C8)
58 #define LVTS_PROTTC(__base) (__base + 0x00CC)
59 #define LVTS_CLKEN(__base) (__base + 0x00E4)
61 #define LVTS_PERIOD_UNIT ((118 * 1000) / (256 * 38))
62 #define LVTS_GROUP_INTERVAL 1
63 #define LVTS_FILTER_INTERVAL 1
64 #define LVTS_SENSOR_INTERVAL 1
65 #define LVTS_HW_FILTER 0x2
66 #define LVTS_TSSEL_CONF 0x13121110
67 #define LVTS_CALSCALE_CONF 0x300
68 #define LVTS_MONINT_CONF 0x8300318C
70 #define LVTS_MONINT_OFFSET_SENSOR0 0xC
71 #define LVTS_MONINT_OFFSET_SENSOR1 0x180
72 #define LVTS_MONINT_OFFSET_SENSOR2 0x3000
73 #define LVTS_MONINT_OFFSET_SENSOR3 0x3000000
75 #define LVTS_INT_SENSOR0 0x0009001F
76 #define LVTS_INT_SENSOR1 0x001203E0
77 #define LVTS_INT_SENSOR2 0x00247C00
78 #define LVTS_INT_SENSOR3 0x1FC00000
80 #define LVTS_SENSOR_MAX 4
81 #define LVTS_GOLDEN_TEMP_MAX 62
82 #define LVTS_GOLDEN_TEMP_DEFAULT 50
83 #define LVTS_COEFF_A -250460
84 #define LVTS_COEFF_B 250460
86 #define LVTS_MSR_IMMEDIATE_MODE 0
87 #define LVTS_MSR_FILTERED_MODE 1
89 #define LVTS_HW_SHUTDOWN_MT8195 105000
91 #define LVTS_MINIMUM_THRESHOLD 20000
93 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT;
94 static int coeff_b = LVTS_COEFF_B;
96 struct lvts_sensor_data {
100 struct lvts_ctrl_data {
101 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX];
102 int cal_offset[LVTS_SENSOR_MAX];
110 const struct lvts_ctrl_data *lvts_ctrl;
115 struct thermal_zone_device *tz;
125 struct lvts_sensor sensors[LVTS_SENSOR_MAX];
126 u32 calibration[LVTS_SENSOR_MAX];
127 u32 hw_tshut_raw_temp;
136 struct lvts_ctrl *lvts_ctrl;
137 struct reset_control *reset;
143 #ifdef CONFIG_DEBUG_FS
144 struct dentry *dom_dentry;
148 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS
150 #define LVTS_DEBUG_FS_REGS(__reg) \
152 .name = __stringify(__reg), \
153 .offset = __reg(0), \
156 static const struct debugfs_reg32 lvts_regs[] = {
157 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0),
158 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1),
159 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2),
160 LVTS_DEBUG_FS_REGS(LVTS_MONINT),
161 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS),
162 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0),
163 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1),
164 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2),
165 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3),
166 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE),
167 LVTS_DEBUG_FS_REGS(LVTS_HTHRE),
168 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH),
169 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL),
170 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0),
171 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1),
172 LVTS_DEBUG_FS_REGS(LVTS_TSSEL),
173 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE),
174 LVTS_DEBUG_FS_REGS(LVTS_ID),
175 LVTS_DEBUG_FS_REGS(LVTS_CONFIG),
176 LVTS_DEBUG_FS_REGS(LVTS_EDATA00),
177 LVTS_DEBUG_FS_REGS(LVTS_EDATA01),
178 LVTS_DEBUG_FS_REGS(LVTS_EDATA02),
179 LVTS_DEBUG_FS_REGS(LVTS_EDATA03),
180 LVTS_DEBUG_FS_REGS(LVTS_MSR0),
181 LVTS_DEBUG_FS_REGS(LVTS_MSR1),
182 LVTS_DEBUG_FS_REGS(LVTS_MSR2),
183 LVTS_DEBUG_FS_REGS(LVTS_MSR3),
184 LVTS_DEBUG_FS_REGS(LVTS_IMMD0),
185 LVTS_DEBUG_FS_REGS(LVTS_IMMD1),
186 LVTS_DEBUG_FS_REGS(LVTS_IMMD2),
187 LVTS_DEBUG_FS_REGS(LVTS_IMMD3),
188 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL),
189 LVTS_DEBUG_FS_REGS(LVTS_PROTTA),
190 LVTS_DEBUG_FS_REGS(LVTS_PROTTB),
191 LVTS_DEBUG_FS_REGS(LVTS_PROTTC),
192 LVTS_DEBUG_FS_REGS(LVTS_CLKEN),
195 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td)
197 struct debugfs_regset32 *regset;
198 struct lvts_ctrl *lvts_ctrl;
199 struct dentry *dentry;
203 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL);
204 if (IS_ERR(lvts_td->dom_dentry))
207 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
209 lvts_ctrl = &lvts_td->lvts_ctrl[i];
211 sprintf(name, "controller%d", i);
212 dentry = debugfs_create_dir(name, lvts_td->dom_dentry);
216 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL);
220 regset->base = lvts_ctrl->base;
221 regset->regs = lvts_regs;
222 regset->nregs = ARRAY_SIZE(lvts_regs);
224 debugfs_create_regset32("registers", 0400, dentry, regset);
230 static void lvts_debugfs_exit(struct lvts_domain *lvts_td)
232 debugfs_remove_recursive(lvts_td->dom_dentry);
237 static inline int lvts_debugfs_init(struct device *dev,
238 struct lvts_domain *lvts_td)
243 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { }
247 static int lvts_raw_to_temp(u32 raw_temp)
251 temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14;
252 temperature += coeff_b;
257 static u32 lvts_temp_to_raw(int temperature)
259 u32 raw_temp = ((s64)(coeff_b - temperature)) << 14;
261 raw_temp = div_s64(raw_temp, -LVTS_COEFF_A);
266 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp)
268 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
269 void __iomem *msr = lvts_sensor->msr;
273 * Measurement registers:
275 * LVTS_MSR[0-3] / LVTS_IMMD[0-3]
280 * 16 : Valid temperature
281 * 15-0 : Raw temperature
286 * As the thermal zone temperature will read before the
287 * hardware sensor is fully initialized, we have to check the
288 * validity of the temperature returned when reading the
289 * measurement register. The thermal controller will set the
290 * valid bit temperature only when it is totally initialized.
292 * Otherwise, we may end up with garbage values out of the
293 * functionning temperature and directly jump to a system
296 if (!(value & BIT(16)))
299 *temp = lvts_raw_to_temp(value & 0xFFFF);
304 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl)
307 LVTS_MONINT_OFFSET_SENSOR0,
308 LVTS_MONINT_OFFSET_SENSOR1,
309 LVTS_MONINT_OFFSET_SENSOR2,
310 LVTS_MONINT_OFFSET_SENSOR3,
315 value = readl(LVTS_MONINT(lvts_ctrl->base));
317 for (i = 0; i < ARRAY_SIZE(masks); i++) {
318 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
319 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
325 writel(value, LVTS_MONINT(lvts_ctrl->base));
328 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high)
332 if (high > lvts_ctrl->high_thresh)
335 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++)
336 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh
337 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh)
343 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high)
345 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz);
346 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]);
347 void __iomem *base = lvts_sensor->base;
348 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD);
349 u32 raw_high = lvts_temp_to_raw(high);
350 bool should_update_thresh;
352 lvts_sensor->low_thresh = low;
353 lvts_sensor->high_thresh = high;
355 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high);
356 if (should_update_thresh) {
357 lvts_ctrl->high_thresh = high;
358 lvts_ctrl->low_thresh = low;
360 lvts_update_irq_mask(lvts_ctrl);
362 if (!should_update_thresh)
366 * Low offset temperature threshold
372 * 14-0 : Raw temperature for threshold
374 pr_debug("%s: Setting low limit temperature interrupt: %d\n",
375 thermal_zone_device_type(tz), low);
376 writel(raw_low, LVTS_OFFSETL(base));
379 * High offset temperature threshold
385 * 14-0 : Raw temperature for threshold
387 pr_debug("%s: Setting high limit temperature interrupt: %d\n",
388 thermal_zone_device_type(tz), high);
389 writel(raw_high, LVTS_OFFSETH(base));
394 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl)
396 irqreturn_t iret = IRQ_NONE;
407 * Interrupt monitoring status
413 * 31 : Interrupt for stage 3
414 * 30 : Interrupt for stage 2
415 * 29 : Interrupt for state 1
416 * 28 : Interrupt using filter on sensor 3
418 * 27 : Interrupt using immediate on sensor 3
419 * 26 : Interrupt normal to hot on sensor 3
420 * 25 : Interrupt high offset on sensor 3
421 * 24 : Interrupt low offset on sensor 3
423 * 23 : Interrupt hot threshold on sensor 3
424 * 22 : Interrupt cold threshold on sensor 3
425 * 21 : Interrupt using filter on sensor 2
426 * 20 : Interrupt using filter on sensor 1
428 * 19 : Interrupt using filter on sensor 0
429 * 18 : Interrupt using immediate on sensor 2
430 * 17 : Interrupt using immediate on sensor 1
431 * 16 : Interrupt using immediate on sensor 0
433 * 15 : Interrupt device access timeout interrupt
434 * 14 : Interrupt normal to hot on sensor 2
435 * 13 : Interrupt high offset interrupt on sensor 2
436 * 12 : Interrupt low offset interrupt on sensor 2
438 * 11 : Interrupt hot threshold on sensor 2
439 * 10 : Interrupt cold threshold on sensor 2
440 * 9 : Interrupt normal to hot on sensor 1
441 * 8 : Interrupt high offset interrupt on sensor 1
443 * 7 : Interrupt low offset interrupt on sensor 1
444 * 6 : Interrupt hot threshold on sensor 1
445 * 5 : Interrupt cold threshold on sensor 1
446 * 4 : Interrupt normal to hot on sensor 0
448 * 3 : Interrupt high offset interrupt on sensor 0
449 * 2 : Interrupt low offset interrupt on sensor 0
450 * 1 : Interrupt hot threshold on sensor 0
451 * 0 : Interrupt cold threshold on sensor 0
453 * We are interested in the sensor(s) responsible of the
454 * interrupt event. We update the thermal framework with the
455 * thermal zone associated with the sensor. The framework will
456 * take care of the rest whatever the kind of interrupt, we
457 * are only interested in which sensor raised the interrupt.
459 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000
461 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000
463 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000
465 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111
468 value = readl(LVTS_MONINTSTS(lvts_ctrl->base));
471 * Let's figure out which sensors raised the interrupt
473 * NOTE: the masks array must be ordered with the index
474 * corresponding to the sensor id eg. index=0, mask for
477 for (i = 0; i < ARRAY_SIZE(masks); i++) {
479 if (!(value & masks[i]))
482 thermal_zone_device_update(lvts_ctrl->sensors[i].tz,
483 THERMAL_TRIP_VIOLATED);
488 * Write back to clear the interrupt status (W1C)
490 writel(value, LVTS_MONINTSTS(lvts_ctrl->base));
496 * Temperature interrupt handler. Even if the driver supports more
497 * interrupt modes, we use the interrupt when the temperature crosses
498 * the hot threshold the way up and the way down (modulo the
501 * Each thermal domain has a couple of interrupts, one for hardware
502 * reset and another one for all the thermal events happening on the
505 * The interrupt is configured for thermal events when crossing the
506 * hot temperature limit. At each interrupt, we check in every
507 * controller if there is an interrupt pending.
509 static irqreturn_t lvts_irq_handler(int irq, void *data)
511 struct lvts_domain *lvts_td = data;
512 irqreturn_t aux, iret = IRQ_NONE;
515 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
517 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]);
518 if (aux != IRQ_HANDLED)
527 static struct thermal_zone_device_ops lvts_ops = {
528 .get_temp = lvts_get_temp,
529 .set_trips = lvts_set_trips,
532 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
533 const struct lvts_ctrl_data *lvts_ctrl_data)
535 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors;
536 void __iomem *msr_regs[] = {
537 LVTS_MSR0(lvts_ctrl->base),
538 LVTS_MSR1(lvts_ctrl->base),
539 LVTS_MSR2(lvts_ctrl->base),
540 LVTS_MSR3(lvts_ctrl->base)
543 void __iomem *imm_regs[] = {
544 LVTS_IMMD0(lvts_ctrl->base),
545 LVTS_IMMD1(lvts_ctrl->base),
546 LVTS_IMMD2(lvts_ctrl->base),
547 LVTS_IMMD3(lvts_ctrl->base)
552 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) {
554 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id;
557 * At this point, we don't know which id matches which
558 * sensor. Let's set arbitrally the id from the index.
560 lvts_sensor[i].id = i;
563 * The thermal zone registration will set the trip
564 * point interrupt in the thermal controller
565 * register. But this one will be reset in the
566 * initialization after. So we need to post pone the
567 * thermal zone creation after the controller is
568 * setup. For this reason, we store the device tree
569 * node id from the data in the sensor structure
571 lvts_sensor[i].dt_id = dt_id;
574 * We assign the base address of the thermal
575 * controller as a back pointer. So it will be
576 * accessible from the different thermal framework ops
577 * as we pass the lvts_sensor pointer as thermal zone
580 lvts_sensor[i].base = lvts_ctrl->base;
583 * Each sensor has its own register address to read from.
585 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ?
586 imm_regs[i] : msr_regs[i];
588 lvts_sensor[i].low_thresh = INT_MIN;
589 lvts_sensor[i].high_thresh = INT_MIN;
592 lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor;
598 * The efuse blob values follows the sensor enumeration per thermal
599 * controller. The decoding of the stream is as follow:
601 * stream index map for MCU Domain :
603 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1----->
604 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09
606 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3----->
607 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12
609 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7----->
610 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21
612 * stream index map for AP Domain :
614 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1----->
615 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A
617 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3----->
618 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33
620 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6----->
621 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F
623 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8----->
624 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48
626 * The data description gives the offset of the calibration data in
627 * this bytes stream for each sensor.
629 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl,
630 const struct lvts_ctrl_data *lvts_ctrl_data,
631 u8 *efuse_calibration)
635 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++)
636 memcpy(&lvts_ctrl->calibration[i],
637 efuse_calibration + lvts_ctrl_data->cal_offset[i], 2);
643 * The efuse bytes stream can be split into different chunk of
644 * nvmems. This function reads and concatenate those into a single
645 * buffer so it can be read sequentially when initializing the
648 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td,
649 const struct lvts_data *lvts_data)
651 struct device_node *np = dev_of_node(dev);
652 struct nvmem_cell *cell;
653 struct property *prop;
654 const char *cell_name;
656 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) {
660 cell = of_nvmem_cell_get(np, cell_name);
662 dev_err(dev, "Failed to get cell '%s'\n", cell_name);
663 return PTR_ERR(cell);
666 efuse = nvmem_cell_read(cell, &len);
668 nvmem_cell_put(cell);
671 dev_err(dev, "Failed to read cell '%s'\n", cell_name);
672 return PTR_ERR(efuse);
675 lvts_td->calib = devm_krealloc(dev, lvts_td->calib,
676 lvts_td->calib_len + len, GFP_KERNEL);
680 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len);
682 lvts_td->calib_len += len;
690 static int lvts_golden_temp_init(struct device *dev, u32 *value)
696 if (gt && gt < LVTS_GOLDEN_TEMP_MAX)
699 coeff_b = golden_temp * 500 + LVTS_COEFF_B;
704 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td,
705 const struct lvts_data *lvts_data)
707 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl;
708 struct lvts_ctrl *lvts_ctrl;
712 * Create the calibration bytes stream from efuse data
714 ret = lvts_calibration_read(dev, lvts_td, lvts_data);
719 * The golden temp information is contained in the first chunk
722 ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib);
726 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL);
730 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) {
732 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset;
734 ret = lvts_sensor_init(dev, &lvts_ctrl[i],
735 &lvts_data->lvts_ctrl[i]);
739 ret = lvts_calibration_init(dev, &lvts_ctrl[i],
740 &lvts_data->lvts_ctrl[i],
746 * The mode the ctrl will use to read the temperature
747 * (filtered or immediate)
749 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode;
752 * The temperature to raw temperature must be done
753 * after initializing the calibration.
755 lvts_ctrl[i].hw_tshut_raw_temp =
756 lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp);
758 lvts_ctrl[i].low_thresh = INT_MIN;
759 lvts_ctrl[i].high_thresh = INT_MIN;
763 * We no longer need the efuse bytes stream, let's free it
765 devm_kfree(dev, lvts_td->calib);
767 lvts_td->lvts_ctrl = lvts_ctrl;
768 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl;
774 * At this point the configuration register is the only place in the
775 * driver where we write multiple values. Per hardware constraint,
776 * each write in the configuration register must be separated by a
779 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds)
784 * Configuration register
786 for (i = 0; i < nr_cmds; i++) {
787 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base));
792 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl)
795 * LVTS_PROTCTL : Thermal Protection Sensor Selection
799 * 19-18 : Sensor to base the protection on
801 * 00 : Average of 4 sensors
802 * 01 : Max of 4 sensors
803 * 10 : Selected sensor with bits 19-18
806 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base));
809 * LVTS_PROTTA : Stage 1 temperature threshold
810 * LVTS_PROTTB : Stage 2 temperature threshold
811 * LVTS_PROTTC : Stage 3 temperature threshold
815 * 14-0: Raw temperature threshold
817 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base));
818 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base));
820 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base));
823 * LVTS_MONINT : Interrupt configuration register
825 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS
826 * register, except we set the bits to enable the interrupt.
828 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base));
833 static int lvts_domain_reset(struct device *dev, struct reset_control *reset)
837 ret = reset_control_assert(reset);
841 return reset_control_deassert(reset);
845 * Enable or disable the clocks of a specified thermal controller
847 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable)
850 * LVTS_CLKEN : Internal LVTS clock
854 * 0 : enable / disable clock
856 writel(enable, LVTS_CLKEN(lvts_ctrl->base));
861 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl)
863 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 };
865 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
868 * LVTS_ID : Get ID and status of the thermal controller
872 * 0-5 : thermal controller id
873 * 7 : thermal controller connection is valid
875 id = readl(LVTS_ID(lvts_ctrl->base));
882 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl)
885 * Write device mask: 0xC1030000
888 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1,
889 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300,
890 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC,
891 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1
894 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds));
899 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl)
902 void __iomem *lvts_edata[] = {
903 LVTS_EDATA00(lvts_ctrl->base),
904 LVTS_EDATA01(lvts_ctrl->base),
905 LVTS_EDATA02(lvts_ctrl->base),
906 LVTS_EDATA03(lvts_ctrl->base)
910 * LVTS_EDATA0X : Efuse calibration reference value for sensor X
914 * 20-0 : Efuse value for normalization data
916 for (i = 0; i < LVTS_SENSOR_MAX; i++)
917 writel(lvts_ctrl->calibration[i], lvts_edata[i]);
922 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl)
927 * LVTS_TSSEL : Sensing point index numbering
936 value = LVTS_TSSEL_CONF;
937 writel(value, LVTS_TSSEL(lvts_ctrl->base));
940 * LVTS_CALSCALE : ADC voltage round
943 value = LVTS_CALSCALE_CONF;
946 * LVTS_MSRCTL0 : Sensor filtering strategy
951 * 001 : Avg 2 samples
952 * 010 : 4 samples, drop min and max, avg 2 samples
953 * 011 : 6 samples, drop min and max, avg 4 samples
954 * 100 : 10 samples, drop min and max, avg 8 samples
955 * 101 : 18 samples, drop min and max, avg 16 samples
959 * 0-2 : Sensor0 filter
960 * 3-5 : Sensor1 filter
961 * 6-8 : Sensor2 filter
962 * 9-11 : Sensor3 filter
964 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 |
965 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER;
966 writel(value, LVTS_MSRCTL0(lvts_ctrl->base));
969 * LVTS_MONCTL1 : Period unit and group interval configuration
971 * The clock source of LVTS thermal controller is 26MHz.
973 * The period unit is a time base for all the interval delays
974 * specified in the registers. By default we use 12. The time
975 * conversion is done by multiplying by 256 and 1/26.10^6
977 * An interval delay multiplied by the period unit gives the
978 * duration in seconds.
980 * - Filter interval delay is a delay between two samples of
983 * - Sensor interval delay is a delay between two samples of
986 * - Group interval delay is a delay between different rounds.
989 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1,
990 * and two sensors, TS1 and TS2, are in a LVTS thermal controller
992 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us
993 * Filter interval delay = 1 * Period unit = 118.149us
994 * Sensor interval delay = 2 * Period unit = 236.298us
995 * Group interval delay = 1 * Period unit = 118.149us
997 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1...
998 * <--> Filter interval delay
999 * <--> Sensor interval delay
1000 * <--> Group interval delay
1002 * 29 - 20 : Group interval
1003 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1)
1004 * or an interrupt everytime the hot threshold is crossed (0)
1005 * 9 - 0 : Period unit
1008 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT;
1009 writel(value, LVTS_MONCTL1(lvts_ctrl->base));
1012 * LVTS_MONCTL2 : Filtering and sensor interval
1016 * 25-16 : Interval unit in PERIOD_UNIT between sample on
1017 * the same sensor, filter interval
1018 * 9-0 : Interval unit in PERIOD_UNIT between each sensor
1021 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL;
1022 writel(value, LVTS_MONCTL2(lvts_ctrl->base));
1024 return lvts_irq_init(lvts_ctrl);
1027 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl)
1029 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors;
1030 struct thermal_zone_device *tz;
1034 * Bitmaps to enable each sensor on immediate and filtered modes, as
1035 * described in MSRCTL1 and MONCTL0 registers below, respectively.
1037 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) };
1038 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) };
1040 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ?
1041 sensor_imm_bitmap : sensor_filt_bitmap;
1043 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) {
1045 int dt_id = lvts_sensors[i].dt_id;
1047 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i],
1051 * This thermal zone is not described in the
1052 * device tree. It is not an error from the
1053 * thermal OF code POV, we just continue.
1055 if (PTR_ERR(tz) == -ENODEV)
1061 devm_thermal_add_hwmon_sysfs(dev, tz);
1064 * The thermal zone pointer will be needed in the
1065 * interrupt handler, we store it in the sensor
1066 * structure. The thermal domain structure will be
1067 * passed to the interrupt handler private data as the
1068 * interrupt is shared for all the controller
1069 * belonging to the thermal domain.
1071 lvts_sensors[i].tz = tz;
1074 * This sensor was correctly associated with a thermal
1075 * zone, let's set the corresponding bit in the sensor
1076 * map, so we can enable the temperature monitoring in
1077 * the hardware thermal controller.
1079 sensor_map |= sensor_bitmap[i];
1083 * The initialization of the thermal zones give us
1084 * which sensor point to enable. If any thermal zone
1085 * was not described in the device tree, it won't be
1086 * enabled here in the sensor map.
1088 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) {
1090 * LVTS_MSRCTL1 : Measurement control
1094 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3
1095 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2
1096 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1
1097 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0
1099 * That configuration will ignore the filtering and the delays
1100 * introduced in MONCTL1 and MONCTL2
1102 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base));
1106 * 9: Single point access flow
1107 * 0-3: Enable sensing point 0-3
1109 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base));
1115 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td,
1116 const struct lvts_data *lvts_data)
1118 struct lvts_ctrl *lvts_ctrl;
1121 ret = lvts_ctrl_init(dev, lvts_td, lvts_data);
1125 ret = lvts_domain_reset(dev, lvts_td->reset);
1127 dev_dbg(dev, "Failed to reset domain");
1131 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) {
1133 lvts_ctrl = &lvts_td->lvts_ctrl[i];
1136 * Initialization steps:
1138 * - Enable the clock
1139 * - Connect to the LVTS
1140 * - Initialize the LVTS
1141 * - Prepare the calibration data
1142 * - Select monitored sensors
1143 * [ Configure sampling ]
1144 * [ Configure the interrupt ]
1145 * - Start measurement
1147 ret = lvts_ctrl_set_enable(lvts_ctrl, true);
1149 dev_dbg(dev, "Failed to enable LVTS clock");
1153 ret = lvts_ctrl_connect(dev, lvts_ctrl);
1155 dev_dbg(dev, "Failed to connect to LVTS controller");
1159 ret = lvts_ctrl_initialize(dev, lvts_ctrl);
1161 dev_dbg(dev, "Failed to initialize controller");
1165 ret = lvts_ctrl_calibrate(dev, lvts_ctrl);
1167 dev_dbg(dev, "Failed to calibrate controller");
1171 ret = lvts_ctrl_configure(dev, lvts_ctrl);
1173 dev_dbg(dev, "Failed to configure controller");
1177 ret = lvts_ctrl_start(dev, lvts_ctrl);
1179 dev_dbg(dev, "Failed to start controller");
1184 return lvts_debugfs_init(dev, lvts_td);
1187 static int lvts_probe(struct platform_device *pdev)
1189 const struct lvts_data *lvts_data;
1190 struct lvts_domain *lvts_td;
1191 struct device *dev = &pdev->dev;
1192 struct resource *res;
1195 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL);
1199 lvts_data = of_device_get_match_data(dev);
1201 lvts_td->clk = devm_clk_get_enabled(dev, NULL);
1202 if (IS_ERR(lvts_td->clk))
1203 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n");
1205 res = platform_get_mem_or_io(pdev, 0);
1207 return dev_err_probe(dev, (-ENXIO), "No IO resource\n");
1209 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1210 if (IS_ERR(lvts_td->base))
1211 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n");
1213 lvts_td->reset = devm_reset_control_get_by_index(dev, 0);
1214 if (IS_ERR(lvts_td->reset))
1215 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n");
1217 irq = platform_get_irq(pdev, 0);
1221 ret = lvts_domain_init(dev, lvts_td, lvts_data);
1223 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n");
1226 * At this point the LVTS is initialized and enabled. We can
1227 * safely enable the interrupt.
1229 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler,
1230 IRQF_ONESHOT, dev_name(dev), lvts_td);
1232 return dev_err_probe(dev, ret, "Failed to request interrupt\n");
1234 platform_set_drvdata(pdev, lvts_td);
1239 static int lvts_remove(struct platform_device *pdev)
1241 struct lvts_domain *lvts_td;
1244 lvts_td = platform_get_drvdata(pdev);
1246 for (i = 0; i < lvts_td->num_lvts_ctrl; i++)
1247 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false);
1249 lvts_debugfs_exit(lvts_td);
1254 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
1256 .cal_offset = { 0x04, 0x07 },
1258 { .dt_id = MT8195_MCU_BIG_CPU0 },
1259 { .dt_id = MT8195_MCU_BIG_CPU1 }
1261 .num_lvts_sensor = 2,
1263 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1266 .cal_offset = { 0x0d, 0x10 },
1268 { .dt_id = MT8195_MCU_BIG_CPU2 },
1269 { .dt_id = MT8195_MCU_BIG_CPU3 }
1271 .num_lvts_sensor = 2,
1273 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1276 .cal_offset = { 0x16, 0x19, 0x1c, 0x1f },
1278 { .dt_id = MT8195_MCU_LITTLE_CPU0 },
1279 { .dt_id = MT8195_MCU_LITTLE_CPU1 },
1280 { .dt_id = MT8195_MCU_LITTLE_CPU2 },
1281 { .dt_id = MT8195_MCU_LITTLE_CPU3 }
1283 .num_lvts_sensor = 4,
1285 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1289 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = {
1291 .cal_offset = { 0x25, 0x28 },
1293 { .dt_id = MT8195_AP_VPU0 },
1294 { .dt_id = MT8195_AP_VPU1 }
1296 .num_lvts_sensor = 2,
1298 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1301 .cal_offset = { 0x2e, 0x31 },
1303 { .dt_id = MT8195_AP_GPU0 },
1304 { .dt_id = MT8195_AP_GPU1 }
1306 .num_lvts_sensor = 2,
1308 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1311 .cal_offset = { 0x37, 0x3a, 0x3d },
1313 { .dt_id = MT8195_AP_VDEC },
1314 { .dt_id = MT8195_AP_IMG },
1315 { .dt_id = MT8195_AP_INFRA },
1317 .num_lvts_sensor = 3,
1319 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1322 .cal_offset = { 0x43, 0x46 },
1324 { .dt_id = MT8195_AP_CAM0 },
1325 { .dt_id = MT8195_AP_CAM1 }
1327 .num_lvts_sensor = 2,
1329 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195,
1333 static const struct lvts_data mt8195_lvts_mcu_data = {
1334 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
1335 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
1338 static const struct lvts_data mt8195_lvts_ap_data = {
1339 .lvts_ctrl = mt8195_lvts_ap_data_ctrl,
1340 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl),
1343 static const struct of_device_id lvts_of_match[] = {
1344 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
1345 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
1348 MODULE_DEVICE_TABLE(of, lvts_of_match);
1350 static struct platform_driver lvts_driver = {
1351 .probe = lvts_probe,
1352 .remove = lvts_remove,
1354 .name = "mtk-lvts-thermal",
1355 .of_match_table = lvts_of_match,
1358 module_platform_driver(lvts_driver);
1360 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>");
1361 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver");
1362 MODULE_LICENSE("GPL");