1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015 MediaTek Inc.
4 * Author: Hanyi Wu <hanyi.wu@mediatek.com>
5 * Sascha Hauer <s.hauer@pengutronix.de>
6 * Dawei Chien <dawei.chien@mediatek.com>
7 * Louis Yu <louis.yu@mediatek.com>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/nvmem-consumer.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
22 #include <linux/thermal.h>
23 #include <linux/reset.h>
24 #include <linux/types.h>
26 #include "../thermal_hwmon.h"
28 /* AUXADC Registers */
29 #define AUXADC_CON1_SET_V 0x008
30 #define AUXADC_CON1_CLR_V 0x00c
31 #define AUXADC_CON2_V 0x010
32 #define AUXADC_DATA(channel) (0x14 + (channel) * 4)
34 #define APMIXED_SYS_TS_CON0 0x600
35 #define APMIXED_SYS_TS_CON1 0x604
37 /* Thermal Controller Registers */
38 #define TEMP_MONCTL0 0x000
39 #define TEMP_MONCTL1 0x004
40 #define TEMP_MONCTL2 0x008
41 #define TEMP_MONIDET0 0x014
42 #define TEMP_MONIDET1 0x018
43 #define TEMP_MSRCTL0 0x038
44 #define TEMP_MSRCTL1 0x03c
45 #define TEMP_AHBPOLL 0x040
46 #define TEMP_AHBTO 0x044
47 #define TEMP_ADCPNP0 0x048
48 #define TEMP_ADCPNP1 0x04c
49 #define TEMP_ADCPNP2 0x050
50 #define TEMP_ADCPNP3 0x0b4
52 #define TEMP_ADCMUX 0x054
53 #define TEMP_ADCEN 0x060
54 #define TEMP_PNPMUXADDR 0x064
55 #define TEMP_ADCMUXADDR 0x068
56 #define TEMP_ADCENADDR 0x074
57 #define TEMP_ADCVALIDADDR 0x078
58 #define TEMP_ADCVOLTADDR 0x07c
59 #define TEMP_RDCTRL 0x080
60 #define TEMP_ADCVALIDMASK 0x084
61 #define TEMP_ADCVOLTAGESHIFT 0x088
62 #define TEMP_ADCWRITECTRL 0x08c
63 #define TEMP_MSR0 0x090
64 #define TEMP_MSR1 0x094
65 #define TEMP_MSR2 0x098
66 #define TEMP_MSR3 0x0B8
68 #define TEMP_SPARE0 0x0f0
70 #define TEMP_ADCPNP0_1 0x148
71 #define TEMP_ADCPNP1_1 0x14c
72 #define TEMP_ADCPNP2_1 0x150
73 #define TEMP_MSR0_1 0x190
74 #define TEMP_MSR1_1 0x194
75 #define TEMP_MSR2_1 0x198
76 #define TEMP_ADCPNP3_1 0x1b4
77 #define TEMP_MSR3_1 0x1B8
79 #define PTPCORESEL 0x400
81 #define TEMP_MONCTL1_PERIOD_UNIT(x) ((x) & 0x3ff)
83 #define TEMP_MONCTL2_FILTER_INTERVAL(x) (((x) & 0x3ff) << 16)
84 #define TEMP_MONCTL2_SENSOR_INTERVAL(x) ((x) & 0x3ff)
86 #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x) (x)
88 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE BIT(0)
89 #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE BIT(1)
91 #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5)
92 #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit)
94 /* MT8173 thermal sensors */
99 #define MT8173_TSABB 4
101 /* AUXADC channel 11 is used for the temperature sensors */
102 #define MT8173_TEMP_AUXADC_CHANNEL 11
104 /* The total number of temperature sensors in the MT8173 */
105 #define MT8173_NUM_SENSORS 5
107 /* The number of banks in the MT8173 */
108 #define MT8173_NUM_ZONES 4
110 /* The number of sensing points per bank */
111 #define MT8173_NUM_SENSORS_PER_ZONE 4
113 /* The number of controller in the MT8173 */
114 #define MT8173_NUM_CONTROLLER 1
116 /* The calibration coefficient of sensor */
117 #define MT8173_CALIBRATION 165
120 * Layout of the fuses providing the calibration data
121 * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
122 * MT8183 has 6 sensors and needs 6 VTS calibration data.
123 * MT8173 has 5 sensors and needs 5 VTS calibration data.
124 * MT2701 has 3 sensors and needs 3 VTS calibration data.
125 * MT2712 has 4 sensors and needs 4 VTS calibration data.
127 #define CALIB_BUF0_VALID_V1 BIT(0)
128 #define CALIB_BUF1_ADC_GE_V1(x) (((x) >> 22) & 0x3ff)
129 #define CALIB_BUF0_VTS_TS1_V1(x) (((x) >> 17) & 0x1ff)
130 #define CALIB_BUF0_VTS_TS2_V1(x) (((x) >> 8) & 0x1ff)
131 #define CALIB_BUF1_VTS_TS3_V1(x) (((x) >> 0) & 0x1ff)
132 #define CALIB_BUF2_VTS_TS4_V1(x) (((x) >> 23) & 0x1ff)
133 #define CALIB_BUF2_VTS_TS5_V1(x) (((x) >> 5) & 0x1ff)
134 #define CALIB_BUF2_VTS_TSABB_V1(x) (((x) >> 14) & 0x1ff)
135 #define CALIB_BUF0_DEGC_CALI_V1(x) (((x) >> 1) & 0x3f)
136 #define CALIB_BUF0_O_SLOPE_V1(x) (((x) >> 26) & 0x3f)
137 #define CALIB_BUF0_O_SLOPE_SIGN_V1(x) (((x) >> 7) & 0x1)
138 #define CALIB_BUF1_ID_V1(x) (((x) >> 9) & 0x1)
141 * Layout of the fuses providing the calibration data
142 * These macros could be used for MT7622.
144 #define CALIB_BUF0_ADC_OE_V2(x) (((x) >> 22) & 0x3ff)
145 #define CALIB_BUF0_ADC_GE_V2(x) (((x) >> 12) & 0x3ff)
146 #define CALIB_BUF0_DEGC_CALI_V2(x) (((x) >> 6) & 0x3f)
147 #define CALIB_BUF0_O_SLOPE_V2(x) (((x) >> 0) & 0x3f)
148 #define CALIB_BUF1_VTS_TS1_V2(x) (((x) >> 23) & 0x1ff)
149 #define CALIB_BUF1_VTS_TS2_V2(x) (((x) >> 14) & 0x1ff)
150 #define CALIB_BUF1_VTS_TSABB_V2(x) (((x) >> 5) & 0x1ff)
151 #define CALIB_BUF1_VALID_V2(x) (((x) >> 4) & 0x1)
152 #define CALIB_BUF1_O_SLOPE_SIGN_V2(x) (((x) >> 3) & 0x1)
155 * Layout of the fuses providing the calibration data
156 * These macros can be used for MT7981 and MT7986.
158 #define CALIB_BUF0_ADC_GE_V3(x) (((x) >> 0) & 0x3ff)
159 #define CALIB_BUF0_DEGC_CALI_V3(x) (((x) >> 20) & 0x3f)
160 #define CALIB_BUF0_O_SLOPE_V3(x) (((x) >> 26) & 0x3f)
161 #define CALIB_BUF1_VTS_TS1_V3(x) (((x) >> 0) & 0x1ff)
162 #define CALIB_BUF1_VTS_TS2_V3(x) (((x) >> 21) & 0x1ff)
163 #define CALIB_BUF1_VTS_TSABB_V3(x) (((x) >> 9) & 0x1ff)
164 #define CALIB_BUF1_VALID_V3(x) (((x) >> 18) & 0x1)
165 #define CALIB_BUF1_O_SLOPE_SIGN_V3(x) (((x) >> 19) & 0x1)
166 #define CALIB_BUF1_ID_V3(x) (((x) >> 20) & 0x1)
178 enum mtk_thermal_version {
184 /* MT2701 thermal sensors */
187 #define MT2701_TSABB 2
189 /* AUXADC channel 11 is used for the temperature sensors */
190 #define MT2701_TEMP_AUXADC_CHANNEL 11
192 /* The total number of temperature sensors in the MT2701 */
193 #define MT2701_NUM_SENSORS 3
195 /* The number of sensing points per bank */
196 #define MT2701_NUM_SENSORS_PER_ZONE 3
198 /* The number of controller in the MT2701 */
199 #define MT2701_NUM_CONTROLLER 1
201 /* The calibration coefficient of sensor */
202 #define MT2701_CALIBRATION 165
204 /* MT2712 thermal sensors */
210 /* AUXADC channel 11 is used for the temperature sensors */
211 #define MT2712_TEMP_AUXADC_CHANNEL 11
213 /* The total number of temperature sensors in the MT2712 */
214 #define MT2712_NUM_SENSORS 4
216 /* The number of sensing points per bank */
217 #define MT2712_NUM_SENSORS_PER_ZONE 4
219 /* The number of controller in the MT2712 */
220 #define MT2712_NUM_CONTROLLER 1
222 /* The calibration coefficient of sensor */
223 #define MT2712_CALIBRATION 165
225 #define MT7622_TEMP_AUXADC_CHANNEL 11
226 #define MT7622_NUM_SENSORS 1
227 #define MT7622_NUM_ZONES 1
228 #define MT7622_NUM_SENSORS_PER_ZONE 1
230 #define MT7622_NUM_CONTROLLER 1
232 /* The maximum number of banks */
233 #define MAX_NUM_ZONES 8
235 /* The calibration coefficient of sensor */
236 #define MT7622_CALIBRATION 165
238 /* MT8183 thermal sensors */
244 #define MT8183_TSABB 5
246 /* AUXADC channel is used for the temperature sensors */
247 #define MT8183_TEMP_AUXADC_CHANNEL 11
249 /* The total number of temperature sensors in the MT8183 */
250 #define MT8183_NUM_SENSORS 6
252 /* The number of banks in the MT8183 */
253 #define MT8183_NUM_ZONES 1
255 /* The number of sensing points per bank */
256 #define MT8183_NUM_SENSORS_PER_ZONE 6
258 /* The number of controller in the MT8183 */
259 #define MT8183_NUM_CONTROLLER 2
261 /* The calibration coefficient of sensor */
262 #define MT8183_CALIBRATION 153
264 /* AUXADC channel 11 is used for the temperature sensors */
265 #define MT7986_TEMP_AUXADC_CHANNEL 11
267 /* The total number of temperature sensors in the MT7986 */
268 #define MT7986_NUM_SENSORS 1
270 /* The number of banks in the MT7986 */
271 #define MT7986_NUM_ZONES 1
273 /* The number of sensing points per bank */
274 #define MT7986_NUM_SENSORS_PER_ZONE 1
276 /* MT7986 thermal sensors */
279 /* The number of controller in the MT7986 */
280 #define MT7986_NUM_CONTROLLER 1
282 /* The calibration coefficient of sensor */
283 #define MT7986_CALIBRATION 165
286 #define MT8365_TEMP_AUXADC_CHANNEL 11
287 #define MT8365_CALIBRATION 164
288 #define MT8365_NUM_CONTROLLER 1
289 #define MT8365_NUM_BANKS 1
290 #define MT8365_NUM_SENSORS 3
291 #define MT8365_NUM_SENSORS_PER_ZONE 3
298 struct thermal_bank_cfg {
299 unsigned int num_sensors;
303 struct mtk_thermal_bank {
304 struct mtk_thermal *mt;
308 struct mtk_thermal_data {
312 const int *vts_index;
313 const int *sensor_mux_values;
317 const int num_controller;
318 const int *controller_offset;
319 bool need_switch_bank;
320 struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
321 enum mtk_thermal_version version;
322 u32 apmixed_buffer_ctl_reg;
323 u32 apmixed_buffer_ctl_mask;
324 u32 apmixed_buffer_ctl_set;
329 void __iomem *thermal_base;
331 struct clk *clk_peri_therm;
332 struct clk *clk_auxadc;
333 /* lock: for getting and putting banks */
336 /* Calibration values */
342 s32 vts[MAX_NUM_VTS];
344 const struct mtk_thermal_data *conf;
345 struct mtk_thermal_bank banks[MAX_NUM_ZONES];
347 int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
350 /* MT8183 thermal sensor data */
351 static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
352 MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
355 static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
356 TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
359 static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
360 TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
361 TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
364 static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
365 static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
367 static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
368 VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
371 /* MT8173 thermal sensor data */
372 static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
373 { MT8173_TS2, MT8173_TS3 },
374 { MT8173_TS2, MT8173_TS4 },
375 { MT8173_TS1, MT8173_TS2, MT8173_TSABB },
379 static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
380 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
383 static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
384 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
387 static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
388 static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
390 static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
391 VTS1, VTS2, VTS3, VTS4, VTSABB
394 /* MT2701 thermal sensor data */
395 static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
396 MT2701_TS1, MT2701_TS2, MT2701_TSABB
399 static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
400 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
403 static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
404 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
407 static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
408 static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
410 static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
414 /* MT2712 thermal sensor data */
415 static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
416 MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
419 static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
420 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
423 static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
424 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
427 static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
428 static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
430 static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
431 VTS1, VTS2, VTS3, VTS4
434 /* MT7622 thermal sensor data */
435 static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
436 static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
437 static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
438 static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
439 static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
440 static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
442 /* MT7986 thermal sensor data */
443 static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
444 static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
445 static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
446 static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
447 static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
448 static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
450 /* MT8365 thermal sensor data */
451 static const int mt8365_bank_data[MT8365_NUM_SENSORS] = {
452 MT8365_TS1, MT8365_TS2, MT8365_TS3
455 static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = {
456 TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
459 static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = {
460 TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
463 static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 };
464 static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 };
466 static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 };
469 * The MT8173 thermal controller has four banks. Each bank can read up to
470 * four temperature sensors simultaneously. The MT8173 has a total of 5
471 * temperature sensors. We use each bank to measure a certain area of the
472 * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
473 * areas, hence is used in different banks.
475 * The thermal core only gets the maximum temperature of all banks, so
476 * the bank concept wouldn't be necessary here. However, the SVS (Smart
477 * Voltage Scaling) unit makes its decisions based on the same bank
478 * data, and this indeed needs the temperatures of the individual banks
479 * for making better decisions.
481 static const struct mtk_thermal_data mt8173_thermal_data = {
482 .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
483 .num_banks = MT8173_NUM_ZONES,
484 .num_sensors = MT8173_NUM_SENSORS,
485 .vts_index = mt8173_vts_index,
486 .cali_val = MT8173_CALIBRATION,
487 .num_controller = MT8173_NUM_CONTROLLER,
488 .controller_offset = mt8173_tc_offset,
489 .need_switch_bank = true,
493 .sensors = mt8173_bank_data[0],
496 .sensors = mt8173_bank_data[1],
499 .sensors = mt8173_bank_data[2],
502 .sensors = mt8173_bank_data[3],
506 .adcpnp = mt8173_adcpnp,
507 .sensor_mux_values = mt8173_mux_values,
508 .version = MTK_THERMAL_V1,
512 * The MT2701 thermal controller has one bank, which can read up to
513 * three temperature sensors simultaneously. The MT2701 has a total of 3
514 * temperature sensors.
516 * The thermal core only gets the maximum temperature of this one bank,
517 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
518 * Voltage Scaling) unit makes its decisions based on the same bank
521 static const struct mtk_thermal_data mt2701_thermal_data = {
522 .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
524 .num_sensors = MT2701_NUM_SENSORS,
525 .vts_index = mt2701_vts_index,
526 .cali_val = MT2701_CALIBRATION,
527 .num_controller = MT2701_NUM_CONTROLLER,
528 .controller_offset = mt2701_tc_offset,
529 .need_switch_bank = true,
533 .sensors = mt2701_bank_data,
537 .adcpnp = mt2701_adcpnp,
538 .sensor_mux_values = mt2701_mux_values,
539 .version = MTK_THERMAL_V1,
543 * The MT8365 thermal controller has one bank, which can read up to
544 * four temperature sensors simultaneously. The MT8365 has a total of 3
545 * temperature sensors.
547 * The thermal core only gets the maximum temperature of this one bank,
548 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
549 * Voltage Scaling) unit makes its decisions based on the same bank
552 static const struct mtk_thermal_data mt8365_thermal_data = {
553 .auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL,
554 .num_banks = MT8365_NUM_BANKS,
555 .num_sensors = MT8365_NUM_SENSORS,
556 .vts_index = mt8365_vts_index,
557 .cali_val = MT8365_CALIBRATION,
558 .num_controller = MT8365_NUM_CONTROLLER,
559 .controller_offset = mt8365_tc_offset,
560 .need_switch_bank = false,
563 .num_sensors = MT8365_NUM_SENSORS,
564 .sensors = mt8365_bank_data
568 .adcpnp = mt8365_adcpnp,
569 .sensor_mux_values = mt8365_mux_values,
570 .version = MTK_THERMAL_V1,
571 .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0,
572 .apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28),
573 .apmixed_buffer_ctl_set = 0,
577 * The MT2712 thermal controller has one bank, which can read up to
578 * four temperature sensors simultaneously. The MT2712 has a total of 4
579 * temperature sensors.
581 * The thermal core only gets the maximum temperature of this one bank,
582 * so the bank concept wouldn't be necessary here. However, the SVS (Smart
583 * Voltage Scaling) unit makes its decisions based on the same bank
586 static const struct mtk_thermal_data mt2712_thermal_data = {
587 .auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
589 .num_sensors = MT2712_NUM_SENSORS,
590 .vts_index = mt2712_vts_index,
591 .cali_val = MT2712_CALIBRATION,
592 .num_controller = MT2712_NUM_CONTROLLER,
593 .controller_offset = mt2712_tc_offset,
594 .need_switch_bank = true,
598 .sensors = mt2712_bank_data,
602 .adcpnp = mt2712_adcpnp,
603 .sensor_mux_values = mt2712_mux_values,
604 .version = MTK_THERMAL_V1,
608 * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
611 static const struct mtk_thermal_data mt7622_thermal_data = {
612 .auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
613 .num_banks = MT7622_NUM_ZONES,
614 .num_sensors = MT7622_NUM_SENSORS,
615 .vts_index = mt7622_vts_index,
616 .cali_val = MT7622_CALIBRATION,
617 .num_controller = MT7622_NUM_CONTROLLER,
618 .controller_offset = mt7622_tc_offset,
619 .need_switch_bank = true,
623 .sensors = mt7622_bank_data,
627 .adcpnp = mt7622_adcpnp,
628 .sensor_mux_values = mt7622_mux_values,
629 .version = MTK_THERMAL_V2,
630 .apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1,
631 .apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),
632 .apmixed_buffer_ctl_set = BIT(0),
636 * The MT8183 thermal controller has one bank for the current SW framework.
637 * The MT8183 has a total of 6 temperature sensors.
638 * There are two thermal controller to control the six sensor.
639 * The first one bind 2 sensor, and the other bind 4 sensors.
640 * The thermal core only gets the maximum temperature of all sensor, so
641 * the bank concept wouldn't be necessary here. However, the SVS (Smart
642 * Voltage Scaling) unit makes its decisions based on the same bank
643 * data, and this indeed needs the temperatures of the individual banks
644 * for making better decisions.
646 static const struct mtk_thermal_data mt8183_thermal_data = {
647 .auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
648 .num_banks = MT8183_NUM_ZONES,
649 .num_sensors = MT8183_NUM_SENSORS,
650 .vts_index = mt8183_vts_index,
651 .cali_val = MT8183_CALIBRATION,
652 .num_controller = MT8183_NUM_CONTROLLER,
653 .controller_offset = mt8183_tc_offset,
654 .need_switch_bank = false,
658 .sensors = mt8183_bank_data,
663 .adcpnp = mt8183_adcpnp,
664 .sensor_mux_values = mt8183_mux_values,
665 .version = MTK_THERMAL_V1,
669 * MT7986 uses AUXADC Channel 11 for raw data access.
671 static const struct mtk_thermal_data mt7986_thermal_data = {
672 .auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
673 .num_banks = MT7986_NUM_ZONES,
674 .num_sensors = MT7986_NUM_SENSORS,
675 .vts_index = mt7986_vts_index,
676 .cali_val = MT7986_CALIBRATION,
677 .num_controller = MT7986_NUM_CONTROLLER,
678 .controller_offset = mt7986_tc_offset,
679 .need_switch_bank = true,
683 .sensors = mt7986_bank_data,
687 .adcpnp = mt7986_adcpnp,
688 .sensor_mux_values = mt7986_mux_values,
689 .version = MTK_THERMAL_V3,
693 * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
694 * @mt: The thermal controller
695 * @sensno: sensor number
696 * @raw: raw ADC value
698 * This converts the raw ADC value to mcelsius using the SoC specific
699 * calibration constants
701 static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
707 tmp = 203450520 << 3;
708 tmp /= mt->conf->cali_val + mt->o_slope;
709 tmp /= 10000 + mt->adc_ge;
710 tmp *= raw - mt->vts[sensno] - 3350;
713 return mt->degc_cali * 500 - tmp;
716 static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
729 g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
730 g_oe = mt->adc_oe - 512;
731 format_1 = mt->vts[VTS2] + 3105 - g_oe;
732 format_2 = (mt->degc_cali * 10) >> 1;
733 g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
735 tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
736 tmp = tmp * 10 * 100 / 11;
738 if (mt->o_slope_sign == 0)
739 tmp = tmp / (165 - mt->o_slope);
741 tmp = tmp / (165 + mt->o_slope);
743 return (format_2 - tmp) * 100;
746 static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
754 tmp = 100000 * 15 / 16 * 10000;
755 tmp /= 4096 - 512 + mt->adc_ge;
757 tmp *= raw - mt->vts[sensno] - 2900;
759 return mt->degc_cali * 500 - tmp;
763 * mtk_thermal_get_bank - get bank
766 * The bank registers are banked, we have to select a bank in the
767 * PTPCORESEL register to access it.
769 static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
771 struct mtk_thermal *mt = bank->mt;
774 if (mt->conf->need_switch_bank) {
775 mutex_lock(&mt->lock);
777 val = readl(mt->thermal_base + PTPCORESEL);
780 writel(val, mt->thermal_base + PTPCORESEL);
785 * mtk_thermal_put_bank - release bank
788 * release a bank previously taken with mtk_thermal_get_bank,
790 static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
792 struct mtk_thermal *mt = bank->mt;
794 if (mt->conf->need_switch_bank)
795 mutex_unlock(&mt->lock);
799 * mtk_thermal_bank_temperature - get the temperature of a bank
802 * The temperature of a bank is considered the maximum temperature of
803 * the sensors associated to the bank.
805 static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
807 struct mtk_thermal *mt = bank->mt;
808 const struct mtk_thermal_data *conf = mt->conf;
809 int i, temp = INT_MIN, max = INT_MIN;
812 for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
813 raw = readl(mt->thermal_base + conf->msr[i]);
815 temp = mt->raw_to_mcelsius(
816 mt, conf->bank_data[bank->id].sensors[i], raw);
820 * The first read of a sensor often contains very high bogus
821 * temperature value. Filter these out so that the system does
822 * not immediately shut down.
834 static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
836 struct mtk_thermal *mt = thermal_zone_device_priv(tz);
838 int tempmax = INT_MIN;
840 for (i = 0; i < mt->conf->num_banks; i++) {
841 struct mtk_thermal_bank *bank = &mt->banks[i];
843 mtk_thermal_get_bank(bank);
845 tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
847 mtk_thermal_put_bank(bank);
850 *temperature = tempmax;
855 static const struct thermal_zone_device_ops mtk_thermal_ops = {
856 .get_temp = mtk_read_temp,
859 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
860 u32 apmixed_phys_base, u32 auxadc_phys_base,
863 struct mtk_thermal_bank *bank = &mt->banks[num];
864 const struct mtk_thermal_data *conf = mt->conf;
867 int offset = mt->conf->controller_offset[ctrl_id];
868 void __iomem *controller_base = mt->thermal_base + offset;
873 mtk_thermal_get_bank(bank);
875 /* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
876 writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
879 * filt interval is 1 * 46.540us = 46.54us,
880 * sen interval is 429 * 46.540us = 19.96ms
882 writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
883 TEMP_MONCTL2_SENSOR_INTERVAL(429),
884 controller_base + TEMP_MONCTL2);
886 /* poll is set to 10u */
887 writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
888 controller_base + TEMP_AHBPOLL);
890 /* temperature sampling control, 1 sample */
891 writel(0x0, controller_base + TEMP_MSRCTL0);
893 /* exceed this polling time, IRQ would be inserted */
894 writel(0xffffffff, controller_base + TEMP_AHBTO);
896 /* number of interrupts per event, 1 is enough */
897 writel(0x0, controller_base + TEMP_MONIDET0);
898 writel(0x0, controller_base + TEMP_MONIDET1);
901 * The MT8173 thermal controller does not have its own ADC. Instead it
902 * uses AHB bus accesses to control the AUXADC. To do this the thermal
903 * controller has to be programmed with the physical addresses of the
904 * AUXADC registers and with the various bit positions in the AUXADC.
905 * Also the thermal controller controls a mux in the APMIXEDSYS register
910 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
911 * automatically by hw
913 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
915 /* AHB address for auxadc mux selection */
916 writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
917 controller_base + TEMP_ADCMUXADDR);
919 if (mt->conf->version == MTK_THERMAL_V1) {
920 /* AHB address for pnp sensor mux selection */
921 writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
922 controller_base + TEMP_PNPMUXADDR);
925 /* AHB value for auxadc enable */
926 writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
928 /* AHB address for auxadc enable (channel 0 immediate mode selected) */
929 writel(auxadc_phys_base + AUXADC_CON1_SET_V,
930 controller_base + TEMP_ADCENADDR);
932 /* AHB address for auxadc valid bit */
933 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
934 controller_base + TEMP_ADCVALIDADDR);
936 /* AHB address for auxadc voltage output */
937 writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
938 controller_base + TEMP_ADCVOLTADDR);
940 /* read valid & voltage are at the same register */
941 writel(0x0, controller_base + TEMP_RDCTRL);
943 /* indicate where the valid bit is */
944 writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
945 controller_base + TEMP_ADCVALIDMASK);
948 writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
950 /* enable auxadc mux write transaction */
951 writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
952 controller_base + TEMP_ADCWRITECTRL);
954 for (i = 0; i < conf->bank_data[num].num_sensors; i++)
955 writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
956 mt->thermal_base + conf->adcpnp[i]);
958 writel((1 << conf->bank_data[num].num_sensors) - 1,
959 controller_base + TEMP_MONCTL0);
961 writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
962 TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
963 controller_base + TEMP_ADCWRITECTRL);
965 mtk_thermal_put_bank(bank);
968 static u64 of_get_phys_base(struct device_node *np)
971 const __be32 *regaddr_p;
973 regaddr_p = of_get_address(np, 0, &size64, NULL);
977 return of_translate_address(np, regaddr_p);
980 static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
984 if (!(buf[0] & CALIB_BUF0_VALID_V1))
987 mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
989 for (i = 0; i < mt->conf->num_sensors; i++) {
990 switch (mt->conf->vts_index[i]) {
992 mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
995 mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
998 mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
1001 mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
1004 mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
1008 CALIB_BUF2_VTS_TSABB_V1(buf[2]);
1015 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
1016 if (CALIB_BUF1_ID_V1(buf[1]) &
1017 CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
1018 mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
1020 mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
1025 static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
1027 if (!CALIB_BUF1_VALID_V2(buf[1]))
1030 mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
1031 mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
1032 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
1033 mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
1034 mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
1035 mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
1036 mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
1037 mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
1042 static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
1044 if (!CALIB_BUF1_VALID_V3(buf[1]))
1047 mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
1048 mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
1049 mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
1050 mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
1051 mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
1052 mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
1053 mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
1055 if (CALIB_BUF1_ID_V3(buf[1]) == 0)
1061 static int mtk_thermal_get_calibration_data(struct device *dev,
1062 struct mtk_thermal *mt)
1064 struct nvmem_cell *cell;
1069 /* Start with default values */
1072 for (i = 0; i < mt->conf->num_sensors; i++)
1077 cell = nvmem_cell_get(dev, "calibration-data");
1079 if (PTR_ERR(cell) == -EPROBE_DEFER)
1080 return PTR_ERR(cell);
1084 buf = (u32 *)nvmem_cell_read(cell, &len);
1086 nvmem_cell_put(cell);
1089 return PTR_ERR(buf);
1091 if (len < 3 * sizeof(u32)) {
1092 dev_warn(dev, "invalid calibration data\n");
1097 switch (mt->conf->version) {
1098 case MTK_THERMAL_V1:
1099 ret = mtk_thermal_extract_efuse_v1(mt, buf);
1101 case MTK_THERMAL_V2:
1102 ret = mtk_thermal_extract_efuse_v2(mt, buf);
1104 case MTK_THERMAL_V3:
1105 ret = mtk_thermal_extract_efuse_v3(mt, buf);
1113 dev_info(dev, "Device not calibrated, using default calibration values\n");
1123 static const struct of_device_id mtk_thermal_of_match[] = {
1125 .compatible = "mediatek,mt8173-thermal",
1126 .data = (void *)&mt8173_thermal_data,
1129 .compatible = "mediatek,mt2701-thermal",
1130 .data = (void *)&mt2701_thermal_data,
1133 .compatible = "mediatek,mt2712-thermal",
1134 .data = (void *)&mt2712_thermal_data,
1137 .compatible = "mediatek,mt7622-thermal",
1138 .data = (void *)&mt7622_thermal_data,
1141 .compatible = "mediatek,mt7986-thermal",
1142 .data = (void *)&mt7986_thermal_data,
1145 .compatible = "mediatek,mt8183-thermal",
1146 .data = (void *)&mt8183_thermal_data,
1149 .compatible = "mediatek,mt8365-thermal",
1150 .data = (void *)&mt8365_thermal_data,
1154 MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
1156 static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt,
1157 void __iomem *apmixed_base)
1161 if (!mt->conf->apmixed_buffer_ctl_reg)
1164 tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
1165 tmp &= mt->conf->apmixed_buffer_ctl_mask;
1166 tmp |= mt->conf->apmixed_buffer_ctl_set;
1167 writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
1171 static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
1172 void __iomem *auxadc_base)
1176 writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
1177 writel(0x1, mt->thermal_base + TEMP_MONCTL0);
1178 tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
1179 writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
1182 static int mtk_thermal_probe(struct platform_device *pdev)
1184 int ret, i, ctrl_id;
1185 struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
1186 struct mtk_thermal *mt;
1187 u64 auxadc_phys_base, apmixed_phys_base;
1188 struct thermal_zone_device *tzdev;
1189 void __iomem *apmixed_base, *auxadc_base;
1191 mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
1195 mt->conf = of_device_get_match_data(&pdev->dev);
1197 mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm");
1198 if (IS_ERR(mt->clk_peri_therm))
1199 return PTR_ERR(mt->clk_peri_therm);
1201 mt->clk_auxadc = devm_clk_get(&pdev->dev, "auxadc");
1202 if (IS_ERR(mt->clk_auxadc))
1203 return PTR_ERR(mt->clk_auxadc);
1205 mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1206 if (IS_ERR(mt->thermal_base))
1207 return PTR_ERR(mt->thermal_base);
1209 ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
1213 mutex_init(&mt->lock);
1215 mt->dev = &pdev->dev;
1217 auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
1219 dev_err(&pdev->dev, "missing auxadc node\n");
1223 auxadc_base = of_iomap(auxadc, 0);
1224 auxadc_phys_base = of_get_phys_base(auxadc);
1226 of_node_put(auxadc);
1228 if (auxadc_phys_base == OF_BAD_ADDR) {
1229 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1233 apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
1235 dev_err(&pdev->dev, "missing apmixedsys node\n");
1239 apmixed_base = of_iomap(apmixedsys, 0);
1240 apmixed_phys_base = of_get_phys_base(apmixedsys);
1242 of_node_put(apmixedsys);
1244 if (apmixed_phys_base == OF_BAD_ADDR) {
1245 dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1249 ret = device_reset_optional(&pdev->dev);
1253 ret = clk_prepare_enable(mt->clk_auxadc);
1255 dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
1259 ret = clk_prepare_enable(mt->clk_peri_therm);
1261 dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
1262 goto err_disable_clk_auxadc;
1265 mtk_thermal_turn_on_buffer(mt, apmixed_base);
1267 if (mt->conf->version != MTK_THERMAL_V2)
1268 mtk_thermal_release_periodic_ts(mt, auxadc_base);
1270 if (mt->conf->version == MTK_THERMAL_V1)
1271 mt->raw_to_mcelsius = raw_to_mcelsius_v1;
1272 else if (mt->conf->version == MTK_THERMAL_V2)
1273 mt->raw_to_mcelsius = raw_to_mcelsius_v2;
1275 mt->raw_to_mcelsius = raw_to_mcelsius_v3;
1277 for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
1278 for (i = 0; i < mt->conf->num_banks; i++)
1279 mtk_thermal_init_bank(mt, i, apmixed_phys_base,
1280 auxadc_phys_base, ctrl_id);
1282 platform_set_drvdata(pdev, mt);
1284 tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
1286 if (IS_ERR(tzdev)) {
1287 ret = PTR_ERR(tzdev);
1288 goto err_disable_clk_peri_therm;
1291 ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev);
1293 dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
1297 err_disable_clk_peri_therm:
1298 clk_disable_unprepare(mt->clk_peri_therm);
1299 err_disable_clk_auxadc:
1300 clk_disable_unprepare(mt->clk_auxadc);
1305 static int mtk_thermal_remove(struct platform_device *pdev)
1307 struct mtk_thermal *mt = platform_get_drvdata(pdev);
1309 clk_disable_unprepare(mt->clk_peri_therm);
1310 clk_disable_unprepare(mt->clk_auxadc);
1315 static struct platform_driver mtk_thermal_driver = {
1316 .probe = mtk_thermal_probe,
1317 .remove = mtk_thermal_remove,
1319 .name = "mtk-thermal",
1320 .of_match_table = mtk_thermal_of_match,
1324 module_platform_driver(mtk_thermal_driver);
1326 MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
1327 MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
1328 MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
1329 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1330 MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
1331 MODULE_DESCRIPTION("Mediatek thermal driver");
1332 MODULE_LICENSE("GPL v2");