2 * Copyright (c) 2004 Picture Elements, Inc.
3 * Stephen Williams (XXXXXXXXXXXXXXXX)
5 * This source code is free software; you can redistribute it
6 * and/or modify it in source code form under the terms of the GNU
7 * General Public License as published by the Free Software
8 * Foundation; either version 2 of the License, or (at your option)
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
22 * The Xilinx SystemACE chip support is activated by defining
23 * CONFIG_SYSTEMACE to turn on support, and CFG_SYSTEMACE_BASE
24 * to set the base address of the device. This code currently
25 * assumes that the chip is connected via a byte-wide bus.
27 * The CONFIG_SYSTEMACE also adds to fat support the device class
28 * "ace" that allows the user to execute "fatls ace 0" and the
29 * like. This works by making the systemace_get_dev function
30 * available to cmd_fat.c:get_dev and filling in a block device
31 * description that has all the bits needed for FAT support to
34 * According to Xilinx technical support, before accessing the
35 * SystemACE CF you need to set the following control bits:
43 #include <systemace.h>
47 #ifdef CONFIG_SYSTEMACE
50 * The ace_readw and writew functions read/write 16bit words, but the
51 * offset value is the BYTE offset as most used in the Xilinx
52 * datasheet for the SystemACE chip. The CFG_SYSTEMACE_BASE is defined
53 * to be the base address for the chip, usually in the local
56 static unsigned ace_readw(unsigned offset)
58 #if (CFG_SYSTEMACE_WIDTH == 8)
61 #if !defined(__BIG_ENDIAN)
62 temp = ((u16) readb(CFG_SYSTEMACE_BASE + offset) << 8);
63 temp |= (u16) readb(CFG_SYSTEMACE_BASE + offset + 1);
65 temp = (u16) readb(CFG_SYSTEMACE_BASE + offset);
66 temp |= ((u16) readb(CFG_SYSTEMACE_BASE + offset + 1) << 8);
70 return readw(CFG_SYSTEMACE_BASE + offset);
74 static void ace_writew(unsigned val, unsigned offset)
76 #if (CFG_SYSTEMACE_WIDTH == 8)
77 #if !defined(__BIG_ENDIAN)
78 writeb((u8) (val >> 8), CFG_SYSTEMACE_BASE + offset);
79 writeb((u8) val, CFG_SYSTEMACE_BASE + offset + 1);
81 writeb((u8) val, CFG_SYSTEMACE_BASE + offset);
82 writeb((u8) (val >> 8), CFG_SYSTEMACE_BASE + offset + 1);
85 writew(val, CFG_SYSTEMACE_BASE + offset);
91 static unsigned long systemace_read(int dev, unsigned long start,
93 unsigned long *buffer);
95 static block_dev_desc_t systemace_dev = { 0 };
97 static int get_cf_lock(void)
101 /* CONTROLREG = LOCKREG */
102 unsigned val = ace_readw(0x18);
104 ace_writew((val & 0xffff), 0x18);
106 /* Wait for MPULOCK in STATUSREG[15:0] */
107 while (!(ace_readw(0x04) & 0x0002)) {
119 static void release_cf_lock(void)
121 unsigned val = ace_readw(0x18);
123 ace_writew((val & 0xffff), 0x18);
126 block_dev_desc_t *systemace_get_dev(int dev)
128 /* The first time through this, the systemace_dev object is
129 not yet initialized. In that case, fill it in. */
130 if (systemace_dev.blksz == 0) {
131 systemace_dev.if_type = IF_TYPE_UNKNOWN;
132 systemace_dev.dev = 0;
133 systemace_dev.part_type = PART_TYPE_UNKNOWN;
134 systemace_dev.type = DEV_TYPE_HARDDISK;
135 systemace_dev.blksz = 512;
136 systemace_dev.removable = 1;
137 systemace_dev.block_read = systemace_read;
139 init_part(&systemace_dev);
143 return &systemace_dev;
147 * This function is called (by dereferencing the block_read pointer in
148 * the dev_desc) to read blocks of data. The return value is the
149 * number of blocks read. A zero return indicates an error.
151 static unsigned long systemace_read(int dev, unsigned long start,
152 unsigned long blkcnt, unsigned long *buffer)
155 unsigned blk_countdown;
156 unsigned char *dp = (unsigned char *)buffer;
159 if (get_cf_lock() < 0) {
160 unsigned status = ace_readw(0x04);
162 /* If CFDETECT is false, card is missing. */
163 if (!(status & 0x0010)) {
164 printf("** CompactFlash card not present. **\n");
168 printf("**** ACE locked away from me (STATUSREG=%04x)\n",
172 #ifdef DEBUG_SYSTEMACE
173 printf("... systemace read %lu sectors at %lu\n", blkcnt, start);
178 val = ace_readw(0x04);
180 /* If CFDETECT is false, card is missing. */
181 if (!(val & 0x0010)) {
182 printf("**** ACE CompactFlash not found.\n");
187 /* If RDYFORCMD, then we are ready to go. */
192 printf("**** SystemACE not ready.\n");
201 /* The SystemACE can only transfer 256 sectors at a time, so
202 limit the current chunk of sectors. The blk_countdown
203 variable is the number of sectors left to transfer. */
205 blk_countdown = blkcnt;
206 while (blk_countdown > 0) {
207 unsigned trans = blk_countdown;
212 #ifdef DEBUG_SYSTEMACE
213 printf("... transfer %lu sector in a chunk\n", trans);
215 /* Write LBA block address */
216 ace_writew((start >> 0) & 0xffff, 0x10);
217 ace_writew((start >> 16) & 0x00ff, 0x12);
219 /* NOTE: in the Write Sector count below, a count of 0
220 causes a transfer of 256, so &0xff gives the right
221 value for whatever transfer count we want. */
223 /* Write sector count | ReadMemCardData. */
224 ace_writew((trans & 0xff) | 0x0300, 0x14);
226 /* Reset the configruation controller */
227 val = ace_readw(0x18);
229 ace_writew(val, 0x18);
235 /* Wait for buffer to become ready. */
236 while (!(ace_readw(0x04) & 0x0020)) {
240 /* Read 16 words of 2bytes from the sector buffer. */
241 for (idx = 0; idx < 16; idx += 1) {
242 unsigned short val = ace_readw(0x40);
244 *dp++ = (val >> 8) & 0xff;
250 /* Clear the configruation controller reset */
251 val = ace_readw(0x18);
253 ace_writew(val, 0x18);
255 /* Count the blocks we transfer this time. */
257 blk_countdown -= trans;
264 #endif /* CONFIG_SYSTEMACE */