4 * DSP-BIOS Bridge driver support functions for TI OMAP processors.
6 * Processor Manager Driver for TI OMAP3430 EVM.
8 * Copyright (C) 2005-2006 Texas Instruments, Inc.
10 * This package is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
16 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
19 #include <linux/platform_data/dsp-omap.h>
21 #include <linux/types.h>
22 /* ----------------------------------- Host OS */
23 #include <dspbridge/host_os.h>
25 #include <linux/mmzone.h>
27 /* ----------------------------------- DSP/BIOS Bridge */
28 #include <dspbridge/dbdefs.h>
30 /* ----------------------------------- OS Adaptation Layer */
31 #include <dspbridge/drv.h>
32 #include <dspbridge/sync.h>
34 /* ------------------------------------ Hardware Abstraction Layer */
38 /* ----------------------------------- Link Driver */
39 #include <dspbridge/dspdefs.h>
40 #include <dspbridge/dspchnl.h>
41 #include <dspbridge/dspdeh.h>
42 #include <dspbridge/dspio.h>
43 #include <dspbridge/dspmsg.h>
44 #include <dspbridge/pwr.h>
45 #include <dspbridge/io_sm.h>
47 /* ----------------------------------- Platform Manager */
48 #include <dspbridge/dev.h>
49 #include <dspbridge/dspapi.h>
50 #include <dspbridge/dmm.h>
51 #include <dspbridge/wdt.h>
53 /* ----------------------------------- Local */
55 #include "_tiomap_pwr.h"
56 #include "tiomap_io.h"
58 /* Offset in shared mem to write to in order to synchronize start with DSP */
59 #define SHMSYNCOFFSET 4 /* GPP byte offset */
61 #define BUFFERSIZE 1024
63 #define TIHELEN_ACKTIMEOUT 10000
65 #define MMU_SECTION_ADDR_MASK 0xFFF00000
66 #define MMU_SSECTION_ADDR_MASK 0xFF000000
67 #define MMU_LARGE_PAGE_MASK 0xFFFF0000
68 #define MMU_SMALL_PAGE_MASK 0xFFFFF000
69 #define OMAP3_IVA2_BOOTADDR_MASK 0xFFFFFC00
70 #define PAGES_II_LVL_TABLE 512
71 #define PHYS_TO_PAGE(phys) pfn_to_page((phys) >> PAGE_SHIFT)
77 /* Forward Declarations: */
78 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt);
79 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
81 u32 dsp_addr, u32 ul_num_bytes,
83 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
85 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
87 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt);
88 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
90 u32 dsp_addr, u32 ul_num_bytes,
92 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
94 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
95 u32 dsp_dest_addr, u32 dsp_src_addr,
96 u32 ul_num_bytes, u32 mem_type);
97 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
98 u8 *host_buff, u32 dsp_addr,
99 u32 ul_num_bytes, u32 mem_type);
100 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
101 u32 ul_mpu_addr, u32 virt_addr,
102 u32 ul_num_bytes, u32 ul_map_attr,
103 struct page **mapped_pages);
104 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
105 u32 virt_addr, u32 ul_num_bytes);
106 static int bridge_dev_create(struct bridge_dev_context
108 struct dev_object *hdev_obj,
109 struct cfg_hostres *config_param);
110 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
111 u32 dw_cmd, void *pargs);
112 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt);
113 static u32 user_va2_pa(struct mm_struct *mm, u32 address);
114 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
116 struct hw_mmu_map_attrs_t *map_attrs);
117 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
118 u32 size, struct hw_mmu_map_attrs_t *attrs);
119 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
120 u32 ul_mpu_addr, u32 virt_addr,
122 struct hw_mmu_map_attrs_t *hw_attrs);
124 bool wait_for_start(struct bridge_dev_context *dev_context,
125 void __iomem *sync_addr);
127 /* ----------------------------------- Globals */
129 /* Attributes of L2 page tables for DSP MMU */
131 u32 num_entries; /* Number of valid PTEs in the L2 PT */
134 /* Attributes used to manage the DSP MMU page tables */
135 struct pg_table_attrs {
136 spinlock_t pg_lock; /* Critical section object handle */
138 u32 l1_base_pa; /* Physical address of the L1 PT */
139 u32 l1_base_va; /* Virtual address of the L1 PT */
140 u32 l1_size; /* Size of the L1 PT */
142 /* Physical address of Allocated mem for L1 table. May not be aligned */
144 /* Virtual address of Allocated mem for L1 table. May not be aligned */
146 /* Size of consistent memory allocated for L1 table.
147 * May not be aligned */
149 u32 l2_base_pa; /* Physical address of the L2 PT */
150 u32 l2_base_va; /* Virtual address of the L2 PT */
151 u32 l2_size; /* Size of the L2 PT */
153 /* Physical address of Allocated mem for L2 table. May not be aligned */
155 /* Virtual address of Allocated mem for L2 table. May not be aligned */
157 /* Size of consistent memory allocated for L2 table.
158 * May not be aligned */
160 u32 l2_num_pages; /* Number of allocated L2 PT */
161 /* Array [l2_num_pages] of L2 PT info structs */
162 struct page_info *pg_info;
166 * This Bridge driver's function interface table.
168 static struct bridge_drv_interface drv_interface_fxns = {
169 /* Bridge API ver. for which this bridge driver is built. */
170 BRD_API_MAJOR_VERSION,
171 BRD_API_MINOR_VERSION,
181 bridge_brd_set_state,
183 bridge_brd_mem_write,
185 bridge_brd_mem_un_map,
186 /* The following CHNL functions are provided by chnl_io.lib: */
191 bridge_chnl_add_io_req,
193 bridge_chnl_cancel_io,
194 bridge_chnl_flush_io,
195 bridge_chnl_get_info,
196 bridge_chnl_get_mgr_info,
198 bridge_chnl_register_notify,
199 /* The following IO functions are provided by chnl_io.lib: */
203 bridge_io_get_proc_load,
204 /* The following msg_ctrl functions are provided by chnl_io.lib: */
206 bridge_msg_create_queue,
208 bridge_msg_delete_queue,
211 bridge_msg_register_notify,
212 bridge_msg_set_queue_id,
215 static struct notifier_block dsp_mbox_notifier = {
216 .notifier_call = io_mbox_msg,
219 static inline void flush_all(struct bridge_dev_context *dev_context)
221 if (dev_context->brd_state == BRD_DSP_HIBERNATION ||
222 dev_context->brd_state == BRD_HIBERNATION)
223 wake_dsp(dev_context, NULL);
225 hw_mmu_tlb_flush_all(dev_context->dsp_mmu_base);
228 static void bad_page_dump(u32 pa, struct page *pg)
230 pr_emerg("DSPBRIDGE: MAP function: COUNT 0 FOR PA 0x%x\n", pa);
231 pr_emerg("Bad page state in process '%s'\n"
232 "page:%p flags:0x%0*lx mapping:%p mapcount:%d count:%d\n"
234 current->comm, pg, (int)(2 * sizeof(unsigned long)),
235 (unsigned long)pg->flags, pg->mapping,
236 page_mapcount(pg), page_count(pg));
241 * ======== bridge_drv_entry ========
243 * Bridge Driver entry point.
245 void bridge_drv_entry(struct bridge_drv_interface **drv_intf,
246 const char *driver_file_name)
248 if (strcmp(driver_file_name, "UMA") == 0)
249 *drv_intf = &drv_interface_fxns;
251 dev_dbg(bridge, "%s Unknown Bridge file name", __func__);
256 * ======== bridge_brd_monitor ========
258 * This bridge_brd_monitor puts DSP into a Loadable state.
259 * i.e Application can load and start the device.
262 * Device in 'OFF' state.
264 static int bridge_brd_monitor(struct bridge_dev_context *dev_ctxt)
266 struct bridge_dev_context *dev_context = dev_ctxt;
268 struct omap_dsp_platform_data *pdata =
269 omap_dspbridge_dev->dev.platform_data;
271 temp = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
272 OMAP_POWERSTATEST_MASK;
273 if (!(temp & 0x02)) {
274 /* IVA2 is not in ON state */
275 /* Read and set PM_PWSTCTRL_IVA2 to ON */
276 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
277 PWRDM_POWER_ON, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
278 /* Set the SW supervised state transition */
279 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_WAKEUP,
280 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
282 /* Wait until the state has moved to ON */
283 while ((*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
284 OMAP_INTRANSITION_MASK)
286 /* Disable Automatic transition */
287 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_DISABLE_AUTO,
288 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
290 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
291 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
292 dsp_clk_enable(DSP_CLK_IVA2);
294 /* set the device state to IDLE */
295 dev_context->brd_state = BRD_IDLE;
301 * ======== bridge_brd_read ========
303 * Reads buffers for DSP memory.
305 static int bridge_brd_read(struct bridge_dev_context *dev_ctxt,
306 u8 *host_buff, u32 dsp_addr,
307 u32 ul_num_bytes, u32 mem_type)
310 struct bridge_dev_context *dev_context = dev_ctxt;
312 u32 dsp_base_addr = dev_ctxt->dsp_base_addr;
314 if (dsp_addr < dev_context->dsp_start_add) {
318 /* change here to account for the 3 bands of the DSP internal memory */
319 if ((dsp_addr - dev_context->dsp_start_add) <
320 dev_context->internal_size) {
321 offset = dsp_addr - dev_context->dsp_start_add;
323 status = read_ext_dsp_data(dev_context, host_buff, dsp_addr,
324 ul_num_bytes, mem_type);
327 /* copy the data from DSP memory */
328 memcpy(host_buff, (void *)(dsp_base_addr + offset), ul_num_bytes);
333 * ======== bridge_brd_set_state ========
335 * This routine updates the Board status.
337 static int bridge_brd_set_state(struct bridge_dev_context *dev_ctxt,
341 struct bridge_dev_context *dev_context = dev_ctxt;
343 dev_context->brd_state = brd_state;
348 * ======== bridge_brd_start ========
350 * Initializes DSP MMU and Starts DSP.
353 * a) DSP domain is 'ACTIVE'.
354 * b) DSP_RST1 is asserted.
355 * b) DSP_RST2 is released.
357 static int bridge_brd_start(struct bridge_dev_context *dev_ctxt,
361 struct bridge_dev_context *dev_context = dev_ctxt;
362 void __iomem *sync_addr;
363 u32 ul_shm_base; /* Gpp Phys SM base addr(byte) */
364 u32 ul_shm_base_virt; /* Dsp Virt SM base addr */
365 u32 ul_tlb_base_virt; /* Base of MMU TLB entry */
367 /* Offset of shm_base_virt from tlb_base_virt */
368 u32 ul_shm_offset_virt;
370 s32 itmp_entry_ndx = 0; /* DSP-MMU TLB entry base address */
371 struct cfg_hostres *resources = NULL;
375 u32 ul_bios_gp_timer;
377 struct io_mgr *hio_mgr;
378 u32 ul_load_monitor_timer;
380 struct omap_dsp_platform_data *pdata =
381 omap_dspbridge_dev->dev.platform_data;
383 /* The device context contains all the mmu setup info from when the
384 * last dsp base image was loaded. The first entry is always
386 /* Get SHM_BEG - convert to byte address */
387 (void)dev_get_symbol(dev_context->dev_obj, SHMBASENAME,
389 ul_shm_base_virt *= DSPWORDSIZE;
390 /* DSP Virtual address */
391 ul_tlb_base_virt = dev_context->atlb_entry[0].dsp_va;
393 ul_shm_base_virt - (ul_tlb_base_virt * DSPWORDSIZE);
394 /* Kernel logical address */
395 ul_shm_base = dev_context->atlb_entry[0].gpp_va + ul_shm_offset_virt;
397 /* SHM physical sync address */
398 shm_sync_pa = dev_context->atlb_entry[0].gpp_pa + ul_shm_offset_virt +
401 /* 2nd wd is used as sync field */
402 sync_addr = ioremap(shm_sync_pa, SZ_32);
406 /* Write a signature into the shm base + offset; this will
407 * get cleared when the DSP program starts. */
408 if ((ul_shm_base_virt == 0) || (ul_shm_base == 0)) {
409 pr_err("%s: Illegal SM base\n", __func__);
412 __raw_writel(0xffffffff, sync_addr);
415 resources = dev_context->resources;
419 /* Assert RST1 i.e only the RST only for DSP megacell */
421 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK,
422 OMAP3430_RST1_IVA2_MASK, OMAP3430_IVA2_MOD,
425 /* Mask address with 1K for compatibility */
426 pdata->set_bootaddr(dsp_addr &
427 OMAP3_IVA2_BOOTADDR_MASK);
428 pdata->set_bootmode(dsp_debug ? IDLE : DIRECT);
432 /* Reset and Unreset the RST2, so that BOOTADDR is copied to
433 * IVA2 SYSC register */
434 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK,
435 OMAP3430_RST2_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
437 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
438 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
441 /* Disbale the DSP MMU */
442 hw_mmu_disable(resources->dmmu_base);
444 hw_mmu_twl_disable(resources->dmmu_base);
446 /* Only make TLB entry if both addresses are non-zero */
447 for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB;
449 struct bridge_ioctl_extproc *e = &dev_context->atlb_entry[entry_ndx];
450 struct hw_mmu_map_attrs_t map_attrs = {
451 .endianism = e->endianism,
452 .element_size = e->elem_size,
453 .mixed_size = e->mixed_mode,
456 if (!e->gpp_pa || !e->dsp_va)
460 "MMU %d, pa: 0x%x, va: 0x%x, size: 0x%x",
466 hw_mmu_tlb_add(dev_context->dsp_mmu_base,
477 /* Lock the above TLB entries and get the BIOS and load monitor timer
480 hw_mmu_num_locked_set(resources->dmmu_base, itmp_entry_ndx);
481 hw_mmu_victim_num_set(resources->dmmu_base, itmp_entry_ndx);
482 hw_mmu_ttb_set(resources->dmmu_base,
483 dev_context->pt_attrs->l1_base_pa);
484 hw_mmu_twl_enable(resources->dmmu_base);
485 /* Enable the SmartIdle and AutoIdle bit for MMU_SYSCONFIG */
487 temp = __raw_readl((resources->dmmu_base) + 0x10);
488 temp = (temp & 0xFFFFFFEF) | 0x11;
489 __raw_writel(temp, (resources->dmmu_base) + 0x10);
491 /* Let the DSP MMU run */
492 hw_mmu_enable(resources->dmmu_base);
494 /* Enable the BIOS clock */
495 (void)dev_get_symbol(dev_context->dev_obj,
496 BRIDGEINIT_BIOSGPTIMER, &ul_bios_gp_timer);
497 (void)dev_get_symbol(dev_context->dev_obj,
498 BRIDGEINIT_LOADMON_GPTIMER,
499 &ul_load_monitor_timer);
503 if (ul_load_monitor_timer != 0xFFFF) {
504 clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
505 ul_load_monitor_timer;
506 dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
508 dev_dbg(bridge, "Not able to get the symbol for Load "
514 if (ul_bios_gp_timer != 0xFFFF) {
515 clk_cmd = (BPWR_ENABLE_CLOCK << MBX_PM_CLK_CMDSHIFT) |
517 dsp_peripheral_clk_ctrl(dev_context, &clk_cmd);
520 "Not able to get the symbol for BIOS Timer\n");
525 /* Set the DSP clock rate */
526 (void)dev_get_symbol(dev_context->dev_obj,
527 "_BRIDGEINIT_DSP_FREQ", &ul_dsp_clk_addr);
528 /*Set Autoidle Mode for IVA2 PLL */
529 (*pdata->dsp_cm_write)(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT,
530 OMAP3430_IVA2_MOD, OMAP3430_CM_AUTOIDLE_PLL);
532 if ((unsigned int *)ul_dsp_clk_addr != NULL) {
533 /* Get the clock rate */
534 ul_dsp_clk_rate = dsp_clk_get_iva2_rate();
535 dev_dbg(bridge, "%s: DSP clock rate (KHZ): 0x%x \n",
536 __func__, ul_dsp_clk_rate);
537 (void)bridge_brd_write(dev_context,
538 (u8 *) &ul_dsp_clk_rate,
539 ul_dsp_clk_addr, sizeof(u32), 0);
542 * Enable Mailbox events and also drain any pending
545 dev_context->mbox = omap_mbox_get("dsp", &dsp_mbox_notifier);
546 if (IS_ERR(dev_context->mbox)) {
547 dev_context->mbox = NULL;
548 pr_err("%s: Failed to get dsp mailbox handle\n",
555 /*PM_IVA2GRPSEL_PER = 0xC0;*/
556 temp = readl(resources->per_pm_base + 0xA8);
557 temp = (temp & 0xFFFFFF30) | 0xC0;
558 writel(temp, resources->per_pm_base + 0xA8);
560 /*PM_MPUGRPSEL_PER &= 0xFFFFFF3F; */
561 temp = readl(resources->per_pm_base + 0xA4);
562 temp = (temp & 0xFFFFFF3F);
563 writel(temp, resources->per_pm_base + 0xA4);
564 /*CM_SLEEPDEP_PER |= 0x04; */
565 temp = readl(resources->per_base + 0x44);
566 temp = (temp & 0xFFFFFFFB) | 0x04;
567 writel(temp, resources->per_base + 0x44);
569 /*CM_CLKSTCTRL_IVA2 = 0x00000003 -To Allow automatic transitions */
570 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_ENABLE_AUTO,
571 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
574 dev_dbg(bridge, "%s Unreset\n", __func__);
575 /* Enable DSP MMU Interrupts */
576 hw_mmu_event_enable(resources->dmmu_base,
577 HW_MMU_ALL_INTERRUPTS);
578 /* release the RST1, DSP starts executing now .. */
579 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST1_IVA2_MASK, 0,
580 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
582 dev_dbg(bridge, "Waiting for Sync @ 0x%x\n", *(u32 *)sync_addr);
583 dev_dbg(bridge, "DSP c_int00 Address = 0x%x\n", dsp_addr);
585 while (__raw_readw(sync_addr))
588 /* Wait for DSP to clear word in shared memory */
589 /* Read the Location */
590 if (!wait_for_start(dev_context, sync_addr))
593 dev_get_symbol(dev_context->dev_obj, "_WDT_enable", &wdt_en);
596 dsp_wdt_sm_set((void *)ul_shm_base);
597 dsp_wdt_enable(true);
600 status = dev_get_io_mgr(dev_context->dev_obj, &hio_mgr);
602 io_sh_msetting(hio_mgr, SHM_OPPINFO, NULL);
603 /* Write the synchronization bit to indicate the
604 * completion of OPP table update to DSP
606 __raw_writel(0XCAFECAFE, sync_addr);
608 /* update board state */
609 dev_context->brd_state = BRD_RUNNING;
610 /* (void)chnlsm_enable_interrupt(dev_context); */
612 dev_context->brd_state = BRD_UNKNOWN;
622 * ======== bridge_brd_stop ========
624 * Puts DSP in self loop.
629 static int bridge_brd_stop(struct bridge_dev_context *dev_ctxt)
632 struct bridge_dev_context *dev_context = dev_ctxt;
633 struct pg_table_attrs *pt_attrs;
635 struct omap_dsp_platform_data *pdata =
636 omap_dspbridge_dev->dev.platform_data;
638 if (dev_context->brd_state == BRD_STOPPED)
641 /* as per TRM, it is advised to first drive the IVA2 to 'Standby' mode,
642 * before turning off the clocks.. This is to ensure that there are no
643 * pending L3 or other transactons from IVA2 */
644 dsp_pwr_state = (*pdata->dsp_prm_read)(OMAP3430_IVA2_MOD, OMAP2_PM_PWSTST) &
645 OMAP_POWERSTATEST_MASK;
646 if (dsp_pwr_state != PWRDM_POWER_OFF) {
647 (*pdata->dsp_prm_rmw_bits)(OMAP3430_RST2_IVA2_MASK, 0,
648 OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
649 sm_interrupt_dsp(dev_context, MBX_PM_DSPIDLE);
652 /* IVA2 is not in OFF state */
653 /* Set PM_PWSTCTRL_IVA2 to OFF */
654 (*pdata->dsp_prm_rmw_bits)(OMAP_POWERSTATEST_MASK,
655 PWRDM_POWER_OFF, OMAP3430_IVA2_MOD, OMAP2_PM_PWSTCTRL);
656 /* Set the SW supervised state transition for Sleep */
657 (*pdata->dsp_cm_write)(OMAP34XX_CLKSTCTRL_FORCE_SLEEP,
658 OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL);
661 /* Release the Ext Base virtual Address as the next DSP Program
662 * may have a different load address */
663 if (dev_context->dsp_ext_base_addr)
664 dev_context->dsp_ext_base_addr = 0;
666 dev_context->brd_state = BRD_STOPPED; /* update board state */
668 dsp_wdt_enable(false);
670 /* This is a good place to clear the MMU page tables as well */
671 if (dev_context->pt_attrs) {
672 pt_attrs = dev_context->pt_attrs;
673 memset((u8 *) pt_attrs->l1_base_va, 0x00, pt_attrs->l1_size);
674 memset((u8 *) pt_attrs->l2_base_va, 0x00, pt_attrs->l2_size);
675 memset((u8 *) pt_attrs->pg_info, 0x00,
676 (pt_attrs->l2_num_pages * sizeof(struct page_info)));
678 /* Disable the mailbox interrupts */
679 if (dev_context->mbox) {
680 omap_mbox_disable_irq(dev_context->mbox, IRQ_RX);
681 omap_mbox_put(dev_context->mbox, &dsp_mbox_notifier);
682 dev_context->mbox = NULL;
684 /* Reset IVA2 clocks*/
685 (*pdata->dsp_prm_write)(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK |
686 OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL);
688 dsp_clock_disable_all(dev_context->dsp_per_clks);
689 dsp_clk_disable(DSP_CLK_IVA2);
695 * ======== bridge_brd_status ========
696 * Returns the board status.
698 static int bridge_brd_status(struct bridge_dev_context *dev_ctxt,
701 struct bridge_dev_context *dev_context = dev_ctxt;
702 *board_state = dev_context->brd_state;
707 * ======== bridge_brd_write ========
708 * Copies the buffers to DSP internal or external memory.
710 static int bridge_brd_write(struct bridge_dev_context *dev_ctxt,
711 u8 *host_buff, u32 dsp_addr,
712 u32 ul_num_bytes, u32 mem_type)
715 struct bridge_dev_context *dev_context = dev_ctxt;
717 if (dsp_addr < dev_context->dsp_start_add) {
721 if ((dsp_addr - dev_context->dsp_start_add) <
722 dev_context->internal_size) {
723 status = write_dsp_data(dev_ctxt, host_buff, dsp_addr,
724 ul_num_bytes, mem_type);
726 status = write_ext_dsp_data(dev_context, host_buff, dsp_addr,
727 ul_num_bytes, mem_type, false);
734 * ======== bridge_dev_create ========
735 * Creates a driver object. Puts DSP in self loop.
737 static int bridge_dev_create(struct bridge_dev_context
739 struct dev_object *hdev_obj,
740 struct cfg_hostres *config_param)
743 struct bridge_dev_context *dev_context = NULL;
745 struct cfg_hostres *resources = config_param;
746 struct pg_table_attrs *pt_attrs;
750 struct drv_data *drv_datap = dev_get_drvdata(bridge);
752 /* Allocate and initialize a data structure to contain the bridge driver
753 * state, which becomes the context for later calls into this driver */
754 dev_context = kzalloc(sizeof(struct bridge_dev_context), GFP_KERNEL);
760 dev_context->dsp_start_add = (u32) OMAP_GEM_BASE;
761 dev_context->self_loop = (u32) NULL;
762 dev_context->dsp_per_clks = 0;
763 dev_context->internal_size = OMAP_DSP_SIZE;
764 /* Clear dev context MMU table entries.
765 * These get set on bridge_io_on_loaded() call after program loaded. */
766 for (entry_ndx = 0; entry_ndx < BRDIOCTL_NUMOFMMUTLB; entry_ndx++) {
767 dev_context->atlb_entry[entry_ndx].gpp_pa =
768 dev_context->atlb_entry[entry_ndx].dsp_va = 0;
770 dev_context->dsp_base_addr = (u32) MEM_LINEAR_ADDRESS((void *)
777 if (!dev_context->dsp_base_addr)
780 pt_attrs = kzalloc(sizeof(struct pg_table_attrs), GFP_KERNEL);
781 if (pt_attrs != NULL) {
782 pt_attrs->l1_size = SZ_16K; /* 4096 entries of 32 bits */
783 align_size = pt_attrs->l1_size;
784 /* Align sizes are expected to be power of 2 */
785 /* we like to get aligned on L1 table size */
786 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l1_size,
787 align_size, &pg_tbl_pa);
789 /* Check if the PA is aligned for us */
790 if ((pg_tbl_pa) & (align_size - 1)) {
791 /* PA not aligned to page table size ,
792 * try with more allocation and align */
793 mem_free_phys_mem((void *)pg_tbl_va, pg_tbl_pa,
795 /* we like to get aligned on L1 table size */
797 (u32) mem_alloc_phys_mem((pt_attrs->l1_size) * 2,
798 align_size, &pg_tbl_pa);
799 /* We should be able to get aligned table now */
800 pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
801 pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
802 pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size * 2;
803 /* Align the PA to the next 'align' boundary */
804 pt_attrs->l1_base_pa =
806 (align_size - 1)) & (~(align_size - 1));
807 pt_attrs->l1_base_va =
808 pg_tbl_va + (pt_attrs->l1_base_pa - pg_tbl_pa);
810 /* We got aligned PA, cool */
811 pt_attrs->l1_tbl_alloc_pa = pg_tbl_pa;
812 pt_attrs->l1_tbl_alloc_va = pg_tbl_va;
813 pt_attrs->l1_tbl_alloc_sz = pt_attrs->l1_size;
814 pt_attrs->l1_base_pa = pg_tbl_pa;
815 pt_attrs->l1_base_va = pg_tbl_va;
817 if (pt_attrs->l1_base_va)
818 memset((u8 *) pt_attrs->l1_base_va, 0x00,
821 /* number of L2 page tables = DMM pool used + SHMMEM +EXTMEM +
823 pt_attrs->l2_num_pages = ((DMMPOOLSIZE >> 20) + 6);
824 pt_attrs->l2_size = HW_MMU_COARSE_PAGE_SIZE *
825 pt_attrs->l2_num_pages;
826 align_size = 4; /* Make it u32 aligned */
827 /* we like to get aligned on L1 table size */
828 pg_tbl_va = (u32) mem_alloc_phys_mem(pt_attrs->l2_size,
829 align_size, &pg_tbl_pa);
830 pt_attrs->l2_tbl_alloc_pa = pg_tbl_pa;
831 pt_attrs->l2_tbl_alloc_va = pg_tbl_va;
832 pt_attrs->l2_tbl_alloc_sz = pt_attrs->l2_size;
833 pt_attrs->l2_base_pa = pg_tbl_pa;
834 pt_attrs->l2_base_va = pg_tbl_va;
836 if (pt_attrs->l2_base_va)
837 memset((u8 *) pt_attrs->l2_base_va, 0x00,
840 pt_attrs->pg_info = kzalloc(pt_attrs->l2_num_pages *
841 sizeof(struct page_info), GFP_KERNEL);
843 "L1 pa %x, va %x, size %x\n L2 pa %x, va "
844 "%x, size %x\n", pt_attrs->l1_base_pa,
845 pt_attrs->l1_base_va, pt_attrs->l1_size,
846 pt_attrs->l2_base_pa, pt_attrs->l2_base_va,
848 dev_dbg(bridge, "pt_attrs %p L2 NumPages %x pg_info %p\n",
849 pt_attrs, pt_attrs->l2_num_pages, pt_attrs->pg_info);
851 if ((pt_attrs != NULL) && (pt_attrs->l1_base_va != 0) &&
852 (pt_attrs->l2_base_va != 0) && (pt_attrs->pg_info != NULL))
853 dev_context->pt_attrs = pt_attrs;
858 spin_lock_init(&pt_attrs->pg_lock);
859 dev_context->tc_word_swap_on = drv_datap->tc_wordswapon;
861 /* Set the Clock Divisor for the DSP module */
863 /* MMU address is obtained from the host
864 * resources struct */
865 dev_context->dsp_mmu_base = resources->dmmu_base;
868 dev_context->dev_obj = hdev_obj;
869 /* Store current board state. */
870 dev_context->brd_state = BRD_UNKNOWN;
871 dev_context->resources = resources;
872 dsp_clk_enable(DSP_CLK_IVA2);
873 bridge_brd_stop(dev_context);
874 /* Return ptr to our device state to the DSP API for storage */
875 *dev_cntxt = dev_context;
877 if (pt_attrs != NULL) {
878 kfree(pt_attrs->pg_info);
880 if (pt_attrs->l2_tbl_alloc_va) {
881 mem_free_phys_mem((void *)
882 pt_attrs->l2_tbl_alloc_va,
883 pt_attrs->l2_tbl_alloc_pa,
884 pt_attrs->l2_tbl_alloc_sz);
886 if (pt_attrs->l1_tbl_alloc_va) {
887 mem_free_phys_mem((void *)
888 pt_attrs->l1_tbl_alloc_va,
889 pt_attrs->l1_tbl_alloc_pa,
890 pt_attrs->l1_tbl_alloc_sz);
901 * ======== bridge_dev_ctrl ========
902 * Receives device specific commands.
904 static int bridge_dev_ctrl(struct bridge_dev_context *dev_context,
905 u32 dw_cmd, void *pargs)
908 struct bridge_ioctl_extproc *pa_ext_proc =
909 (struct bridge_ioctl_extproc *)pargs;
913 case BRDIOCTL_CHNLREAD:
915 case BRDIOCTL_CHNLWRITE:
917 case BRDIOCTL_SETMMUCONFIG:
918 /* store away dsp-mmu setup values for later use */
919 for (ndx = 0; ndx < BRDIOCTL_NUMOFMMUTLB; ndx++, pa_ext_proc++)
920 dev_context->atlb_entry[ndx] = *pa_ext_proc;
922 case BRDIOCTL_DEEPSLEEP:
923 case BRDIOCTL_EMERGENCYSLEEP:
924 /* Currently only DSP Idle is supported Need to update for
926 status = sleep_dsp(dev_context, PWR_DEEPSLEEP, pargs);
928 case BRDIOCTL_WAKEUP:
929 status = wake_dsp(dev_context, pargs);
931 case BRDIOCTL_CLK_CTRL:
933 /* Looking For Baseport Fix for Clocks */
934 status = dsp_peripheral_clk_ctrl(dev_context, pargs);
936 case BRDIOCTL_PWR_HIBERNATE:
937 status = handle_hibernation_from_dsp(dev_context);
939 case BRDIOCTL_PRESCALE_NOTIFY:
940 status = pre_scale_dsp(dev_context, pargs);
942 case BRDIOCTL_POSTSCALE_NOTIFY:
943 status = post_scale_dsp(dev_context, pargs);
945 case BRDIOCTL_CONSTRAINT_REQUEST:
946 status = handle_constraints_set(dev_context, pargs);
956 * ======== bridge_dev_destroy ========
957 * Destroys the driver object.
959 static int bridge_dev_destroy(struct bridge_dev_context *dev_ctxt)
961 struct pg_table_attrs *pt_attrs;
963 struct bridge_dev_context *dev_context = (struct bridge_dev_context *)
965 struct cfg_hostres *host_res;
967 struct drv_data *drv_datap = dev_get_drvdata(bridge);
969 /* It should never happen */
973 /* first put the device to stop state */
974 bridge_brd_stop(dev_context);
975 if (dev_context->pt_attrs) {
976 pt_attrs = dev_context->pt_attrs;
977 kfree(pt_attrs->pg_info);
979 if (pt_attrs->l2_tbl_alloc_va) {
980 mem_free_phys_mem((void *)pt_attrs->l2_tbl_alloc_va,
981 pt_attrs->l2_tbl_alloc_pa,
982 pt_attrs->l2_tbl_alloc_sz);
984 if (pt_attrs->l1_tbl_alloc_va) {
985 mem_free_phys_mem((void *)pt_attrs->l1_tbl_alloc_va,
986 pt_attrs->l1_tbl_alloc_pa,
987 pt_attrs->l1_tbl_alloc_sz);
993 if (dev_context->resources) {
994 host_res = dev_context->resources;
995 shm_size = drv_datap->shm_size;
996 if (shm_size >= 0x10000) {
997 if ((host_res->mem_base[1]) &&
998 (host_res->mem_phys[1])) {
999 mem_free_phys_mem((void *)
1006 dev_dbg(bridge, "%s: Error getting shm size "
1007 "from registry: %x. Not calling "
1008 "mem_free_phys_mem\n", __func__,
1011 host_res->mem_base[1] = 0;
1012 host_res->mem_phys[1] = 0;
1014 if (host_res->mem_base[0])
1015 iounmap((void *)host_res->mem_base[0]);
1016 if (host_res->mem_base[2])
1017 iounmap((void *)host_res->mem_base[2]);
1018 if (host_res->mem_base[3])
1019 iounmap((void *)host_res->mem_base[3]);
1020 if (host_res->mem_base[4])
1021 iounmap((void *)host_res->mem_base[4]);
1022 if (host_res->dmmu_base)
1023 iounmap(host_res->dmmu_base);
1024 if (host_res->per_base)
1025 iounmap(host_res->per_base);
1026 if (host_res->per_pm_base)
1027 iounmap((void *)host_res->per_pm_base);
1028 if (host_res->core_pm_base)
1029 iounmap((void *)host_res->core_pm_base);
1031 host_res->mem_base[0] = (u32) NULL;
1032 host_res->mem_base[2] = (u32) NULL;
1033 host_res->mem_base[3] = (u32) NULL;
1034 host_res->mem_base[4] = (u32) NULL;
1035 host_res->dmmu_base = NULL;
1040 /* Free the driver's device context: */
1041 kfree(drv_datap->base_img);
1042 kfree((void *)dev_ctxt);
1046 static int bridge_brd_mem_copy(struct bridge_dev_context *dev_ctxt,
1047 u32 dsp_dest_addr, u32 dsp_src_addr,
1048 u32 ul_num_bytes, u32 mem_type)
1051 u32 src_addr = dsp_src_addr;
1052 u32 dest_addr = dsp_dest_addr;
1054 u32 total_bytes = ul_num_bytes;
1055 u8 host_buf[BUFFERSIZE];
1056 struct bridge_dev_context *dev_context = dev_ctxt;
1057 while (total_bytes > 0 && !status) {
1059 total_bytes > BUFFERSIZE ? BUFFERSIZE : total_bytes;
1060 /* Read from External memory */
1061 status = read_ext_dsp_data(dev_ctxt, host_buf, src_addr,
1062 copy_bytes, mem_type);
1064 if (dest_addr < (dev_context->dsp_start_add +
1065 dev_context->internal_size)) {
1066 /* Write to Internal memory */
1067 status = write_dsp_data(dev_ctxt, host_buf,
1068 dest_addr, copy_bytes,
1071 /* Write to External memory */
1073 write_ext_dsp_data(dev_ctxt, host_buf,
1074 dest_addr, copy_bytes,
1078 total_bytes -= copy_bytes;
1079 src_addr += copy_bytes;
1080 dest_addr += copy_bytes;
1085 /* Mem Write does not halt the DSP to write unlike bridge_brd_write */
1086 static int bridge_brd_mem_write(struct bridge_dev_context *dev_ctxt,
1087 u8 *host_buff, u32 dsp_addr,
1088 u32 ul_num_bytes, u32 mem_type)
1091 struct bridge_dev_context *dev_context = dev_ctxt;
1092 u32 ul_remain_bytes = 0;
1094 ul_remain_bytes = ul_num_bytes;
1095 while (ul_remain_bytes > 0 && !status) {
1097 ul_remain_bytes > BUFFERSIZE ? BUFFERSIZE : ul_remain_bytes;
1098 if (dsp_addr < (dev_context->dsp_start_add +
1099 dev_context->internal_size)) {
1101 write_dsp_data(dev_ctxt, host_buff, dsp_addr,
1102 ul_bytes, mem_type);
1104 status = write_ext_dsp_data(dev_ctxt, host_buff,
1108 ul_remain_bytes -= ul_bytes;
1109 dsp_addr += ul_bytes;
1110 host_buff = host_buff + ul_bytes;
1116 * ======== bridge_brd_mem_map ========
1117 * This function maps MPU buffer to the DSP address space. It performs
1118 * linear to physical address translation if required. It translates each
1119 * page since linear addresses can be physically non-contiguous
1120 * All address & size arguments are assumed to be page aligned (in proc.c)
1122 * TODO: Disable MMU while updating the page tables (but that'll stall DSP)
1124 static int bridge_brd_mem_map(struct bridge_dev_context *dev_ctxt,
1125 u32 ul_mpu_addr, u32 virt_addr,
1126 u32 ul_num_bytes, u32 ul_map_attr,
1127 struct page **mapped_pages)
1131 struct bridge_dev_context *dev_context = dev_ctxt;
1132 struct hw_mmu_map_attrs_t hw_attrs;
1133 struct vm_area_struct *vma;
1134 struct mm_struct *mm = current->mm;
1136 u32 num_usr_pgs = 0;
1137 struct page *mapped_page, *pg;
1140 struct task_struct *curr_task = current;
1145 "%s hDevCtxt %p, pa %x, va %x, size %x, ul_map_attr %x\n",
1146 __func__, dev_ctxt, ul_mpu_addr, virt_addr, ul_num_bytes,
1148 if (ul_num_bytes == 0)
1151 if (ul_map_attr & DSP_MAP_DIR_MASK) {
1152 attrs = ul_map_attr;
1154 /* Assign default attributes */
1155 attrs = ul_map_attr | (DSP_MAPVIRTUALADDR | DSP_MAPELEMSIZE16);
1157 /* Take mapping properties */
1158 if (attrs & DSP_MAPBIGENDIAN)
1159 hw_attrs.endianism = HW_BIG_ENDIAN;
1161 hw_attrs.endianism = HW_LITTLE_ENDIAN;
1163 hw_attrs.mixed_size = (enum hw_mmu_mixed_size_t)
1164 ((attrs & DSP_MAPMIXEDELEMSIZE) >> 2);
1165 /* Ignore element_size if mixed_size is enabled */
1166 if (hw_attrs.mixed_size == 0) {
1167 if (attrs & DSP_MAPELEMSIZE8) {
1169 hw_attrs.element_size = HW_ELEM_SIZE8BIT;
1170 } else if (attrs & DSP_MAPELEMSIZE16) {
1171 /* Size is 16 bit */
1172 hw_attrs.element_size = HW_ELEM_SIZE16BIT;
1173 } else if (attrs & DSP_MAPELEMSIZE32) {
1174 /* Size is 32 bit */
1175 hw_attrs.element_size = HW_ELEM_SIZE32BIT;
1176 } else if (attrs & DSP_MAPELEMSIZE64) {
1177 /* Size is 64 bit */
1178 hw_attrs.element_size = HW_ELEM_SIZE64BIT;
1181 * Mixedsize isn't enabled, so size can't be
1187 if (attrs & DSP_MAPDONOTLOCK)
1188 hw_attrs.donotlockmpupage = 1;
1190 hw_attrs.donotlockmpupage = 0;
1192 if (attrs & DSP_MAPVMALLOCADDR) {
1193 return mem_map_vmalloc(dev_ctxt, ul_mpu_addr, virt_addr,
1194 ul_num_bytes, &hw_attrs);
1197 * Do OS-specific user-va to pa translation.
1198 * Combine physically contiguous regions to reduce TLBs.
1199 * Pass the translated pa to pte_update.
1201 if ((attrs & DSP_MAPPHYSICALADDR)) {
1202 status = pte_update(dev_context, ul_mpu_addr, virt_addr,
1203 ul_num_bytes, &hw_attrs);
1208 * Important Note: ul_mpu_addr is mapped from user application process
1209 * to current process - it must lie completely within the current
1210 * virtual memory address space in order to be of use to us here!
1212 down_read(&mm->mmap_sem);
1213 vma = find_vma(mm, ul_mpu_addr);
1216 "VMAfor UserBuf: ul_mpu_addr=%x, ul_num_bytes=%x, "
1217 "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1218 ul_num_bytes, vma->vm_start, vma->vm_end,
1222 * It is observed that under some circumstances, the user buffer is
1223 * spread across several VMAs. So loop through and check if the entire
1224 * user buffer is covered
1226 while ((vma) && (ul_mpu_addr + ul_num_bytes > vma->vm_end)) {
1227 /* jump to the next VMA region */
1228 vma = find_vma(mm, vma->vm_end + 1);
1230 "VMA for UserBuf ul_mpu_addr=%x ul_num_bytes=%x, "
1231 "vm_start=%lx, vm_end=%lx, vm_flags=%lx\n", ul_mpu_addr,
1232 ul_num_bytes, vma->vm_start, vma->vm_end,
1236 pr_err("%s: Failed to get VMA region for 0x%x (%d)\n",
1237 __func__, ul_mpu_addr, ul_num_bytes);
1239 up_read(&mm->mmap_sem);
1243 if (vma->vm_flags & VM_IO) {
1244 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1245 mpu_addr = ul_mpu_addr;
1247 /* Get the physical addresses for user buffer */
1248 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1249 pa = user_va2_pa(mm, mpu_addr);
1252 pr_err("DSPBRIDGE: VM_IO mapping physical"
1253 "address is invalid\n");
1256 if (pfn_valid(__phys_to_pfn(pa))) {
1257 pg = PHYS_TO_PAGE(pa);
1259 if (page_count(pg) < 1) {
1260 pr_err("Bad page in VM_IO buffer\n");
1261 bad_page_dump(pa, pg);
1264 status = pte_set(dev_context->pt_attrs, pa,
1265 va, HW_PAGE_SIZE4KB, &hw_attrs);
1269 va += HW_PAGE_SIZE4KB;
1270 mpu_addr += HW_PAGE_SIZE4KB;
1271 pa += HW_PAGE_SIZE4KB;
1274 num_usr_pgs = ul_num_bytes / PG_SIZE4K;
1275 if (vma->vm_flags & (VM_WRITE | VM_MAYWRITE))
1278 for (pg_i = 0; pg_i < num_usr_pgs; pg_i++) {
1279 pg_num = get_user_pages(curr_task, mm, ul_mpu_addr, 1,
1280 write, 1, &mapped_page, NULL);
1282 if (page_count(mapped_page) < 1) {
1283 pr_err("Bad page count after doing"
1286 bad_page_dump(page_to_phys(mapped_page),
1289 status = pte_set(dev_context->pt_attrs,
1290 page_to_phys(mapped_page), va,
1291 HW_PAGE_SIZE4KB, &hw_attrs);
1296 mapped_pages[pg_i] = mapped_page;
1298 va += HW_PAGE_SIZE4KB;
1299 ul_mpu_addr += HW_PAGE_SIZE4KB;
1301 pr_err("DSPBRIDGE: get_user_pages FAILED,"
1303 "vma->vm_flags = 0x%lx,"
1304 "get_user_pages Err"
1305 "Value = %d, Buffer"
1306 "size=0x%x\n", ul_mpu_addr,
1307 vma->vm_flags, pg_num, ul_num_bytes);
1313 up_read(&mm->mmap_sem);
1317 * Roll out the mapped pages incase it failed in middle of
1321 bridge_brd_mem_un_map(dev_context, virt_addr,
1322 (pg_i * PG_SIZE4K));
1327 * In any case, flush the TLB
1328 * This is called from here instead from pte_update to avoid unnecessary
1329 * repetition while mapping non-contiguous physical regions of a virtual
1332 flush_all(dev_context);
1333 dev_dbg(bridge, "%s status %x\n", __func__, status);
1338 * ======== bridge_brd_mem_un_map ========
1339 * Invalidate the PTEs for the DSP VA block to be unmapped.
1341 * PTEs of a mapped memory block are contiguous in any page table
1342 * So, instead of looking up the PTE address for every 4K block,
1343 * we clear consecutive PTEs until we unmap all the bytes
1345 static int bridge_brd_mem_un_map(struct bridge_dev_context *dev_ctxt,
1346 u32 virt_addr, u32 ul_num_bytes)
1356 u32 pte_addr_l2 = 0;
1360 struct page *pg = NULL;
1362 struct bridge_dev_context *dev_context = dev_ctxt;
1363 struct pg_table_attrs *pt = dev_context->pt_attrs;
1366 u32 numof4k_pages = 0;
1368 va_curr = virt_addr;
1369 rem_bytes = ul_num_bytes;
1371 l1_base_va = pt->l1_base_va;
1372 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1373 dev_dbg(bridge, "%s dev_ctxt %p, va %x, NumBytes %x l1_base_va %x, "
1374 "pte_addr_l1 %x\n", __func__, dev_ctxt, virt_addr,
1375 ul_num_bytes, l1_base_va, pte_addr_l1);
1377 while (rem_bytes && !status) {
1378 u32 va_curr_orig = va_curr;
1379 /* Find whether the L1 PTE points to a valid L2 PT */
1380 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va_curr);
1381 pte_val = *(u32 *) pte_addr_l1;
1382 pte_size = hw_mmu_pte_size_l1(pte_val);
1384 if (pte_size != HW_MMU_COARSE_PAGE_SIZE)
1385 goto skip_coarse_page;
1388 * Get the L2 PA from the L1 PTE, and find
1389 * corresponding L2 VA
1391 l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1392 l2_base_va = l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1394 (l2_base_pa - pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1396 * Find the L2 PTE address from which we will start
1397 * clearing, the number of PTEs to be cleared on this
1398 * page, and the size of VA space that needs to be
1399 * cleared on this L2 page
1401 pte_addr_l2 = hw_mmu_pte_addr_l2(l2_base_va, va_curr);
1402 pte_count = pte_addr_l2 & (HW_MMU_COARSE_PAGE_SIZE - 1);
1403 pte_count = (HW_MMU_COARSE_PAGE_SIZE - pte_count) / sizeof(u32);
1404 if (rem_bytes < (pte_count * PG_SIZE4K))
1405 pte_count = rem_bytes / PG_SIZE4K;
1406 rem_bytes_l2 = pte_count * PG_SIZE4K;
1409 * Unmap the VA space on this L2 PT. A quicker way
1410 * would be to clear pte_count entries starting from
1411 * pte_addr_l2. However, below code checks that we don't
1412 * clear invalid entries or less than 64KB for a 64KB
1413 * entry. Similar checking is done for L1 PTEs too
1416 while (rem_bytes_l2 && !status) {
1417 pte_val = *(u32 *) pte_addr_l2;
1418 pte_size = hw_mmu_pte_size_l2(pte_val);
1419 /* va_curr aligned to pte_size? */
1420 if (pte_size == 0 || rem_bytes_l2 < pte_size ||
1421 va_curr & (pte_size - 1)) {
1426 /* Collect Physical addresses from VA */
1427 paddr = (pte_val & ~(pte_size - 1));
1428 if (pte_size == HW_PAGE_SIZE64KB)
1433 while (temp++ < numof4k_pages) {
1434 if (!pfn_valid(__phys_to_pfn(paddr))) {
1435 paddr += HW_PAGE_SIZE4KB;
1438 pg = PHYS_TO_PAGE(paddr);
1439 if (page_count(pg) < 1) {
1440 pr_info("DSPBRIDGE: UNMAP function: "
1441 "COUNT 0 FOR PA 0x%x, size = "
1442 "0x%x\n", paddr, ul_num_bytes);
1443 bad_page_dump(paddr, pg);
1446 page_cache_release(pg);
1448 paddr += HW_PAGE_SIZE4KB;
1450 if (hw_mmu_pte_clear(pte_addr_l2, va_curr, pte_size)) {
1456 rem_bytes_l2 -= pte_size;
1457 va_curr += pte_size;
1458 pte_addr_l2 += (pte_size >> 12) * sizeof(u32);
1460 spin_lock(&pt->pg_lock);
1461 if (rem_bytes_l2 == 0) {
1462 pt->pg_info[l2_page_num].num_entries -= pte_count;
1463 if (pt->pg_info[l2_page_num].num_entries == 0) {
1465 * Clear the L1 PTE pointing to the L2 PT
1467 if (!hw_mmu_pte_clear(l1_base_va, va_curr_orig,
1468 HW_MMU_COARSE_PAGE_SIZE))
1472 spin_unlock(&pt->pg_lock);
1476 rem_bytes -= pte_count * PG_SIZE4K;
1480 spin_unlock(&pt->pg_lock);
1483 /* va_curr aligned to pte_size? */
1484 /* pte_size = 1 MB or 16 MB */
1485 if (pte_size == 0 || rem_bytes < pte_size ||
1486 va_curr & (pte_size - 1)) {
1491 if (pte_size == HW_PAGE_SIZE1MB)
1492 numof4k_pages = 256;
1494 numof4k_pages = 4096;
1496 /* Collect Physical addresses from VA */
1497 paddr = (pte_val & ~(pte_size - 1));
1498 while (temp++ < numof4k_pages) {
1499 if (pfn_valid(__phys_to_pfn(paddr))) {
1500 pg = PHYS_TO_PAGE(paddr);
1501 if (page_count(pg) < 1) {
1502 pr_info("DSPBRIDGE: UNMAP function: "
1503 "COUNT 0 FOR PA 0x%x, size = "
1504 "0x%x\n", paddr, ul_num_bytes);
1505 bad_page_dump(paddr, pg);
1508 page_cache_release(pg);
1511 paddr += HW_PAGE_SIZE4KB;
1513 if (!hw_mmu_pte_clear(l1_base_va, va_curr, pte_size)) {
1515 rem_bytes -= pte_size;
1516 va_curr += pte_size;
1523 * It is better to flush the TLB here, so that any stale old entries
1527 flush_all(dev_context);
1529 "%s: va_curr %x, pte_addr_l1 %x pte_addr_l2 %x rem_bytes %x,"
1530 " rem_bytes_l2 %x status %x\n", __func__, va_curr, pte_addr_l1,
1531 pte_addr_l2, rem_bytes, rem_bytes_l2, status);
1536 * ======== user_va2_pa ========
1538 * This function walks through the page tables to convert a userland
1539 * virtual address to physical address
1541 static u32 user_va2_pa(struct mm_struct *mm, u32 address)
1548 pgd = pgd_offset(mm, address);
1549 if (pgd_none(*pgd) || pgd_bad(*pgd))
1552 pud = pud_offset(pgd, address);
1553 if (pud_none(*pud) || pud_bad(*pud))
1556 pmd = pmd_offset(pud, address);
1557 if (pmd_none(*pmd) || pmd_bad(*pmd))
1560 ptep = pte_offset_map(pmd, address);
1563 if (pte_present(pte))
1564 return pte & PAGE_MASK;
1571 * ======== pte_update ========
1572 * This function calculates the optimum page-aligned addresses and sizes
1573 * Caller must pass page-aligned values
1575 static int pte_update(struct bridge_dev_context *dev_ctxt, u32 pa,
1577 struct hw_mmu_map_attrs_t *map_attrs)
1583 u32 num_bytes = size;
1584 struct bridge_dev_context *dev_context = dev_ctxt;
1586 u32 page_size[] = { HW_PAGE_SIZE16MB, HW_PAGE_SIZE1MB,
1587 HW_PAGE_SIZE64KB, HW_PAGE_SIZE4KB
1590 while (num_bytes && !status) {
1591 /* To find the max. page size with which both PA & VA are
1593 all_bits = pa_curr | va_curr;
1595 for (i = 0; i < 4; i++) {
1596 if ((num_bytes >= page_size[i]) && ((all_bits &
1600 pte_set(dev_context->pt_attrs, pa_curr,
1601 va_curr, page_size[i], map_attrs);
1602 pa_curr += page_size[i];
1603 va_curr += page_size[i];
1604 num_bytes -= page_size[i];
1605 /* Don't try smaller sizes. Hopefully we have
1606 * reached an address aligned to a bigger page
1617 * ======== pte_set ========
1618 * This function calculates PTE address (MPU virtual) to be updated
1619 * It also manages the L2 page tables
1621 static int pte_set(struct pg_table_attrs *pt, u32 pa, u32 va,
1622 u32 size, struct hw_mmu_map_attrs_t *attrs)
1628 /* Base address of the PT that will be updated */
1631 /* Compiler warns that the next three variables might be used
1632 * uninitialized in this function. Doesn't seem so. Working around,
1636 u32 l2_page_num = 0;
1639 l1_base_va = pt->l1_base_va;
1640 pg_tbl_va = l1_base_va;
1641 if ((size == HW_PAGE_SIZE64KB) || (size == HW_PAGE_SIZE4KB)) {
1642 /* Find whether the L1 PTE points to a valid L2 PT */
1643 pte_addr_l1 = hw_mmu_pte_addr_l1(l1_base_va, va);
1644 if (pte_addr_l1 <= (pt->l1_base_va + pt->l1_size)) {
1645 pte_val = *(u32 *) pte_addr_l1;
1646 pte_size = hw_mmu_pte_size_l1(pte_val);
1650 spin_lock(&pt->pg_lock);
1651 if (pte_size == HW_MMU_COARSE_PAGE_SIZE) {
1652 /* Get the L2 PA from the L1 PTE, and find
1653 * corresponding L2 VA */
1654 l2_base_pa = hw_mmu_pte_coarse_l1(pte_val);
1656 l2_base_pa - pt->l2_base_pa + pt->l2_base_va;
1659 pt->l2_base_pa) / HW_MMU_COARSE_PAGE_SIZE;
1660 } else if (pte_size == 0) {
1661 /* L1 PTE is invalid. Allocate a L2 PT and
1662 * point the L1 PTE to it */
1663 /* Find a free L2 PT. */
1664 for (i = 0; (i < pt->l2_num_pages) &&
1665 (pt->pg_info[i].num_entries != 0); i++)
1667 if (i < pt->l2_num_pages) {
1669 l2_base_pa = pt->l2_base_pa + (l2_page_num *
1670 HW_MMU_COARSE_PAGE_SIZE);
1671 l2_base_va = pt->l2_base_va + (l2_page_num *
1672 HW_MMU_COARSE_PAGE_SIZE);
1673 /* Endianness attributes are ignored for
1674 * HW_MMU_COARSE_PAGE_SIZE */
1676 hw_mmu_pte_set(l1_base_va, l2_base_pa, va,
1677 HW_MMU_COARSE_PAGE_SIZE,
1683 /* Found valid L1 PTE of another size.
1684 * Should not overwrite it. */
1688 pg_tbl_va = l2_base_va;
1689 if (size == HW_PAGE_SIZE64KB)
1690 pt->pg_info[l2_page_num].num_entries += 16;
1692 pt->pg_info[l2_page_num].num_entries++;
1693 dev_dbg(bridge, "PTE: L2 BaseVa %x, BasePa %x, PageNum "
1694 "%x, num_entries %x\n", l2_base_va,
1695 l2_base_pa, l2_page_num,
1696 pt->pg_info[l2_page_num].num_entries);
1698 spin_unlock(&pt->pg_lock);
1701 dev_dbg(bridge, "PTE: pg_tbl_va %x, pa %x, va %x, size %x\n",
1702 pg_tbl_va, pa, va, size);
1703 dev_dbg(bridge, "PTE: endianism %x, element_size %x, "
1704 "mixed_size %x\n", attrs->endianism,
1705 attrs->element_size, attrs->mixed_size);
1706 status = hw_mmu_pte_set(pg_tbl_va, pa, va, size, attrs);
1712 /* Memory map kernel VA -- memory allocated with vmalloc */
1713 static int mem_map_vmalloc(struct bridge_dev_context *dev_context,
1714 u32 ul_mpu_addr, u32 virt_addr,
1716 struct hw_mmu_map_attrs_t *hw_attrs)
1719 struct page *page[1];
1731 * Do Kernel va to pa translation.
1732 * Combine physically contiguous regions to reduce TLBs.
1733 * Pass the translated pa to pte_update.
1735 num_pages = ul_num_bytes / PAGE_SIZE; /* PAGE_SIZE = OS page size */
1737 va_curr = ul_mpu_addr;
1738 page[0] = vmalloc_to_page((void *)va_curr);
1739 pa_next = page_to_phys(page[0]);
1740 while (!status && (i < num_pages)) {
1742 * Reuse pa_next from the previous iteration to avoid
1743 * an extra va2pa call
1746 size_curr = PAGE_SIZE;
1748 * If the next page is physically contiguous,
1749 * map it with the current one by increasing
1750 * the size of the region to be mapped
1752 while (++i < num_pages) {
1754 vmalloc_to_page((void *)(va_curr + size_curr));
1755 pa_next = page_to_phys(page[0]);
1757 if (pa_next == (pa_curr + size_curr))
1758 size_curr += PAGE_SIZE;
1768 num_of4k_pages = size_curr / HW_PAGE_SIZE4KB;
1769 while (temp++ < num_of4k_pages) {
1770 get_page(PHYS_TO_PAGE(pa));
1771 pa += HW_PAGE_SIZE4KB;
1773 status = pte_update(dev_context, pa_curr, virt_addr +
1774 (va_curr - ul_mpu_addr), size_curr,
1776 va_curr += size_curr;
1779 * In any case, flush the TLB
1780 * This is called from here instead from pte_update to avoid unnecessary
1781 * repetition while mapping non-contiguous physical regions of a virtual
1784 flush_all(dev_context);
1785 dev_dbg(bridge, "%s status %x\n", __func__, status);
1790 * ======== wait_for_start ========
1791 * Wait for the singal from DSP that it has started, or time out.
1793 bool wait_for_start(struct bridge_dev_context *dev_context,
1794 void __iomem *sync_addr)
1796 u16 timeout = TIHELEN_ACKTIMEOUT;
1798 /* Wait for response from board */
1799 while (__raw_readw(sync_addr) && --timeout)
1802 /* If timed out: return false */
1804 pr_err("%s: Timed out waiting DSP to Start\n", __func__);