drivers/staging/rts_pstor/rtsx_chip.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   wwang (wei_wang@realsil.com.cn)
  20  *   No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/vmalloc.h>
  28
  29 #include "rtsx.h"
  30 #include "rtsx_transport.h"
  31 #include "rtsx_scsi.h"
  32 #include "rtsx_card.h"
  33 #include "rtsx_chip.h"
  34 #include "rtsx_sys.h"
  35 #include "general.h"
  36
  37 #include "sd.h"
  38 #include "xd.h"
  39 #include "ms.h"
  40
  41 static void rtsx_calibration(struct rtsx_chip *chip)
  42 {
  43         rtsx_write_phy_register(chip, 0x1B, 0x135E);
  44         wait_timeout(10);
  45         rtsx_write_phy_register(chip, 0x00, 0x0280);
  46         rtsx_write_phy_register(chip, 0x01, 0x7112);
  47         rtsx_write_phy_register(chip, 0x01, 0x7110);
  48         rtsx_write_phy_register(chip, 0x01, 0x7112);
  49         rtsx_write_phy_register(chip, 0x01, 0x7113);
  50         rtsx_write_phy_register(chip, 0x00, 0x0288);
  51 }
  52
  53 void rtsx_disable_card_int(struct rtsx_chip *chip)
  54 {
  55         u32 reg = rtsx_readl(chip, RTSX_BIER);
  56
  57         reg &= ~(XD_INT_EN | SD_INT_EN | MS_INT_EN);
  58         rtsx_writel(chip, RTSX_BIER, reg);
  59 }
  60
  61 void rtsx_enable_card_int(struct rtsx_chip *chip)
  62 {
  63         u32 reg = rtsx_readl(chip, RTSX_BIER);
  64         int i;
  65
  66         for (i = 0; i <= chip->max_lun; i++) {
  67                 if (chip->lun2card[i] & XD_CARD)
  68                         reg |= XD_INT_EN;
  69                 if (chip->lun2card[i] & SD_CARD)
  70                         reg |= SD_INT_EN;
  71                 if (chip->lun2card[i] & MS_CARD)
  72                         reg |= MS_INT_EN;
  73         }
  74         if (chip->hw_bypass_sd)
  75                 reg &= ~((u32)SD_INT_EN);
  76
  77         rtsx_writel(chip, RTSX_BIER, reg);
  78 }
  79
  80 void rtsx_enable_bus_int(struct rtsx_chip *chip)
  81 {
  82         u32 reg = 0;
  83 #ifndef DISABLE_CARD_INT
  84         int i;
  85 #endif
  86
  87         reg = TRANS_OK_INT_EN | TRANS_FAIL_INT_EN;
  88
  89 #ifndef DISABLE_CARD_INT
  90         for (i = 0; i <= chip->max_lun; i++) {
  91                 RTSX_DEBUGP("lun2card[%d] = 0x%02x\n", i, chip->lun2card[i]);
  92
  93                 if (chip->lun2card[i] & XD_CARD)
  94                         reg |= XD_INT_EN;
  95                 if (chip->lun2card[i] & SD_CARD)
  96                         reg |= SD_INT_EN;
  97                 if (chip->lun2card[i] & MS_CARD)
  98                         reg |= MS_INT_EN;
  99         }
 100         if (chip->hw_bypass_sd)
 101                 reg &= ~((u32)SD_INT_EN);
 102 #endif
 103
 104         if (chip->ic_version >= IC_VER_C)
 105                 reg |= DELINK_INT_EN;
 106 #ifdef SUPPORT_OCP
 107         if (CHECK_PID(chip, 0x5209)) {
 108                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
 109                         reg |= MS_OC_INT_EN | SD_OC_INT_EN;
 110                 else
 111                         reg |= SD_OC_INT_EN;
 112         } else {
 113                 reg |= OC_INT_EN;
 114         }
 115 #endif
 116         if (!chip->adma_mode)
 117                 reg |= DATA_DONE_INT_EN;
 118
 119         /* Enable Bus Interrupt */
 120         rtsx_writel(chip, RTSX_BIER, reg);
 121
 122         RTSX_DEBUGP("RTSX_BIER: 0x%08x\n", reg);
 123 }
 124
 125 void rtsx_disable_bus_int(struct rtsx_chip *chip)
 126 {
 127         rtsx_writel(chip, RTSX_BIER, 0);
 128 }
 129
 130 static int rtsx_pre_handle_sdio_old(struct rtsx_chip *chip)
 131 {
 132         if (chip->ignore_sd && CHK_SDIO_EXIST(chip)) {
 133                 if (chip->asic_code) {
 134                         RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
 135                                 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
 136                 } else {
 137                         RTSX_WRITE_REG(chip, FPGA_PULL_CTL, 0xFF, FPGA_SD_PULL_CTL_EN);
 138                 }
 139                 RTSX_WRITE_REG(chip, CARD_SHARE_MODE, 0xFF, CARD_SHARE_48_SD);
 140
 141                 /* Enable SDIO internal clock */
 142                 RTSX_WRITE_REG(chip, 0xFF2C, 0x01, 0x01);
 143
 144                 RTSX_WRITE_REG(chip, SDIO_CTRL, 0xFF, SDIO_BUS_CTRL | SDIO_CD_CTRL);
 145
 146                 chip->sd_int = 1;
 147                 chip->sd_io = 1;
 148         } else {
 149                 chip->need_reset |= SD_CARD;
 150         }
 151
 152         return STATUS_SUCCESS;
 153 }
 154
 155 #ifdef HW_AUTO_SWITCH_SD_BUS
 156 static int rtsx_pre_handle_sdio_new(struct rtsx_chip *chip)
 157 {
 158         u8 tmp;
 159         int sw_bypass_sd = 0;
 160         int retval;
 161
 162         if (chip->driver_first_load) {
 163                 if (CHECK_PID(chip, 0x5288)) {
 164                         RTSX_READ_REG(chip, 0xFE5A, &tmp);
 165                         if (tmp & 0x08)
 166                                 sw_bypass_sd = 1;
 167                 } else if (CHECK_PID(chip, 0x5208)) {
 168                         RTSX_READ_REG(chip, 0xFE70, &tmp);
 169                         if (tmp & 0x80)
 170                                 sw_bypass_sd = 1;
 171                 } else if (CHECK_PID(chip, 0x5209)) {
 172                         RTSX_READ_REG(chip, SDIO_CFG, &tmp);
 173                         if (tmp & SDIO_BUS_AUTO_SWITCH)
 174                                 sw_bypass_sd = 1;
 175                 }
 176         } else {
 177                 if (chip->sdio_in_charge)
 178                         sw_bypass_sd = 1;
 179         }
 180         RTSX_DEBUGP("chip->sdio_in_charge = %d\n", chip->sdio_in_charge);
 181         RTSX_DEBUGP("chip->driver_first_load = %d\n", chip->driver_first_load);
 182         RTSX_DEBUGP("sw_bypass_sd = %d\n", sw_bypass_sd);
 183
 184         if (sw_bypass_sd) {
 185                 u8 cd_toggle_mask = 0;
 186
 187                 RTSX_READ_REG(chip, TLPTISTAT, &tmp);
 188                 if (CHECK_PID(chip, 0x5209))
 189                         cd_toggle_mask = 0x10;
 190                 else
 191                         cd_toggle_mask = 0x08;
 192
 193                 if (tmp & cd_toggle_mask) {
 194                         /* Disable sdio_bus_auto_switch */
 195                         if (CHECK_PID(chip, 0x5288))
 196                                 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x00);
 197                         else if (CHECK_PID(chip, 0x5208))
 198                                 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x00);
 199                         else
 200                                 RTSX_WRITE_REG(chip, SDIO_CFG, SDIO_BUS_AUTO_SWITCH, 0);
 201
 202                         RTSX_WRITE_REG(chip, TLPTISTAT, 0xFF, tmp);
 203
 204                         chip->need_reset |= SD_CARD;
 205                 } else {
 206                         RTSX_DEBUGP("Chip inserted with SDIO!\n");
 207
 208                         if (chip->asic_code) {
 209                                 retval = sd_pull_ctl_enable(chip);
 210                                 if (retval != STATUS_SUCCESS)
 211                                         TRACE_RET(chip, STATUS_FAIL);
 212                         } else {
 213                                 RTSX_WRITE_REG(chip, FPGA_PULL_CTL, FPGA_SD_PULL_CTL_BIT | 0x20, 0);
 214                         }
 215                         retval = card_share_mode(chip, SD_CARD);
 216                         if (retval != STATUS_SUCCESS)
 217                                 TRACE_RET(chip, STATUS_FAIL);
 218
 219                         /* Enable sdio_bus_auto_switch */
 220                         if (CHECK_PID(chip, 0x5288)) {
 221                                 RTSX_WRITE_REG(chip, 0xFE5A, 0x08, 0x08);
 222                         } else if (CHECK_PID(chip, 0x5208)) {
 223                                 RTSX_WRITE_REG(chip, 0xFE70, 0x80, 0x80);
 224                         } else {
 225                                 RTSX_WRITE_REG(chip, SDIO_CFG,
 226                                         SDIO_BUS_AUTO_SWITCH, SDIO_BUS_AUTO_SWITCH);
 227                         }
 228                         chip->chip_insert_with_sdio = 1;
 229                         chip->sd_io = 1;
 230                 }
 231         } else {
 232                 if (CHECK_PID(chip, 0x5209))
 233                         RTSX_WRITE_REG(chip, TLPTISTAT, 0x10, 0x10);
 234                 else
 235                         RTSX_WRITE_REG(chip, TLPTISTAT, 0x08, 0x08);
 236
 237                 chip->need_reset |= SD_CARD;
 238         }
 239
 240         return STATUS_SUCCESS;
 241 }
 242 #endif
 243
 244 int rtsx_reset_chip(struct rtsx_chip *chip)
 245 {
 246         int retval;
 247
 248         rtsx_writel(chip, RTSX_HCBAR, chip->host_cmds_addr);
 249
 250         rtsx_disable_aspm(chip);
 251
 252         if (CHECK_PID(chip, 0x5209) && chip->asic_code) {
 253                 u16 val;
 254
 255                 /* optimize PHY */
 256                 retval = rtsx_write_phy_register(chip, 0x00, 0xB966);
 257                 if (retval != STATUS_SUCCESS)
 258                         TRACE_RET(chip, STATUS_FAIL);
 259
 260                 retval = rtsx_write_phy_register(chip, 0x01, 0x713F);
 261                 if (retval != STATUS_SUCCESS)
 262                         TRACE_RET(chip, STATUS_FAIL);
 263
 264                 retval = rtsx_write_phy_register(chip, 0x03, 0xA549);
 265                 if (retval != STATUS_SUCCESS)
 266                         TRACE_RET(chip, STATUS_FAIL);
 267
 268                 retval = rtsx_write_phy_register(chip, 0x06, 0xB235);
 269                 if (retval != STATUS_SUCCESS)
 270                         TRACE_RET(chip, STATUS_FAIL);
 271
 272                 retval = rtsx_write_phy_register(chip, 0x07, 0xEF40);
 273                 if (retval != STATUS_SUCCESS)
 274                         TRACE_RET(chip, STATUS_FAIL);
 275
 276                 retval = rtsx_write_phy_register(chip, 0x1E, 0xF8EB);
 277                 if (retval != STATUS_SUCCESS)
 278                         TRACE_RET(chip, STATUS_FAIL);
 279
 280                 retval = rtsx_write_phy_register(chip, 0x19, 0xFE6C);
 281                 if (retval != STATUS_SUCCESS)
 282                         TRACE_RET(chip, STATUS_FAIL);
 283
 284                 wait_timeout(1);
 285                 retval = rtsx_write_phy_register(chip, 0x0A, 0x05C0);
 286                 if (retval != STATUS_SUCCESS)
 287                         TRACE_RET(chip, STATUS_FAIL);
 288
 289
 290                 retval = rtsx_write_cfg_dw(chip, 1, 0x110, 0xFFFF, 0xFFFF);
 291                 if (retval != STATUS_SUCCESS)
 292                         TRACE_RET(chip, STATUS_FAIL);
 293
 294                 retval = rtsx_read_phy_register(chip, 0x08, &val);
 295                 if (retval != STATUS_SUCCESS)
 296                         TRACE_RET(chip, STATUS_FAIL);
 297
 298                 RTSX_DEBUGP("Read from phy 0x08: 0x%04x\n", val);
 299
 300                 if (chip->phy_voltage) {
 301                         chip->phy_voltage &= 0x3F;
 302                         RTSX_DEBUGP("chip->phy_voltage = 0x%x\n", chip->phy_voltage);
 303                         val &= ~0x3F;
 304                         val |= chip->phy_voltage;
 305                         RTSX_DEBUGP("Write to phy 0x08: 0x%04x\n", val);
 306                         retval = rtsx_write_phy_register(chip, 0x08, val);
 307                         if (retval != STATUS_SUCCESS)
 308                                 TRACE_RET(chip, STATUS_FAIL);
 309
 310                 } else {
 311                         chip->phy_voltage = (u8)(val & 0x3F);
 312                         RTSX_DEBUGP("Default, chip->phy_voltage = 0x%x\n", chip->phy_voltage);
 313                 }
 314         }
 315
 316         RTSX_WRITE_REG(chip, HOST_SLEEP_STATE, 0x03, 0x00);
 317
 318         /* Disable card clock */
 319         RTSX_WRITE_REG(chip, CARD_CLK_EN, 0x1E, 0);
 320
 321 #ifdef SUPPORT_OCP
 322         /* SSC power on, OCD power on */
 323         if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
 324                 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, 0);
 325         else
 326                 RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, MS_OC_POWER_DOWN);
 327
 328         if (CHECK_PID(chip, 0x5209)) {
 329                 RTSX_WRITE_REG(chip, OCPPARA1, SD_OCP_TIME_MASK | MS_OCP_TIME_MASK,
 330                                     SD_OCP_TIME_800 | MS_OCP_TIME_800);
 331                 RTSX_WRITE_REG(chip, OCPPARA2, SD_OCP_THD_MASK | MS_OCP_THD_MASK,
 332                                     chip->sd_400mA_ocp_thd | (chip->ms_ocp_thd << 4));
 333                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
 334                         RTSX_WRITE_REG(chip, OCPGLITCH, SD_OCP_GLITCH_MASK | MS_OCP_GLITCH_MASK,
 335                                        SD_OCP_GLITCH_10000 | MS_OCP_GLITCH_10000);
 336                 } else {
 337                         RTSX_WRITE_REG(chip, OCPGLITCH, SD_OCP_GLITCH_MASK, SD_OCP_GLITCH_10000);
 338                 }
 339                 RTSX_WRITE_REG(chip, OCPCTL, 0xFF,
 340                                     SD_OCP_INT_EN | SD_DETECT_EN | MS_OCP_INT_EN | MS_DETECT_EN);
 341         } else {
 342                 RTSX_WRITE_REG(chip, OCPPARA1, OCP_TIME_MASK, OCP_TIME_800);
 343                 RTSX_WRITE_REG(chip, OCPPARA2, OCP_THD_MASK, OCP_THD_244_946);
 344                 RTSX_WRITE_REG(chip, OCPCTL, 0xFF, CARD_OC_INT_EN | CARD_DETECT_EN);
 345         }
 346 #else
 347         /* OC power down */
 348         RTSX_WRITE_REG(chip, FPDCTL, OC_POWER_DOWN, OC_POWER_DOWN);
 349 #endif
 350
 351         if (!CHECK_PID(chip, 0x5288))
 352                 RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0xFF, 0x03);
 353
 354         /* Turn off LED */
 355         RTSX_WRITE_REG(chip, CARD_GPIO, 0xFF, 0x03);
 356
 357         /* Reset delink mode */
 358         RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x0A, 0);
 359
 360         /* Card driving select */
 361         RTSX_WRITE_REG(chip, CARD_DRIVE_SEL, 0xFF, chip->card_drive_sel);
 362         if (CHECK_PID(chip, 0x5209))
 363                 RTSX_WRITE_REG(chip, SD30_DRIVE_SEL, 0x07, chip->sd30_drive_sel_3v3);
 364
 365 #ifdef LED_AUTO_BLINK
 366         RTSX_WRITE_REG(chip, CARD_AUTO_BLINK, 0xFF,
 367                         LED_BLINK_SPEED | BLINK_EN | LED_GPIO0);
 368 #endif
 369
 370         if (chip->asic_code) {
 371                 /* Enable SSC Clock */
 372                 RTSX_WRITE_REG(chip, SSC_CTL1, 0xFF, SSC_8X_EN | SSC_SEL_4M);
 373                 RTSX_WRITE_REG(chip, SSC_CTL2, 0xFF, 0x12);
 374         }
 375
 376         /* Disable cd_pwr_save (u_force_rst_core_en=0, u_cd_rst_core_en=0)
 377               0xFE5B
 378               bit[1]    u_cd_rst_core_en        rst_value = 0
 379               bit[2]    u_force_rst_core_en     rst_value = 0
 380               bit[5]    u_mac_phy_rst_n_dbg     rst_value = 1
 381               bit[4]    u_non_sticky_rst_n_dbg  rst_value = 0
 382         */
 383         RTSX_WRITE_REG(chip, CHANGE_LINK_STATE, 0x16, 0x10);
 384
 385         /* Enable ASPM */
 386         if (chip->aspm_l0s_l1_en) {
 387                 if (chip->dynamic_aspm) {
 388                         if (CHK_SDIO_EXIST(chip)) {
 389                                 if (CHECK_PID(chip, 0x5209)) {
 390                                         retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 391                                         if (retval != STATUS_SUCCESS)
 392                                                 TRACE_RET(chip, STATUS_FAIL);
 393
 394                                 } else if (CHECK_PID(chip, 0x5288)) {
 395                                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 396                                         if (retval != STATUS_SUCCESS)
 397                                                 TRACE_RET(chip, STATUS_FAIL);
 398                                 }
 399                         }
 400                 } else {
 401                         if (CHECK_PID(chip, 0x5208))
 402                                 RTSX_WRITE_REG(chip, ASPM_FORCE_CTL, 0xFF, 0x3F);
 403
 404                         retval = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
 405                         if (retval != STATUS_SUCCESS)
 406                                 TRACE_RET(chip, STATUS_FAIL);
 407
 408                         chip->aspm_level[0] = chip->aspm_l0s_l1_en;
 409                         if (CHK_SDIO_EXIST(chip)) {
 410                                 chip->aspm_level[1] = chip->aspm_l0s_l1_en;
 411                                 if (CHECK_PID(chip, 0x5288))
 412                                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 413                                 else
 414                                         retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF, chip->aspm_l0s_l1_en);
 415
 416                                 if (retval != STATUS_SUCCESS)
 417                                         TRACE_RET(chip, STATUS_FAIL);
 418
 419                         }
 420
 421                         chip->aspm_enabled = 1;
 422                 }
 423         } else {
 424                 if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 425                         retval = rtsx_write_phy_register(chip, 0x07, 0x0129);
 426                         if (retval != STATUS_SUCCESS)
 427                                 TRACE_RET(chip, STATUS_FAIL);
 428                 }
 429                 retval = rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
 430                 if (retval != STATUS_SUCCESS)
 431                         TRACE_RET(chip, STATUS_FAIL);
 432         }
 433
 434         retval = rtsx_write_config_byte(chip, 0x81, 1);
 435         if (retval != STATUS_SUCCESS)
 436                 TRACE_RET(chip, STATUS_FAIL);
 437
 438         if (CHK_SDIO_EXIST(chip)) {
 439                 if (CHECK_PID(chip, 0x5288))
 440                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF00, 0x0100);
 441                 else
 442                         retval = rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF00, 0x0100);
 443
 444                 if (retval != STATUS_SUCCESS)
 445                         TRACE_RET(chip, STATUS_FAIL);
 446
 447         }
 448
 449         if (CHECK_PID(chip, 0x5209)) {
 450                 retval = rtsx_write_cfg_dw(chip, 0, 0x70C, 0xFF000000, 0x5B);
 451                 if (retval != STATUS_SUCCESS)
 452                         TRACE_RET(chip, STATUS_FAIL);
 453         }
 454
 455         if (CHECK_PID(chip, 0x5288)) {
 456                 if (!CHK_SDIO_EXIST(chip)) {
 457                         retval = rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, 0x0103);
 458                         if (retval != STATUS_SUCCESS)
 459                                 TRACE_RET(chip, STATUS_FAIL);
 460
 461                         retval = rtsx_write_cfg_dw(chip, 2, 0x84, 0xFF, 0x03);
 462                         if (retval != STATUS_SUCCESS)
 463                                 TRACE_RET(chip, STATUS_FAIL);
 464
 465                 }
 466         }
 467
 468         RTSX_WRITE_REG(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
 469
 470         RTSX_WRITE_REG(chip, PERST_GLITCH_WIDTH, 0xFF, 0x80);
 471
 472         if (CHECK_PID(chip, 0x5209)) {
 473                 RTSX_WRITE_REG(chip, PWD_SUSPEND_EN, 0xFF, 0xFF);
 474                 RTSX_WRITE_REG(chip, PWR_GATE_CTRL, PWR_GATE_EN, PWR_GATE_EN);
 475         }
 476
 477         /* Enable PCIE interrupt */
 478         if (chip->asic_code) {
 479                 if (CHECK_PID(chip, 0x5208)) {
 480                         if (chip->phy_debug_mode) {
 481                                 RTSX_WRITE_REG(chip, CDRESUMECTL, 0x77, 0);
 482                                 rtsx_disable_bus_int(chip);
 483                         } else {
 484                                 rtsx_enable_bus_int(chip);
 485                         }
 486
 487                         if (chip->ic_version >= IC_VER_D) {
 488                                 u16 reg;
 489                                 retval = rtsx_read_phy_register(chip, 0x00, &reg);
 490                                 if (retval != STATUS_SUCCESS)
 491                                         TRACE_RET(chip, STATUS_FAIL);
 492
 493                                 reg &= 0xFE7F;
 494                                 reg |= 0x80;
 495                                 retval = rtsx_write_phy_register(chip, 0x00, reg);
 496                                 if (retval != STATUS_SUCCESS)
 497                                         TRACE_RET(chip, STATUS_FAIL);
 498
 499                                 retval = rtsx_read_phy_register(chip, 0x1C, &reg);
 500                                 if (retval != STATUS_SUCCESS)
 501                                         TRACE_RET(chip, STATUS_FAIL);
 502
 503                                 reg &= 0xFFF7;
 504                                 retval = rtsx_write_phy_register(chip, 0x1C, reg);
 505                                 if (retval != STATUS_SUCCESS)
 506                                         TRACE_RET(chip, STATUS_FAIL);
 507
 508                         }
 509
 510                         if (chip->driver_first_load && (chip->ic_version < IC_VER_C))
 511                                 rtsx_calibration(chip);
 512
 513                 } else {
 514                         rtsx_enable_bus_int(chip);
 515                 }
 516         } else {
 517                 rtsx_enable_bus_int(chip);
 518         }
 519
 520 #ifdef HW_INT_WRITE_CLR
 521         if (CHECK_PID(chip, 0x5209)) {
 522                 /* Set interrupt write clear */
 523                 RTSX_WRITE_REG(chip, NFTS_TX_CTRL, 0x02, 0);
 524         }
 525 #endif
 526
 527         chip->need_reset = 0;
 528
 529         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
 530 #ifdef HW_INT_WRITE_CLR
 531         if (CHECK_PID(chip, 0x5209)) {
 532                 /* Clear interrupt flag */
 533                 rtsx_writel(chip, RTSX_BIPR, chip->int_reg);
 534         }
 535 #endif
 536         if (chip->hw_bypass_sd)
 537                 goto NextCard;
 538         RTSX_DEBUGP("In rtsx_reset_chip, chip->int_reg = 0x%x\n", chip->int_reg);
 539         if (chip->int_reg & SD_EXIST) {
 540 #ifdef HW_AUTO_SWITCH_SD_BUS
 541                 if (CHECK_PID(chip, 0x5208) && (chip->ic_version < IC_VER_C))
 542                         retval = rtsx_pre_handle_sdio_old(chip);
 543                 else
 544                         retval = rtsx_pre_handle_sdio_new(chip);
 545
 546                 RTSX_DEBUGP("chip->need_reset = 0x%x (rtsx_reset_chip)\n", (unsigned int)(chip->need_reset));
 547 #else  /* HW_AUTO_SWITCH_SD_BUS */
 548                 retval = rtsx_pre_handle_sdio_old(chip);
 549 #endif  /* HW_AUTO_SWITCH_SD_BUS */
 550                 if (retval != STATUS_SUCCESS)
 551                         TRACE_RET(chip, STATUS_FAIL);
 552
 553         } else {
 554                 chip->sd_io = 0;
 555                 RTSX_WRITE_REG(chip, SDIO_CTRL, SDIO_BUS_CTRL | SDIO_CD_CTRL, 0);
 556         }
 557
 558 NextCard:
 559         if (chip->int_reg & XD_EXIST)
 560                 chip->need_reset |= XD_CARD;
 561         if (chip->int_reg & MS_EXIST)
 562                 chip->need_reset |= MS_CARD;
 563         if (chip->int_reg & CARD_EXIST)
 564                 RTSX_WRITE_REG(chip, SSC_CTL1, SSC_RSTB, SSC_RSTB);
 565
 566         RTSX_DEBUGP("In rtsx_init_chip, chip->need_reset = 0x%x\n", (unsigned int)(chip->need_reset));
 567
 568         RTSX_WRITE_REG(chip, RCCTL, 0x01, 0x00);
 569
 570         if (CHECK_PID(chip, 0x5208) || CHECK_PID(chip, 0x5288)) {
 571                 /* Turn off main power when entering S3/S4 state */
 572                 RTSX_WRITE_REG(chip, MAIN_PWR_OFF_CTL, 0x03, 0x03);
 573         }
 574
 575         if (chip->remote_wakeup_en && !chip->auto_delink_en) {
 576                 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x07);
 577                 if (chip->aux_pwr_exist)
 578                         RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x33);
 579         } else {
 580                 RTSX_WRITE_REG(chip, WAKE_SEL_CTL, 0x07, 0x04);
 581                 RTSX_WRITE_REG(chip, PME_FORCE_CTL, 0xFF, 0x30);
 582         }
 583
 584         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
 585                 RTSX_WRITE_REG(chip, PETXCFG, 0x1C, 0x14);
 586         } else if (CHECK_PID(chip, 0x5209)) {
 587                 if (chip->force_clkreq_0)
 588                         RTSX_WRITE_REG(chip, PETXCFG, 0x08, 0x08);
 589                 else
 590                         RTSX_WRITE_REG(chip, PETXCFG, 0x08, 0x00);
 591         }
 592
 593         if (chip->asic_code && CHECK_PID(chip, 0x5208)) {
 594                 retval = rtsx_clr_phy_reg_bit(chip, 0x1C, 2);
 595                 if (retval != STATUS_SUCCESS)
 596                         TRACE_RET(chip, STATUS_FAIL);
 597         }
 598
 599         if (chip->ft2_fast_mode) {
 600                 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, MS_PARTIAL_POWER_ON | SD_PARTIAL_POWER_ON);
 601                 udelay(chip->pmos_pwr_on_interval);
 602                 RTSX_WRITE_REG(chip, CARD_PWR_CTL, 0xFF, MS_POWER_ON | SD_POWER_ON);
 603
 604                 wait_timeout(200);
 605         }
 606
 607         /* Reset card */
 608         rtsx_reset_detected_cards(chip, 0);
 609
 610         chip->driver_first_load = 0;
 611
 612         return STATUS_SUCCESS;
 613 }
 614
 615 static inline int check_sd_speed_prior(u32 sd_speed_prior)
 616 {
 617         int i, fake_para = 0;
 618
 619         for (i = 0; i < 4; i++) {
 620                 u8 tmp = (u8)(sd_speed_prior >> (i*8));
 621                 if ((tmp < 0x01) || (tmp > 0x04)) {
 622                         fake_para = 1;
 623                         break;
 624                 }
 625         }
 626
 627         return !fake_para;
 628 }
 629
 630 static inline int check_sd_current_prior(u32 sd_current_prior)
 631 {
 632         int i, fake_para = 0;
 633
 634         for (i = 0; i < 4; i++) {
 635                 u8 tmp = (u8)(sd_current_prior >> (i*8));
 636                 if (tmp > 0x03) {
 637                         fake_para = 1;
 638                         break;
 639                 }
 640         }
 641
 642         return !fake_para;
 643 }
 644
 645 static int rts5209_init(struct rtsx_chip *chip)
 646 {
 647         int retval;
 648         u32 lval = 0;
 649         u8 val = 0;
 650
 651         val = rtsx_readb(chip, 0x1C);
 652         if ((val & 0x10) == 0)
 653                 chip->asic_code = 1;
 654         else
 655                 chip->asic_code = 0;
 656
 657         chip->ic_version = val & 0x0F;
 658         chip->phy_debug_mode = 0;
 659
 660         chip->aux_pwr_exist = 0;
 661
 662         chip->ms_power_class_en = 0x03;
 663
 664         retval = rtsx_read_cfg_dw(chip, 0, 0x724, &lval);
 665         if (retval != STATUS_SUCCESS)
 666                 TRACE_RET(chip, STATUS_FAIL);
 667
 668         RTSX_DEBUGP("dw in 0x724: 0x%x\n", lval);
 669         val = (u8)lval;
 670         if (!(val & 0x80)) {
 671                 if (val & 0x08)
 672                         chip->lun_mode = DEFAULT_SINGLE;
 673                 else
 674                         chip->lun_mode = SD_MS_2LUN;
 675
 676                 if (val & 0x04)
 677                         SET_SDIO_EXIST(chip);
 678                 else
 679                         CLR_SDIO_EXIST(chip);
 680
 681                 if (val & 0x02)
 682                         chip->hw_bypass_sd = 0;
 683                 else
 684                         chip->hw_bypass_sd = 1;
 685
 686         } else {
 687                 SET_SDIO_EXIST(chip);
 688                 chip->hw_bypass_sd = 0;
 689         }
 690
 691         if (chip->use_hw_setting) {
 692                 u8 clk;
 693
 694                 chip->aspm_l0s_l1_en = (val >> 5) & 0x03;
 695
 696                 val = (u8)(lval >> 8);
 697
 698                 clk = (val >> 5) & 0x07;
 699                 if (clk != 0x07)
 700                         chip->asic_sd_sdr50_clk = 98 - clk * 2;
 701
 702                 if (val & 0x10)
 703                         chip->auto_delink_en = 1;
 704                 else
 705                         chip->auto_delink_en = 0;
 706
 707                 if (chip->ss_en == 2) {
 708                         chip->ss_en = 0;
 709                 } else {
 710                         if (val & 0x08)
 711                                 chip->ss_en = 1;
 712                         else
 713                                 chip->ss_en = 0;
 714                 }
 715
 716                 clk = val & 0x07;
 717                 if (clk != 0x07)
 718                         chip->asic_ms_hg_clk = (59 - clk) * 2;
 719
 720                 val = (u8)(lval >> 16);
 721
 722                 clk = (val >> 6) & 0x03;
 723                 if (clk != 0x03) {
 724                         chip->asic_sd_hs_clk = (49 - clk * 2) * 2;
 725                         chip->asic_mmc_52m_clk = (49 - clk * 2) * 2;
 726                 }
 727
 728                 clk = (val >> 4) & 0x03;
 729                 if (clk != 0x03)
 730                         chip->asic_sd_ddr50_clk = (48 - clk * 2) * 2;
 731
 732                 if (val & 0x01)
 733                         chip->sdr104_en = 1;
 734                 else
 735                         chip->sdr104_en = 0;
 736
 737                 if (val & 0x02)
 738                         chip->ddr50_en = 1;
 739                 else
 740                         chip->ddr50_en = 0;
 741
 742                 if (val & 0x04)
 743                         chip->sdr50_en = 1;
 744                 else
 745                         chip->sdr50_en = 0;
 746
 747
 748                 val = (u8)(lval >> 24);
 749
 750                 clk = (val >> 5) & 0x07;
 751                 if (clk != 0x07)
 752                         chip->asic_sd_sdr104_clk = 206 - clk * 3;
 753
 754                 if (val & 0x10)
 755                         chip->power_down_in_ss = 1;
 756                 else
 757                         chip->power_down_in_ss = 0;
 758
 759                 chip->ms_power_class_en = val & 0x03;
 760         }
 761
 762         if (chip->hp_watch_bios_hotplug && chip->auto_delink_en) {
 763                 u8 reg58, reg5b;
 764
 765                 retval = rtsx_read_pci_cfg_byte(0x00,
 766                                                 0x1C, 0x02, 0x58, &reg58);
 767                 if (retval < 0)
 768                         return STATUS_SUCCESS;
 769
 770                 retval = rtsx_read_pci_cfg_byte(0x00,
 771                                                 0x1C, 0x02, 0x5B, &reg5b);
 772                 if (retval < 0)
 773                         return STATUS_SUCCESS;
 774
 775                 RTSX_DEBUGP("reg58 = 0x%x, reg5b = 0x%x\n", reg58, reg5b);
 776
 777                 if ((reg58 == 0x00) && (reg5b == 0x01))
 778                         chip->auto_delink_en = 0;
 779
 780         }
 781
 782         return STATUS_SUCCESS;
 783 }
 784
 785 static int rts5208_init(struct rtsx_chip *chip)
 786 {
 787         int retval;
 788         u16 reg = 0;
 789         u8 val = 0;
 790
 791         RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03);
 792         RTSX_READ_REG(chip, CLK_SEL, &val);
 793         if (val == 0)
 794                 chip->asic_code = 1;
 795         else
 796                 chip->asic_code = 0;
 797
 798         if (chip->asic_code) {
 799                 retval = rtsx_read_phy_register(chip, 0x1C, &reg);
 800                 if (retval != STATUS_SUCCESS)
 801                         TRACE_RET(chip, STATUS_FAIL);
 802
 803                 RTSX_DEBUGP("Value of phy register 0x1C is 0x%x\n", reg);
 804                 chip->ic_version = (reg >> 4) & 0x07;
 805                 if (reg & PHY_DEBUG_MODE)
 806                         chip->phy_debug_mode = 1;
 807                 else
 808                         chip->phy_debug_mode = 0;
 809
 810         } else {
 811                 RTSX_READ_REG(chip, 0xFE80, &val);
 812                 chip->ic_version = val;
 813                 chip->phy_debug_mode = 0;
 814         }
 815
 816         RTSX_READ_REG(chip, PDINFO, &val);
 817         RTSX_DEBUGP("PDINFO: 0x%x\n", val);
 818         if (val & AUX_PWR_DETECTED)
 819                 chip->aux_pwr_exist = 1;
 820         else
 821                 chip->aux_pwr_exist = 0;
 822
 823         RTSX_READ_REG(chip, 0xFE50, &val);
 824         if (val & 0x01)
 825                 chip->hw_bypass_sd = 1;
 826         else
 827                 chip->hw_bypass_sd = 0;
 828
 829         rtsx_read_config_byte(chip, 0x0E, &val);
 830         if (val & 0x80)
 831                 SET_SDIO_EXIST(chip);
 832         else
 833                 CLR_SDIO_EXIST(chip);
 834
 835         if (chip->use_hw_setting) {
 836                 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val);
 837                 if (val & 0x80)
 838                         chip->auto_delink_en = 1;
 839                 else
 840                         chip->auto_delink_en = 0;
 841         }
 842
 843         return STATUS_SUCCESS;
 844 }
 845
 846 static int rts5288_init(struct rtsx_chip *chip)
 847 {
 848         int retval;
 849         u8 val = 0, max_func;
 850         u32 lval = 0;
 851
 852         RTSX_WRITE_REG(chip, CLK_SEL, 0x03, 0x03);
 853         RTSX_READ_REG(chip, CLK_SEL, &val);
 854         if (val == 0)
 855                 chip->asic_code = 1;
 856         else
 857                 chip->asic_code = 0;
 858
 859         chip->ic_version = 0;
 860         chip->phy_debug_mode = 0;
 861
 862         RTSX_READ_REG(chip, PDINFO, &val);
 863         RTSX_DEBUGP("PDINFO: 0x%x\n", val);
 864         if (val & AUX_PWR_DETECTED)
 865                 chip->aux_pwr_exist = 1;
 866         else
 867                 chip->aux_pwr_exist = 0;
 868
 869         RTSX_READ_REG(chip, CARD_SHARE_MODE, &val);
 870         RTSX_DEBUGP("CARD_SHARE_MODE: 0x%x\n", val);
 871         if (val & 0x04)
 872                 chip->baro_pkg = QFN;
 873         else
 874                 chip->baro_pkg = LQFP;
 875
 876         RTSX_READ_REG(chip, 0xFE5A, &val);
 877         if (val & 0x10)
 878                 chip->hw_bypass_sd = 1;
 879         else
 880                 chip->hw_bypass_sd = 0;
 881
 882         retval = rtsx_read_cfg_dw(chip, 0, 0x718, &lval);
 883         if (retval != STATUS_SUCCESS)
 884                 TRACE_RET(chip, STATUS_FAIL);
 885
 886         max_func = (u8)((lval >> 29) & 0x07);
 887         RTSX_DEBUGP("Max function number: %d\n", max_func);
 888         if (max_func == 0x02)
 889                 SET_SDIO_EXIST(chip);
 890         else
 891                 CLR_SDIO_EXIST(chip);
 892
 893         if (chip->use_hw_setting) {
 894                 RTSX_READ_REG(chip, CHANGE_LINK_STATE, &val);
 895                 if (val & 0x80)
 896                         chip->auto_delink_en = 1;
 897                 else
 898                         chip->auto_delink_en = 0;
 899
 900                 if (CHECK_BARO_PKG(chip, LQFP))
 901                         chip->lun_mode = SD_MS_1LUN;
 902                 else
 903                         chip->lun_mode = DEFAULT_SINGLE;
 904
 905         }
 906
 907         return STATUS_SUCCESS;
 908 }
 909
 910 int rtsx_init_chip(struct rtsx_chip *chip)
 911 {
 912         struct sd_info *sd_card = &(chip->sd_card);
 913         struct xd_info *xd_card = &(chip->xd_card);
 914         struct ms_info *ms_card = &(chip->ms_card);
 915         int retval;
 916         unsigned int i;
 917
 918         RTSX_DEBUGP("Vendor ID: 0x%04x, Product ID: 0x%04x\n",
 919                      chip->vendor_id, chip->product_id);
 920
 921         chip->ic_version = 0;
 922
 923 #ifdef _MSG_TRACE
 924         chip->msg_idx = 0;
 925 #endif
 926
 927         memset(xd_card, 0, sizeof(struct xd_info));
 928         memset(sd_card, 0, sizeof(struct sd_info));
 929         memset(ms_card, 0, sizeof(struct ms_info));
 930
 931         chip->xd_reset_counter = 0;
 932         chip->sd_reset_counter = 0;
 933         chip->ms_reset_counter = 0;
 934
 935         chip->xd_show_cnt = MAX_SHOW_CNT;
 936         chip->sd_show_cnt = MAX_SHOW_CNT;
 937         chip->ms_show_cnt = MAX_SHOW_CNT;
 938
 939         chip->sd_io = 0;
 940         chip->auto_delink_cnt = 0;
 941         chip->auto_delink_allowed = 1;
 942         rtsx_set_stat(chip, RTSX_STAT_INIT);
 943
 944         chip->aspm_enabled = 0;
 945         chip->chip_insert_with_sdio = 0;
 946         chip->sdio_aspm = 0;
 947         chip->sdio_idle = 0;
 948         chip->sdio_counter = 0;
 949         chip->cur_card = 0;
 950         chip->phy_debug_mode = 0;
 951         chip->sdio_func_exist = 0;
 952         memset(chip->sdio_raw_data, 0, 12);
 953
 954         for (i = 0; i < MAX_ALLOWED_LUN_CNT; i++) {
 955                 set_sense_type(chip, i, SENSE_TYPE_NO_SENSE);
 956                 chip->rw_fail_cnt[i] = 0;
 957         }
 958
 959         if (!check_sd_speed_prior(chip->sd_speed_prior))
 960                 chip->sd_speed_prior = 0x01040203;
 961
 962         RTSX_DEBUGP("sd_speed_prior = 0x%08x\n", chip->sd_speed_prior);
 963
 964         if (!check_sd_current_prior(chip->sd_current_prior))
 965                 chip->sd_current_prior = 0x00010203;
 966
 967         RTSX_DEBUGP("sd_current_prior = 0x%08x\n", chip->sd_current_prior);
 968
 969         if ((chip->sd_ddr_tx_phase > 31) || (chip->sd_ddr_tx_phase < 0))
 970                 chip->sd_ddr_tx_phase = 0;
 971
 972         if ((chip->mmc_ddr_tx_phase > 31) || (chip->mmc_ddr_tx_phase < 0))
 973                 chip->mmc_ddr_tx_phase = 0;
 974
 975         RTSX_WRITE_REG(chip, FPDCTL, SSC_POWER_DOWN, 0);
 976         wait_timeout(200);
 977         RTSX_WRITE_REG(chip, CLK_DIV, 0x07, 0x07);
 978         RTSX_DEBUGP("chip->use_hw_setting = %d\n", chip->use_hw_setting);
 979
 980         if (CHECK_PID(chip, 0x5209)) {
 981                 retval = rts5209_init(chip);
 982                 if (retval != STATUS_SUCCESS)
 983                         TRACE_RET(chip, STATUS_FAIL);
 984
 985         } else if (CHECK_PID(chip, 0x5208)) {
 986                 retval = rts5208_init(chip);
 987                 if (retval != STATUS_SUCCESS)
 988                         TRACE_RET(chip, STATUS_FAIL);
 989
 990         } else if (CHECK_PID(chip, 0x5288)) {
 991                 retval = rts5288_init(chip);
 992                 if (retval != STATUS_SUCCESS)
 993                         TRACE_RET(chip, STATUS_FAIL);
 994
 995         }
 996
 997         if (chip->ss_en == 2)
 998                 chip->ss_en = 0;
 999
1000         RTSX_DEBUGP("chip->asic_code = %d\n", chip->asic_code);
1001         RTSX_DEBUGP("chip->ic_version = 0x%x\n", chip->ic_version);
1002         RTSX_DEBUGP("chip->phy_debug_mode = %d\n", chip->phy_debug_mode);
1003         RTSX_DEBUGP("chip->aux_pwr_exist = %d\n", chip->aux_pwr_exist);
1004         RTSX_DEBUGP("chip->sdio_func_exist = %d\n", chip->sdio_func_exist);
1005         RTSX_DEBUGP("chip->hw_bypass_sd = %d\n", chip->hw_bypass_sd);
1006         RTSX_DEBUGP("chip->aspm_l0s_l1_en = %d\n", chip->aspm_l0s_l1_en);
1007         RTSX_DEBUGP("chip->lun_mode = %d\n", chip->lun_mode);
1008         RTSX_DEBUGP("chip->auto_delink_en = %d\n", chip->auto_delink_en);
1009         RTSX_DEBUGP("chip->ss_en = %d\n", chip->ss_en);
1010         RTSX_DEBUGP("chip->baro_pkg = %d\n", chip->baro_pkg);
1011
1012         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1013                 chip->card2lun[SD_CARD] = 0;
1014                 chip->card2lun[MS_CARD] = 1;
1015                 chip->card2lun[XD_CARD] = 0xFF;
1016                 chip->lun2card[0] = SD_CARD;
1017                 chip->lun2card[1] = MS_CARD;
1018                 chip->max_lun = 1;
1019                 SET_SDIO_IGNORED(chip);
1020         } else if (CHECK_LUN_MODE(chip, SD_MS_1LUN)) {
1021                 chip->card2lun[SD_CARD] = 0;
1022                 chip->card2lun[MS_CARD] = 0;
1023                 chip->card2lun[XD_CARD] = 0xFF;
1024                 chip->lun2card[0] = SD_CARD | MS_CARD;
1025                 chip->max_lun = 0;
1026         } else {
1027                 chip->card2lun[XD_CARD] = 0;
1028                 chip->card2lun[SD_CARD] = 0;
1029                 chip->card2lun[MS_CARD] = 0;
1030                 chip->lun2card[0] = XD_CARD | SD_CARD | MS_CARD;
1031                 chip->max_lun = 0;
1032         }
1033
1034         retval = rtsx_reset_chip(chip);
1035         if (retval != STATUS_SUCCESS)
1036                 TRACE_RET(chip, STATUS_FAIL);
1037
1038         return STATUS_SUCCESS;
1039 }
1040
1041 void rtsx_release_chip(struct rtsx_chip *chip)
1042 {
1043         xd_free_l2p_tbl(chip);
1044         ms_free_l2p_tbl(chip);
1045         chip->card_exist = 0;
1046         chip->card_ready = 0;
1047 }
1048
1049 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1050 static inline void rtsx_blink_led(struct rtsx_chip *chip)
1051 {
1052         if (chip->card_exist && chip->blink_led) {
1053                 if (chip->led_toggle_counter < LED_TOGGLE_INTERVAL) {
1054                         chip->led_toggle_counter++;
1055                 } else {
1056                         chip->led_toggle_counter = 0;
1057                         toggle_gpio(chip, LED_GPIO);
1058                 }
1059         }
1060 }
1061 #endif
1062
1063 static void rtsx_monitor_aspm_config(struct rtsx_chip *chip)
1064 {
1065         int maybe_support_aspm, reg_changed;
1066         u32 tmp = 0;
1067         u8 reg0 = 0, reg1 = 0;
1068
1069         maybe_support_aspm = 0;
1070         reg_changed = 0;
1071         rtsx_read_config_byte(chip, LCTLR, &reg0);
1072         if (chip->aspm_level[0] != reg0) {
1073                 reg_changed = 1;
1074                 chip->aspm_level[0] = reg0;
1075         }
1076         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1077                 rtsx_read_cfg_dw(chip, 1, 0xC0, &tmp);
1078                 reg1 = (u8)tmp;
1079                 if (chip->aspm_level[1] != reg1) {
1080                         reg_changed = 1;
1081                         chip->aspm_level[1] = reg1;
1082                 }
1083
1084                 if ((reg0 & 0x03) && (reg1 & 0x03))
1085                         maybe_support_aspm = 1;
1086
1087         } else {
1088                 if (reg0 & 0x03)
1089                         maybe_support_aspm = 1;
1090
1091         }
1092
1093         if (reg_changed) {
1094                 if (maybe_support_aspm)
1095                         chip->aspm_l0s_l1_en = 0x03;
1096
1097                 RTSX_DEBUGP("aspm_level[0] = 0x%02x, aspm_level[1] = 0x%02x\n",
1098                               chip->aspm_level[0], chip->aspm_level[1]);
1099
1100                 if (chip->aspm_l0s_l1_en) {
1101                         chip->aspm_enabled = 1;
1102                 } else {
1103                         chip->aspm_enabled = 0;
1104                         chip->sdio_aspm = 0;
1105                 }
1106                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xFF,
1107                         0x30 | chip->aspm_level[0] | (chip->aspm_level[1] << 2));
1108         }
1109 }
1110
1111 void rtsx_polling_func(struct rtsx_chip *chip)
1112 {
1113 #ifdef SUPPORT_SD_LOCK
1114         struct sd_info *sd_card = &(chip->sd_card);
1115 #endif
1116         int ss_allowed;
1117
1118         if (rtsx_chk_stat(chip, RTSX_STAT_SUSPEND))
1119                 return;
1120
1121         if (rtsx_chk_stat(chip, RTSX_STAT_DELINK))
1122                 goto Delink_Stage;
1123
1124         if (chip->polling_config) {
1125                 u8 val;
1126                 rtsx_read_config_byte(chip, 0, &val);
1127         }
1128
1129         if (rtsx_chk_stat(chip, RTSX_STAT_SS))
1130                 return;
1131
1132 #ifdef SUPPORT_OCP
1133         if (chip->ocp_int) {
1134                 rtsx_read_register(chip, OCPSTAT, &(chip->ocp_stat));
1135
1136                 if (CHECK_PID(chip, 0x5209) &&
1137                                 CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1138                         if (chip->ocp_int & SD_OC_INT)
1139                                 sd_power_off_card3v3(chip);
1140                         if (chip->ocp_int & MS_OC_INT)
1141                                 ms_power_off_card3v3(chip);
1142                 } else {
1143                         if (chip->card_exist & SD_CARD)
1144                                 sd_power_off_card3v3(chip);
1145                         else if (chip->card_exist & MS_CARD)
1146                                 ms_power_off_card3v3(chip);
1147                         else if (chip->card_exist & XD_CARD)
1148                                 xd_power_off_card3v3(chip);
1149
1150                 }
1151
1152                 chip->ocp_int = 0;
1153         }
1154 #endif
1155
1156 #ifdef SUPPORT_SD_LOCK
1157         if (sd_card->sd_erase_status) {
1158                 if (chip->card_exist & SD_CARD) {
1159                         u8 val;
1160                         if (CHECK_PID(chip, 0x5209)) {
1161                                 rtsx_read_register(chip, SD_BUS_STAT, &val);
1162                                 if (val & SD_DAT0_STATUS) {
1163                                         sd_card->sd_erase_status = SD_NOT_ERASE;
1164                                         sd_card->sd_lock_notify = 1;
1165                                         chip->need_reinit |= SD_CARD;
1166                                 }
1167                         } else {
1168                                 rtsx_read_register(chip, 0xFD30, &val);
1169                                 if (val & 0x02) {
1170                                         sd_card->sd_erase_status = SD_NOT_ERASE;
1171                                         sd_card->sd_lock_notify = 1;
1172                                         chip->need_reinit |= SD_CARD;
1173                                 }
1174                         }
1175                 } else {
1176                         sd_card->sd_erase_status = SD_NOT_ERASE;
1177                 }
1178         }
1179 #endif
1180
1181         rtsx_init_cards(chip);
1182
1183         if (chip->ss_en) {
1184                 ss_allowed = 1;
1185
1186                 if (CHECK_PID(chip, 0x5288)) {
1187                         ss_allowed = 0;
1188                 } else {
1189                         if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip)) {
1190                                 u32 val;
1191                                 rtsx_read_cfg_dw(chip, 1, 0x04, &val);
1192                                 if (val & 0x07)
1193                                         ss_allowed = 0;
1194
1195                         }
1196                 }
1197         } else {
1198                 ss_allowed = 0;
1199         }
1200
1201         if (ss_allowed && !chip->sd_io) {
1202                 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1203                         chip->ss_counter = 0;
1204                 } else {
1205                         if (chip->ss_counter <
1206                                 (chip->ss_idle_period / POLLING_INTERVAL)) {
1207                                 chip->ss_counter++;
1208                         } else {
1209                                 rtsx_exclusive_enter_ss(chip);
1210                                 return;
1211                         }
1212                 }
1213         }
1214
1215         if (CHECK_PID(chip, 0x5208)) {
1216                 rtsx_monitor_aspm_config(chip);
1217
1218 #ifdef SUPPORT_SDIO_ASPM
1219                 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) &&
1220                                 chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
1221                         if (chip->sd_io) {
1222                                 dynamic_configure_sdio_aspm(chip);
1223                         } else {
1224                                 if (!chip->sdio_aspm) {
1225                                         RTSX_DEBUGP("SDIO enter ASPM!\n");
1226                                         rtsx_write_register(chip,
1227                                                 ASPM_FORCE_CTL, 0xFC,
1228                                                 0x30 | (chip->aspm_level[1] << 2));
1229                                         chip->sdio_aspm = 1;
1230                                 }
1231                         }
1232                 }
1233 #endif
1234         }
1235
1236         if (chip->idle_counter < IDLE_MAX_COUNT) {
1237                 chip->idle_counter++;
1238         } else {
1239                 if (rtsx_get_stat(chip) != RTSX_STAT_IDLE) {
1240                         RTSX_DEBUGP("Idle state!\n");
1241                         rtsx_set_stat(chip, RTSX_STAT_IDLE);
1242
1243 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1244                         chip->led_toggle_counter = 0;
1245 #endif
1246                         rtsx_force_power_on(chip, SSC_PDCTL);
1247
1248                         turn_off_led(chip, LED_GPIO);
1249
1250                         if (chip->auto_power_down && !chip->card_ready && !chip->sd_io)
1251                                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1252
1253                 }
1254         }
1255
1256         switch (rtsx_get_stat(chip)) {
1257         case RTSX_STAT_RUN:
1258 #if !defined(LED_AUTO_BLINK) && defined(REGULAR_BLINK)
1259                 rtsx_blink_led(chip);
1260 #endif
1261                 do_remaining_work(chip);
1262                 break;
1263
1264         case RTSX_STAT_IDLE:
1265                 if (chip->sd_io && !chip->sd_int)
1266                         try_to_switch_sdio_ctrl(chip);
1267
1268                 rtsx_enable_aspm(chip);
1269                 break;
1270
1271         default:
1272                 break;
1273         }
1274
1275
1276 #ifdef SUPPORT_OCP
1277         if (CHECK_LUN_MODE(chip, SD_MS_2LUN)) {
1278 #ifdef CONFIG_RTS_PSTOR_DEBUG
1279                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER | MS_OC_NOW | MS_OC_EVER))
1280                         RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
1281 #endif
1282
1283                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
1284                         if (chip->card_exist & SD_CARD) {
1285                                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1286                                 card_power_off(chip, SD_CARD);
1287                                 chip->card_fail |= SD_CARD;
1288                         }
1289                 }
1290                 if (chip->ocp_stat & (MS_OC_NOW | MS_OC_EVER)) {
1291                         if (chip->card_exist & MS_CARD) {
1292                                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1293                                 card_power_off(chip, MS_CARD);
1294                                 chip->card_fail |= MS_CARD;
1295                         }
1296                 }
1297         } else {
1298                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
1299                         RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n", chip->ocp_stat);
1300                         if (chip->card_exist & SD_CARD) {
1301                                 rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
1302                                 chip->card_fail |= SD_CARD;
1303                         } else if (chip->card_exist & MS_CARD) {
1304                                 rtsx_write_register(chip, CARD_OE, MS_OUTPUT_EN, 0);
1305                                 chip->card_fail |= MS_CARD;
1306                         } else if (chip->card_exist & XD_CARD) {
1307                                 rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
1308                                 chip->card_fail |= XD_CARD;
1309                         }
1310                         card_power_off(chip, SD_CARD);
1311                 }
1312         }
1313 #endif
1314
1315 Delink_Stage:
1316         if (chip->auto_delink_en && chip->auto_delink_allowed &&
1317                         !chip->card_ready && !chip->card_ejected && !chip->sd_io) {
1318                 int enter_L1 = chip->auto_delink_in_L1 && (chip->aspm_l0s_l1_en || chip->ss_en);
1319                 int delink_stage1_cnt = chip->delink_stage1_step;
1320                 int delink_stage2_cnt = delink_stage1_cnt + chip->delink_stage2_step;
1321                 int delink_stage3_cnt = delink_stage2_cnt + chip->delink_stage3_step;
1322
1323                 if (chip->auto_delink_cnt <= delink_stage3_cnt) {
1324                         if (chip->auto_delink_cnt == delink_stage1_cnt) {
1325                                 rtsx_set_stat(chip, RTSX_STAT_DELINK);
1326
1327                                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1328                                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1329
1330                                 if (chip->card_exist) {
1331                                         RTSX_DEBUGP("False card inserted, do force delink\n");
1332
1333                                         if (enter_L1)
1334                                                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1335
1336                                         rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A);
1337
1338                                         if (enter_L1)
1339                                                 rtsx_enter_L1(chip);
1340
1341                                         chip->auto_delink_cnt = delink_stage3_cnt + 1;
1342                                 } else {
1343                                         RTSX_DEBUGP("No card inserted, do delink\n");
1344
1345                                         if (enter_L1)
1346                                                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, 1);
1347
1348 #ifdef HW_INT_WRITE_CLR
1349                                         if (CHECK_PID(chip, 0x5209)) {
1350                                                 rtsx_writel(chip, RTSX_BIPR, 0xFFFFFFFF);
1351                                                 RTSX_DEBUGP("RTSX_BIPR: 0x%x\n", rtsx_readl(chip, RTSX_BIPR));
1352                                         }
1353 #endif
1354                                         rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0x02);
1355
1356                                         if (enter_L1)
1357                                                 rtsx_enter_L1(chip);
1358
1359                                 }
1360                         }
1361
1362                         if (chip->auto_delink_cnt == delink_stage2_cnt) {
1363                                 RTSX_DEBUGP("Try to do force delink\n");
1364
1365                                 if (enter_L1)
1366                                         rtsx_exit_L1(chip);
1367
1368                                 if (chip->asic_code && CHECK_PID(chip, 0x5208))
1369                                         rtsx_set_phy_reg_bit(chip, 0x1C, 2);
1370
1371                                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x0A);
1372                         }
1373
1374                         chip->auto_delink_cnt++;
1375                 }
1376         } else {
1377                 chip->auto_delink_cnt = 0;
1378         }
1379 }
1380
1381 void rtsx_undo_delink(struct rtsx_chip *chip)
1382 {
1383         chip->auto_delink_allowed = 0;
1384         rtsx_write_register(chip, CHANGE_LINK_STATE, 0x0A, 0x00);
1385 }
1386
1387 /**
1388  * rtsx_stop_cmd - stop command transfer and DMA transfer
1389  * @chip: Realtek's card reader chip
1390  * @card: flash card type
1391  *
1392  * Stop command transfer and DMA transfer.
1393  * This function is called in error handler.
1394  */
1395 void rtsx_stop_cmd(struct rtsx_chip *chip, int card)
1396 {
1397         int i;
1398
1399         for (i = 0; i <= 8; i++) {
1400                 int addr = RTSX_HCBAR + i * 4;
1401                 u32 reg;
1402                 reg = rtsx_readl(chip, addr);
1403                 RTSX_DEBUGP("BAR (0x%02x): 0x%08x\n", addr, reg);
1404         }
1405         rtsx_writel(chip, RTSX_HCBCTLR, STOP_CMD);
1406         rtsx_writel(chip, RTSX_HDBCTLR, STOP_DMA);
1407
1408         for (i = 0; i < 16; i++) {
1409                 u16 addr = 0xFE20 + (u16)i;
1410                 u8 val;
1411                 rtsx_read_register(chip, addr, &val);
1412                 RTSX_DEBUGP("0x%04X: 0x%02x\n", addr, val);
1413         }
1414
1415         rtsx_write_register(chip, DMACTL, 0x80, 0x80);
1416         rtsx_write_register(chip, RBCTL, 0x80, 0x80);
1417 }
1418
1419 #define MAX_RW_REG_CNT          1024
1420
1421 int rtsx_write_register(struct rtsx_chip *chip, u16 addr, u8 mask, u8 data)
1422 {
1423         int i;
1424         u32 val = 3 << 30;
1425
1426         val |= (u32)(addr & 0x3FFF) << 16;
1427         val |= (u32)mask << 8;
1428         val |= (u32)data;
1429
1430         rtsx_writel(chip, RTSX_HAIMR, val);
1431
1432         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1433                 val = rtsx_readl(chip, RTSX_HAIMR);
1434                 if ((val & (1 << 31)) == 0) {
1435                         if (data != (u8)val)
1436                                 TRACE_RET(chip, STATUS_FAIL);
1437
1438                         return STATUS_SUCCESS;
1439                 }
1440         }
1441
1442         TRACE_RET(chip, STATUS_TIMEDOUT);
1443 }
1444
1445 int rtsx_read_register(struct rtsx_chip *chip, u16 addr, u8 *data)
1446 {
1447         u32 val = 2 << 30;
1448         int i;
1449
1450         if (data)
1451                 *data = 0;
1452
1453         val |= (u32)(addr & 0x3FFF) << 16;
1454
1455         rtsx_writel(chip, RTSX_HAIMR, val);
1456
1457         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1458                 val = rtsx_readl(chip, RTSX_HAIMR);
1459                 if ((val & (1 << 31)) == 0)
1460                         break;
1461         }
1462
1463         if (i >= MAX_RW_REG_CNT)
1464                 TRACE_RET(chip, STATUS_TIMEDOUT);
1465
1466         if (data)
1467                 *data = (u8)(val & 0xFF);
1468
1469         return STATUS_SUCCESS;
1470 }
1471
1472 int rtsx_write_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 mask, u32 val)
1473 {
1474         u8 mode = 0, tmp;
1475         int i;
1476
1477         for (i = 0; i < 4; i++) {
1478                 if (mask & 0xFF) {
1479                         RTSX_WRITE_REG(chip, CFGDATA0 + i,
1480                                        0xFF, (u8)(val & mask & 0xFF));
1481                         mode |= (1 << i);
1482                 }
1483                 mask >>= 8;
1484                 val >>= 8;
1485         }
1486
1487         if (mode) {
1488                 RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr);
1489                 RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1490
1491                 RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF,
1492                                0x80 | mode | ((func_no & 0x03) << 4));
1493
1494                 for (i = 0; i < MAX_RW_REG_CNT; i++) {
1495                         RTSX_READ_REG(chip, CFGRWCTL, &tmp);
1496                         if ((tmp & 0x80) == 0)
1497                                 break;
1498                 }
1499         }
1500
1501         return STATUS_SUCCESS;
1502 }
1503
1504 int rtsx_read_cfg_dw(struct rtsx_chip *chip, u8 func_no, u16 addr, u32 *val)
1505 {
1506         int i;
1507         u8 tmp;
1508         u32 data = 0;
1509
1510         RTSX_WRITE_REG(chip, CFGADDR0, 0xFF, (u8)addr);
1511         RTSX_WRITE_REG(chip, CFGADDR1, 0xFF, (u8)(addr >> 8));
1512         RTSX_WRITE_REG(chip, CFGRWCTL, 0xFF, 0x80 | ((func_no & 0x03) << 4));
1513
1514         for (i = 0; i < MAX_RW_REG_CNT; i++) {
1515                 RTSX_READ_REG(chip, CFGRWCTL, &tmp);
1516                 if ((tmp & 0x80) == 0)
1517                         break;
1518         }
1519
1520         for (i = 0; i < 4; i++) {
1521                 RTSX_READ_REG(chip, CFGDATA0 + i, &tmp);
1522                 data |= (u32)tmp << (i * 8);
1523         }
1524
1525         if (val)
1526                 *val = data;
1527
1528         return STATUS_SUCCESS;
1529 }
1530
1531 int rtsx_write_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len)
1532 {
1533         u32 *data, *mask;
1534         u16 offset = addr % 4;
1535         u16 aligned_addr = addr - offset;
1536         int dw_len, i, j;
1537         int retval;
1538
1539         RTSX_DEBUGP("%s\n", __func__);
1540
1541         if (!buf)
1542                 TRACE_RET(chip, STATUS_NOMEM);
1543
1544         if ((len + offset) % 4)
1545                 dw_len = (len + offset) / 4 + 1;
1546         else
1547                 dw_len = (len + offset) / 4;
1548
1549         RTSX_DEBUGP("dw_len = %d\n", dw_len);
1550
1551         data = vzalloc(dw_len * 4);
1552         if (!data)
1553                 TRACE_RET(chip, STATUS_NOMEM);
1554
1555         mask = vzalloc(dw_len * 4);
1556         if (!mask) {
1557                 vfree(data);
1558                 TRACE_RET(chip, STATUS_NOMEM);
1559         }
1560
1561         j = 0;
1562         for (i = 0; i < len; i++) {
1563                 mask[j] |= 0xFF << (offset * 8);
1564                 data[j] |= buf[i] << (offset * 8);
1565                 if (++offset == 4) {
1566                         j++;
1567                         offset = 0;
1568                 }
1569         }
1570
1571         RTSX_DUMP(mask, dw_len * 4);
1572         RTSX_DUMP(data, dw_len * 4);
1573
1574         for (i = 0; i < dw_len; i++) {
1575                 retval = rtsx_write_cfg_dw(chip, func, aligned_addr + i * 4, mask[i], data[i]);
1576                 if (retval != STATUS_SUCCESS) {
1577                         vfree(data);
1578                         vfree(mask);
1579                         TRACE_RET(chip, STATUS_FAIL);
1580                 }
1581         }
1582
1583         vfree(data);
1584         vfree(mask);
1585
1586         return STATUS_SUCCESS;
1587 }
1588
1589 int rtsx_read_cfg_seq(struct rtsx_chip *chip, u8 func, u16 addr, u8 *buf, int len)
1590 {
1591         u32 *data;
1592         u16 offset = addr % 4;
1593         u16 aligned_addr = addr - offset;
1594         int dw_len, i, j;
1595         int retval;
1596
1597         RTSX_DEBUGP("%s\n", __func__);
1598
1599         if ((len + offset) % 4)
1600                 dw_len = (len + offset) / 4 + 1;
1601         else
1602                 dw_len = (len + offset) / 4;
1603
1604         RTSX_DEBUGP("dw_len = %d\n", dw_len);
1605
1606         data = (u32 *)vmalloc(dw_len * 4);
1607         if (!data)
1608                 TRACE_RET(chip, STATUS_NOMEM);
1609
1610         for (i = 0; i < dw_len; i++) {
1611                 retval = rtsx_read_cfg_dw(chip, func, aligned_addr + i * 4, data + i);
1612                 if (retval != STATUS_SUCCESS) {
1613                         vfree(data);
1614                         TRACE_RET(chip, STATUS_FAIL);
1615                 }
1616         }
1617
1618         if (buf) {
1619                 j = 0;
1620
1621                 for (i = 0; i < len; i++) {
1622                         buf[i] = (u8)(data[j] >> (offset * 8));
1623                         if (++offset == 4) {
1624                                 j++;
1625                                 offset = 0;
1626                         }
1627                 }
1628         }
1629
1630         vfree(data);
1631
1632         return STATUS_SUCCESS;
1633 }
1634
1635 int rtsx_write_phy_register(struct rtsx_chip *chip, u8 addr, u16 val)
1636 {
1637         int i, finished = 0;
1638         u8 tmp;
1639
1640         RTSX_WRITE_REG(chip, PHYDATA0, 0xFF, (u8)val);
1641         RTSX_WRITE_REG(chip, PHYDATA1, 0xFF, (u8)(val >> 8));
1642         RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr);
1643         RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x81);
1644
1645         for (i = 0; i < 100000; i++) {
1646                 RTSX_READ_REG(chip, PHYRWCTL, &tmp);
1647                 if (!(tmp & 0x80)) {
1648                         finished = 1;
1649                         break;
1650                 }
1651         }
1652
1653         if (!finished)
1654                 TRACE_RET(chip, STATUS_FAIL);
1655
1656         return STATUS_SUCCESS;
1657 }
1658
1659 int rtsx_read_phy_register(struct rtsx_chip *chip, u8 addr, u16 *val)
1660 {
1661         int i, finished = 0;
1662         u16 data = 0;
1663         u8 tmp;
1664
1665         RTSX_WRITE_REG(chip, PHYADDR, 0xFF, addr);
1666         RTSX_WRITE_REG(chip, PHYRWCTL, 0xFF, 0x80);
1667
1668         for (i = 0; i < 100000; i++) {
1669                 RTSX_READ_REG(chip, PHYRWCTL, &tmp);
1670                 if (!(tmp & 0x80)) {
1671                         finished = 1;
1672                         break;
1673                 }
1674         }
1675
1676         if (!finished)
1677                 TRACE_RET(chip, STATUS_FAIL);
1678
1679         RTSX_READ_REG(chip, PHYDATA0, &tmp);
1680         data = tmp;
1681         RTSX_READ_REG(chip, PHYDATA1, &tmp);
1682         data |= (u16)tmp << 8;
1683
1684         if (val)
1685                 *val = data;
1686
1687         return STATUS_SUCCESS;
1688 }
1689
1690 int rtsx_read_efuse(struct rtsx_chip *chip, u8 addr, u8 *val)
1691 {
1692         int i;
1693         u8 data = 0;
1694
1695         RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0x80|addr);
1696
1697         for (i = 0; i < 100; i++) {
1698                 RTSX_READ_REG(chip, EFUSE_CTRL, &data);
1699                 if (!(data & 0x80))
1700                         break;
1701                 udelay(1);
1702         }
1703
1704         if (data & 0x80)
1705                 TRACE_RET(chip, STATUS_TIMEDOUT);
1706
1707         RTSX_READ_REG(chip, EFUSE_DATA, &data);
1708         if (val)
1709                 *val = data;
1710
1711         return STATUS_SUCCESS;
1712 }
1713
1714 int rtsx_write_efuse(struct rtsx_chip *chip, u8 addr, u8 val)
1715 {
1716         int i, j;
1717         u8 data = 0, tmp = 0xFF;
1718
1719         for (i = 0; i < 8; i++) {
1720                 if (val & (u8)(1 << i))
1721                         continue;
1722
1723                 tmp &= (~(u8)(1 << i));
1724                 RTSX_DEBUGP("Write 0x%x to 0x%x\n", tmp, addr);
1725
1726                 RTSX_WRITE_REG(chip, EFUSE_DATA, 0xFF, tmp);
1727                 RTSX_WRITE_REG(chip, EFUSE_CTRL, 0xFF, 0xA0|addr);
1728
1729                 for (j = 0; j < 100; j++) {
1730                         RTSX_READ_REG(chip, EFUSE_CTRL, &data);
1731                         if (!(data & 0x80))
1732                                 break;
1733                         wait_timeout(3);
1734                 }
1735
1736                 if (data & 0x80)
1737                         TRACE_RET(chip, STATUS_TIMEDOUT);
1738
1739                 wait_timeout(5);
1740         }
1741
1742         return STATUS_SUCCESS;
1743 }
1744
1745 int rtsx_clr_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1746 {
1747         int retval;
1748         u16 value;
1749
1750         retval = rtsx_read_phy_register(chip, reg, &value);
1751         if (retval != STATUS_SUCCESS)
1752                 TRACE_RET(chip, STATUS_FAIL);
1753
1754         if (value & (1 << bit)) {
1755                 value &= ~(1 << bit);
1756                 retval = rtsx_write_phy_register(chip, reg, value);
1757                 if (retval != STATUS_SUCCESS)
1758                         TRACE_RET(chip, STATUS_FAIL);
1759         }
1760
1761         return STATUS_SUCCESS;
1762 }
1763
1764 int rtsx_set_phy_reg_bit(struct rtsx_chip *chip, u8 reg, u8 bit)
1765 {
1766         int retval;
1767         u16 value;
1768
1769         retval = rtsx_read_phy_register(chip, reg, &value);
1770         if (retval != STATUS_SUCCESS)
1771                 TRACE_RET(chip, STATUS_FAIL);
1772
1773         if (0 == (value & (1 << bit))) {
1774                 value |= (1 << bit);
1775                 retval = rtsx_write_phy_register(chip, reg, value);
1776                 if (retval != STATUS_SUCCESS)
1777                         TRACE_RET(chip, STATUS_FAIL);
1778         }
1779
1780         return STATUS_SUCCESS;
1781 }
1782
1783 int rtsx_check_link_ready(struct rtsx_chip *chip)
1784 {
1785         u8 val;
1786
1787         RTSX_READ_REG(chip, IRQSTAT0, &val);
1788
1789         RTSX_DEBUGP("IRQSTAT0: 0x%x\n", val);
1790         if (val & LINK_RDY_INT) {
1791                 RTSX_DEBUGP("Delinked!\n");
1792                 rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1793                 return STATUS_FAIL;
1794         }
1795
1796         return STATUS_SUCCESS;
1797 }
1798
1799 static void rtsx_handle_pm_dstate(struct rtsx_chip *chip, u8 dstate)
1800 {
1801         u32 ultmp;
1802
1803         RTSX_DEBUGP("%04x set pm_dstate to %d\n", chip->product_id, dstate);
1804
1805         if (CHK_SDIO_EXIST(chip)) {
1806                 u8 func_no;
1807
1808                 if (CHECK_PID(chip, 0x5288))
1809                         func_no = 2;
1810                 else
1811                         func_no = 1;
1812
1813                 rtsx_read_cfg_dw(chip, func_no, 0x84, &ultmp);
1814                 RTSX_DEBUGP("pm_dstate of function %d: 0x%x\n", (int)func_no, ultmp);
1815                 rtsx_write_cfg_dw(chip, func_no, 0x84, 0xFF, dstate);
1816         }
1817
1818         rtsx_write_config_byte(chip, 0x44, dstate);
1819         rtsx_write_config_byte(chip, 0x45, 0);
1820 }
1821
1822 void rtsx_enter_L1(struct rtsx_chip *chip)
1823 {
1824         rtsx_handle_pm_dstate(chip, 2);
1825 }
1826
1827 void rtsx_exit_L1(struct rtsx_chip *chip)
1828 {
1829         rtsx_write_config_byte(chip, 0x44, 0);
1830         rtsx_write_config_byte(chip, 0x45, 0);
1831 }
1832
1833 void rtsx_enter_ss(struct rtsx_chip *chip)
1834 {
1835         RTSX_DEBUGP("Enter Selective Suspend State!\n");
1836
1837         rtsx_write_register(chip, IRQSTAT0, LINK_RDY_INT, LINK_RDY_INT);
1838
1839         if (chip->power_down_in_ss) {
1840                 rtsx_power_off_card(chip);
1841                 rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
1842         }
1843
1844         if (CHK_SDIO_EXIST(chip)) {
1845                 if (CHECK_PID(chip, 0x5288))
1846                         rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFF00, 0x0100);
1847                 else
1848                         rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFF00, 0x0100);
1849         }
1850
1851         if (chip->auto_delink_en) {
1852                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x01, 0x01);
1853         } else {
1854                 if (!chip->phy_debug_mode) {
1855                         u32 tmp;
1856                         tmp = rtsx_readl(chip, RTSX_BIER);
1857                         tmp |= CARD_INT;
1858                         rtsx_writel(chip, RTSX_BIER, tmp);
1859                 }
1860
1861                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 0);
1862         }
1863
1864         rtsx_enter_L1(chip);
1865
1866         RTSX_CLR_DELINK(chip);
1867         rtsx_set_stat(chip, RTSX_STAT_SS);
1868 }
1869
1870 void rtsx_exit_ss(struct rtsx_chip *chip)
1871 {
1872         RTSX_DEBUGP("Exit Selective Suspend State!\n");
1873
1874         rtsx_exit_L1(chip);
1875
1876         if (chip->power_down_in_ss) {
1877                 rtsx_force_power_on(chip, SSC_PDCTL | OC_PDCTL);
1878                 udelay(1000);
1879         }
1880
1881         if (RTSX_TST_DELINK(chip)) {
1882                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1883                 rtsx_reinit_cards(chip, 1);
1884                 RTSX_CLR_DELINK(chip);
1885         } else if (chip->power_down_in_ss) {
1886                 chip->need_reinit = SD_CARD | MS_CARD | XD_CARD;
1887                 rtsx_reinit_cards(chip, 0);
1888         }
1889 }
1890
1891 int rtsx_pre_handle_interrupt(struct rtsx_chip *chip)
1892 {
1893         u32 status, int_enable;
1894         int exit_ss = 0;
1895 #ifdef SUPPORT_OCP
1896         u32 ocp_int = 0;
1897
1898         if (CHECK_PID(chip, 0x5209)) {
1899                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
1900                         ocp_int = MS_OC_INT | SD_OC_INT;
1901                 else
1902                         ocp_int = SD_OC_INT;
1903
1904         } else {
1905                 ocp_int = OC_INT;
1906         }
1907 #endif
1908
1909         if (chip->ss_en) {
1910                 chip->ss_counter = 0;
1911                 if (rtsx_get_stat(chip) == RTSX_STAT_SS) {
1912                         exit_ss = 1;
1913                         rtsx_exit_L1(chip);
1914                         rtsx_set_stat(chip, RTSX_STAT_RUN);
1915                 }
1916         }
1917
1918         int_enable = rtsx_readl(chip, RTSX_BIER);
1919         chip->int_reg = rtsx_readl(chip, RTSX_BIPR);
1920
1921 #ifdef HW_INT_WRITE_CLR
1922         if (CHECK_PID(chip, 0x5209))
1923                 rtsx_writel(chip, RTSX_BIPR, chip->int_reg);
1924 #endif
1925
1926         if (((chip->int_reg & int_enable) == 0) || (chip->int_reg == 0xFFFFFFFF))
1927                 return STATUS_FAIL;
1928
1929         if (!chip->msi_en) {
1930                 if (CHECK_PID(chip, 0x5209)) {
1931                         u8 val;
1932                         rtsx_read_config_byte(chip, 0x05, &val);
1933                         if (val & 0x04)
1934                                 return STATUS_FAIL;
1935                 }
1936         }
1937
1938         status = chip->int_reg &= (int_enable | 0x7FFFFF);
1939
1940         if (status & CARD_INT) {
1941                 chip->auto_delink_cnt = 0;
1942
1943                 if (status & SD_INT) {
1944                         if (status & SD_EXIST) {
1945                                 set_bit(SD_NR, &(chip->need_reset));
1946                         } else {
1947                                 set_bit(SD_NR, &(chip->need_release));
1948                                 chip->sd_reset_counter = 0;
1949                                 chip->sd_show_cnt = 0;
1950                                 clear_bit(SD_NR, &(chip->need_reset));
1951                         }
1952                 } else {
1953                         /* If multi-luns, it's possible that
1954                            when plugging/unplugging one card
1955                            there is another card which still
1956                            exists in the slot. In this case,
1957                            all existed cards should be reset.
1958                         */
1959                         if (exit_ss && (status & SD_EXIST))
1960                                 set_bit(SD_NR, &(chip->need_reinit));
1961                 }
1962                 if (!CHECK_PID(chip, 0x5288) || CHECK_BARO_PKG(chip, QFN)) {
1963                         if (status & XD_INT) {
1964                                 if (status & XD_EXIST) {
1965                                         set_bit(XD_NR, &(chip->need_reset));
1966                                 } else {
1967                                         set_bit(XD_NR, &(chip->need_release));
1968                                         chip->xd_reset_counter = 0;
1969                                         chip->xd_show_cnt = 0;
1970                                         clear_bit(XD_NR, &(chip->need_reset));
1971                                 }
1972                         } else {
1973                                 if (exit_ss && (status & XD_EXIST))
1974                                         set_bit(XD_NR, &(chip->need_reinit));
1975                         }
1976                 }
1977                 if (status & MS_INT) {
1978                         if (status & MS_EXIST) {
1979                                 set_bit(MS_NR, &(chip->need_reset));
1980                         } else {
1981                                 set_bit(MS_NR, &(chip->need_release));
1982                                 chip->ms_reset_counter = 0;
1983                                 chip->ms_show_cnt = 0;
1984                                 clear_bit(MS_NR, &(chip->need_reset));
1985                         }
1986                 } else {
1987                         if (exit_ss && (status & MS_EXIST))
1988                                 set_bit(MS_NR, &(chip->need_reinit));
1989                 }
1990         }
1991
1992 #ifdef SUPPORT_OCP
1993         chip->ocp_int = ocp_int & status;
1994 #endif
1995
1996         if (chip->sd_io) {
1997                 if (chip->int_reg & DATA_DONE_INT)
1998                         chip->int_reg &= ~(u32)DATA_DONE_INT;
1999         }
2000
2001         return STATUS_SUCCESS;
2002 }
2003
2004 void rtsx_do_before_power_down(struct rtsx_chip *chip, int pm_stat)
2005 {
2006         int retval;
2007
2008         RTSX_DEBUGP("rtsx_do_before_power_down, pm_stat = %d\n", pm_stat);
2009
2010         rtsx_set_stat(chip, RTSX_STAT_SUSPEND);
2011
2012         retval = rtsx_force_power_on(chip, SSC_PDCTL);
2013         if (retval != STATUS_SUCCESS)
2014                 return;
2015
2016         rtsx_release_cards(chip);
2017         rtsx_disable_bus_int(chip);
2018         turn_off_led(chip, LED_GPIO);
2019
2020 #ifdef HW_AUTO_SWITCH_SD_BUS
2021         if (chip->sd_io) {
2022                 chip->sdio_in_charge = 1;
2023                 if (CHECK_PID(chip, 0x5208)) {
2024                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2025                         /* Enable sdio_bus_auto_switch */
2026                         rtsx_write_register(chip, 0xFE70, 0x80, 0x80);
2027                 } else if (CHECK_PID(chip, 0x5288)) {
2028                         rtsx_write_register(chip, TLPTISTAT, 0x08, 0x08);
2029                         /* Enable sdio_bus_auto_switch */
2030                         rtsx_write_register(chip, 0xFE5A, 0x08, 0x08);
2031                 } else if (CHECK_PID(chip, 0x5209)) {
2032                         rtsx_write_register(chip, TLPTISTAT, 0x10, 0x10);
2033                         /* Enable sdio_bus_auto_switch */
2034                         rtsx_write_register(chip, SDIO_CFG, SDIO_BUS_AUTO_SWITCH, SDIO_BUS_AUTO_SWITCH);
2035                 }
2036         }
2037 #endif
2038
2039         if (CHECK_PID(chip, 0x5208) && (chip->ic_version >= IC_VER_D)) {
2040                 /* u_force_clkreq_0 */
2041                 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
2042         } else if (CHECK_PID(chip, 0x5209)) {
2043                 /* u_force_clkreq_0 */
2044                 rtsx_write_register(chip, PETXCFG, 0x08, 0x08);
2045         }
2046
2047         if (pm_stat == PM_S1) {
2048                 RTSX_DEBUGP("Host enter S1\n");
2049                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, HOST_ENTER_S1);
2050         } else if (pm_stat == PM_S3) {
2051                 if (chip->s3_pwr_off_delay > 0)
2052                         wait_timeout(chip->s3_pwr_off_delay);
2053
2054                 RTSX_DEBUGP("Host enter S3\n");
2055                 rtsx_write_register(chip, HOST_SLEEP_STATE, 0x03, HOST_ENTER_S3);
2056         }
2057
2058         if (chip->do_delink_before_power_down && chip->auto_delink_en)
2059                 rtsx_write_register(chip, CHANGE_LINK_STATE, 0x02, 2);
2060
2061         rtsx_force_power_down(chip, SSC_PDCTL | OC_PDCTL);
2062
2063         chip->cur_clk = 0;
2064         chip->cur_card = 0;
2065         chip->card_exist = 0;
2066 }
2067
2068 void rtsx_enable_aspm(struct rtsx_chip *chip)
2069 {
2070         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
2071                 if (!chip->aspm_enabled) {
2072                         RTSX_DEBUGP("Try to enable ASPM\n");
2073                         chip->aspm_enabled = 1;
2074
2075                         if (chip->asic_code && CHECK_PID(chip, 0x5208))
2076                                 rtsx_write_phy_register(chip, 0x07, 0);
2077                         if (CHECK_PID(chip, 0x5208)) {
2078                                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3,
2079                                         0x30 | chip->aspm_level[0]);
2080                         } else {
2081                                 rtsx_write_config_byte(chip, LCTLR, chip->aspm_l0s_l1_en);
2082                         }
2083
2084                         if (CHK_SDIO_EXIST(chip)) {
2085                                 u16 val = chip->aspm_l0s_l1_en | 0x0100;
2086                                 if (CHECK_PID(chip, 0x5288))
2087                                         rtsx_write_cfg_dw(chip, 2, 0xC0, 0xFFFF, val);
2088                                 else
2089                                         rtsx_write_cfg_dw(chip, 1, 0xC0, 0xFFFF, val);
2090                         }
2091                 }
2092         }
2093
2094         return;
2095 }
2096
2097 void rtsx_disable_aspm(struct rtsx_chip *chip)
2098 {
2099         if (CHECK_PID(chip, 0x5208))
2100                 rtsx_monitor_aspm_config(chip);
2101
2102         if (chip->aspm_l0s_l1_en && chip->dynamic_aspm) {
2103                 if (chip->aspm_enabled) {
2104                         RTSX_DEBUGP("Try to disable ASPM\n");
2105                         chip->aspm_enabled = 0;
2106
2107                         if (chip->asic_code && CHECK_PID(chip, 0x5208))
2108                                 rtsx_write_phy_register(chip, 0x07, 0x0129);
2109                         if (CHECK_PID(chip, 0x5208))
2110                                 rtsx_write_register(chip, ASPM_FORCE_CTL, 0xF3, 0x30);
2111                         else
2112                                 rtsx_write_config_byte(chip, LCTLR, 0x00);
2113
2114                         wait_timeout(1);
2115                 }
2116         }
2117
2118         return;
2119 }
2120
2121 int rtsx_read_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2122 {
2123         int retval;
2124         int i, j;
2125         u16 reg_addr;
2126         u8 *ptr;
2127
2128         if (!buf)
2129                 TRACE_RET(chip, STATUS_ERROR);
2130
2131         ptr = buf;
2132         reg_addr = PPBUF_BASE2;
2133         for (i = 0; i < buf_len/256; i++) {
2134                 rtsx_init_cmd(chip);
2135
2136                 for (j = 0; j < 256; j++)
2137                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2138
2139                 retval = rtsx_send_cmd(chip, 0, 250);
2140                 if (retval < 0)
2141                         TRACE_RET(chip, STATUS_FAIL);
2142
2143                 memcpy(ptr, rtsx_get_cmd_data(chip), 256);
2144                 ptr += 256;
2145         }
2146
2147         if (buf_len%256) {
2148                 rtsx_init_cmd(chip);
2149
2150                 for (j = 0; j < buf_len%256; j++)
2151                         rtsx_add_cmd(chip, READ_REG_CMD, reg_addr++, 0, 0);
2152
2153                 retval = rtsx_send_cmd(chip, 0, 250);
2154                 if (retval < 0)
2155                         TRACE_RET(chip, STATUS_FAIL);
2156         }
2157
2158         memcpy(ptr, rtsx_get_cmd_data(chip), buf_len%256);
2159
2160         return STATUS_SUCCESS;
2161 }
2162
2163 int rtsx_write_ppbuf(struct rtsx_chip *chip, u8 *buf, int buf_len)
2164 {
2165         int retval;
2166         int i, j;
2167         u16 reg_addr;
2168         u8 *ptr;
2169
2170         if (!buf)
2171                 TRACE_RET(chip, STATUS_ERROR);
2172
2173         ptr = buf;
2174         reg_addr = PPBUF_BASE2;
2175         for (i = 0; i < buf_len/256; i++) {
2176                 rtsx_init_cmd(chip);
2177
2178                 for (j = 0; j < 256; j++) {
2179                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, *ptr);
2180                         ptr++;
2181                 }
2182
2183                 retval = rtsx_send_cmd(chip, 0, 250);
2184                 if (retval < 0)
2185                         TRACE_RET(chip, STATUS_FAIL);
2186         }
2187
2188         if (buf_len%256) {
2189                 rtsx_init_cmd(chip);
2190
2191                 for (j = 0; j < buf_len%256; j++) {
2192                         rtsx_add_cmd(chip, WRITE_REG_CMD, reg_addr++, 0xFF, *ptr);
2193                         ptr++;
2194                 }
2195
2196                 retval = rtsx_send_cmd(chip, 0, 250);
2197                 if (retval < 0)
2198                         TRACE_RET(chip, STATUS_FAIL);
2199         }
2200
2201         return STATUS_SUCCESS;
2202 }
2203
2204 int rtsx_check_chip_exist(struct rtsx_chip *chip)
2205 {
2206         if (rtsx_readl(chip, 0) == 0xFFFFFFFF)
2207                 TRACE_RET(chip, STATUS_FAIL);
2208
2209         return STATUS_SUCCESS;
2210 }
2211
2212 int rtsx_force_power_on(struct rtsx_chip *chip, u8 ctl)
2213 {
2214         int retval;
2215         u8 mask = 0;
2216
2217         if (ctl & SSC_PDCTL)
2218                 mask |= SSC_POWER_DOWN;
2219
2220 #ifdef SUPPORT_OCP
2221         if (ctl & OC_PDCTL) {
2222                 mask |= SD_OC_POWER_DOWN;
2223                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2224                         mask |= MS_OC_POWER_DOWN;
2225         }
2226 #endif
2227
2228         if (mask) {
2229                 retval = rtsx_write_register(chip, FPDCTL, mask, 0);
2230                 if (retval != STATUS_SUCCESS)
2231                         TRACE_RET(chip, STATUS_FAIL);
2232
2233                 if (CHECK_PID(chip, 0x5288))
2234                         wait_timeout(200);
2235         }
2236
2237         return STATUS_SUCCESS;
2238 }
2239
2240 int rtsx_force_power_down(struct rtsx_chip *chip, u8 ctl)
2241 {
2242         int retval;
2243         u8 mask = 0, val = 0;
2244
2245         if (ctl & SSC_PDCTL)
2246                 mask |= SSC_POWER_DOWN;
2247
2248 #ifdef SUPPORT_OCP
2249         if (ctl & OC_PDCTL) {
2250                 mask |= SD_OC_POWER_DOWN;
2251                 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
2252                         mask |= MS_OC_POWER_DOWN;
2253         }
2254 #endif
2255
2256         if (mask) {
2257                 val = mask;
2258                 retval = rtsx_write_register(chip, FPDCTL, mask, val);
2259                 if (retval != STATUS_SUCCESS)
2260                         TRACE_RET(chip, STATUS_FAIL);
2261         }
2262
2263         return STATUS_SUCCESS;
2264 }