1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
28 #include "rtsx_transport.h"
29 #include "rtsx_scsi.h"
30 #include "rtsx_card.h"
33 static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code)
35 struct spi_info *spi = &(chip->spi);
37 spi->err_code = err_code;
40 static int spi_init(struct rtsx_chip *chip)
42 RTSX_WRITE_REG(chip, SPI_CONTROL, 0xFF,
43 CS_POLARITY_LOW | DTO_MSB_FIRST | SPI_MASTER | SPI_MODE0 |
45 RTSX_WRITE_REG(chip, SPI_TCTL, EDO_TIMING_MASK, SAMPLE_DELAY_HALF);
47 return STATUS_SUCCESS;
50 static int spi_set_init_para(struct rtsx_chip *chip)
52 struct spi_info *spi = &(chip->spi);
55 RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER1, 0xFF, (u8)(spi->clk_div >> 8));
56 RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER0, 0xFF, (u8)(spi->clk_div));
58 retval = switch_clock(chip, spi->spi_clock);
59 if (retval != STATUS_SUCCESS)
60 TRACE_RET(chip, STATUS_FAIL);
62 retval = select_card(chip, SPI_CARD);
63 if (retval != STATUS_SUCCESS)
64 TRACE_RET(chip, STATUS_FAIL);
66 RTSX_WRITE_REG(chip, CARD_CLK_EN, SPI_CLK_EN, SPI_CLK_EN);
67 RTSX_WRITE_REG(chip, CARD_OE, SPI_OUTPUT_EN, SPI_OUTPUT_EN);
71 retval = spi_init(chip);
72 if (retval != STATUS_SUCCESS)
73 TRACE_RET(chip, STATUS_FAIL);
75 return STATUS_SUCCESS;
78 static int sf_polling_status(struct rtsx_chip *chip, int msec)
84 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR);
85 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
86 SPI_TRANSFER0_START | SPI_POLLING_MODE0);
87 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
90 retval = rtsx_send_cmd(chip, 0, msec);
92 rtsx_clear_spi_error(chip);
93 spi_set_err_code(chip, SPI_BUSY_ERR);
94 TRACE_RET(chip, STATUS_FAIL);
97 return STATUS_SUCCESS;
100 static int sf_enable_write(struct rtsx_chip *chip, u8 ins)
102 struct spi_info *spi = &(chip->spi);
106 return STATUS_SUCCESS;
110 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
111 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
112 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
113 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
114 SPI_TRANSFER0_START | SPI_C_MODE0);
115 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
118 retval = rtsx_send_cmd(chip, 0, 100);
120 rtsx_clear_spi_error(chip);
121 spi_set_err_code(chip, SPI_HW_ERR);
122 TRACE_RET(chip, STATUS_FAIL);
125 return STATUS_SUCCESS;
128 static int sf_disable_write(struct rtsx_chip *chip, u8 ins)
130 struct spi_info *spi = &(chip->spi);
134 return STATUS_SUCCESS;
138 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
139 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
140 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
141 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
142 SPI_TRANSFER0_START | SPI_C_MODE0);
143 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
146 retval = rtsx_send_cmd(chip, 0, 100);
148 rtsx_clear_spi_error(chip);
149 spi_set_err_code(chip, SPI_HW_ERR);
150 TRACE_RET(chip, STATUS_FAIL);
153 return STATUS_SUCCESS;
156 static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr,
159 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
160 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
161 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
162 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len);
163 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8));
165 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
166 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
168 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
170 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
171 SPI_TRANSFER0_START | SPI_CADO_MODE0);
173 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
174 SPI_TRANSFER0_START | SPI_CDO_MODE0);
176 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
180 static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr)
186 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
187 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
188 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
190 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
191 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
193 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
195 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
196 SPI_TRANSFER0_START | SPI_CA_MODE0);
198 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
199 SPI_TRANSFER0_START | SPI_C_MODE0);
201 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
204 retval = rtsx_send_cmd(chip, 0, 100);
206 rtsx_clear_spi_error(chip);
207 spi_set_err_code(chip, SPI_HW_ERR);
208 TRACE_RET(chip, STATUS_FAIL);
211 return STATUS_SUCCESS;
214 static int spi_init_eeprom(struct rtsx_chip *chip)
224 RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00);
225 RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27);
227 retval = switch_clock(chip, clk);
228 if (retval != STATUS_SUCCESS)
229 TRACE_RET(chip, STATUS_FAIL);
231 retval = select_card(chip, SPI_CARD);
232 if (retval != STATUS_SUCCESS)
233 TRACE_RET(chip, STATUS_FAIL);
235 RTSX_WRITE_REG(chip, CARD_CLK_EN, SPI_CLK_EN, SPI_CLK_EN);
236 RTSX_WRITE_REG(chip, CARD_OE, SPI_OUTPUT_EN, SPI_OUTPUT_EN);
240 RTSX_WRITE_REG(chip, SPI_CONTROL, 0xFF,
241 CS_POLARITY_HIGH | SPI_EEPROM_AUTO);
242 RTSX_WRITE_REG(chip, SPI_TCTL, EDO_TIMING_MASK, SAMPLE_DELAY_HALF);
244 return STATUS_SUCCESS;
247 static int spi_eeprom_program_enable(struct rtsx_chip *chip)
253 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86);
254 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13);
255 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
256 SPI_TRANSFER0_START | SPI_CA_MODE0);
257 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
260 retval = rtsx_send_cmd(chip, 0, 100);
262 TRACE_RET(chip, STATUS_FAIL);
264 return STATUS_SUCCESS;
267 int spi_erase_eeprom_chip(struct rtsx_chip *chip)
271 retval = spi_init_eeprom(chip);
272 if (retval != STATUS_SUCCESS)
273 TRACE_RET(chip, STATUS_FAIL);
275 retval = spi_eeprom_program_enable(chip);
276 if (retval != STATUS_SUCCESS)
277 TRACE_RET(chip, STATUS_FAIL);
281 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
282 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
283 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12);
284 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84);
285 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
286 SPI_TRANSFER0_START | SPI_CA_MODE0);
287 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
290 retval = rtsx_send_cmd(chip, 0, 100);
292 TRACE_RET(chip, STATUS_FAIL);
294 RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01);
296 return STATUS_SUCCESS;
299 int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr)
303 retval = spi_init_eeprom(chip);
304 if (retval != STATUS_SUCCESS)
305 TRACE_RET(chip, STATUS_FAIL);
307 retval = spi_eeprom_program_enable(chip);
308 if (retval != STATUS_SUCCESS)
309 TRACE_RET(chip, STATUS_FAIL);
313 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
314 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
315 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x07);
316 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
317 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
318 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
319 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
320 SPI_TRANSFER0_START | SPI_CA_MODE0);
321 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
324 retval = rtsx_send_cmd(chip, 0, 100);
326 TRACE_RET(chip, STATUS_FAIL);
328 RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01);
330 return STATUS_SUCCESS;
334 int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val)
339 retval = spi_init_eeprom(chip);
340 if (retval != STATUS_SUCCESS)
341 TRACE_RET(chip, STATUS_FAIL);
345 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
346 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
347 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x06);
348 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
349 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
350 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
351 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
352 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
353 SPI_TRANSFER0_START | SPI_CADI_MODE0);
354 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
357 retval = rtsx_send_cmd(chip, 0, 100);
359 TRACE_RET(chip, STATUS_FAIL);
362 RTSX_READ_REG(chip, SPI_DATA, &data);
367 RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01);
369 return STATUS_SUCCESS;
372 int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val)
376 retval = spi_init_eeprom(chip);
377 if (retval != STATUS_SUCCESS)
378 TRACE_RET(chip, STATUS_FAIL);
380 retval = spi_eeprom_program_enable(chip);
381 if (retval != STATUS_SUCCESS)
382 TRACE_RET(chip, STATUS_FAIL);
386 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
387 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
388 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x05);
389 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val);
390 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)addr);
391 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8));
392 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E);
393 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
394 SPI_TRANSFER0_START | SPI_CA_MODE0);
395 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
398 retval = rtsx_send_cmd(chip, 0, 100);
400 TRACE_RET(chip, STATUS_FAIL);
402 RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01);
404 return STATUS_SUCCESS;
408 int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
410 struct spi_info *spi = &(chip->spi);
412 RTSX_DEBUGP("spi_get_status: err_code = 0x%x\n", spi->err_code);
413 rtsx_stor_set_xfer_buf(&(spi->err_code),
414 min_t(int, scsi_bufflen(srb), 1), srb);
415 scsi_set_resid(srb, scsi_bufflen(srb) - 1);
417 return STATUS_SUCCESS;
420 int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip)
422 struct spi_info *spi = &(chip->spi);
424 spi_set_err_code(chip, SPI_NO_ERR);
427 spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9];
429 spi->spi_clock = srb->cmnd[3];
431 spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5];
432 spi->write_en = srb->cmnd[6];
434 RTSX_DEBUGP("spi_set_parameter: spi_clock = %d, clk_div = %d, write_en = %d\n",
435 spi->spi_clock, spi->clk_div, spi->write_en);
437 return STATUS_SUCCESS;
440 int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
446 spi_set_err_code(chip, SPI_NO_ERR);
448 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
450 spi_set_err_code(chip, SPI_INVALID_COMMAND);
451 TRACE_RET(chip, STATUS_FAIL);
454 retval = spi_set_init_para(chip);
455 if (retval != STATUS_SUCCESS) {
456 spi_set_err_code(chip, SPI_HW_ERR);
457 TRACE_RET(chip, STATUS_FAIL);
462 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
465 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]);
466 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]);
467 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]);
468 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]);
469 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
470 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
471 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]);
472 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]);
476 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
477 0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0);
479 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
480 0xFF, SPI_TRANSFER0_START | SPI_C_MODE0);
484 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
485 SPI_TRANSFER0_START | SPI_CADI_MODE0);
487 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
488 SPI_TRANSFER0_START | SPI_CDI_MODE0);
492 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
495 retval = rtsx_send_cmd(chip, 0, 100);
497 rtsx_clear_spi_error(chip);
498 spi_set_err_code(chip, SPI_HW_ERR);
499 TRACE_RET(chip, STATUS_FAIL);
503 buf = kmalloc(len, GFP_KERNEL);
505 TRACE_RET(chip, STATUS_ERROR);
507 retval = rtsx_read_ppbuf(chip, buf, len);
508 if (retval != STATUS_SUCCESS) {
509 spi_set_err_code(chip, SPI_READ_ERR);
511 TRACE_RET(chip, STATUS_FAIL);
514 rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb);
515 scsi_set_resid(srb, 0);
520 return STATUS_SUCCESS;
523 int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
526 unsigned int index = 0, offset = 0;
532 spi_set_err_code(chip, SPI_NO_ERR);
535 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
536 << 8) | srb->cmnd[6];
537 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
538 slow_read = srb->cmnd[9];
540 retval = spi_set_init_para(chip);
541 if (retval != STATUS_SUCCESS) {
542 spi_set_err_code(chip, SPI_HW_ERR);
543 TRACE_RET(chip, STATUS_FAIL);
546 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
548 TRACE_RET(chip, STATUS_ERROR);
551 u16 pagelen = SF_PAGE_LEN - (u8)addr;
558 trans_dma_enable(DMA_FROM_DEVICE, chip, 256, DMA_256);
560 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
563 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF,
565 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
567 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
569 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
570 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
572 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
574 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
576 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF,
578 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
579 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32);
582 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF,
584 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF,
587 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
588 SPI_TRANSFER0_START | SPI_CADI_MODE0);
589 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0,
590 SPI_TRANSFER0_END, SPI_TRANSFER0_END);
592 rtsx_send_cmd_no_wait(chip);
594 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
595 DMA_FROM_DEVICE, 10000);
598 rtsx_clear_spi_error(chip);
599 spi_set_err_code(chip, SPI_HW_ERR);
600 TRACE_RET(chip, STATUS_FAIL);
603 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset,
610 scsi_set_resid(srb, 0);
613 return STATUS_SUCCESS;
616 int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
619 u8 ins, program_mode;
623 unsigned int index = 0, offset = 0;
625 spi_set_err_code(chip, SPI_NO_ERR);
628 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
629 << 8) | srb->cmnd[6];
630 len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
631 program_mode = srb->cmnd[9];
633 retval = spi_set_init_para(chip);
634 if (retval != STATUS_SUCCESS) {
635 spi_set_err_code(chip, SPI_HW_ERR);
636 TRACE_RET(chip, STATUS_FAIL);
639 if (program_mode == BYTE_PROGRAM) {
640 buf = kmalloc(4, GFP_KERNEL);
642 TRACE_RET(chip, STATUS_ERROR);
645 retval = sf_enable_write(chip, SPI_WREN);
646 if (retval != STATUS_SUCCESS) {
648 TRACE_RET(chip, STATUS_FAIL);
651 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
656 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
657 0x01, PINGPONG_BUFFER);
658 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
660 sf_program(chip, ins, 1, addr, 1);
662 retval = rtsx_send_cmd(chip, 0, 100);
665 rtsx_clear_spi_error(chip);
666 spi_set_err_code(chip, SPI_HW_ERR);
667 TRACE_RET(chip, STATUS_FAIL);
670 retval = sf_polling_status(chip, 100);
671 if (retval != STATUS_SUCCESS) {
673 TRACE_RET(chip, STATUS_FAIL);
682 } else if (program_mode == AAI_PROGRAM) {
685 retval = sf_enable_write(chip, SPI_WREN);
686 if (retval != STATUS_SUCCESS)
687 TRACE_RET(chip, STATUS_FAIL);
689 buf = kmalloc(4, GFP_KERNEL);
691 TRACE_RET(chip, STATUS_ERROR);
694 rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
699 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
700 0x01, PINGPONG_BUFFER);
701 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
704 sf_program(chip, ins, 1, addr, 1);
707 sf_program(chip, ins, 0, 0, 1);
710 retval = rtsx_send_cmd(chip, 0, 100);
713 rtsx_clear_spi_error(chip);
714 spi_set_err_code(chip, SPI_HW_ERR);
715 TRACE_RET(chip, STATUS_FAIL);
718 retval = sf_polling_status(chip, 100);
719 if (retval != STATUS_SUCCESS) {
721 TRACE_RET(chip, STATUS_FAIL);
729 retval = sf_disable_write(chip, SPI_WRDI);
730 if (retval != STATUS_SUCCESS)
731 TRACE_RET(chip, STATUS_FAIL);
733 retval = sf_polling_status(chip, 100);
734 if (retval != STATUS_SUCCESS)
735 TRACE_RET(chip, STATUS_FAIL);
736 } else if (program_mode == PAGE_PROGRAM) {
737 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
739 TRACE_RET(chip, STATUS_NOMEM);
742 u16 pagelen = SF_PAGE_LEN - (u8)addr;
747 retval = sf_enable_write(chip, SPI_WREN);
748 if (retval != STATUS_SUCCESS) {
750 TRACE_RET(chip, STATUS_FAIL);
755 trans_dma_enable(DMA_TO_DEVICE, chip, 256, DMA_256);
756 sf_program(chip, ins, 1, addr, pagelen);
758 rtsx_send_cmd_no_wait(chip);
760 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index,
761 &offset, FROM_XFER_BUF);
763 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
767 rtsx_clear_spi_error(chip);
768 spi_set_err_code(chip, SPI_HW_ERR);
769 TRACE_RET(chip, STATUS_FAIL);
772 retval = sf_polling_status(chip, 100);
773 if (retval != STATUS_SUCCESS) {
775 TRACE_RET(chip, STATUS_FAIL);
784 spi_set_err_code(chip, SPI_INVALID_COMMAND);
785 TRACE_RET(chip, STATUS_FAIL);
788 return STATUS_SUCCESS;
791 int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
797 spi_set_err_code(chip, SPI_NO_ERR);
800 addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
801 << 8) | srb->cmnd[6];
802 erase_mode = srb->cmnd[9];
804 retval = spi_set_init_para(chip);
805 if (retval != STATUS_SUCCESS) {
806 spi_set_err_code(chip, SPI_HW_ERR);
807 TRACE_RET(chip, STATUS_FAIL);
810 if (erase_mode == PAGE_ERASE) {
811 retval = sf_enable_write(chip, SPI_WREN);
812 if (retval != STATUS_SUCCESS)
813 TRACE_RET(chip, STATUS_FAIL);
815 retval = sf_erase(chip, ins, 1, addr);
816 if (retval != STATUS_SUCCESS)
817 TRACE_RET(chip, STATUS_FAIL);
818 } else if (erase_mode == CHIP_ERASE) {
819 retval = sf_enable_write(chip, SPI_WREN);
820 if (retval != STATUS_SUCCESS)
821 TRACE_RET(chip, STATUS_FAIL);
823 retval = sf_erase(chip, ins, 0, 0);
824 if (retval != STATUS_SUCCESS)
825 TRACE_RET(chip, STATUS_FAIL);
827 spi_set_err_code(chip, SPI_INVALID_COMMAND);
828 TRACE_RET(chip, STATUS_FAIL);
831 return STATUS_SUCCESS;
834 int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
837 u8 ins, status, ewsr;
840 status = srb->cmnd[4];
843 retval = spi_set_init_para(chip);
844 if (retval != STATUS_SUCCESS) {
845 spi_set_err_code(chip, SPI_HW_ERR);
846 TRACE_RET(chip, STATUS_FAIL);
849 retval = sf_enable_write(chip, ewsr);
850 if (retval != STATUS_SUCCESS)
851 TRACE_RET(chip, STATUS_FAIL);
855 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
858 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
859 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
860 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
861 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0);
862 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
863 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status);
864 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
865 SPI_TRANSFER0_START | SPI_CDO_MODE0);
866 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
869 retval = rtsx_send_cmd(chip, 0, 100);
870 if (retval != STATUS_SUCCESS) {
871 rtsx_clear_spi_error(chip);
872 spi_set_err_code(chip, SPI_HW_ERR);
873 TRACE_RET(chip, STATUS_FAIL);
876 return STATUS_SUCCESS;