1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
30 #define SD_MAX_RETRY_COUNT 3
32 static u16 REG_SD_CFG1;
33 static u16 REG_SD_CFG2;
34 static u16 REG_SD_CFG3;
35 static u16 REG_SD_STAT1;
36 static u16 REG_SD_STAT2;
37 static u16 REG_SD_BUS_STAT;
38 static u16 REG_SD_PAD_CTL;
39 static u16 REG_SD_SAMPLE_POINT_CTL;
40 static u16 REG_SD_PUSH_POINT_CTL;
41 static u16 REG_SD_CMD0;
42 static u16 REG_SD_CMD1;
43 static u16 REG_SD_CMD2;
44 static u16 REG_SD_CMD3;
45 static u16 REG_SD_CMD4;
46 static u16 REG_SD_CMD5;
47 static u16 REG_SD_BYTE_CNT_L;
48 static u16 REG_SD_BYTE_CNT_H;
49 static u16 REG_SD_BLOCK_CNT_L;
50 static u16 REG_SD_BLOCK_CNT_H;
51 static u16 REG_SD_TRANSFER;
52 static u16 REG_SD_VPCLK0_CTL;
53 static u16 REG_SD_VPCLK1_CTL;
54 static u16 REG_SD_DCMPS0_CTL;
55 static u16 REG_SD_DCMPS1_CTL;
57 static inline void sd_set_err_code(struct rtsx_chip *chip, u8 err_code)
59 struct sd_info *sd_card = &chip->sd_card;
61 sd_card->err_code |= err_code;
64 static inline void sd_clr_err_code(struct rtsx_chip *chip)
66 struct sd_info *sd_card = &chip->sd_card;
68 sd_card->err_code = 0;
71 static inline int sd_check_err_code(struct rtsx_chip *chip, u8 err_code)
73 struct sd_info *sd_card = &chip->sd_card;
75 return sd_card->err_code & err_code;
78 static void sd_init_reg_addr(struct rtsx_chip *chip)
83 REG_SD_STAT1 = 0xFD30;
87 REG_SD_SAMPLE_POINT_CTL = 0;
88 REG_SD_PUSH_POINT_CTL = 0;
95 REG_SD_BYTE_CNT_L = 0xFD39;
96 REG_SD_BYTE_CNT_H = 0xFD3A;
97 REG_SD_BLOCK_CNT_L = 0xFD3B;
98 REG_SD_BLOCK_CNT_H = 0xFD3C;
99 REG_SD_TRANSFER = 0xFD32;
100 REG_SD_VPCLK0_CTL = 0;
101 REG_SD_VPCLK1_CTL = 0;
102 REG_SD_DCMPS0_CTL = 0;
103 REG_SD_DCMPS1_CTL = 0;
106 static int sd_check_data0_status(struct rtsx_chip *chip)
111 retval = rtsx_read_register(chip, REG_SD_STAT1, &stat);
117 if (!(stat & SD_DAT0_STATUS)) {
118 sd_set_err_code(chip, SD_BUSY);
123 return STATUS_SUCCESS;
126 static int sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx,
127 u32 arg, u8 rsp_type, u8 *rsp, int rsp_len)
129 struct sd_info *sd_card = &chip->sd_card;
137 sd_clr_err_code(chip);
139 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d, arg = 0x%08x\n", cmd_idx, arg);
141 if (rsp_type == SD_RSP_TYPE_R1b)
148 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
149 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
150 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
151 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
152 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
154 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
155 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
156 0x01, PINGPONG_BUFFER);
157 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
158 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
159 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
160 SD_TRANSFER_END | SD_STAT_IDLE, SD_TRANSFER_END |
163 if (rsp_type == SD_RSP_TYPE_R2) {
164 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
166 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
169 } else if (rsp_type != SD_RSP_TYPE_R0) {
170 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
172 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
177 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
179 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
183 rtsx_read_register(chip, REG_SD_STAT1, &val);
184 dev_dbg(rtsx_dev(chip), "SD_STAT1: 0x%x\n", val);
186 rtsx_read_register(chip, REG_SD_CFG3, &val);
187 dev_dbg(rtsx_dev(chip), "SD_CFG3: 0x%x\n", val);
189 if (retval == -ETIMEDOUT) {
190 if (rsp_type & SD_WAIT_BUSY_END) {
191 retval = sd_check_data0_status(chip);
192 if (retval != STATUS_SUCCESS) {
193 rtsx_clear_sd_error(chip);
198 sd_set_err_code(chip, SD_TO_ERR);
200 retval = STATUS_TIMEDOUT;
202 retval = STATUS_FAIL;
204 rtsx_clear_sd_error(chip);
210 if (rsp_type == SD_RSP_TYPE_R0)
211 return STATUS_SUCCESS;
213 ptr = rtsx_get_cmd_data(chip) + 1;
215 if ((ptr[0] & 0xC0) != 0) {
216 sd_set_err_code(chip, SD_STS_ERR);
221 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
222 if (ptr[stat_idx] & SD_CRC7_ERR) {
223 if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
224 sd_set_err_code(chip, SD_CRC_ERR);
228 if (rty_cnt < SD_MAX_RETRY_COUNT) {
233 sd_set_err_code(chip, SD_CRC_ERR);
240 if ((rsp_type == SD_RSP_TYPE_R1) || (rsp_type == SD_RSP_TYPE_R1b)) {
241 if ((cmd_idx != SEND_RELATIVE_ADDR) &&
242 (cmd_idx != SEND_IF_COND)) {
243 if (cmd_idx != STOP_TRANSMISSION) {
249 #ifdef SUPPORT_SD_LOCK
254 dev_dbg(rtsx_dev(chip), "ptr[1]: 0x%02x\n",
260 dev_dbg(rtsx_dev(chip), "ptr[2]: 0x%02x\n",
266 dev_dbg(rtsx_dev(chip), "ptr[3]: 0x%02x\n",
272 sd_card->sd_data_buf_ready = 1;
274 sd_card->sd_data_buf_ready = 0;
279 memcpy(rsp, ptr, rsp_len);
281 return STATUS_SUCCESS;
284 static int sd_read_data(struct rtsx_chip *chip,
285 u8 trans_mode, u8 *cmd, int cmd_len, u16 byte_cnt,
286 u16 blk_cnt, u8 bus_width, u8 *buf, int buf_len,
289 struct sd_info *sd_card = &chip->sd_card;
293 sd_clr_err_code(chip);
306 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
307 for (i = 0; i < (min(cmd_len, 6)); i++)
308 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0 + i,
311 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
313 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
314 (u8)(byte_cnt >> 8));
315 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
317 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
320 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
322 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
323 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
324 SD_CHECK_CRC7 | SD_RSP_LEN_6);
325 if (trans_mode != SD_TM_AUTO_TUNING)
326 rtsx_add_cmd(chip, WRITE_REG_CMD,
327 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
329 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
330 trans_mode | SD_TRANSFER_START);
331 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
334 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
336 if (retval == -ETIMEDOUT) {
337 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
338 SD_RSP_TYPE_R1, NULL, 0);
345 if (buf && buf_len) {
346 retval = rtsx_read_ppbuf(chip, buf, buf_len);
347 if (retval != STATUS_SUCCESS) {
353 return STATUS_SUCCESS;
356 static int sd_write_data(struct rtsx_chip *chip, u8 trans_mode,
357 u8 *cmd, int cmd_len, u16 byte_cnt, u16 blk_cnt,
358 u8 bus_width, u8 *buf, int buf_len, int timeout)
360 struct sd_info *sd_card = &chip->sd_card;
364 sd_clr_err_code(chip);
370 /* This function can't write data more than one page */
375 if (buf && buf_len) {
376 retval = rtsx_write_ppbuf(chip, buf, buf_len);
377 if (retval != STATUS_SUCCESS) {
386 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", cmd[0] - 0x40);
387 for (i = 0; i < (min(cmd_len, 6)); i++) {
388 rtsx_add_cmd(chip, WRITE_REG_CMD,
389 REG_SD_CMD0 + i, 0xFF, cmd[i]);
392 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
394 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
395 (u8)(byte_cnt >> 8));
396 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
398 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
401 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
403 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
404 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
405 SD_CHECK_CRC7 | SD_RSP_LEN_6);
407 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
408 trans_mode | SD_TRANSFER_START);
409 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
412 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
414 if (retval == -ETIMEDOUT) {
415 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
416 SD_RSP_TYPE_R1, NULL, 0);
423 return STATUS_SUCCESS;
426 static int sd_check_csd(struct rtsx_chip *chip, char check_wp)
428 struct sd_info *sd_card = &chip->sd_card;
431 u8 csd_ver, trans_speed;
434 for (i = 0; i < 6; i++) {
435 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
436 sd_set_err_code(chip, SD_NO_CARD);
441 retval = sd_send_cmd_get_rsp(chip, SEND_CSD, sd_card->sd_addr,
442 SD_RSP_TYPE_R2, rsp, 16);
443 if (retval == STATUS_SUCCESS)
452 memcpy(sd_card->raw_csd, rsp + 1, 15);
454 dev_dbg(rtsx_dev(chip), "CSD Response:\n");
455 dev_dbg(rtsx_dev(chip), "%*ph\n", 16, sd_card->raw_csd);
457 csd_ver = (rsp[1] & 0xc0) >> 6;
458 dev_dbg(rtsx_dev(chip), "csd_ver = %d\n", csd_ver);
460 trans_speed = rsp[4];
461 if ((trans_speed & 0x07) == 0x02) {
462 if ((trans_speed & 0xf8) >= 0x30) {
464 sd_card->sd_clock = 47;
466 sd_card->sd_clock = CLK_50;
468 } else if ((trans_speed & 0xf8) == 0x28) {
470 sd_card->sd_clock = 39;
472 sd_card->sd_clock = CLK_40;
474 } else if ((trans_speed & 0xf8) == 0x20) {
476 sd_card->sd_clock = 29;
478 sd_card->sd_clock = CLK_30;
480 } else if ((trans_speed & 0xf8) >= 0x10) {
482 sd_card->sd_clock = 23;
484 sd_card->sd_clock = CLK_20;
486 } else if ((trans_speed & 0x08) >= 0x08) {
488 sd_card->sd_clock = 19;
490 sd_card->sd_clock = CLK_20;
500 if (CHK_MMC_SECTOR_MODE(sd_card)) {
501 sd_card->capacity = 0;
503 if ((!CHK_SD_HCXC(sd_card)) || (csd_ver == 0)) {
504 u8 blk_size, c_size_mult;
507 blk_size = rsp[6] & 0x0F;
508 c_size = ((u16)(rsp[7] & 0x03) << 10)
510 + ((u16)(rsp[9] & 0xC0) >> 6);
511 c_size_mult = (u8)((rsp[10] & 0x03) << 1);
512 c_size_mult += (rsp[11] & 0x80) >> 7;
513 sd_card->capacity = (((u32)(c_size + 1)) *
514 (1 << (c_size_mult + 2)))
517 u32 total_sector = 0;
519 total_sector = (((u32)rsp[8] & 0x3f) << 16) |
520 ((u32)rsp[9] << 8) | (u32)rsp[10];
521 sd_card->capacity = (total_sector + 1) << 10;
527 chip->card_wp |= SD_CARD;
529 dev_dbg(rtsx_dev(chip), "CSD WP Status: 0x%x\n", rsp[15]);
532 return STATUS_SUCCESS;
535 static int sd_set_sample_push_timing(struct rtsx_chip *chip)
538 struct sd_info *sd_card = &chip->sd_card;
541 if ((chip->sd_ctl & SD_PUSH_POINT_CTL_MASK) == SD_PUSH_POINT_DELAY)
544 if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) == SD_SAMPLE_POINT_AUTO) {
545 if (chip->asic_code) {
546 if (CHK_SD_HS(sd_card) || CHK_MMC_52M(sd_card)) {
558 } else if ((chip->sd_ctl & SD_SAMPLE_POINT_CTL_MASK) ==
559 SD_SAMPLE_POINT_DELAY) {
566 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x1C, val);
572 return STATUS_SUCCESS;
575 static void sd_choose_proper_clock(struct rtsx_chip *chip)
577 struct sd_info *sd_card = &chip->sd_card;
579 if (CHK_SD_SDR104(sd_card)) {
581 sd_card->sd_clock = chip->asic_sd_sdr104_clk;
583 sd_card->sd_clock = chip->fpga_sd_sdr104_clk;
585 } else if (CHK_SD_DDR50(sd_card)) {
587 sd_card->sd_clock = chip->asic_sd_ddr50_clk;
589 sd_card->sd_clock = chip->fpga_sd_ddr50_clk;
591 } else if (CHK_SD_SDR50(sd_card)) {
593 sd_card->sd_clock = chip->asic_sd_sdr50_clk;
595 sd_card->sd_clock = chip->fpga_sd_sdr50_clk;
597 } else if (CHK_SD_HS(sd_card)) {
599 sd_card->sd_clock = chip->asic_sd_hs_clk;
601 sd_card->sd_clock = chip->fpga_sd_hs_clk;
603 } else if (CHK_MMC_52M(sd_card) || CHK_MMC_DDR52(sd_card)) {
605 sd_card->sd_clock = chip->asic_mmc_52m_clk;
607 sd_card->sd_clock = chip->fpga_mmc_52m_clk;
609 } else if (CHK_MMC_26M(sd_card)) {
611 sd_card->sd_clock = 48;
613 sd_card->sd_clock = CLK_50;
617 static int sd_set_clock_divider(struct rtsx_chip *chip, u8 clk_div)
620 u8 mask = 0, val = 0;
623 if (clk_div == SD_CLK_DIVIDE_0)
625 else if (clk_div == SD_CLK_DIVIDE_128)
627 else if (clk_div == SD_CLK_DIVIDE_256)
630 retval = rtsx_write_register(chip, REG_SD_CFG1, mask, val);
636 return STATUS_SUCCESS;
639 static int sd_set_init_para(struct rtsx_chip *chip)
641 struct sd_info *sd_card = &chip->sd_card;
644 retval = sd_set_sample_push_timing(chip);
645 if (retval != STATUS_SUCCESS) {
650 sd_choose_proper_clock(chip);
652 retval = switch_clock(chip, sd_card->sd_clock);
653 if (retval != STATUS_SUCCESS) {
658 return STATUS_SUCCESS;
661 int sd_select_card(struct rtsx_chip *chip, int select)
663 struct sd_info *sd_card = &chip->sd_card;
665 u8 cmd_idx, cmd_type;
669 cmd_idx = SELECT_CARD;
670 cmd_type = SD_RSP_TYPE_R1;
671 addr = sd_card->sd_addr;
673 cmd_idx = DESELECT_CARD;
674 cmd_type = SD_RSP_TYPE_R0;
678 retval = sd_send_cmd_get_rsp(chip, cmd_idx, addr, cmd_type, NULL, 0);
679 if (retval != STATUS_SUCCESS) {
684 return STATUS_SUCCESS;
687 #ifdef SUPPORT_SD_LOCK
688 static int sd_update_lock_status(struct rtsx_chip *chip)
690 struct sd_info *sd_card = &chip->sd_card;
694 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
695 SD_RSP_TYPE_R1, rsp, 5);
696 if (retval != STATUS_SUCCESS) {
702 sd_card->sd_lock_status |= SD_LOCKED;
704 sd_card->sd_lock_status &= ~SD_LOCKED;
706 dev_dbg(rtsx_dev(chip), "sd_card->sd_lock_status = 0x%x\n",
707 sd_card->sd_lock_status);
714 return STATUS_SUCCESS;
718 static int sd_wait_state_data_ready(struct rtsx_chip *chip, u8 state,
719 u8 data_ready, int polling_cnt)
721 struct sd_info *sd_card = &chip->sd_card;
725 for (i = 0; i < polling_cnt; i++) {
726 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
727 sd_card->sd_addr, SD_RSP_TYPE_R1,
729 if (retval != STATUS_SUCCESS) {
734 if (((rsp[3] & 0x1E) == state) &&
735 ((rsp[3] & 0x01) == data_ready))
736 return STATUS_SUCCESS;
743 static int sd_change_bank_voltage(struct rtsx_chip *chip, u8 voltage)
747 if (voltage == SD_IO_3V3) {
748 if (chip->asic_code) {
749 retval = rtsx_write_phy_register(chip, 0x08,
752 if (retval != STATUS_SUCCESS) {
757 retval = rtsx_write_register(chip, SD_PAD_CTL,
764 } else if (voltage == SD_IO_1V8) {
765 if (chip->asic_code) {
766 retval = rtsx_write_phy_register(chip, 0x08,
769 if (retval != STATUS_SUCCESS) {
774 retval = rtsx_write_register(chip, SD_PAD_CTL,
787 return STATUS_SUCCESS;
790 static int sd_voltage_switch(struct rtsx_chip *chip)
795 retval = rtsx_write_register(chip, SD_BUS_STAT,
796 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP,
803 retval = sd_send_cmd_get_rsp(chip, VOLTAGE_SWITCH, 0, SD_RSP_TYPE_R1,
805 if (retval != STATUS_SUCCESS) {
810 udelay(chip->sd_voltage_switch_delay);
812 retval = rtsx_read_register(chip, SD_BUS_STAT, &stat);
817 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
818 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
823 retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF,
829 retval = sd_change_bank_voltage(chip, SD_IO_1V8);
830 if (retval != STATUS_SUCCESS) {
837 retval = rtsx_write_register(chip, SD_BUS_STAT, 0xFF,
845 retval = rtsx_read_register(chip, SD_BUS_STAT, &stat);
850 if ((stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
851 SD_DAT1_STATUS | SD_DAT0_STATUS)) !=
852 (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS |
853 SD_DAT1_STATUS | SD_DAT0_STATUS)) {
854 dev_dbg(rtsx_dev(chip), "SD_BUS_STAT: 0x%x\n", stat);
855 rtsx_write_register(chip, SD_BUS_STAT, SD_CLK_TOGGLE_EN |
856 SD_CLK_FORCE_STOP, 0);
857 rtsx_write_register(chip, CARD_CLK_EN, 0xFF, 0);
862 retval = rtsx_write_register(chip, SD_BUS_STAT,
863 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0);
869 return STATUS_SUCCESS;
872 static int sd_reset_dcm(struct rtsx_chip *chip, u8 tune_dir)
876 if (tune_dir == TUNE_RX) {
877 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF,
883 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_RX);
889 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF,
895 retval = rtsx_write_register(chip, DCM_DRP_CTL, 0xFF, DCM_TX);
902 return STATUS_SUCCESS;
905 static int sd_change_phase(struct rtsx_chip *chip, u8 sample_point, u8 tune_dir)
907 struct sd_info *sd_card = &chip->sd_card;
908 u16 SD_VP_CTL, SD_DCMPS_CTL;
913 dev_dbg(rtsx_dev(chip), "%s (sample_point = %d, tune_dir = %d)\n",
914 __func__, sample_point, tune_dir);
916 if (tune_dir == TUNE_RX) {
917 SD_VP_CTL = SD_VPRX_CTL;
918 SD_DCMPS_CTL = SD_DCMPS_RX_CTL;
919 if (CHK_SD_DDR50(sd_card))
922 SD_VP_CTL = SD_VPTX_CTL;
923 SD_DCMPS_CTL = SD_DCMPS_TX_CTL;
926 if (chip->asic_code) {
927 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK,
933 retval = rtsx_write_register(chip, SD_VP_CTL, 0x1F,
939 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
945 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
946 PHASE_NOT_RESET, PHASE_NOT_RESET);
951 retval = rtsx_write_register(chip, CLK_CTL, CHANGE_CLK, 0);
957 rtsx_read_register(chip, SD_VP_CTL, &val);
958 dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
959 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
960 dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
963 retval = rtsx_write_register(chip, SD_VP_CTL,
971 retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF,
980 retval = rtsx_write_register(chip, CLK_CTL,
981 CHANGE_CLK, CHANGE_CLK);
987 retval = rtsx_write_register(chip, SD_VP_CTL, 0xFF,
998 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_DCMPS_CTL, DCMPS_CHANGE,
1000 rtsx_add_cmd(chip, CHECK_REG_CMD, SD_DCMPS_CTL,
1001 DCMPS_CHANGE_DONE, DCMPS_CHANGE_DONE);
1002 retval = rtsx_send_cmd(chip, SD_CARD, 100);
1003 if (retval != STATUS_SUCCESS) {
1008 val = *rtsx_get_cmd_data(chip);
1009 if (val & DCMPS_ERROR) {
1014 if ((val & DCMPS_CURRENT_PHASE) != sample_point) {
1019 retval = rtsx_write_register(chip, SD_DCMPS_CTL,
1026 retval = rtsx_write_register(chip, SD_VP_CTL,
1033 retval = rtsx_write_register(chip, CLK_CTL,
1044 retval = rtsx_write_register(chip, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0);
1050 return STATUS_SUCCESS;
1053 rtsx_read_register(chip, SD_VP_CTL, &val);
1054 dev_dbg(rtsx_dev(chip), "SD_VP_CTL: 0x%x\n", val);
1055 rtsx_read_register(chip, SD_DCMPS_CTL, &val);
1056 dev_dbg(rtsx_dev(chip), "SD_DCMPS_CTL: 0x%x\n", val);
1058 rtsx_write_register(chip, SD_DCMPS_CTL, DCMPS_CHANGE, 0);
1059 rtsx_write_register(chip, SD_VP_CTL, PHASE_CHANGE, 0);
1061 sd_reset_dcm(chip, tune_dir);
1065 static int sd_check_spec(struct rtsx_chip *chip, u8 bus_width)
1067 struct sd_info *sd_card = &chip->sd_card;
1071 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
1072 SD_RSP_TYPE_R1, NULL, 0);
1073 if (retval != STATUS_SUCCESS) {
1078 cmd[0] = 0x40 | SEND_SCR;
1084 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 8, 1, bus_width,
1086 if (retval != STATUS_SUCCESS) {
1087 rtsx_clear_sd_error(chip);
1092 memcpy(sd_card->raw_scr, buf, 8);
1094 if ((buf[0] & 0x0F) == 0) {
1099 return STATUS_SUCCESS;
1102 static int sd_query_switch_result(struct rtsx_chip *chip, u8 func_group,
1103 u8 func_to_switch, u8 *buf, int buf_len)
1105 u8 support_mask = 0, query_switch = 0, switch_busy = 0;
1106 int support_offset = 0, query_switch_offset = 0, check_busy_offset = 0;
1108 if (func_group == SD_FUNC_GROUP_1) {
1109 support_offset = FUNCTION_GROUP1_SUPPORT_OFFSET;
1110 query_switch_offset = FUNCTION_GROUP1_QUERY_SWITCH_OFFSET;
1111 check_busy_offset = FUNCTION_GROUP1_CHECK_BUSY_OFFSET;
1113 switch (func_to_switch) {
1115 support_mask = HS_SUPPORT_MASK;
1116 query_switch = HS_QUERY_SWITCH_OK;
1117 switch_busy = HS_SWITCH_BUSY;
1121 support_mask = SDR50_SUPPORT_MASK;
1122 query_switch = SDR50_QUERY_SWITCH_OK;
1123 switch_busy = SDR50_SWITCH_BUSY;
1126 case SDR104_SUPPORT:
1127 support_mask = SDR104_SUPPORT_MASK;
1128 query_switch = SDR104_QUERY_SWITCH_OK;
1129 switch_busy = SDR104_SWITCH_BUSY;
1133 support_mask = DDR50_SUPPORT_MASK;
1134 query_switch = DDR50_QUERY_SWITCH_OK;
1135 switch_busy = DDR50_SWITCH_BUSY;
1142 } else if (func_group == SD_FUNC_GROUP_3) {
1143 support_offset = FUNCTION_GROUP3_SUPPORT_OFFSET;
1144 query_switch_offset = FUNCTION_GROUP3_QUERY_SWITCH_OFFSET;
1145 check_busy_offset = FUNCTION_GROUP3_CHECK_BUSY_OFFSET;
1147 switch (func_to_switch) {
1148 case DRIVING_TYPE_A:
1149 support_mask = DRIVING_TYPE_A_MASK;
1150 query_switch = TYPE_A_QUERY_SWITCH_OK;
1151 switch_busy = TYPE_A_SWITCH_BUSY;
1154 case DRIVING_TYPE_C:
1155 support_mask = DRIVING_TYPE_C_MASK;
1156 query_switch = TYPE_C_QUERY_SWITCH_OK;
1157 switch_busy = TYPE_C_SWITCH_BUSY;
1160 case DRIVING_TYPE_D:
1161 support_mask = DRIVING_TYPE_D_MASK;
1162 query_switch = TYPE_D_QUERY_SWITCH_OK;
1163 switch_busy = TYPE_D_SWITCH_BUSY;
1170 } else if (func_group == SD_FUNC_GROUP_4) {
1171 support_offset = FUNCTION_GROUP4_SUPPORT_OFFSET;
1172 query_switch_offset = FUNCTION_GROUP4_QUERY_SWITCH_OFFSET;
1173 check_busy_offset = FUNCTION_GROUP4_CHECK_BUSY_OFFSET;
1175 switch (func_to_switch) {
1176 case CURRENT_LIMIT_400:
1177 support_mask = CURRENT_LIMIT_400_MASK;
1178 query_switch = CURRENT_LIMIT_400_QUERY_SWITCH_OK;
1179 switch_busy = CURRENT_LIMIT_400_SWITCH_BUSY;
1182 case CURRENT_LIMIT_600:
1183 support_mask = CURRENT_LIMIT_600_MASK;
1184 query_switch = CURRENT_LIMIT_600_QUERY_SWITCH_OK;
1185 switch_busy = CURRENT_LIMIT_600_SWITCH_BUSY;
1188 case CURRENT_LIMIT_800:
1189 support_mask = CURRENT_LIMIT_800_MASK;
1190 query_switch = CURRENT_LIMIT_800_QUERY_SWITCH_OK;
1191 switch_busy = CURRENT_LIMIT_800_SWITCH_BUSY;
1203 if (func_group == SD_FUNC_GROUP_1) {
1204 if (!(buf[support_offset] & support_mask) ||
1205 ((buf[query_switch_offset] & 0x0F) != query_switch)) {
1211 /* Check 'Busy Status' */
1212 if ((buf[DATA_STRUCTURE_VER_OFFSET] == 0x01) &&
1213 ((buf[check_busy_offset] & switch_busy) == switch_busy)) {
1218 return STATUS_SUCCESS;
1221 static int sd_check_switch_mode(struct rtsx_chip *chip, u8 mode, u8 func_group,
1222 u8 func_to_switch, u8 bus_width)
1224 struct sd_info *sd_card = &chip->sd_card;
1228 dev_dbg(rtsx_dev(chip), "%s (mode = %d, func_group = %d, func_to_switch = %d)\n",
1229 __func__, mode, func_group, func_to_switch);
1231 cmd[0] = 0x40 | SWITCH;
1234 if (func_group == SD_FUNC_GROUP_1) {
1237 cmd[4] = 0xF0 + func_to_switch;
1238 } else if (func_group == SD_FUNC_GROUP_3) {
1240 cmd[3] = 0xF0 + func_to_switch;
1242 } else if (func_group == SD_FUNC_GROUP_4) {
1244 cmd[3] = 0x0F + (func_to_switch << 4);
1247 cmd[1] = SD_CHECK_MODE;
1253 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1, bus_width,
1255 if (retval != STATUS_SUCCESS) {
1256 rtsx_clear_sd_error(chip);
1261 dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf);
1263 if (func_group == NO_ARGUMENT) {
1264 sd_card->func_group1_mask = buf[0x0D];
1265 sd_card->func_group2_mask = buf[0x0B];
1266 sd_card->func_group3_mask = buf[0x09];
1267 sd_card->func_group4_mask = buf[0x07];
1269 dev_dbg(rtsx_dev(chip), "func_group1_mask = 0x%02x\n",
1271 dev_dbg(rtsx_dev(chip), "func_group2_mask = 0x%02x\n",
1273 dev_dbg(rtsx_dev(chip), "func_group3_mask = 0x%02x\n",
1275 dev_dbg(rtsx_dev(chip), "func_group4_mask = 0x%02x\n",
1278 /* Maximum current consumption, check whether current is
1279 * acceptable; bit[511:496] = 0x0000 means some error happened.
1281 u16 cc = ((u16)buf[0] << 8) | buf[1];
1283 dev_dbg(rtsx_dev(chip), "Maximum current consumption: %dmA\n",
1285 if ((cc == 0) || (cc > 800)) {
1290 retval = sd_query_switch_result(chip, func_group,
1291 func_to_switch, buf, 64);
1292 if (retval != STATUS_SUCCESS) {
1297 if ((cc > 400) || (func_to_switch > CURRENT_LIMIT_400)) {
1298 retval = rtsx_write_register(chip, OCPPARA2,
1300 chip->sd_800mA_ocp_thd);
1305 retval = rtsx_write_register(chip, CARD_PWR_CTL,
1315 return STATUS_SUCCESS;
1318 static u8 downgrade_switch_mode(u8 func_group, u8 func_to_switch)
1320 if (func_group == SD_FUNC_GROUP_1) {
1321 if (func_to_switch > HS_SUPPORT)
1324 } else if (func_group == SD_FUNC_GROUP_4) {
1325 if (func_to_switch > CURRENT_LIMIT_200)
1329 return func_to_switch;
1332 static int sd_check_switch(struct rtsx_chip *chip,
1333 u8 func_group, u8 func_to_switch, u8 bus_width)
1337 bool switch_good = false;
1339 for (i = 0; i < 3; i++) {
1340 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1341 sd_set_err_code(chip, SD_NO_CARD);
1346 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, func_group,
1347 func_to_switch, bus_width);
1348 if (retval == STATUS_SUCCESS) {
1351 retval = sd_check_switch_mode(chip, SD_SWITCH_MODE,
1355 if (retval == STATUS_SUCCESS) {
1360 retval = rtsx_read_register(chip, SD_STAT1, &stat);
1365 if (stat & SD_CRC16_ERR) {
1366 dev_dbg(rtsx_dev(chip), "SD CRC16 error when switching mode\n");
1372 func_to_switch = downgrade_switch_mode(func_group,
1383 return STATUS_SUCCESS;
1386 static int sd_switch_function(struct rtsx_chip *chip, u8 bus_width)
1388 struct sd_info *sd_card = &chip->sd_card;
1391 u8 func_to_switch = 0;
1393 /* Get supported functions */
1394 retval = sd_check_switch_mode(chip, SD_CHECK_MODE, NO_ARGUMENT,
1395 NO_ARGUMENT, bus_width);
1396 if (retval != STATUS_SUCCESS) {
1401 sd_card->func_group1_mask &= ~(sd_card->sd_switch_fail);
1403 /* Function Group 1: Access Mode */
1404 for (i = 0; i < 4; i++) {
1405 switch ((u8)(chip->sd_speed_prior >> (i * 8))) {
1406 case SDR104_SUPPORT:
1407 if ((sd_card->func_group1_mask & SDR104_SUPPORT_MASK) &&
1409 func_to_switch = SDR104_SUPPORT;
1414 if ((sd_card->func_group1_mask & DDR50_SUPPORT_MASK) &&
1416 func_to_switch = DDR50_SUPPORT;
1421 if ((sd_card->func_group1_mask & SDR50_SUPPORT_MASK) &&
1423 func_to_switch = SDR50_SUPPORT;
1428 if (sd_card->func_group1_mask & HS_SUPPORT_MASK)
1429 func_to_switch = HS_SUPPORT;
1440 dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_1: func_to_switch = 0x%02x",
1443 #ifdef SUPPORT_SD_LOCK
1444 if ((sd_card->sd_lock_status & SD_SDR_RST) &&
1445 (func_to_switch == DDR50_SUPPORT) &&
1446 (sd_card->func_group1_mask & SDR50_SUPPORT_MASK)) {
1447 func_to_switch = SDR50_SUPPORT;
1448 dev_dbg(rtsx_dev(chip), "Using SDR50 instead of DDR50 for SD Lock\n");
1452 if (func_to_switch) {
1453 retval = sd_check_switch(chip, SD_FUNC_GROUP_1, func_to_switch,
1455 if (retval != STATUS_SUCCESS) {
1456 if (func_to_switch == SDR104_SUPPORT) {
1457 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK;
1458 } else if (func_to_switch == DDR50_SUPPORT) {
1459 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1461 } else if (func_to_switch == SDR50_SUPPORT) {
1462 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
1463 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
1469 if (func_to_switch == SDR104_SUPPORT)
1470 SET_SD_SDR104(sd_card);
1471 else if (func_to_switch == DDR50_SUPPORT)
1472 SET_SD_DDR50(sd_card);
1473 else if (func_to_switch == SDR50_SUPPORT)
1474 SET_SD_SDR50(sd_card);
1479 if (CHK_SD_DDR50(sd_card)) {
1480 retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06,
1486 retval = sd_set_sample_push_timing(chip);
1487 if (retval != STATUS_SUCCESS) {
1493 if (!func_to_switch || (func_to_switch == HS_SUPPORT)) {
1494 /* Do not try to switch current limit if the card doesn't
1495 * support UHS mode or we don't want it to support UHS mode
1497 return STATUS_SUCCESS;
1500 /* Function Group 4: Current Limit */
1501 func_to_switch = 0xFF;
1503 for (i = 0; i < 4; i++) {
1504 switch ((u8)(chip->sd_current_prior >> (i * 8))) {
1505 case CURRENT_LIMIT_800:
1506 if (sd_card->func_group4_mask & CURRENT_LIMIT_800_MASK)
1507 func_to_switch = CURRENT_LIMIT_800;
1511 case CURRENT_LIMIT_600:
1512 if (sd_card->func_group4_mask & CURRENT_LIMIT_600_MASK)
1513 func_to_switch = CURRENT_LIMIT_600;
1517 case CURRENT_LIMIT_400:
1518 if (sd_card->func_group4_mask & CURRENT_LIMIT_400_MASK)
1519 func_to_switch = CURRENT_LIMIT_400;
1523 case CURRENT_LIMIT_200:
1524 if (sd_card->func_group4_mask & CURRENT_LIMIT_200_MASK)
1525 func_to_switch = CURRENT_LIMIT_200;
1533 if (func_to_switch != 0xFF)
1537 dev_dbg(rtsx_dev(chip), "SD_FUNC_GROUP_4: func_to_switch = 0x%02x",
1540 if (func_to_switch <= CURRENT_LIMIT_800) {
1541 retval = sd_check_switch(chip, SD_FUNC_GROUP_4, func_to_switch,
1543 if (retval != STATUS_SUCCESS) {
1544 if (sd_check_err_code(chip, SD_NO_CARD)) {
1549 dev_dbg(rtsx_dev(chip), "Switch current limit finished! (%d)\n",
1553 if (CHK_SD_DDR50(sd_card)) {
1554 retval = rtsx_write_register(chip, SD_PUSH_POINT_CTL, 0x06, 0);
1561 return STATUS_SUCCESS;
1564 static int sd_wait_data_idle(struct rtsx_chip *chip)
1566 int retval = STATUS_TIMEDOUT;
1570 for (i = 0; i < 100; i++) {
1571 retval = rtsx_read_register(chip, SD_DATA_STATE, &val);
1576 if (val & SD_DATA_IDLE) {
1577 retval = STATUS_SUCCESS;
1582 dev_dbg(rtsx_dev(chip), "SD_DATA_STATE: 0x%02x\n", val);
1587 static int sd_sdr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1592 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1593 if (retval != STATUS_SUCCESS) {
1598 cmd[0] = 0x40 | SEND_TUNING_PATTERN;
1604 retval = sd_read_data(chip, SD_TM_AUTO_TUNING, cmd, 5, 0x40, 1,
1605 SD_BUS_WIDTH_4, NULL, 0, 100);
1606 if (retval != STATUS_SUCCESS) {
1607 (void)sd_wait_data_idle(chip);
1609 rtsx_clear_sd_error(chip);
1614 return STATUS_SUCCESS;
1617 static int sd_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1619 struct sd_info *sd_card = &chip->sd_card;
1623 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1624 if (retval != STATUS_SUCCESS) {
1629 dev_dbg(rtsx_dev(chip), "sd ddr tuning rx\n");
1631 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
1632 SD_RSP_TYPE_R1, NULL, 0);
1633 if (retval != STATUS_SUCCESS) {
1638 cmd[0] = 0x40 | SD_STATUS;
1644 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1,
1645 SD_BUS_WIDTH_4, NULL, 0, 100);
1646 if (retval != STATUS_SUCCESS) {
1647 (void)sd_wait_data_idle(chip);
1649 rtsx_clear_sd_error(chip);
1654 return STATUS_SUCCESS;
1657 static int mmc_ddr_tuning_rx_cmd(struct rtsx_chip *chip, u8 sample_point)
1659 struct sd_info *sd_card = &chip->sd_card;
1661 u8 cmd[5], bus_width;
1663 if (CHK_MMC_8BIT(sd_card))
1664 bus_width = SD_BUS_WIDTH_8;
1665 else if (CHK_MMC_4BIT(sd_card))
1666 bus_width = SD_BUS_WIDTH_4;
1668 bus_width = SD_BUS_WIDTH_1;
1670 retval = sd_change_phase(chip, sample_point, TUNE_RX);
1671 if (retval != STATUS_SUCCESS) {
1676 dev_dbg(rtsx_dev(chip), "mmc ddr tuning rx\n");
1678 cmd[0] = 0x40 | SEND_EXT_CSD;
1684 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 0x200, 1,
1685 bus_width, NULL, 0, 100);
1686 if (retval != STATUS_SUCCESS) {
1687 (void)sd_wait_data_idle(chip);
1689 rtsx_clear_sd_error(chip);
1694 return STATUS_SUCCESS;
1697 static int sd_sdr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1699 struct sd_info *sd_card = &chip->sd_card;
1702 retval = sd_change_phase(chip, sample_point, TUNE_TX);
1703 if (retval != STATUS_SUCCESS) {
1708 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1709 SD_RSP_80CLK_TIMEOUT_EN);
1715 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
1716 SD_RSP_TYPE_R1, NULL, 0);
1717 if (retval != STATUS_SUCCESS) {
1718 if (sd_check_err_code(chip, SD_RSP_TIMEOUT)) {
1719 rtsx_write_register(chip, SD_CFG3,
1720 SD_RSP_80CLK_TIMEOUT_EN, 0);
1726 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1733 return STATUS_SUCCESS;
1736 static int sd_ddr_tuning_tx_cmd(struct rtsx_chip *chip, u8 sample_point)
1738 struct sd_info *sd_card = &chip->sd_card;
1740 u8 cmd[5], bus_width;
1742 retval = sd_change_phase(chip, sample_point, TUNE_TX);
1743 if (retval != STATUS_SUCCESS) {
1748 if (CHK_SD(sd_card)) {
1749 bus_width = SD_BUS_WIDTH_4;
1751 if (CHK_MMC_8BIT(sd_card))
1752 bus_width = SD_BUS_WIDTH_8;
1753 else if (CHK_MMC_4BIT(sd_card))
1754 bus_width = SD_BUS_WIDTH_4;
1756 bus_width = SD_BUS_WIDTH_1;
1759 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
1760 if (retval != STATUS_SUCCESS) {
1765 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1766 SD_RSP_80CLK_TIMEOUT_EN);
1772 cmd[0] = 0x40 | PROGRAM_CSD;
1778 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_2, cmd, 5, 16, 1,
1779 bus_width, sd_card->raw_csd, 16, 100);
1780 if (retval != STATUS_SUCCESS) {
1781 rtsx_clear_sd_error(chip);
1782 rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0);
1787 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1794 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr, SD_RSP_TYPE_R1,
1797 return STATUS_SUCCESS;
1800 static u8 sd_search_final_phase(struct rtsx_chip *chip, u32 phase_map,
1803 struct sd_info *sd_card = &chip->sd_card;
1804 struct timing_phase_path path[MAX_PHASE + 1];
1805 int i, j, cont_path_cnt;
1807 int max_len, final_path_idx;
1808 u8 final_phase = 0xFF;
1810 if (phase_map == 0xFFFFFFFF) {
1811 if (tune_dir == TUNE_RX)
1812 final_phase = (u8)chip->sd_default_rx_phase;
1814 final_phase = (u8)chip->sd_default_tx_phase;
1822 for (i = 0; i < MAX_PHASE + 1; i++) {
1823 if (phase_map & (1 << i)) {
1826 j = cont_path_cnt++;
1834 if (cont_path_cnt) {
1835 int idx = cont_path_cnt - 1;
1837 path[idx].len = path[idx].end -
1838 path[idx].start + 1;
1839 path[idx].mid = path[idx].start +
1845 if (cont_path_cnt == 0) {
1846 dev_dbg(rtsx_dev(chip), "No continuous phase path\n");
1849 int idx = cont_path_cnt - 1;
1851 path[idx].len = path[idx].end - path[idx].start + 1;
1852 path[idx].mid = path[idx].start + path[idx].len / 2;
1855 if ((path[0].start == 0) &&
1856 (path[cont_path_cnt - 1].end == MAX_PHASE)) {
1857 path[0].start = path[cont_path_cnt - 1].start - MAX_PHASE - 1;
1858 path[0].len += path[cont_path_cnt - 1].len;
1859 path[0].mid = path[0].start + path[0].len / 2;
1860 if (path[0].mid < 0)
1861 path[0].mid += MAX_PHASE + 1;
1869 for (i = 0; i < cont_path_cnt; i++) {
1870 if (path[i].len > max_len) {
1871 max_len = path[i].len;
1872 final_phase = (u8)path[i].mid;
1876 dev_dbg(rtsx_dev(chip), "path[%d].start = %d\n",
1878 dev_dbg(rtsx_dev(chip), "path[%d].end = %d\n", i, path[i].end);
1879 dev_dbg(rtsx_dev(chip), "path[%d].len = %d\n", i, path[i].len);
1880 dev_dbg(rtsx_dev(chip), "path[%d].mid = %d\n", i, path[i].mid);
1881 dev_dbg(rtsx_dev(chip), "\n");
1884 if (tune_dir == TUNE_TX) {
1885 if (CHK_SD_SDR104(sd_card)) {
1887 int temp_mid = (max_len - 16) / 2;
1888 int temp_final_phase =
1889 path[final_path_idx].end -
1890 (max_len - (6 + temp_mid));
1892 if (temp_final_phase < 0)
1893 final_phase = (u8)(temp_final_phase +
1896 final_phase = (u8)temp_final_phase;
1898 } else if (CHK_SD_SDR50(sd_card)) {
1900 int temp_mid = (max_len - 13) / 2;
1901 int temp_final_phase =
1902 path[final_path_idx].end -
1903 (max_len - (3 + temp_mid));
1905 if (temp_final_phase < 0)
1906 final_phase = (u8)(temp_final_phase +
1909 final_phase = (u8)temp_final_phase;
1915 dev_dbg(rtsx_dev(chip), "Final chosen phase: %d\n", final_phase);
1919 static int sd_tuning_rx(struct rtsx_chip *chip)
1921 struct sd_info *sd_card = &chip->sd_card;
1924 u32 raw_phase_map[3], phase_map;
1926 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
1928 if (CHK_SD(sd_card)) {
1929 if (CHK_SD_DDR50(sd_card))
1930 tuning_cmd = sd_ddr_tuning_rx_cmd;
1932 tuning_cmd = sd_sdr_tuning_rx_cmd;
1935 if (CHK_MMC_DDR52(sd_card)) {
1936 tuning_cmd = mmc_ddr_tuning_rx_cmd;
1943 for (i = 0; i < 3; i++) {
1944 raw_phase_map[i] = 0;
1945 for (j = MAX_PHASE; j >= 0; j--) {
1946 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1947 sd_set_err_code(chip, SD_NO_CARD);
1952 retval = tuning_cmd(chip, (u8)j);
1953 if (retval == STATUS_SUCCESS)
1954 raw_phase_map[i] |= 1 << j;
1958 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
1959 for (i = 0; i < 3; i++)
1960 dev_dbg(rtsx_dev(chip), "RX raw_phase_map[%d] = 0x%08x\n",
1961 i, raw_phase_map[i]);
1963 dev_dbg(rtsx_dev(chip), "RX phase_map = 0x%08x\n", phase_map);
1965 final_phase = sd_search_final_phase(chip, phase_map, TUNE_RX);
1966 if (final_phase == 0xFF) {
1971 retval = sd_change_phase(chip, final_phase, TUNE_RX);
1972 if (retval != STATUS_SUCCESS) {
1977 return STATUS_SUCCESS;
1980 static int sd_ddr_pre_tuning_tx(struct rtsx_chip *chip)
1982 struct sd_info *sd_card = &chip->sd_card;
1988 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
1989 SD_RSP_80CLK_TIMEOUT_EN);
1996 for (i = MAX_PHASE; i >= 0; i--) {
1997 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
1998 sd_set_err_code(chip, SD_NO_CARD);
1999 rtsx_write_register(chip, SD_CFG3,
2000 SD_RSP_80CLK_TIMEOUT_EN, 0);
2005 retval = sd_change_phase(chip, (u8)i, TUNE_TX);
2006 if (retval != STATUS_SUCCESS)
2009 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
2010 sd_card->sd_addr, SD_RSP_TYPE_R1,
2012 if ((retval == STATUS_SUCCESS) ||
2013 !sd_check_err_code(chip, SD_RSP_TIMEOUT))
2014 phase_map |= 1 << i;
2017 retval = rtsx_write_register(chip, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN,
2024 dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase_map = 0x%08x\n",
2027 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
2028 if (final_phase == 0xFF) {
2033 retval = sd_change_phase(chip, final_phase, TUNE_TX);
2034 if (retval != STATUS_SUCCESS) {
2039 dev_dbg(rtsx_dev(chip), "DDR TX pre tune phase: %d\n",
2042 return STATUS_SUCCESS;
2045 static int sd_tuning_tx(struct rtsx_chip *chip)
2047 struct sd_info *sd_card = &chip->sd_card;
2050 u32 raw_phase_map[3], phase_map;
2052 int (*tuning_cmd)(struct rtsx_chip *chip, u8 sample_point);
2054 if (CHK_SD(sd_card)) {
2055 if (CHK_SD_DDR50(sd_card))
2056 tuning_cmd = sd_ddr_tuning_tx_cmd;
2058 tuning_cmd = sd_sdr_tuning_tx_cmd;
2061 if (CHK_MMC_DDR52(sd_card)) {
2062 tuning_cmd = sd_ddr_tuning_tx_cmd;
2069 for (i = 0; i < 3; i++) {
2070 raw_phase_map[i] = 0;
2071 for (j = MAX_PHASE; j >= 0; j--) {
2072 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2073 sd_set_err_code(chip, SD_NO_CARD);
2074 rtsx_write_register(chip, SD_CFG3,
2075 SD_RSP_80CLK_TIMEOUT_EN, 0);
2080 retval = tuning_cmd(chip, (u8)j);
2081 if (retval == STATUS_SUCCESS)
2082 raw_phase_map[i] |= 1 << j;
2086 phase_map = raw_phase_map[0] & raw_phase_map[1] & raw_phase_map[2];
2087 for (i = 0; i < 3; i++)
2088 dev_dbg(rtsx_dev(chip), "TX raw_phase_map[%d] = 0x%08x\n",
2089 i, raw_phase_map[i]);
2091 dev_dbg(rtsx_dev(chip), "TX phase_map = 0x%08x\n", phase_map);
2093 final_phase = sd_search_final_phase(chip, phase_map, TUNE_TX);
2094 if (final_phase == 0xFF) {
2099 retval = sd_change_phase(chip, final_phase, TUNE_TX);
2100 if (retval != STATUS_SUCCESS) {
2105 return STATUS_SUCCESS;
2108 static int sd_sdr_tuning(struct rtsx_chip *chip)
2112 retval = sd_tuning_tx(chip);
2113 if (retval != STATUS_SUCCESS) {
2118 retval = sd_tuning_rx(chip);
2119 if (retval != STATUS_SUCCESS) {
2124 return STATUS_SUCCESS;
2127 static int sd_ddr_tuning(struct rtsx_chip *chip)
2131 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
2132 retval = sd_ddr_pre_tuning_tx(chip);
2133 if (retval != STATUS_SUCCESS) {
2138 retval = sd_change_phase(chip, (u8)chip->sd_ddr_tx_phase,
2140 if (retval != STATUS_SUCCESS) {
2146 retval = sd_tuning_rx(chip);
2147 if (retval != STATUS_SUCCESS) {
2152 if (!(chip->sd_ctl & SD_DDR_TX_PHASE_SET_BY_USER)) {
2153 retval = sd_tuning_tx(chip);
2154 if (retval != STATUS_SUCCESS) {
2160 return STATUS_SUCCESS;
2163 static int mmc_ddr_tuning(struct rtsx_chip *chip)
2167 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
2168 retval = sd_ddr_pre_tuning_tx(chip);
2169 if (retval != STATUS_SUCCESS) {
2174 retval = sd_change_phase(chip, (u8)chip->mmc_ddr_tx_phase,
2176 if (retval != STATUS_SUCCESS) {
2182 retval = sd_tuning_rx(chip);
2183 if (retval != STATUS_SUCCESS) {
2188 if (!(chip->sd_ctl & MMC_DDR_TX_PHASE_SET_BY_USER)) {
2189 retval = sd_tuning_tx(chip);
2190 if (retval != STATUS_SUCCESS) {
2196 return STATUS_SUCCESS;
2199 int sd_switch_clock(struct rtsx_chip *chip)
2201 struct sd_info *sd_card = &chip->sd_card;
2205 retval = select_card(chip, SD_CARD);
2206 if (retval != STATUS_SUCCESS) {
2211 retval = switch_clock(chip, sd_card->sd_clock);
2212 if (retval != STATUS_SUCCESS) {
2218 if (CHK_SD(sd_card)) {
2219 if (CHK_SD_DDR50(sd_card))
2220 retval = sd_ddr_tuning(chip);
2222 retval = sd_sdr_tuning(chip);
2224 if (CHK_MMC_DDR52(sd_card))
2225 retval = mmc_ddr_tuning(chip);
2228 if (retval != STATUS_SUCCESS) {
2234 return STATUS_SUCCESS;
2237 static int sd_prepare_reset(struct rtsx_chip *chip)
2239 struct sd_info *sd_card = &chip->sd_card;
2242 if (chip->asic_code)
2243 sd_card->sd_clock = 29;
2245 sd_card->sd_clock = CLK_30;
2247 sd_card->sd_type = 0;
2248 sd_card->seq_mode = 0;
2249 sd_card->sd_data_buf_ready = 0;
2250 sd_card->capacity = 0;
2252 #ifdef SUPPORT_SD_LOCK
2253 sd_card->sd_lock_status = 0;
2254 sd_card->sd_erase_status = 0;
2257 chip->capacity[chip->card2lun[SD_CARD]] = 0;
2260 retval = sd_set_init_para(chip);
2261 if (retval != STATUS_SUCCESS) {
2266 retval = rtsx_write_register(chip, REG_SD_CFG1, 0xFF, 0x40);
2272 retval = rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR,
2273 SD_STOP | SD_CLR_ERR);
2279 retval = select_card(chip, SD_CARD);
2280 if (retval != STATUS_SUCCESS) {
2285 return STATUS_SUCCESS;
2288 static int sd_pull_ctl_disable(struct rtsx_chip *chip)
2292 if (CHECK_PID(chip, 0x5208)) {
2293 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF,
2294 XD_D3_PD | SD_D7_PD | SD_CLK_PD |
2300 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF,
2301 SD_D6_PD | SD_D0_PD | SD_D1_PD |
2307 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF,
2308 SD_D4_PD | XD_CE_PD | XD_CLE_PD |
2314 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF,
2315 XD_RDY_PD | SD_D3_PD | SD_D2_PD |
2321 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF,
2322 MS_INS_PU | SD_WP_PD | SD_CD_PU |
2328 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF,
2329 MS_D5_PD | MS_D4_PD);
2334 } else if (CHECK_PID(chip, 0x5288)) {
2335 if (CHECK_BARO_PKG(chip, QFN)) {
2336 retval = rtsx_write_register(chip, CARD_PULL_CTL1,
2342 retval = rtsx_write_register(chip, CARD_PULL_CTL2,
2348 retval = rtsx_write_register(chip, CARD_PULL_CTL3,
2354 retval = rtsx_write_register(chip, CARD_PULL_CTL4,
2363 return STATUS_SUCCESS;
2366 int sd_pull_ctl_enable(struct rtsx_chip *chip)
2370 rtsx_init_cmd(chip);
2372 if (CHECK_PID(chip, 0x5208)) {
2373 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2374 XD_D3_PD | SD_DAT7_PU | SD_CLK_NP | SD_D5_PU);
2375 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2376 SD_D6_PU | SD_D0_PU | SD_D1_PU | XD_D5_PD);
2377 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2378 SD_D4_PU | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
2379 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2380 XD_RDY_PD | SD_D3_PU | SD_D2_PU | XD_ALE_PD);
2381 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
2382 MS_INS_PU | SD_WP_PU | SD_CD_PU | SD_CMD_PU);
2383 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
2384 MS_D5_PD | MS_D4_PD);
2385 } else if (CHECK_PID(chip, 0x5288)) {
2386 if (CHECK_BARO_PKG(chip, QFN)) {
2387 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
2389 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
2391 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
2393 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
2398 retval = rtsx_send_cmd(chip, SD_CARD, 100);
2404 return STATUS_SUCCESS;
2407 static int sd_init_power(struct rtsx_chip *chip)
2411 retval = sd_power_off_card3v3(chip);
2412 if (retval != STATUS_SUCCESS) {
2417 if (!chip->ft2_fast_mode)
2420 retval = enable_card_clock(chip, SD_CARD);
2421 if (retval != STATUS_SUCCESS) {
2426 if (chip->asic_code) {
2427 retval = sd_pull_ctl_enable(chip);
2428 if (retval != STATUS_SUCCESS) {
2433 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
2434 FPGA_SD_PULL_CTL_BIT | 0x20, 0);
2441 if (!chip->ft2_fast_mode) {
2442 retval = card_power_on(chip, SD_CARD);
2443 if (retval != STATUS_SUCCESS) {
2451 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
2452 dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
2460 retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN,
2467 return STATUS_SUCCESS;
2470 static int sd_dummy_clock(struct rtsx_chip *chip)
2474 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0x01);
2480 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x01, 0);
2486 return STATUS_SUCCESS;
2489 static int sd_read_lba0(struct rtsx_chip *chip)
2491 struct sd_info *sd_card = &chip->sd_card;
2493 u8 cmd[5], bus_width;
2495 cmd[0] = 0x40 | READ_SINGLE_BLOCK;
2501 if (CHK_SD(sd_card)) {
2502 bus_width = SD_BUS_WIDTH_4;
2504 if (CHK_MMC_8BIT(sd_card))
2505 bus_width = SD_BUS_WIDTH_8;
2506 else if (CHK_MMC_4BIT(sd_card))
2507 bus_width = SD_BUS_WIDTH_4;
2509 bus_width = SD_BUS_WIDTH_1;
2512 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 512, 1,
2513 bus_width, NULL, 0, 100);
2514 if (retval != STATUS_SUCCESS) {
2515 rtsx_clear_sd_error(chip);
2520 return STATUS_SUCCESS;
2523 static int sd_check_wp_state(struct rtsx_chip *chip)
2525 struct sd_info *sd_card = &chip->sd_card;
2531 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2532 SD_RSP_TYPE_R1, NULL, 0);
2533 if (retval != STATUS_SUCCESS) {
2538 cmd[0] = 0x40 | SD_STATUS;
2544 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, 64, 1,
2545 SD_BUS_WIDTH_4, buf, 64, 250);
2546 if (retval != STATUS_SUCCESS) {
2547 rtsx_clear_sd_error(chip);
2549 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2550 SD_RSP_TYPE_R1, NULL, 0);
2555 dev_dbg(rtsx_dev(chip), "ACMD13:\n");
2556 dev_dbg(rtsx_dev(chip), "%*ph\n", 64, buf);
2558 sd_card_type = ((u16)buf[2] << 8) | buf[3];
2559 dev_dbg(rtsx_dev(chip), "sd_card_type = 0x%04x\n", sd_card_type);
2560 if ((sd_card_type == 0x0001) || (sd_card_type == 0x0002)) {
2561 /* ROM card or OTP */
2562 chip->card_wp |= SD_CARD;
2565 /* Check SD Machanical Write-Protect Switch */
2566 val = rtsx_readl(chip, RTSX_BIPR);
2567 if (val & SD_WRITE_PROTECT)
2568 chip->card_wp |= SD_CARD;
2570 return STATUS_SUCCESS;
2573 static int reset_sd(struct rtsx_chip *chip)
2575 struct sd_info *sd_card = &chip->sd_card;
2576 bool hi_cap_flow = false;
2577 int retval, i = 0, j = 0, k = 0;
2578 bool sd_dont_switch = false;
2579 bool support_1v8 = false;
2580 bool try_sdio = true;
2582 u8 switch_bus_width;
2584 bool sd20_mode = false;
2593 hi_cap_flow = false;
2595 #ifdef SUPPORT_SD_LOCK
2596 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
2597 goto SD_UNLOCK_ENTRY;
2600 retval = sd_prepare_reset(chip);
2601 if (retval != STATUS_SUCCESS)
2604 retval = sd_dummy_clock(chip);
2605 if (retval != STATUS_SUCCESS)
2608 if (CHK_SDIO_EXIST(chip) && !CHK_SDIO_IGNORED(chip) && try_sdio) {
2611 for (; rty_cnt < chip->sdio_retry_cnt; rty_cnt++) {
2612 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2613 sd_set_err_code(chip, SD_NO_CARD);
2617 retval = sd_send_cmd_get_rsp(chip, IO_SEND_OP_COND, 0,
2618 SD_RSP_TYPE_R4, rsp, 5);
2619 if (retval == STATUS_SUCCESS) {
2620 int func_num = (rsp[1] >> 4) & 0x07;
2623 dev_dbg(rtsx_dev(chip), "SD_IO card (Function number: %d)!\n",
2632 sd_init_power(chip);
2634 sd_dummy_clock(chip);
2637 dev_dbg(rtsx_dev(chip), "Normal card!\n");
2640 /* Start Initialization Process of SD Card */
2642 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
2644 if (retval != STATUS_SUCCESS)
2649 retval = sd_send_cmd_get_rsp(chip, SEND_IF_COND, 0x000001AA,
2650 SD_RSP_TYPE_R7, rsp, 5);
2651 if (retval == STATUS_SUCCESS) {
2652 if ((rsp[4] == 0xAA) && ((rsp[3] & 0x0f) == 0x01)) {
2654 voltage = SUPPORT_VOLTAGE | 0x40000000;
2659 voltage = SUPPORT_VOLTAGE;
2661 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0,
2662 SD_RSP_TYPE_R0, NULL, 0);
2663 if (retval != STATUS_SUCCESS)
2670 retval = sd_send_cmd_get_rsp(chip, APP_CMD, 0, SD_RSP_TYPE_R1,
2672 if (retval != STATUS_SUCCESS) {
2673 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
2674 sd_set_err_code(chip, SD_NO_CARD);
2685 retval = sd_send_cmd_get_rsp(chip, SD_APP_OP_COND, voltage,
2686 SD_RSP_TYPE_R3, rsp, 5);
2687 if (retval != STATUS_SUCCESS) {
2697 } while (!(rsp[1] & 0x80) && (i < 255));
2704 SET_SD_HCXC(sd_card);
2706 CLR_SD_HCXC(sd_card);
2708 support_1v8 = false;
2710 CLR_SD_HCXC(sd_card);
2711 support_1v8 = false;
2713 dev_dbg(rtsx_dev(chip), "support_1v8 = %d\n", support_1v8);
2716 retval = sd_voltage_switch(chip);
2717 if (retval != STATUS_SUCCESS)
2721 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
2723 if (retval != STATUS_SUCCESS)
2726 for (i = 0; i < 3; i++) {
2727 retval = sd_send_cmd_get_rsp(chip, SEND_RELATIVE_ADDR, 0,
2728 SD_RSP_TYPE_R6, rsp, 5);
2729 if (retval != STATUS_SUCCESS)
2732 sd_card->sd_addr = (u32)rsp[1] << 24;
2733 sd_card->sd_addr += (u32)rsp[2] << 16;
2735 if (sd_card->sd_addr)
2739 retval = sd_check_csd(chip, 1);
2740 if (retval != STATUS_SUCCESS)
2743 retval = sd_select_card(chip, 1);
2744 if (retval != STATUS_SUCCESS)
2747 #ifdef SUPPORT_SD_LOCK
2749 retval = sd_update_lock_status(chip);
2750 if (retval != STATUS_SUCCESS)
2753 if (sd_card->sd_lock_status & SD_LOCKED) {
2754 sd_card->sd_lock_status |= (SD_LOCK_1BIT_MODE | SD_PWD_EXIST);
2755 return STATUS_SUCCESS;
2756 } else if (!(sd_card->sd_lock_status & SD_UNLOCK_POW_ON)) {
2757 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
2761 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2762 SD_RSP_TYPE_R1, NULL, 0);
2763 if (retval != STATUS_SUCCESS)
2766 retval = sd_send_cmd_get_rsp(chip, SET_CLR_CARD_DETECT, 0,
2767 SD_RSP_TYPE_R1, NULL, 0);
2768 if (retval != STATUS_SUCCESS)
2772 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2773 SD_RSP_TYPE_R1, NULL, 0);
2774 if (retval != STATUS_SUCCESS)
2777 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2778 SD_RSP_TYPE_R1, NULL, 0);
2779 if (retval != STATUS_SUCCESS)
2782 switch_bus_width = SD_BUS_WIDTH_4;
2784 switch_bus_width = SD_BUS_WIDTH_1;
2787 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
2789 if (retval != STATUS_SUCCESS)
2792 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
2793 if (retval != STATUS_SUCCESS)
2796 if (!(sd_card->raw_csd[4] & 0x40))
2797 sd_dont_switch = true;
2799 if (!sd_dont_switch) {
2801 /* Set sd_switch_fail here, because we needn't
2802 * switch to UHS mode
2804 sd_card->sd_switch_fail = SDR104_SUPPORT_MASK |
2805 DDR50_SUPPORT_MASK | SDR50_SUPPORT_MASK;
2808 /* Check the card whether follow SD1.1 spec or higher */
2809 retval = sd_check_spec(chip, switch_bus_width);
2810 if (retval == STATUS_SUCCESS) {
2811 retval = sd_switch_function(chip, switch_bus_width);
2812 if (retval != STATUS_SUCCESS) {
2813 sd_init_power(chip);
2814 sd_dont_switch = true;
2821 sd_init_power(chip);
2822 sd_dont_switch = true;
2831 retval = sd_send_cmd_get_rsp(chip, APP_CMD, sd_card->sd_addr,
2832 SD_RSP_TYPE_R1, NULL, 0);
2833 if (retval != STATUS_SUCCESS)
2836 retval = sd_send_cmd_get_rsp(chip, SET_BUS_WIDTH, 2,
2837 SD_RSP_TYPE_R1, NULL, 0);
2838 if (retval != STATUS_SUCCESS)
2842 #ifdef SUPPORT_SD_LOCK
2843 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
2846 if (!sd20_mode && CHK_SD30_SPEED(sd_card)) {
2849 retval = rtsx_write_register(chip, SD30_DRIVE_SEL, 0x07,
2850 chip->sd30_drive_sel_1v8);
2856 retval = sd_set_init_para(chip);
2857 if (retval != STATUS_SUCCESS)
2860 if (CHK_SD_DDR50(sd_card))
2861 retval = sd_ddr_tuning(chip);
2863 retval = sd_sdr_tuning(chip);
2865 if (retval != STATUS_SUCCESS) {
2869 retval = sd_init_power(chip);
2870 if (retval != STATUS_SUCCESS)
2879 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
2880 SD_RSP_TYPE_R1, NULL, 0);
2882 if (CHK_SD_DDR50(sd_card)) {
2883 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
2884 if (retval != STATUS_SUCCESS)
2889 retval = sd_read_lba0(chip);
2890 if (retval != STATUS_SUCCESS) {
2894 retval = sd_init_power(chip);
2895 if (retval != STATUS_SUCCESS)
2906 retval = sd_check_wp_state(chip);
2907 if (retval != STATUS_SUCCESS)
2910 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
2912 #ifdef SUPPORT_SD_LOCK
2913 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
2914 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF,
2920 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF,
2929 return STATUS_SUCCESS;
2936 static int mmc_test_switch_bus(struct rtsx_chip *chip, u8 width)
2938 struct sd_info *sd_card = &chip->sd_card;
2940 u8 buf[8] = {0}, bus_width, *ptr;
2944 retval = sd_send_cmd_get_rsp(chip, BUSTEST_W, 0, SD_RSP_TYPE_R1, NULL,
2946 if (retval != STATUS_SUCCESS) {
2951 if (width == MMC_8BIT_BUS) {
2956 bus_width = SD_BUS_WIDTH_8;
2961 bus_width = SD_BUS_WIDTH_4;
2964 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0x02);
2965 if (retval != STATUS_SUCCESS) {
2970 retval = sd_write_data(chip, SD_TM_AUTO_WRITE_3, NULL, 0, byte_cnt, 1,
2971 bus_width, buf, len, 100);
2972 if (retval != STATUS_SUCCESS) {
2973 rtsx_clear_sd_error(chip);
2974 rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2979 retval = rtsx_write_register(chip, REG_SD_CFG3, 0x02, 0);
2980 if (retval != STATUS_SUCCESS) {
2985 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", BUSTEST_R);
2987 rtsx_init_cmd(chip);
2989 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | BUSTEST_R);
2991 if (width == MMC_8BIT_BUS)
2992 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
2995 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L,
2998 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
2999 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
3001 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, SD_CALCULATE_CRC7 |
3002 SD_NO_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3003 SD_CHECK_CRC7 | SD_RSP_LEN_6);
3004 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
3006 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3007 SD_TM_NORMAL_READ | SD_TRANSFER_START);
3008 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
3011 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2, 0, 0);
3012 if (width == MMC_8BIT_BUS)
3013 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 1, 0, 0);
3015 retval = rtsx_send_cmd(chip, SD_CARD, 100);
3017 rtsx_clear_sd_error(chip);
3022 ptr = rtsx_get_cmd_data(chip) + 1;
3024 if (width == MMC_8BIT_BUS) {
3025 dev_dbg(rtsx_dev(chip), "BUSTEST_R [8bits]: 0x%02x 0x%02x\n",
3027 if ((ptr[0] == 0xAA) && (ptr[1] == 0x55)) {
3031 if (CHK_MMC_DDR52(sd_card))
3036 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
3037 SD_RSP_TYPE_R1b, rsp, 5);
3038 if ((retval == STATUS_SUCCESS) &&
3039 !(rsp[4] & MMC_SWITCH_ERR))
3040 return SWITCH_SUCCESS;
3043 dev_dbg(rtsx_dev(chip), "BUSTEST_R [4bits]: 0x%02x\n", ptr[0]);
3044 if (ptr[0] == 0xA5) {
3048 if (CHK_MMC_DDR52(sd_card))
3053 retval = sd_send_cmd_get_rsp(chip, SWITCH, arg,
3054 SD_RSP_TYPE_R1b, rsp, 5);
3055 if ((retval == STATUS_SUCCESS) &&
3056 !(rsp[4] & MMC_SWITCH_ERR))
3057 return SWITCH_SUCCESS;
3065 static int mmc_switch_timing_bus(struct rtsx_chip *chip, bool switch_ddr)
3067 struct sd_info *sd_card = &chip->sd_card;
3069 u8 *ptr, card_type, card_type_mask = 0;
3071 CLR_MMC_HS(sd_card);
3073 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n", SEND_EXT_CSD);
3075 rtsx_init_cmd(chip);
3077 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3078 0x40 | SEND_EXT_CSD);
3079 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, 0);
3080 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, 0);
3081 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, 0);
3082 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, 0);
3084 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0);
3085 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 2);
3086 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF, 1);
3087 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF, 0);
3089 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3090 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | SD_NO_WAIT_BUSY_END |
3091 SD_CHECK_CRC7 | SD_RSP_LEN_6);
3092 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
3094 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3095 SD_TM_NORMAL_READ | SD_TRANSFER_START);
3096 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
3099 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 196, 0xFF, 0);
3100 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 212, 0xFF, 0);
3101 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 213, 0xFF, 0);
3102 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 214, 0xFF, 0);
3103 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 215, 0xFF, 0);
3105 retval = rtsx_send_cmd(chip, SD_CARD, 1000);
3107 if (retval == -ETIMEDOUT) {
3108 rtsx_clear_sd_error(chip);
3109 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3110 SD_RSP_TYPE_R1, NULL, 0);
3116 ptr = rtsx_get_cmd_data(chip);
3117 if (ptr[0] & SD_TRANSFER_ERR) {
3118 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3119 SD_RSP_TYPE_R1, NULL, 0);
3124 if (CHK_MMC_SECTOR_MODE(sd_card)) {
3125 sd_card->capacity = ((u32)ptr[5] << 24) | ((u32)ptr[4] << 16) |
3126 ((u32)ptr[3] << 8) | ((u32)ptr[2]);
3129 card_type_mask = 0x03;
3130 card_type = ptr[1] & card_type_mask;
3134 if (card_type & 0x04) {
3136 SET_MMC_DDR52(sd_card);
3138 SET_MMC_52M(sd_card);
3139 } else if (card_type & 0x02) {
3140 SET_MMC_52M(sd_card);
3142 SET_MMC_26M(sd_card);
3145 retval = sd_send_cmd_get_rsp(chip, SWITCH, 0x03B90100,
3146 SD_RSP_TYPE_R1b, rsp, 5);
3147 if ((retval != STATUS_SUCCESS) || (rsp[4] & MMC_SWITCH_ERR))
3148 CLR_MMC_HS(sd_card);
3151 sd_choose_proper_clock(chip);
3152 retval = switch_clock(chip, sd_card->sd_clock);
3153 if (retval != STATUS_SUCCESS) {
3158 /* Test Bus Procedure */
3159 retval = mmc_test_switch_bus(chip, MMC_8BIT_BUS);
3160 if (retval == SWITCH_SUCCESS) {
3161 SET_MMC_8BIT(sd_card);
3162 chip->card_bus_width[chip->card2lun[SD_CARD]] = 8;
3163 #ifdef SUPPORT_SD_LOCK
3164 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
3166 } else if (retval == SWITCH_FAIL) {
3167 retval = mmc_test_switch_bus(chip, MMC_4BIT_BUS);
3168 if (retval == SWITCH_SUCCESS) {
3169 SET_MMC_4BIT(sd_card);
3170 chip->card_bus_width[chip->card2lun[SD_CARD]] = 4;
3171 #ifdef SUPPORT_SD_LOCK
3172 sd_card->sd_lock_status &= ~SD_LOCK_1BIT_MODE;
3174 } else if (retval == SWITCH_FAIL) {
3175 CLR_MMC_8BIT(sd_card);
3176 CLR_MMC_4BIT(sd_card);
3186 return STATUS_SUCCESS;
3189 static int reset_mmc(struct rtsx_chip *chip)
3191 struct sd_info *sd_card = &chip->sd_card;
3192 int retval, i = 0, j = 0, k = 0;
3193 bool switch_ddr = true;
3198 #ifdef SUPPORT_SD_LOCK
3199 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON)
3200 goto MMC_UNLOCK_ENTRY;
3204 retval = sd_prepare_reset(chip);
3205 if (retval != STATUS_SUCCESS) {
3213 retval = sd_send_cmd_get_rsp(chip, GO_IDLE_STATE, 0, SD_RSP_TYPE_R0,
3215 if (retval != STATUS_SUCCESS) {
3221 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3222 sd_set_err_code(chip, SD_NO_CARD);
3227 retval = sd_send_cmd_get_rsp(chip, SEND_OP_COND,
3228 (SUPPORT_VOLTAGE | 0x40000000),
3229 SD_RSP_TYPE_R3, rsp, 5);
3230 if (retval != STATUS_SUCCESS) {
3231 if (sd_check_err_code(chip, SD_BUSY) ||
3232 sd_check_err_code(chip, SD_TO_ERR)) {
3235 sd_clr_err_code(chip);
3244 sd_clr_err_code(chip);
3255 } while (!(rsp[1] & 0x80) && (i < 255));
3262 if ((rsp[1] & 0x60) == 0x40)
3263 SET_MMC_SECTOR_MODE(sd_card);
3265 CLR_MMC_SECTOR_MODE(sd_card);
3267 retval = sd_send_cmd_get_rsp(chip, ALL_SEND_CID, 0, SD_RSP_TYPE_R2,
3269 if (retval != STATUS_SUCCESS) {
3274 sd_card->sd_addr = 0x00100000;
3275 retval = sd_send_cmd_get_rsp(chip, SET_RELATIVE_ADDR, sd_card->sd_addr,
3276 SD_RSP_TYPE_R6, rsp, 5);
3277 if (retval != STATUS_SUCCESS) {
3282 retval = sd_check_csd(chip, 1);
3283 if (retval != STATUS_SUCCESS) {
3288 spec_ver = (sd_card->raw_csd[0] & 0x3C) >> 2;
3290 retval = sd_select_card(chip, 1);
3291 if (retval != STATUS_SUCCESS) {
3296 retval = sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200, SD_RSP_TYPE_R1,
3298 if (retval != STATUS_SUCCESS) {
3303 #ifdef SUPPORT_SD_LOCK
3305 retval = sd_update_lock_status(chip);
3306 if (retval != STATUS_SUCCESS) {
3312 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3313 if (retval != STATUS_SUCCESS) {
3318 chip->card_bus_width[chip->card2lun[SD_CARD]] = 1;
3320 if (!sd_card->mmc_dont_switch_bus) {
3321 if (spec_ver == 4) {
3323 retval = mmc_switch_timing_bus(chip, switch_ddr);
3324 if (retval != STATUS_SUCCESS) {
3325 retval = sd_init_power(chip);
3326 if (retval != STATUS_SUCCESS) {
3330 sd_card->mmc_dont_switch_bus = 1;
3336 if (CHK_MMC_SECTOR_MODE(sd_card) && (sd_card->capacity == 0)) {
3341 if (switch_ddr && CHK_MMC_DDR52(sd_card)) {
3342 retval = sd_set_init_para(chip);
3343 if (retval != STATUS_SUCCESS) {
3348 retval = mmc_ddr_tuning(chip);
3349 if (retval != STATUS_SUCCESS) {
3350 retval = sd_init_power(chip);
3351 if (retval != STATUS_SUCCESS) {
3361 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3362 if (retval == STATUS_SUCCESS) {
3363 retval = sd_read_lba0(chip);
3364 if (retval != STATUS_SUCCESS) {
3365 retval = sd_init_power(chip);
3366 if (retval != STATUS_SUCCESS) {
3379 #ifdef SUPPORT_SD_LOCK
3380 if (sd_card->sd_lock_status & SD_UNLOCK_POW_ON) {
3381 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_H, 0xFF,
3387 retval = rtsx_write_register(chip, REG_SD_BLOCK_CNT_L, 0xFF,
3396 temp = rtsx_readl(chip, RTSX_BIPR);
3397 if (temp & SD_WRITE_PROTECT)
3398 chip->card_wp |= SD_CARD;
3400 return STATUS_SUCCESS;
3403 int reset_sd_card(struct rtsx_chip *chip)
3405 struct sd_info *sd_card = &chip->sd_card;
3408 sd_init_reg_addr(chip);
3410 memset(sd_card, 0, sizeof(struct sd_info));
3411 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3413 retval = enable_card_clock(chip, SD_CARD);
3414 if (retval != STATUS_SUCCESS) {
3419 if (chip->ignore_sd && CHK_SDIO_EXIST(chip) &&
3420 !CHK_SDIO_IGNORED(chip)) {
3421 if (chip->asic_code) {
3422 retval = sd_pull_ctl_enable(chip);
3423 if (retval != STATUS_SUCCESS) {
3428 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
3429 FPGA_SD_PULL_CTL_BIT |
3431 if (retval != STATUS_SUCCESS) {
3436 retval = card_share_mode(chip, SD_CARD);
3437 if (retval != STATUS_SUCCESS) {
3447 retval = sd_init_power(chip);
3448 if (retval != STATUS_SUCCESS) {
3453 if (chip->sd_ctl & RESET_MMC_FIRST) {
3454 retval = reset_mmc(chip);
3455 if (retval != STATUS_SUCCESS) {
3456 if (sd_check_err_code(chip, SD_NO_CARD)) {
3461 retval = reset_sd(chip);
3462 if (retval != STATUS_SUCCESS) {
3468 retval = reset_sd(chip);
3469 if (retval != STATUS_SUCCESS) {
3470 if (sd_check_err_code(chip, SD_NO_CARD)) {
3479 retval = reset_mmc(chip);
3480 if (retval != STATUS_SUCCESS) {
3487 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3488 if (retval != STATUS_SUCCESS) {
3493 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3498 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3504 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3506 retval = sd_set_init_para(chip);
3507 if (retval != STATUS_SUCCESS) {
3512 dev_dbg(rtsx_dev(chip), "sd_card->sd_type = 0x%x\n", sd_card->sd_type);
3514 return STATUS_SUCCESS;
3517 static int reset_mmc_only(struct rtsx_chip *chip)
3519 struct sd_info *sd_card = &chip->sd_card;
3522 sd_card->sd_type = 0;
3523 sd_card->seq_mode = 0;
3524 sd_card->sd_data_buf_ready = 0;
3525 sd_card->capacity = 0;
3526 sd_card->sd_switch_fail = 0;
3528 #ifdef SUPPORT_SD_LOCK
3529 sd_card->sd_lock_status = 0;
3530 sd_card->sd_erase_status = 0;
3533 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity = 0;
3535 retval = enable_card_clock(chip, SD_CARD);
3536 if (retval != STATUS_SUCCESS) {
3541 retval = sd_init_power(chip);
3542 if (retval != STATUS_SUCCESS) {
3547 retval = reset_mmc(chip);
3548 if (retval != STATUS_SUCCESS) {
3553 retval = sd_set_clock_divider(chip, SD_CLK_DIVIDE_0);
3554 if (retval != STATUS_SUCCESS) {
3559 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_L, 0xFF, 0);
3564 retval = rtsx_write_register(chip, REG_SD_BYTE_CNT_H, 0xFF, 2);
3570 chip->capacity[chip->card2lun[SD_CARD]] = sd_card->capacity;
3572 retval = sd_set_init_para(chip);
3573 if (retval != STATUS_SUCCESS) {
3578 dev_dbg(rtsx_dev(chip), "In %s, sd_card->sd_type = 0x%x\n",
3579 __func__, sd_card->sd_type);
3581 return STATUS_SUCCESS;
3584 #define WAIT_DATA_READY_RTY_CNT 255
3586 static int wait_data_buf_ready(struct rtsx_chip *chip)
3588 struct sd_info *sd_card = &chip->sd_card;
3591 for (i = 0; i < WAIT_DATA_READY_RTY_CNT; i++) {
3592 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3593 sd_set_err_code(chip, SD_NO_CARD);
3598 sd_card->sd_data_buf_ready = 0;
3600 retval = sd_send_cmd_get_rsp(chip, SEND_STATUS,
3601 sd_card->sd_addr, SD_RSP_TYPE_R1,
3603 if (retval != STATUS_SUCCESS) {
3608 if (sd_card->sd_data_buf_ready) {
3609 return sd_send_cmd_get_rsp(chip, SEND_STATUS,
3610 sd_card->sd_addr, SD_RSP_TYPE_R1, NULL, 0);
3614 sd_set_err_code(chip, SD_TO_ERR);
3620 void sd_stop_seq_mode(struct rtsx_chip *chip)
3622 struct sd_info *sd_card = &chip->sd_card;
3625 if (sd_card->seq_mode) {
3626 retval = sd_switch_clock(chip);
3627 if (retval != STATUS_SUCCESS)
3630 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3631 SD_RSP_TYPE_R1b, NULL, 0);
3632 if (retval != STATUS_SUCCESS)
3633 sd_set_err_code(chip, SD_STS_ERR);
3635 retval = sd_wait_state_data_ready(chip, 0x08, 1, 1000);
3636 if (retval != STATUS_SUCCESS)
3637 sd_set_err_code(chip, SD_STS_ERR);
3639 sd_card->seq_mode = 0;
3641 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3645 static inline int sd_auto_tune_clock(struct rtsx_chip *chip)
3647 struct sd_info *sd_card = &chip->sd_card;
3650 if (chip->asic_code) {
3651 if (sd_card->sd_clock > 30)
3652 sd_card->sd_clock -= 20;
3654 switch (sd_card->sd_clock) {
3656 sd_card->sd_clock = CLK_150;
3660 sd_card->sd_clock = CLK_120;
3664 sd_card->sd_clock = CLK_100;
3668 sd_card->sd_clock = CLK_80;
3672 sd_card->sd_clock = CLK_60;
3676 sd_card->sd_clock = CLK_50;
3684 retval = sd_switch_clock(chip);
3685 if (retval != STATUS_SUCCESS) {
3690 return STATUS_SUCCESS;
3693 int sd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip, u32 start_sector,
3696 struct sd_info *sd_card = &chip->sd_card;
3701 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3702 dev_dbg(rtsx_dev(chip), "%s: Read %d %s from 0x%x\n", __func__,
3703 sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3706 dev_dbg(rtsx_dev(chip), "%s: Write %d %s to 0x%x\n", __func__,
3707 sector_cnt, (sector_cnt > 1) ? "sectors" : "sector",
3711 sd_card->cleanup_counter = 0;
3713 if (!(chip->card_ready & SD_CARD)) {
3714 sd_card->seq_mode = 0;
3716 retval = reset_sd_card(chip);
3717 if (retval == STATUS_SUCCESS) {
3718 chip->card_ready |= SD_CARD;
3719 chip->card_fail &= ~SD_CARD;
3721 chip->card_ready &= ~SD_CARD;
3722 chip->card_fail |= SD_CARD;
3723 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3724 chip->rw_need_retry = 1;
3730 if (!CHK_SD_HCXC(sd_card) && !CHK_MMC_SECTOR_MODE(sd_card))
3731 data_addr = start_sector << 9;
3733 data_addr = start_sector;
3735 sd_clr_err_code(chip);
3737 retval = sd_switch_clock(chip);
3738 if (retval != STATUS_SUCCESS) {
3739 sd_set_err_code(chip, SD_IO_ERR);
3744 if (sd_card->seq_mode &&
3745 ((sd_card->pre_dir != srb->sc_data_direction) ||
3746 ((sd_card->pre_sec_addr + sd_card->pre_sec_cnt) !=
3748 if ((sd_card->pre_sec_cnt < 0x80) &&
3749 (sd_card->pre_dir == DMA_FROM_DEVICE) &&
3750 !CHK_SD30_SPEED(sd_card) &&
3751 !CHK_SD_HS(sd_card) &&
3752 !CHK_MMC_HS(sd_card)) {
3753 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3754 SD_RSP_TYPE_R1, NULL, 0);
3757 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3758 SD_RSP_TYPE_R1b, NULL, 0);
3759 if (retval != STATUS_SUCCESS) {
3760 chip->rw_need_retry = 1;
3761 sd_set_err_code(chip, SD_STS_ERR);
3766 sd_card->seq_mode = 0;
3768 retval = rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
3769 if (retval != STATUS_SUCCESS) {
3770 sd_set_err_code(chip, SD_IO_ERR);
3775 if ((sd_card->pre_sec_cnt < 0x80) &&
3776 !CHK_SD30_SPEED(sd_card) &&
3777 !CHK_SD_HS(sd_card) &&
3778 !CHK_MMC_HS(sd_card)) {
3779 sd_send_cmd_get_rsp(chip, SEND_STATUS, sd_card->sd_addr,
3780 SD_RSP_TYPE_R1, NULL, 0);
3784 rtsx_init_cmd(chip);
3786 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF, 0x00);
3787 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF, 0x02);
3788 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
3790 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
3791 (u8)(sector_cnt >> 8));
3793 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
3795 if (CHK_MMC_8BIT(sd_card))
3796 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3797 0x03, SD_BUS_WIDTH_8);
3798 else if (CHK_MMC_4BIT(sd_card) || CHK_SD(sd_card))
3799 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3800 0x03, SD_BUS_WIDTH_4);
3802 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1,
3803 0x03, SD_BUS_WIDTH_1);
3805 if (sd_card->seq_mode) {
3806 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3807 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 |
3809 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, cfg2);
3811 trans_dma_enable(srb->sc_data_direction, chip, sector_cnt * 512,
3814 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3815 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3816 SD_TM_AUTO_READ_3 | SD_TRANSFER_START);
3818 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3819 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3822 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3823 SD_TRANSFER_END, SD_TRANSFER_END);
3825 rtsx_send_cmd_no_wait(chip);
3827 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3828 dev_dbg(rtsx_dev(chip), "SD/MMC CMD %d\n",
3829 READ_MULTIPLE_BLOCK);
3830 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
3831 0x40 | READ_MULTIPLE_BLOCK);
3832 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
3833 (u8)(data_addr >> 24));
3834 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
3835 (u8)(data_addr >> 16));
3836 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
3837 (u8)(data_addr >> 8));
3838 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
3841 cfg2 = SD_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3842 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 |
3844 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3847 trans_dma_enable(srb->sc_data_direction, chip,
3848 sector_cnt * 512, DMA_512);
3850 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3851 SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
3852 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3853 SD_TRANSFER_END, SD_TRANSFER_END);
3855 rtsx_send_cmd_no_wait(chip);
3857 retval = rtsx_send_cmd(chip, SD_CARD, 50);
3859 rtsx_clear_sd_error(chip);
3861 chip->rw_need_retry = 1;
3862 sd_set_err_code(chip, SD_TO_ERR);
3867 retval = wait_data_buf_ready(chip);
3868 if (retval != STATUS_SUCCESS) {
3869 chip->rw_need_retry = 1;
3870 sd_set_err_code(chip, SD_TO_ERR);
3875 retval = sd_send_cmd_get_rsp(chip, WRITE_MULTIPLE_BLOCK,
3876 data_addr, SD_RSP_TYPE_R1,
3878 if (retval != STATUS_SUCCESS) {
3879 chip->rw_need_retry = 1;
3884 rtsx_init_cmd(chip);
3886 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 |
3887 SD_NO_WAIT_BUSY_END |
3888 SD_NO_CHECK_CRC7 | SD_RSP_LEN_0;
3889 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF,
3892 trans_dma_enable(srb->sc_data_direction, chip,
3893 sector_cnt * 512, DMA_512);
3895 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
3896 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
3897 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
3898 SD_TRANSFER_END, SD_TRANSFER_END);
3900 rtsx_send_cmd_no_wait(chip);
3903 sd_card->seq_mode = 1;
3906 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
3907 scsi_bufflen(srb), scsi_sg_count(srb),
3908 srb->sc_data_direction, chip->sd_timeout);
3913 sd_card->seq_mode = 0;
3915 if (retval == -ETIMEDOUT)
3916 err = STATUS_TIMEDOUT;
3920 rtsx_read_register(chip, REG_SD_STAT1, &stat);
3921 rtsx_clear_sd_error(chip);
3922 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3923 chip->rw_need_retry = 0;
3924 dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n",
3930 chip->rw_need_retry = 1;
3932 retval = sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
3933 SD_RSP_TYPE_R1b, NULL, 0);
3934 if (retval != STATUS_SUCCESS) {
3935 sd_set_err_code(chip, SD_STS_ERR);
3940 if (stat & (SD_CRC7_ERR | SD_CRC16_ERR | SD_CRC_WRITE_ERR)) {
3941 dev_dbg(rtsx_dev(chip), "SD CRC error, tune clock!\n");
3942 sd_set_err_code(chip, SD_CRC_ERR);
3947 if (err == STATUS_TIMEDOUT) {
3948 sd_set_err_code(chip, SD_TO_ERR);
3957 sd_card->pre_sec_addr = start_sector;
3958 sd_card->pre_sec_cnt = sector_cnt;
3959 sd_card->pre_dir = srb->sc_data_direction;
3961 return STATUS_SUCCESS;
3964 sd_card->seq_mode = 0;
3966 if (detect_card_cd(chip, SD_CARD) != STATUS_SUCCESS) {
3967 chip->rw_need_retry = 0;
3968 dev_dbg(rtsx_dev(chip), "No card exist, exit %s\n", __func__);
3973 if (sd_check_err_code(chip, SD_CRC_ERR)) {
3974 if (CHK_MMC_4BIT(sd_card) || CHK_MMC_8BIT(sd_card)) {
3975 sd_card->mmc_dont_switch_bus = 1;
3976 reset_mmc_only(chip);
3977 sd_card->mmc_dont_switch_bus = 0;
3979 sd_card->need_retune = 1;
3980 sd_auto_tune_clock(chip);
3982 } else if (sd_check_err_code(chip, SD_TO_ERR | SD_STS_ERR)) {
3983 retval = reset_sd_card(chip);
3984 if (retval != STATUS_SUCCESS) {
3985 chip->card_ready &= ~SD_CARD;
3986 chip->card_fail |= SD_CARD;
3987 chip->capacity[chip->card2lun[SD_CARD]] = 0;
3996 int soft_reset_sd_card(struct rtsx_chip *chip)
3998 return reset_sd(chip);
4001 int ext_sd_send_cmd_get_rsp(struct rtsx_chip *chip, u8 cmd_idx, u32 arg,
4002 u8 rsp_type, u8 *rsp, int rsp_len,
4012 dev_dbg(rtsx_dev(chip), "EXT SD/MMC CMD %d\n", cmd_idx);
4014 if (rsp_type == SD_RSP_TYPE_R1b)
4019 rtsx_init_cmd(chip);
4021 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF, 0x40 | cmd_idx);
4022 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF, (u8)(arg >> 24));
4023 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF, (u8)(arg >> 16));
4024 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF, (u8)(arg >> 8));
4025 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF, (u8)arg);
4027 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
4028 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
4029 0x01, PINGPONG_BUFFER);
4030 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
4031 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START);
4032 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER, SD_TRANSFER_END,
4035 if (rsp_type == SD_RSP_TYPE_R2) {
4036 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
4038 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
4041 } else if (rsp_type != SD_RSP_TYPE_R0) {
4042 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
4044 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
4048 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0, 0);
4050 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_STAT1, 0, 0);
4052 retval = rtsx_send_cmd(chip, SD_CARD, timeout);
4054 if (retval == -ETIMEDOUT) {
4055 rtsx_clear_sd_error(chip);
4057 if (rsp_type & SD_WAIT_BUSY_END) {
4058 retval = sd_check_data0_status(chip);
4059 if (retval != STATUS_SUCCESS) {
4064 sd_set_err_code(chip, SD_TO_ERR);
4071 if (rsp_type == SD_RSP_TYPE_R0)
4072 return STATUS_SUCCESS;
4074 ptr = rtsx_get_cmd_data(chip) + 1;
4076 if ((ptr[0] & 0xC0) != 0) {
4077 sd_set_err_code(chip, SD_STS_ERR);
4082 if (!(rsp_type & SD_NO_CHECK_CRC7)) {
4083 if (ptr[stat_idx] & SD_CRC7_ERR) {
4084 if (cmd_idx == WRITE_MULTIPLE_BLOCK) {
4085 sd_set_err_code(chip, SD_CRC_ERR);
4089 if (rty_cnt < SD_MAX_RETRY_COUNT) {
4094 sd_set_err_code(chip, SD_CRC_ERR);
4101 if ((cmd_idx == SELECT_CARD) || (cmd_idx == APP_CMD) ||
4102 (cmd_idx == SEND_STATUS) || (cmd_idx == STOP_TRANSMISSION)) {
4103 if ((cmd_idx != STOP_TRANSMISSION) && !special_check) {
4104 if (ptr[1] & 0x80) {
4109 #ifdef SUPPORT_SD_LOCK
4110 if (ptr[1] & 0x7D) {
4112 if (ptr[1] & 0x7F) {
4117 if (ptr[2] & 0xF8) {
4122 if (cmd_idx == SELECT_CARD) {
4123 if (rsp_type == SD_RSP_TYPE_R2) {
4124 if ((ptr[3] & 0x1E) != 0x04) {
4133 memcpy(rsp, ptr, rsp_len);
4135 return STATUS_SUCCESS;
4138 int ext_sd_get_rsp(struct rtsx_chip *chip, int len, u8 *rsp, u8 rsp_type)
4140 int retval, rsp_len;
4143 if (rsp_type == SD_RSP_TYPE_R0)
4144 return STATUS_SUCCESS;
4146 rtsx_init_cmd(chip);
4148 if (rsp_type == SD_RSP_TYPE_R2) {
4149 for (reg_addr = PPBUF_BASE2; reg_addr < PPBUF_BASE2 + 16;
4151 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
4154 } else if (rsp_type != SD_RSP_TYPE_R0) {
4155 for (reg_addr = REG_SD_CMD0; reg_addr <= REG_SD_CMD4;
4157 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0xFF, 0);
4161 rtsx_add_cmd(chip, READ_REG_CMD, REG_SD_CMD5, 0xFF, 0);
4163 retval = rtsx_send_cmd(chip, SD_CARD, 100);
4164 if (retval != STATUS_SUCCESS) {
4170 int min_len = (rsp_len < len) ? rsp_len : len;
4172 memcpy(rsp, rtsx_get_cmd_data(chip), min_len);
4174 dev_dbg(rtsx_dev(chip), "min_len = %d\n", min_len);
4175 dev_dbg(rtsx_dev(chip), "Response in cmd buf: 0x%x 0x%x 0x%x 0x%x\n",
4176 rsp[0], rsp[1], rsp[2], rsp[3]);
4179 return STATUS_SUCCESS;
4182 int sd_pass_thru_mode(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4184 struct sd_info *sd_card = &chip->sd_card;
4185 unsigned int lun = SCSI_LUN(srb);
4208 sd_card->pre_cmd_err = 0;
4210 if (!(CHK_BIT(chip->lun_mc, lun))) {
4211 SET_BIT(chip->lun_mc, lun);
4212 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4214 return TRANSPORT_FAILED;
4217 if ((srb->cmnd[2] != 0x53) || (srb->cmnd[3] != 0x44) ||
4218 (srb->cmnd[4] != 0x20) || (srb->cmnd[5] != 0x43) ||
4219 (srb->cmnd[6] != 0x61) || (srb->cmnd[7] != 0x72) ||
4220 (srb->cmnd[8] != 0x64)) {
4221 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4223 return TRANSPORT_FAILED;
4226 switch (srb->cmnd[1] & 0x0F) {
4228 sd_card->sd_pass_thru_en = 0;
4232 sd_card->sd_pass_thru_en = 1;
4236 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4238 return TRANSPORT_FAILED;
4241 buf[5] = (CHK_SD(sd_card) == 1) ? 0x01 : 0x02;
4242 if (chip->card_wp & SD_CARD)
4245 buf[6] = (u8)(sd_card->sd_addr >> 16);
4246 buf[7] = (u8)(sd_card->sd_addr >> 24);
4248 buf[15] = chip->max_lun;
4250 len = min_t(int, 18, scsi_bufflen(srb));
4251 rtsx_stor_set_xfer_buf(buf, len, srb);
4253 return TRANSPORT_GOOD;
4256 static inline int get_rsp_type(struct scsi_cmnd *srb, u8 *rsp_type,
4259 if (!rsp_type || !rsp_len)
4262 switch (srb->cmnd[10]) {
4264 *rsp_type = SD_RSP_TYPE_R0;
4269 *rsp_type = SD_RSP_TYPE_R1;
4274 *rsp_type = SD_RSP_TYPE_R1b;
4279 *rsp_type = SD_RSP_TYPE_R2;
4284 *rsp_type = SD_RSP_TYPE_R3;
4292 return STATUS_SUCCESS;
4295 int sd_execute_no_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4297 struct sd_info *sd_card = &chip->sd_card;
4298 unsigned int lun = SCSI_LUN(srb);
4299 int retval, rsp_len;
4300 u8 cmd_idx, rsp_type;
4301 bool standby = false, acmd = false;
4304 if (!sd_card->sd_pass_thru_en) {
4305 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4307 return TRANSPORT_FAILED;
4310 retval = sd_switch_clock(chip);
4311 if (retval != STATUS_SUCCESS) {
4313 return TRANSPORT_FAILED;
4316 if (sd_card->pre_cmd_err) {
4317 sd_card->pre_cmd_err = 0;
4318 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4320 return TRANSPORT_FAILED;
4323 cmd_idx = srb->cmnd[2] & 0x3F;
4324 if (srb->cmnd[1] & 0x02)
4327 if (srb->cmnd[1] & 0x01)
4330 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4331 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4333 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4334 if (retval != STATUS_SUCCESS) {
4335 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4337 return TRANSPORT_FAILED;
4339 sd_card->last_rsp_type = rsp_type;
4341 retval = sd_switch_clock(chip);
4342 if (retval != STATUS_SUCCESS) {
4344 return TRANSPORT_FAILED;
4347 #ifdef SUPPORT_SD_LOCK
4348 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4349 if (CHK_MMC_8BIT(sd_card)) {
4350 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4352 if (retval != STATUS_SUCCESS) {
4354 return TRANSPORT_FAILED;
4357 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4358 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4360 if (retval != STATUS_SUCCESS) {
4362 return TRANSPORT_FAILED;
4367 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4368 if (retval != STATUS_SUCCESS) {
4370 return TRANSPORT_FAILED;
4375 retval = sd_select_card(chip, 0);
4376 if (retval != STATUS_SUCCESS) {
4378 goto sd_execute_cmd_failed;
4383 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4385 SD_RSP_TYPE_R1, NULL, 0,
4387 if (retval != STATUS_SUCCESS) {
4389 goto sd_execute_cmd_failed;
4393 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4394 sd_card->rsp, rsp_len, false);
4395 if (retval != STATUS_SUCCESS) {
4397 goto sd_execute_cmd_failed;
4401 retval = sd_select_card(chip, 1);
4402 if (retval != STATUS_SUCCESS) {
4404 goto sd_execute_cmd_failed;
4408 #ifdef SUPPORT_SD_LOCK
4409 retval = sd_update_lock_status(chip);
4410 if (retval != STATUS_SUCCESS) {
4412 goto sd_execute_cmd_failed;
4416 scsi_set_resid(srb, 0);
4417 return TRANSPORT_GOOD;
4419 sd_execute_cmd_failed:
4420 sd_card->pre_cmd_err = 1;
4421 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4422 release_sd_card(chip);
4423 do_reset_sd_card(chip);
4424 if (!(chip->card_ready & SD_CARD))
4425 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4428 return TRANSPORT_FAILED;
4431 int sd_execute_read_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4433 struct sd_info *sd_card = &chip->sd_card;
4434 unsigned int lun = SCSI_LUN(srb);
4435 int retval, rsp_len, i;
4436 bool read_err = false, cmd13_checkbit = false;
4437 u8 cmd_idx, rsp_type, bus_width;
4438 bool standby = false, send_cmd12 = false, acmd = false;
4441 if (!sd_card->sd_pass_thru_en) {
4442 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4444 return TRANSPORT_FAILED;
4447 if (sd_card->pre_cmd_err) {
4448 sd_card->pre_cmd_err = 0;
4449 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4451 return TRANSPORT_FAILED;
4454 retval = sd_switch_clock(chip);
4455 if (retval != STATUS_SUCCESS) {
4457 return TRANSPORT_FAILED;
4460 cmd_idx = srb->cmnd[2] & 0x3F;
4461 if (srb->cmnd[1] & 0x04)
4464 if (srb->cmnd[1] & 0x02)
4467 if (srb->cmnd[1] & 0x01)
4470 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
4471 << 8) | srb->cmnd[9];
4473 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4474 if (retval != STATUS_SUCCESS) {
4475 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4477 return TRANSPORT_FAILED;
4479 sd_card->last_rsp_type = rsp_type;
4481 retval = sd_switch_clock(chip);
4482 if (retval != STATUS_SUCCESS) {
4484 return TRANSPORT_FAILED;
4487 #ifdef SUPPORT_SD_LOCK
4488 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4489 if (CHK_MMC_8BIT(sd_card))
4490 bus_width = SD_BUS_WIDTH_8;
4491 else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card))
4492 bus_width = SD_BUS_WIDTH_4;
4494 bus_width = SD_BUS_WIDTH_1;
4496 bus_width = SD_BUS_WIDTH_4;
4498 dev_dbg(rtsx_dev(chip), "bus_width = %d\n", bus_width);
4500 bus_width = SD_BUS_WIDTH_4;
4503 if (data_len < 512) {
4504 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4505 SD_RSP_TYPE_R1, NULL, 0,
4507 if (retval != STATUS_SUCCESS) {
4509 goto sd_execute_read_cmd_failed;
4514 retval = sd_select_card(chip, 0);
4515 if (retval != STATUS_SUCCESS) {
4517 goto sd_execute_read_cmd_failed;
4522 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4524 SD_RSP_TYPE_R1, NULL, 0,
4526 if (retval != STATUS_SUCCESS) {
4528 goto sd_execute_read_cmd_failed;
4532 if (data_len <= 512) {
4535 u16 byte_cnt, blk_cnt;
4538 byte_cnt = ((u16)(srb->cmnd[8] & 0x03) << 8) | srb->cmnd[9];
4541 cmd[0] = 0x40 | cmd_idx;
4542 cmd[1] = srb->cmnd[3];
4543 cmd[2] = srb->cmnd[4];
4544 cmd[3] = srb->cmnd[5];
4545 cmd[4] = srb->cmnd[6];
4547 buf = kmalloc(data_len, GFP_KERNEL);
4550 return TRANSPORT_ERROR;
4553 retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd, 5, byte_cnt,
4554 blk_cnt, bus_width, buf, data_len, 2000);
4555 if (retval != STATUS_SUCCESS) {
4558 rtsx_clear_sd_error(chip);
4560 goto sd_execute_read_cmd_failed;
4563 min_len = min(data_len, scsi_bufflen(srb));
4564 rtsx_stor_set_xfer_buf(buf, min_len, srb);
4567 } else if (!(data_len & 0x1FF)) {
4568 rtsx_init_cmd(chip);
4570 trans_dma_enable(DMA_FROM_DEVICE, chip, data_len, DMA_512);
4572 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4574 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4576 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4577 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4578 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4579 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4581 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD0, 0xFF,
4583 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD1, 0xFF,
4585 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD2, 0xFF,
4587 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD3, 0xFF,
4589 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CMD4, 0xFF,
4592 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG1, 0x03, bus_width);
4593 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_CFG2, 0xFF, rsp_type);
4595 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER,
4596 0xFF, SD_TM_AUTO_READ_2 | SD_TRANSFER_START);
4597 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4598 SD_TRANSFER_END, SD_TRANSFER_END);
4600 rtsx_send_cmd_no_wait(chip);
4602 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
4605 DMA_FROM_DEVICE, 10000);
4608 rtsx_clear_sd_error(chip);
4610 goto sd_execute_read_cmd_failed;
4615 goto sd_execute_read_cmd_failed;
4618 retval = ext_sd_get_rsp(chip, rsp_len, sd_card->rsp, rsp_type);
4619 if (retval != STATUS_SUCCESS) {
4621 goto sd_execute_read_cmd_failed;
4625 retval = sd_select_card(chip, 1);
4626 if (retval != STATUS_SUCCESS) {
4628 goto sd_execute_read_cmd_failed;
4633 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
4634 SD_RSP_TYPE_R1b, NULL, 0,
4636 if (retval != STATUS_SUCCESS) {
4638 goto sd_execute_read_cmd_failed;
4642 if (data_len < 512) {
4643 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4644 SD_RSP_TYPE_R1, NULL, 0,
4646 if (retval != STATUS_SUCCESS) {
4648 goto sd_execute_read_cmd_failed;
4651 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4652 if (retval != STATUS_SUCCESS) {
4654 goto sd_execute_read_cmd_failed;
4657 retval = rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
4658 if (retval != STATUS_SUCCESS) {
4660 goto sd_execute_read_cmd_failed;
4664 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
4665 cmd13_checkbit = true;
4667 for (i = 0; i < 3; i++) {
4668 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
4670 SD_RSP_TYPE_R1, NULL, 0,
4672 if (retval == STATUS_SUCCESS)
4675 if (retval != STATUS_SUCCESS) {
4677 goto sd_execute_read_cmd_failed;
4680 scsi_set_resid(srb, 0);
4681 return TRANSPORT_GOOD;
4683 sd_execute_read_cmd_failed:
4684 sd_card->pre_cmd_err = 1;
4685 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
4687 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4689 release_sd_card(chip);
4690 do_reset_sd_card(chip);
4691 if (!(chip->card_ready & SD_CARD))
4692 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
4695 return TRANSPORT_FAILED;
4698 int sd_execute_write_data(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4700 struct sd_info *sd_card = &chip->sd_card;
4701 unsigned int lun = SCSI_LUN(srb);
4702 int retval, rsp_len, i;
4703 bool write_err = false, cmd13_checkbit = false;
4704 u8 cmd_idx, rsp_type;
4705 bool standby = false, send_cmd12 = false, acmd = false;
4707 #ifdef SUPPORT_SD_LOCK
4708 int lock_cmd_fail = 0;
4709 u8 sd_lock_state = 0;
4710 u8 lock_cmd_type = 0;
4713 if (!sd_card->sd_pass_thru_en) {
4714 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4716 return TRANSPORT_FAILED;
4719 if (sd_card->pre_cmd_err) {
4720 sd_card->pre_cmd_err = 0;
4721 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
4723 return TRANSPORT_FAILED;
4726 retval = sd_switch_clock(chip);
4727 if (retval != STATUS_SUCCESS) {
4729 return TRANSPORT_FAILED;
4732 cmd_idx = srb->cmnd[2] & 0x3F;
4733 if (srb->cmnd[1] & 0x04)
4736 if (srb->cmnd[1] & 0x02)
4739 if (srb->cmnd[1] & 0x01)
4742 data_len = ((u32)srb->cmnd[7] << 16) | ((u32)srb->cmnd[8]
4743 << 8) | srb->cmnd[9];
4744 arg = ((u32)srb->cmnd[3] << 24) | ((u32)srb->cmnd[4] << 16) |
4745 ((u32)srb->cmnd[5] << 8) | srb->cmnd[6];
4747 #ifdef SUPPORT_SD_LOCK
4748 if (cmd_idx == LOCK_UNLOCK) {
4749 sd_lock_state = sd_card->sd_lock_status;
4750 sd_lock_state &= SD_LOCKED;
4754 retval = get_rsp_type(srb, &rsp_type, &rsp_len);
4755 if (retval != STATUS_SUCCESS) {
4756 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
4758 return TRANSPORT_FAILED;
4760 sd_card->last_rsp_type = rsp_type;
4762 retval = sd_switch_clock(chip);
4763 if (retval != STATUS_SUCCESS) {
4765 return TRANSPORT_FAILED;
4768 #ifdef SUPPORT_SD_LOCK
4769 if ((sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) == 0) {
4770 if (CHK_MMC_8BIT(sd_card)) {
4771 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4773 if (retval != STATUS_SUCCESS) {
4775 return TRANSPORT_FAILED;
4778 } else if (CHK_SD(sd_card) || CHK_MMC_4BIT(sd_card)) {
4779 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03,
4781 if (retval != STATUS_SUCCESS) {
4783 return TRANSPORT_FAILED;
4788 retval = rtsx_write_register(chip, REG_SD_CFG1, 0x03, SD_BUS_WIDTH_4);
4789 if (retval != STATUS_SUCCESS) {
4791 return TRANSPORT_FAILED;
4795 if (data_len < 512) {
4796 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, data_len,
4797 SD_RSP_TYPE_R1, NULL, 0,
4799 if (retval != STATUS_SUCCESS) {
4801 goto sd_execute_write_cmd_failed;
4806 retval = sd_select_card(chip, 0);
4807 if (retval != STATUS_SUCCESS) {
4809 goto sd_execute_write_cmd_failed;
4814 retval = ext_sd_send_cmd_get_rsp(chip, APP_CMD,
4816 SD_RSP_TYPE_R1, NULL, 0,
4818 if (retval != STATUS_SUCCESS) {
4820 goto sd_execute_write_cmd_failed;
4824 retval = ext_sd_send_cmd_get_rsp(chip, cmd_idx, arg, rsp_type,
4825 sd_card->rsp, rsp_len, false);
4826 if (retval != STATUS_SUCCESS) {
4828 goto sd_execute_write_cmd_failed;
4831 if (data_len <= 512) {
4835 buf = kmalloc(data_len, GFP_KERNEL);
4838 return TRANSPORT_ERROR;
4841 rtsx_stor_get_xfer_buf(buf, data_len, srb);
4843 #ifdef SUPPORT_SD_LOCK
4844 if (cmd_idx == LOCK_UNLOCK)
4845 lock_cmd_type = buf[0] & 0x0F;
4848 if (data_len > 256) {
4849 rtsx_init_cmd(chip);
4850 for (i = 0; i < 256; i++) {
4851 rtsx_add_cmd(chip, WRITE_REG_CMD,
4852 PPBUF_BASE2 + i, 0xFF, buf[i]);
4854 retval = rtsx_send_cmd(chip, 0, 250);
4855 if (retval != STATUS_SUCCESS) {
4858 goto sd_execute_write_cmd_failed;
4861 rtsx_init_cmd(chip);
4862 for (i = 256; i < data_len; i++) {
4863 rtsx_add_cmd(chip, WRITE_REG_CMD,
4864 PPBUF_BASE2 + i, 0xFF, buf[i]);
4866 retval = rtsx_send_cmd(chip, 0, 250);
4867 if (retval != STATUS_SUCCESS) {
4870 goto sd_execute_write_cmd_failed;
4873 rtsx_init_cmd(chip);
4874 for (i = 0; i < data_len; i++) {
4875 rtsx_add_cmd(chip, WRITE_REG_CMD,
4876 PPBUF_BASE2 + i, 0xFF, buf[i]);
4878 retval = rtsx_send_cmd(chip, 0, 250);
4879 if (retval != STATUS_SUCCESS) {
4882 goto sd_execute_write_cmd_failed;
4888 rtsx_init_cmd(chip);
4890 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4891 srb->cmnd[8] & 0x03);
4892 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4894 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H, 0xFF,
4896 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L, 0xFF,
4898 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
4901 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4902 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4903 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4904 SD_TRANSFER_END, SD_TRANSFER_END);
4906 retval = rtsx_send_cmd(chip, SD_CARD, 250);
4907 } else if (!(data_len & 0x1FF)) {
4908 rtsx_init_cmd(chip);
4910 trans_dma_enable(DMA_TO_DEVICE, chip, data_len, DMA_512);
4912 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_H, 0xFF,
4914 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BYTE_CNT_L, 0xFF,
4916 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_H,
4917 0xFF, (srb->cmnd[7] & 0xFE) >> 1);
4918 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_BLOCK_CNT_L,
4919 0xFF, (u8)((data_len & 0x0001FE00) >> 9));
4921 rtsx_add_cmd(chip, WRITE_REG_CMD, REG_SD_TRANSFER, 0xFF,
4922 SD_TM_AUTO_WRITE_3 | SD_TRANSFER_START);
4923 rtsx_add_cmd(chip, CHECK_REG_CMD, REG_SD_TRANSFER,
4924 SD_TRANSFER_END, SD_TRANSFER_END);
4926 rtsx_send_cmd_no_wait(chip);
4928 retval = rtsx_transfer_data(chip, SD_CARD, scsi_sglist(srb),
4931 DMA_TO_DEVICE, 10000);
4935 goto sd_execute_write_cmd_failed;
4940 rtsx_clear_sd_error(chip);
4942 goto sd_execute_write_cmd_failed;
4945 #ifdef SUPPORT_SD_LOCK
4946 if (cmd_idx == LOCK_UNLOCK) {
4947 if (lock_cmd_type == SD_ERASE) {
4948 sd_card->sd_erase_status = SD_UNDER_ERASING;
4949 scsi_set_resid(srb, 0);
4950 return TRANSPORT_GOOD;
4953 rtsx_init_cmd(chip);
4954 rtsx_add_cmd(chip, CHECK_REG_CMD, 0xFD30, 0x02, 0x02);
4956 rtsx_send_cmd(chip, SD_CARD, 250);
4958 retval = sd_update_lock_status(chip);
4959 if (retval != STATUS_SUCCESS) {
4960 dev_dbg(rtsx_dev(chip), "Lock command fail!\n");
4964 #endif /* SUPPORT_SD_LOCK */
4967 retval = sd_select_card(chip, 1);
4968 if (retval != STATUS_SUCCESS) {
4970 goto sd_execute_write_cmd_failed;
4975 retval = ext_sd_send_cmd_get_rsp(chip, STOP_TRANSMISSION, 0,
4976 SD_RSP_TYPE_R1b, NULL, 0,
4978 if (retval != STATUS_SUCCESS) {
4980 goto sd_execute_write_cmd_failed;
4984 if (data_len < 512) {
4985 retval = ext_sd_send_cmd_get_rsp(chip, SET_BLOCKLEN, 0x200,
4986 SD_RSP_TYPE_R1, NULL, 0,
4988 if (retval != STATUS_SUCCESS) {
4990 goto sd_execute_write_cmd_failed;
4993 retval = rtsx_write_register(chip, SD_BYTE_CNT_H, 0xFF, 0x02);
4994 if (retval != STATUS_SUCCESS) {
4996 goto sd_execute_write_cmd_failed;
4999 rtsx_write_register(chip, SD_BYTE_CNT_L, 0xFF, 0x00);
5000 if (retval != STATUS_SUCCESS) {
5002 goto sd_execute_write_cmd_failed;
5006 if ((srb->cmnd[1] & 0x02) || (srb->cmnd[1] & 0x04))
5007 cmd13_checkbit = true;
5009 for (i = 0; i < 3; i++) {
5010 retval = ext_sd_send_cmd_get_rsp(chip, SEND_STATUS,
5012 SD_RSP_TYPE_R1, NULL, 0,
5014 if (retval == STATUS_SUCCESS)
5017 if (retval != STATUS_SUCCESS) {
5019 goto sd_execute_write_cmd_failed;
5022 #ifdef SUPPORT_SD_LOCK
5023 if (cmd_idx == LOCK_UNLOCK) {
5024 if (!lock_cmd_fail) {
5025 dev_dbg(rtsx_dev(chip), "lock_cmd_type = 0x%x\n",
5027 if (lock_cmd_type & SD_CLR_PWD)
5028 sd_card->sd_lock_status &= ~SD_PWD_EXIST;
5030 if (lock_cmd_type & SD_SET_PWD)
5031 sd_card->sd_lock_status |= SD_PWD_EXIST;
5034 dev_dbg(rtsx_dev(chip), "sd_lock_state = 0x%x, sd_card->sd_lock_status = 0x%x\n",
5035 sd_lock_state, sd_card->sd_lock_status);
5036 if (sd_lock_state ^ (sd_card->sd_lock_status & SD_LOCKED)) {
5037 sd_card->sd_lock_notify = 1;
5038 if (sd_lock_state) {
5039 if (sd_card->sd_lock_status & SD_LOCK_1BIT_MODE) {
5040 sd_card->sd_lock_status |= (
5041 SD_UNLOCK_POW_ON | SD_SDR_RST);
5042 if (CHK_SD(sd_card)) {
5043 retval = reset_sd(chip);
5044 if (retval != STATUS_SUCCESS) {
5045 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
5047 goto sd_execute_write_cmd_failed;
5051 sd_card->sd_lock_status &= ~(SD_UNLOCK_POW_ON | SD_SDR_RST);
5057 if (lock_cmd_fail) {
5058 scsi_set_resid(srb, 0);
5059 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
5061 return TRANSPORT_FAILED;
5063 #endif /* SUPPORT_SD_LOCK */
5065 scsi_set_resid(srb, 0);
5066 return TRANSPORT_GOOD;
5068 sd_execute_write_cmd_failed:
5069 sd_card->pre_cmd_err = 1;
5070 set_sense_type(chip, lun, SENSE_TYPE_NO_SENSE);
5072 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
5074 release_sd_card(chip);
5075 do_reset_sd_card(chip);
5076 if (!(chip->card_ready & SD_CARD))
5077 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
5080 return TRANSPORT_FAILED;
5083 int sd_get_cmd_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
5085 struct sd_info *sd_card = &chip->sd_card;
5086 unsigned int lun = SCSI_LUN(srb);
5090 if (!sd_card->sd_pass_thru_en) {
5091 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
5093 return TRANSPORT_FAILED;
5096 if (sd_card->pre_cmd_err) {
5097 sd_card->pre_cmd_err = 0;
5098 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
5100 return TRANSPORT_FAILED;
5103 data_len = ((u16)srb->cmnd[7] << 8) | srb->cmnd[8];
5105 if (sd_card->last_rsp_type == SD_RSP_TYPE_R0) {
5106 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
5108 return TRANSPORT_FAILED;
5109 } else if (sd_card->last_rsp_type == SD_RSP_TYPE_R2) {
5110 count = (data_len < 17) ? data_len : 17;
5112 count = (data_len < 6) ? data_len : 6;
5114 rtsx_stor_set_xfer_buf(sd_card->rsp, count, srb);
5116 dev_dbg(rtsx_dev(chip), "Response length: %d\n", data_len);
5117 dev_dbg(rtsx_dev(chip), "Response: 0x%x 0x%x 0x%x 0x%x\n",
5118 sd_card->rsp[0], sd_card->rsp[1],
5119 sd_card->rsp[2], sd_card->rsp[3]);
5121 scsi_set_resid(srb, 0);
5122 return TRANSPORT_GOOD;
5125 int sd_hw_rst(struct scsi_cmnd *srb, struct rtsx_chip *chip)
5127 struct sd_info *sd_card = &chip->sd_card;
5128 unsigned int lun = SCSI_LUN(srb);
5131 if (!sd_card->sd_pass_thru_en) {
5132 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
5134 return TRANSPORT_FAILED;
5137 if (sd_card->pre_cmd_err) {
5138 sd_card->pre_cmd_err = 0;
5139 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_CHANGE);
5141 return TRANSPORT_FAILED;
5144 if ((srb->cmnd[2] != 0x53) || (srb->cmnd[3] != 0x44) ||
5145 (srb->cmnd[4] != 0x20) || (srb->cmnd[5] != 0x43) ||
5146 (srb->cmnd[6] != 0x61) || (srb->cmnd[7] != 0x72) ||
5147 (srb->cmnd[8] != 0x64)) {
5148 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
5150 return TRANSPORT_FAILED;
5153 switch (srb->cmnd[1] & 0x0F) {
5155 #ifdef SUPPORT_SD_LOCK
5156 if (srb->cmnd[9] == 0x64)
5157 sd_card->sd_lock_status |= SD_SDR_RST;
5159 retval = reset_sd_card(chip);
5160 if (retval != STATUS_SUCCESS) {
5161 #ifdef SUPPORT_SD_LOCK
5162 sd_card->sd_lock_status &= ~SD_SDR_RST;
5164 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
5165 sd_card->pre_cmd_err = 1;
5167 return TRANSPORT_FAILED;
5169 #ifdef SUPPORT_SD_LOCK
5170 sd_card->sd_lock_status &= ~SD_SDR_RST;
5175 retval = soft_reset_sd_card(chip);
5176 if (retval != STATUS_SUCCESS) {
5177 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
5178 sd_card->pre_cmd_err = 1;
5180 return TRANSPORT_FAILED;
5185 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
5187 return TRANSPORT_FAILED;
5190 scsi_set_resid(srb, 0);
5191 return TRANSPORT_GOOD;
5195 void sd_cleanup_work(struct rtsx_chip *chip)
5197 struct sd_info *sd_card = &chip->sd_card;
5199 if (sd_card->seq_mode) {
5200 dev_dbg(rtsx_dev(chip), "SD: stop transmission\n");
5201 sd_stop_seq_mode(chip);
5202 sd_card->cleanup_counter = 0;
5206 int sd_power_off_card3v3(struct rtsx_chip *chip)
5210 retval = disable_card_clock(chip, SD_CARD);
5211 if (retval != STATUS_SUCCESS) {
5216 retval = rtsx_write_register(chip, CARD_OE, SD_OUTPUT_EN, 0);
5222 if (!chip->ft2_fast_mode) {
5223 retval = card_power_off(chip, SD_CARD);
5224 if (retval != STATUS_SUCCESS) {
5232 if (chip->asic_code) {
5233 retval = sd_pull_ctl_disable(chip);
5234 if (retval != STATUS_SUCCESS) {
5239 retval = rtsx_write_register(chip, FPGA_PULL_CTL,
5240 FPGA_SD_PULL_CTL_BIT | 0x20,
5241 FPGA_SD_PULL_CTL_BIT);
5248 return STATUS_SUCCESS;
5251 int release_sd_card(struct rtsx_chip *chip)
5253 struct sd_info *sd_card = &chip->sd_card;
5256 chip->card_ready &= ~SD_CARD;
5257 chip->card_fail &= ~SD_CARD;
5258 chip->card_wp &= ~SD_CARD;
5263 #ifdef SUPPORT_SD_LOCK
5264 sd_card->sd_lock_status = 0;
5265 sd_card->sd_erase_status = 0;
5268 memset(sd_card->raw_csd, 0, 16);
5269 memset(sd_card->raw_scr, 0, 8);
5271 retval = sd_power_off_card3v3(chip);
5272 if (retval != STATUS_SUCCESS) {
5277 return STATUS_SUCCESS;