1 /* Driver for Realtek RTS51xx USB card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * wwang (wei_wang@realsil.com.cn)
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
22 * Edwin Rong (edwin_rong@realsil.com.cn)
23 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
26 #include <linux/blkdev.h>
27 #include <linux/kthread.h>
28 #include <linux/sched.h>
29 #include <linux/workqueue.h>
31 #include <scsi/scsi.h>
32 #include <scsi/scsi_eh.h>
33 #include <scsi/scsi_device.h>
37 #include "rts51x_chip.h"
38 #include "rts51x_card.h"
39 #include "rts51x_transport.h"
44 void rts51x_do_remaining_work(struct rts51x_chip *chip)
46 struct sd_info *sd_card = &(chip->sd_card);
47 struct xd_info *xd_card = &(chip->xd_card);
48 struct ms_info *ms_card = &(chip->ms_card);
50 if (chip->card_ready & SD_CARD) {
51 if (sd_card->seq_mode) {
52 RTS51X_SET_STAT(chip, STAT_RUN);
59 if (chip->card_ready & XD_CARD) {
60 if (xd_card->delay_write.delay_write_flag) {
61 RTS51X_SET_STAT(chip, STAT_RUN);
68 if (chip->card_ready & MS_CARD) {
69 if (CHK_MSPRO(ms_card)) {
70 if (ms_card->seq_mode) {
71 RTS51X_SET_STAT(chip, STAT_RUN);
77 if (ms_card->delay_write.delay_write_flag) {
78 RTS51X_SET_STAT(chip, STAT_RUN);
86 if (sd_card->counter > POLLING_WAIT_CNT)
87 rts51x_sd_cleanup_work(chip);
89 if (xd_card->counter > POLLING_WAIT_CNT)
90 rts51x_xd_cleanup_work(chip);
92 if (ms_card->counter > POLLING_WAIT_CNT)
93 rts51x_ms_cleanup_work(chip);
96 static void do_rts51x_reset_xd_card(struct rts51x_chip *chip)
100 if (chip->card2lun[XD_CARD] >= MAX_ALLOWED_LUN_CNT)
103 retval = rts51x_reset_xd_card(chip);
104 if (retval == STATUS_SUCCESS) {
105 chip->card_ready |= XD_CARD;
106 chip->card_fail &= ~XD_CARD;
107 chip->rw_card[chip->card2lun[XD_CARD]] = rts51x_xd_rw;
109 chip->card_ready &= ~XD_CARD;
110 chip->card_fail |= XD_CARD;
111 chip->capacity[chip->card2lun[XD_CARD]] = 0;
112 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
114 rts51x_init_cmd(chip);
115 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
116 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
118 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, XD_CLK_EN, 0);
119 rts51x_send_cmd(chip, MODE_C, 100);
123 void rts51x_do_rts51x_reset_sd_card(struct rts51x_chip *chip)
127 if (chip->card2lun[SD_CARD] >= MAX_ALLOWED_LUN_CNT)
130 retval = rts51x_reset_sd_card(chip);
131 if (retval == STATUS_SUCCESS) {
132 chip->card_ready |= SD_CARD;
133 chip->card_fail &= ~SD_CARD;
134 chip->rw_card[chip->card2lun[SD_CARD]] = rts51x_sd_rw;
136 chip->card_ready &= ~SD_CARD;
137 chip->card_fail |= SD_CARD;
138 chip->capacity[chip->card2lun[SD_CARD]] = 0;
139 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
141 rts51x_init_cmd(chip);
142 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0);
143 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
145 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0);
146 rts51x_send_cmd(chip, MODE_C, 100);
150 static void do_rts51x_reset_ms_card(struct rts51x_chip *chip)
154 if (chip->card2lun[MS_CARD] >= MAX_ALLOWED_LUN_CNT)
157 retval = rts51x_reset_ms_card(chip);
158 if (retval == STATUS_SUCCESS) {
159 chip->card_ready |= MS_CARD;
160 chip->card_fail &= ~MS_CARD;
161 chip->rw_card[chip->card2lun[MS_CARD]] = rts51x_ms_rw;
163 chip->card_ready &= ~MS_CARD;
164 chip->card_fail |= MS_CARD;
165 chip->capacity[chip->card2lun[MS_CARD]] = 0;
166 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
168 rts51x_init_cmd(chip);
169 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, MS_OUTPUT_EN, 0);
170 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
172 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, MS_CLK_EN, 0);
173 rts51x_send_cmd(chip, MODE_C, 100);
177 static void card_cd_debounce(struct rts51x_chip *chip, u8 *need_reset,
181 u8 release_map = 0, reset_map = 0;
184 retval = rts51x_get_card_status(chip, &(chip->card_status));
186 chip->ocp_stat = (chip->card_status >> 4) & 0x03;
189 if (retval != STATUS_SUCCESS)
192 if (chip->card_exist) {
193 retval = rts51x_read_register(chip, CARD_INT_PEND, &value);
194 if (retval != STATUS_SUCCESS) {
195 rts51x_ep0_write_register(chip, MC_FIFO_CTL, FIFO_FLUSH,
197 rts51x_ep0_write_register(chip, SFSM_ED, 0xf8, 0xf8);
201 if (chip->card_exist & XD_CARD) {
202 if (!(chip->card_status & XD_CD))
203 release_map |= XD_CARD;
204 } else if (chip->card_exist & SD_CARD) {
205 /* if (!(chip->card_status & SD_CD)) { */
206 if (!(chip->card_status & SD_CD) || (value & SD_INT))
207 release_map |= SD_CARD;
208 } else if (chip->card_exist & MS_CARD) {
209 /* if (!(chip->card_status & MS_CD)) { */
210 if (!(chip->card_status & MS_CD) || (value & MS_INT))
211 release_map |= MS_CARD;
214 if (chip->card_status & XD_CD)
215 reset_map |= XD_CARD;
216 else if (chip->card_status & SD_CD)
217 reset_map |= SD_CARD;
218 else if (chip->card_status & MS_CD)
219 reset_map |= MS_CARD;
222 if (CHECK_PKG(chip, QFN24) && reset_map) {
223 if (chip->card_exist & XD_CARD) {
230 int xd_cnt = 0, sd_cnt = 0, ms_cnt = 0;
233 for (i = 0; i < (chip->option.debounce_num); i++) {
235 rts51x_get_card_status(chip, &(chip->card_status));
236 if (retval != STATUS_SUCCESS) {
237 reset_map = release_map = 0;
240 if (chip->card_status & XD_CD)
244 if (chip->card_status & SD_CD)
248 if (chip->card_status & MS_CD)
256 if (!(chip->card_exist & XD_CARD)
257 && (xd_cnt > (chip->option.debounce_num - 1))) {
258 reset_map |= XD_CARD;
260 if (!(chip->card_exist & SD_CARD)
261 && (sd_cnt > (chip->option.debounce_num - 1))) {
262 reset_map |= SD_CARD;
264 if (!(chip->card_exist & MS_CARD)
265 && (ms_cnt > (chip->option.debounce_num - 1))) {
266 reset_map |= MS_CARD;
269 rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
270 XD_INT | MS_INT | SD_INT);
274 *need_reset = reset_map;
276 *need_release = release_map;
279 void rts51x_init_cards(struct rts51x_chip *chip)
281 u8 need_reset = 0, need_release = 0;
283 card_cd_debounce(chip, &need_reset, &need_release);
286 RTS51X_DEBUGP("need_release = 0x%x\n", need_release);
288 rts51x_prepare_run(chip);
289 RTS51X_SET_STAT(chip, STAT_RUN);
292 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
293 rts51x_write_register(chip, OCPCTL, MS_OCP_CLEAR,
296 RTS51X_DEBUGP("Clear OCP status.\n");
300 if (need_release & XD_CARD) {
301 chip->card_exist &= ~XD_CARD;
302 chip->card_ejected = 0;
303 if (chip->card_ready & XD_CARD) {
304 rts51x_release_xd_card(chip);
305 chip->rw_card[chip->card2lun[XD_CARD]] = NULL;
306 clear_bit(chip->card2lun[XD_CARD],
311 if (need_release & SD_CARD) {
312 chip->card_exist &= ~SD_CARD;
313 chip->card_ejected = 0;
314 if (chip->card_ready & SD_CARD) {
315 rts51x_release_sd_card(chip);
316 chip->rw_card[chip->card2lun[SD_CARD]] = NULL;
317 clear_bit(chip->card2lun[SD_CARD],
322 if (need_release & MS_CARD) {
323 chip->card_exist &= ~MS_CARD;
324 chip->card_ejected = 0;
325 if (chip->card_ready & MS_CARD) {
326 rts51x_release_ms_card(chip);
327 chip->rw_card[chip->card2lun[MS_CARD]] = NULL;
328 clear_bit(chip->card2lun[MS_CARD],
334 if (need_reset && !chip->card_ready) {
335 RTS51X_DEBUGP("need_reset = 0x%x\n", need_reset);
337 rts51x_prepare_run(chip);
338 RTS51X_SET_STAT(chip, STAT_RUN);
340 if (need_reset & XD_CARD) {
341 chip->card_exist |= XD_CARD;
342 do_rts51x_reset_xd_card(chip);
343 } else if (need_reset & SD_CARD) {
344 chip->card_exist |= SD_CARD;
345 rts51x_do_rts51x_reset_sd_card(chip);
346 } else if (need_reset & MS_CARD) {
347 chip->card_exist |= MS_CARD;
348 do_rts51x_reset_ms_card(chip);
353 void rts51x_release_cards(struct rts51x_chip *chip)
355 if (chip->card_ready & SD_CARD) {
356 rts51x_sd_cleanup_work(chip);
357 rts51x_release_sd_card(chip);
358 chip->card_ready &= ~SD_CARD;
361 if (chip->card_ready & XD_CARD) {
362 rts51x_xd_cleanup_work(chip);
363 rts51x_release_xd_card(chip);
364 chip->card_ready &= ~XD_CARD;
367 if (chip->card_ready & MS_CARD) {
368 rts51x_ms_cleanup_work(chip);
369 rts51x_release_ms_card(chip);
370 chip->card_ready &= ~MS_CARD;
374 static inline u8 double_depth(u8 depth)
376 return ((depth > 1) ? (depth - 1) : depth);
379 int rts51x_switch_ssc_clock(struct rts51x_chip *chip, int clk)
381 struct sd_info *sd_card = &(chip->sd_card);
382 struct ms_info *ms_card = &(chip->ms_card);
384 u8 N = (u8) (clk - 2), min_N, max_N;
385 u8 mcu_cnt, div, max_div, ssc_depth;
386 int sd_vpclk_phase_reset = 0;
388 if (chip->cur_clk == clk)
389 return STATUS_SUCCESS;
395 RTS51X_DEBUGP("Switch SSC clock to %dMHz\n", clk);
397 if ((clk <= 2) || (N > max_N))
398 TRACE_RET(chip, STATUS_FAIL);
400 mcu_cnt = (u8) (60 / clk + 3);
403 /* To make sure that the SSC clock div_n is
404 * equal or greater than min_N */
406 while ((N < min_N) && (div < max_div)) {
410 RTS51X_DEBUGP("N = %d, div = %d\n", N, div);
412 if (chip->option.ssc_en) {
413 if (chip->cur_card == SD_CARD) {
414 if (CHK_SD_SDR104(sd_card)) {
415 ssc_depth = chip->option.ssc_depth_sd_sdr104;
416 } else if (CHK_SD_SDR50(sd_card)) {
417 ssc_depth = chip->option.ssc_depth_sd_sdr50;
418 } else if (CHK_SD_DDR50(sd_card)) {
420 double_depth(chip->option.
422 } else if (CHK_SD_HS(sd_card)) {
424 double_depth(chip->option.ssc_depth_sd_hs);
425 } else if (CHK_MMC_52M(sd_card)
426 || CHK_MMC_DDR52(sd_card)) {
428 double_depth(chip->option.
432 double_depth(chip->option.
433 ssc_depth_low_speed);
435 } else if (chip->cur_card == MS_CARD) {
436 if (CHK_MSPRO(ms_card)) {
437 if (CHK_HG8BIT(ms_card)) {
439 double_depth(chip->option.
443 double_depth(chip->option.
447 if (CHK_MS4BIT(ms_card)) {
449 double_depth(chip->option.
453 double_depth(chip->option.
454 ssc_depth_low_speed);
459 double_depth(chip->option.ssc_depth_low_speed);
463 if (div == CLK_DIV_2) {
464 /* If clock divided by 2, ssc depth must
465 * be multiplied by 2 */
469 ssc_depth = SSC_DEPTH_2M;
470 } else if (div == CLK_DIV_4) {
471 /* If clock divided by 4, ssc depth must
472 * be multiplied by 4 */
476 ssc_depth = SSC_DEPTH_2M;
484 RTS51X_DEBUGP("ssc_depth = %d\n", ssc_depth);
486 rts51x_init_cmd(chip);
487 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, CLK_CHANGE);
488 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
489 (div << 4) | mcu_cnt);
490 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CTL1, SSC_RSTB, 0);
491 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CTL2, SSC_DEPTH_MASK,
493 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_DIV_N_0, 0xFF, N);
494 if (sd_vpclk_phase_reset) {
495 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
497 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
498 PHASE_NOT_RESET, PHASE_NOT_RESET);
501 retval = rts51x_send_cmd(chip, MODE_C, 2000);
502 if (retval != STATUS_SUCCESS)
503 TRACE_RET(chip, retval);
504 if (chip->option.ssc_en && ssc_depth)
505 rts51x_write_register(chip, SSC_CTL1, 0xff, 0xD0);
507 rts51x_write_register(chip, SSC_CTL1, 0xff, 0x50);
509 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
513 return STATUS_SUCCESS;
516 int rts51x_switch_normal_clock(struct rts51x_chip *chip, int clk)
519 u8 sel, div, mcu_cnt;
520 int sd_vpclk_phase_reset = 0;
522 if (chip->cur_clk == clk)
523 return STATUS_SUCCESS;
525 if (chip->cur_card == SD_CARD) {
526 struct sd_info *sd_card = &(chip->sd_card);
527 if (CHK_SD30_SPEED(sd_card) || CHK_MMC_DDR52(sd_card))
528 sd_vpclk_phase_reset = 1;
533 RTS51X_DEBUGP("Switch clock to 20MHz\n");
540 RTS51X_DEBUGP("Switch clock to 30MHz\n");
547 RTS51X_DEBUGP("Switch clock to 40MHz\n");
554 RTS51X_DEBUGP("Switch clock to 50MHz\n");
561 RTS51X_DEBUGP("Switch clock to 60MHz\n");
568 RTS51X_DEBUGP("Switch clock to 80MHz\n");
575 RTS51X_DEBUGP("Switch clock to 100MHz\n");
582 RTS51X_DEBUGP("Switch clock to 120MHz\n");
589 RTS51X_DEBUGP("Switch clock to 150MHz\n");
596 RTS51X_DEBUGP("Try to switch to an illegal clock (%d)\n",
598 TRACE_RET(chip, STATUS_FAIL);
601 if (!sd_vpclk_phase_reset) {
602 rts51x_init_cmd(chip);
604 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE,
606 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
607 (div << 4) | mcu_cnt);
608 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CLK_FPGA_SEL, 0xFF,
610 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE, 0);
612 retval = rts51x_send_cmd(chip, MODE_C, 100);
613 if (retval != STATUS_SUCCESS)
614 TRACE_RET(chip, retval);
616 rts51x_init_cmd(chip);
618 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, CLK_CHANGE,
620 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
622 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK1_CTL,
624 rts51x_add_cmd(chip, WRITE_REG_CMD, CLK_DIV, 0x3F,
625 (div << 4) | mcu_cnt);
626 rts51x_add_cmd(chip, WRITE_REG_CMD, SSC_CLK_FPGA_SEL, 0xFF,
629 retval = rts51x_send_cmd(chip, MODE_C, 100);
630 if (retval != STATUS_SUCCESS)
631 TRACE_RET(chip, retval);
635 rts51x_init_cmd(chip);
637 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL,
638 PHASE_NOT_RESET, PHASE_NOT_RESET);
639 rts51x_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK1_CTL,
640 PHASE_NOT_RESET, PHASE_NOT_RESET);
642 retval = rts51x_send_cmd(chip, MODE_C, 100);
643 if (retval != STATUS_SUCCESS)
644 TRACE_RET(chip, retval);
648 RTS51X_WRITE_REG(chip, CLK_DIV, CLK_CHANGE, 0);
653 return STATUS_SUCCESS;
656 int rts51x_card_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 sec_addr,
660 unsigned int lun = SCSI_LUN(srb);
663 if (chip->rw_card[lun] == NULL)
666 RTS51X_DEBUGP("%s card, sector addr: 0x%x, sector cnt: %d\n",
667 (srb->sc_data_direction ==
668 DMA_TO_DEVICE) ? "Write" : "Read", sec_addr, sec_cnt);
670 chip->rw_need_retry = 0;
671 for (i = 0; i < 3; i++) {
672 retval = chip->rw_card[lun] (srb, chip, sec_addr, sec_cnt);
673 if (retval != STATUS_SUCCESS) {
675 if (chip->option.reset_or_rw_fail_set_pad_drive) {
676 rts51x_write_register(chip, CARD_DRIVE_SEL,
682 if (!chip->rw_need_retry)
685 RTS51X_DEBUGP("Retry RW, (i = %d\n)", i);
691 u8 rts51x_get_lun_card(struct rts51x_chip *chip, unsigned int lun)
693 if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD)
695 else if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD)
697 else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD)
703 static int card_share_mode(struct rts51x_chip *chip, int card)
708 value = CARD_SHARE_SD;
709 else if (card == MS_CARD)
710 value = CARD_SHARE_MS;
711 else if (card == XD_CARD)
712 value = CARD_SHARE_XD;
714 TRACE_RET(chip, STATUS_FAIL);
716 RTS51X_WRITE_REG(chip, CARD_SHARE_MODE, CARD_SHARE_MASK, value);
718 return STATUS_SUCCESS;
721 int rts51x_select_card(struct rts51x_chip *chip, int card)
725 if (chip->cur_card != card) {
730 else if (card == MS_CARD)
732 else if (card == XD_CARD)
735 TRACE_RET(chip, STATUS_FAIL);
736 RTS51X_WRITE_REG(chip, CARD_SELECT, 0x07, mod);
737 chip->cur_card = card;
739 retval = card_share_mode(chip, card);
740 if (retval != STATUS_SUCCESS)
741 TRACE_RET(chip, retval);
744 return STATUS_SUCCESS;
747 void rts51x_eject_card(struct rts51x_chip *chip, unsigned int lun)
749 RTS51X_DEBUGP("eject card\n");
750 RTS51X_SET_STAT(chip, STAT_RUN);
751 rts51x_do_remaining_work(chip);
753 if ((chip->card_ready & chip->lun2card[lun]) == SD_CARD) {
754 rts51x_release_sd_card(chip);
755 chip->card_ejected |= SD_CARD;
756 chip->card_ready &= ~SD_CARD;
757 chip->capacity[lun] = 0;
758 } else if ((chip->card_ready & chip->lun2card[lun]) == XD_CARD) {
759 rts51x_release_xd_card(chip);
760 chip->card_ejected |= XD_CARD;
761 chip->card_ready &= ~XD_CARD;
762 chip->capacity[lun] = 0;
763 } else if ((chip->card_ready & chip->lun2card[lun]) == MS_CARD) {
764 rts51x_release_ms_card(chip);
765 chip->card_ejected |= MS_CARD;
766 chip->card_ready &= ~MS_CARD;
767 chip->capacity[lun] = 0;
769 rts51x_write_register(chip, CARD_INT_PEND, XD_INT | MS_INT | SD_INT,
770 XD_INT | MS_INT | SD_INT);
773 void rts51x_trans_dma_enable(enum dma_data_direction dir, struct rts51x_chip *chip,
774 u32 byte_cnt, u8 pack_size)
776 if (pack_size > DMA_1024)
779 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
782 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC3, 0xFF,
783 (u8) (byte_cnt >> 24));
784 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC2, 0xFF,
785 (u8) (byte_cnt >> 16));
786 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC1, 0xFF,
787 (u8) (byte_cnt >> 8));
788 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_TC0, 0xFF, (u8) byte_cnt);
790 if (dir == DMA_FROM_DEVICE) {
791 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_CTL,
792 0x03 | DMA_PACK_SIZE_MASK,
793 DMA_DIR_FROM_CARD | DMA_EN | pack_size);
795 rts51x_add_cmd(chip, WRITE_REG_CMD, MC_DMA_CTL,
796 0x03 | DMA_PACK_SIZE_MASK,
797 DMA_DIR_TO_CARD | DMA_EN | pack_size);
801 int rts51x_enable_card_clock(struct rts51x_chip *chip, u8 card)
812 RTS51X_WRITE_REG(chip, CARD_CLK_EN, clk_en, clk_en);
814 return STATUS_SUCCESS;
817 int rts51x_card_power_on(struct rts51x_chip *chip, u8 card)
822 val1 = PARTIAL_POWER_ON;
825 #ifdef SD_XD_IO_FOLLOW_PWR
826 if ((card == SD_CARD) || (card == XD_CARD)) {
827 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask | LDO3318_PWR_MASK,
831 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val1);
832 #ifdef SD_XD_IO_FOLLOW_PWR
835 udelay(chip->option.pwr_delay);
836 RTS51X_WRITE_REG(chip, CARD_PWR_CTL, mask, val2);
837 #ifdef SD_XD_IO_FOLLOW_PWR
838 if (card == SD_CARD) {
839 rts51x_write_register(chip, CARD_PWR_CTL, LDO3318_PWR_MASK,
844 return STATUS_SUCCESS;
847 int monitor_card_cd(struct rts51x_chip *chip, u8 card)
850 u8 card_cd[32] = { 0 };
852 card_cd[SD_CARD] = SD_CD;
853 card_cd[XD_CARD] = XD_CD;
854 card_cd[MS_CARD] = MS_CD;
856 retval = rts51x_get_card_status(chip, &(chip->card_status));
857 if (retval != STATUS_SUCCESS)
860 if (chip->card_status & card_cd[card])
866 int rts51x_toggle_gpio(struct rts51x_chip *chip, u8 gpio)
870 u8 gpio_output[4] = {
877 retval = rts51x_ep0_read_register(chip, CARD_GPIO, &temp_reg);
878 if (retval != STATUS_SUCCESS)
879 TRACE_RET(chip, STATUS_FAIL);
880 temp_reg ^= gpio_oe[gpio];
881 temp_reg &= 0xfe; /* bit 0 always set 0 */
883 rts51x_ep0_write_register(chip, CARD_GPIO, 0x03, temp_reg);
884 if (retval != STATUS_SUCCESS)
885 TRACE_RET(chip, STATUS_FAIL);
887 retval = rts51x_ep0_read_register(chip, CARD_GPIO, &temp_reg);
888 if (retval != STATUS_SUCCESS)
889 TRACE_RET(chip, STATUS_FAIL);
890 temp_reg ^= gpio_output[gpio];
892 rts51x_ep0_write_register(chip, CARD_GPIO, 0xFF,
893 temp_reg | gpio_oe[gpio]);
894 if (retval != STATUS_SUCCESS)
895 TRACE_RET(chip, STATUS_FAIL);
898 return STATUS_SUCCESS;
901 int rts51x_turn_on_led(struct rts51x_chip *chip, u8 gpio)
912 rts51x_ep0_write_register(chip, CARD_GPIO, gpio_mask[gpio],
914 if (retval != STATUS_SUCCESS)
915 TRACE_RET(chip, STATUS_FAIL);
917 return STATUS_SUCCESS;
920 int rts51x_turn_off_led(struct rts51x_chip *chip, u8 gpio)
923 u8 gpio_output[4] = {
934 rts51x_ep0_write_register(chip, CARD_GPIO, gpio_mask[gpio],
935 gpio_oe[gpio] | gpio_output[gpio]);
936 if (retval != STATUS_SUCCESS)
937 TRACE_RET(chip, STATUS_FAIL);
939 return STATUS_SUCCESS;