drivers/staging/rtl8821ae/rtl8821ae/phy.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL8821AE_PHY_H__
  31 #define __RTL8821AE_PHY_H__
  32
  33 /*It must always set to 4, otherwise read efuse table secquence will be wrong.*/
  34 #define MAX_TX_COUNT    4
  35 #define TX_1S                   0
  36 #define TX_2S                   1
  37 #define TX_3S                   2
  38 #define TX_4S                   3
  39
  40 #define MAX_POWER_INDEX 0x3F
  41
  42 #define MAX_PRECMD_CNT                          16
  43 #define MAX_RFDEPENDCMD_CNT             16
  44 #define MAX_POSTCMD_CNT                         16
  45
  46 #define MAX_DOZE_WAITING_TIMES_9x       64
  47
  48 #define RT_CANNOT_IO(hw)                        false
  49 #define HIGHPOWER_RADIOA_ARRAYLEN       22
  50
  51 #define IQK_ADDA_REG_NUM                        16
  52 #define IQK_BB_REG_NUM                          9
  53 #define MAX_TOLERANCE                           5
  54 #define IQK_DELAY_TIME                          10
  55 #define index_mapping_NUM       15
  56
  57 #define APK_BB_REG_NUM                          5
  58 #define APK_AFE_REG_NUM                         16
  59 #define APK_CURVE_REG_NUM                       4
  60 #define PATH_NUM                                        2
  61
  62 #define LOOP_LIMIT                                      5
  63 #define MAX_STALL_TIME                          50
  64 #define AntennaDiversityValue           0x80
  65 #define MAX_TXPWR_IDX_NMODE_92S         63
  66 #define Reset_Cnt_Limit                         3
  67
  68 #define IQK_ADDA_REG_NUM                        16
  69 #define IQK_MAC_REG_NUM                         4
  70
  71 #define RF6052_MAX_PATH                         2
  72
  73 #define CT_OFFSET_MAC_ADDR                      0X16
  74
  75 #define CT_OFFSET_CCK_TX_PWR_IDX                        0x5A
  76 #define CT_OFFSET_HT401S_TX_PWR_IDX                     0x60
  77 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF        0x66
  78 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF          0x69
  79 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF          0x6C
  80
  81 #define CT_OFFSET_HT40_MAX_PWR_OFFSET           0x6F
  82 #define CT_OFFSET_HT20_MAX_PWR_OFFSET           0x72
  83
  84 #define CT_OFFSET_CHANNEL_PLAH                          0x75
  85 #define CT_OFFSET_THERMAL_METER                         0x78
  86 #define CT_OFFSET_RF_OPTION                                     0x79
  87 #define CT_OFFSET_VERSION                                       0x7E
  88 #define CT_OFFSET_CUSTOMER_ID                           0x7F
  89
  90 #define RTL8821AE_MAX_PATH_NUM                                  2
  91
  92 #define TARGET_CHNL_NUM_2G_5G_8812      59
  93
  94 enum swchnlcmd_id {
  95         CMDID_END,
  96         CMDID_SET_TXPOWEROWER_LEVEL,
  97         CMDID_BBREGWRITE10,
  98         CMDID_WRITEPORT_ULONG,
  99         CMDID_WRITEPORT_USHORT,
 100         CMDID_WRITEPORT_UCHAR,
 101         CMDID_RF_WRITEREG,
 102 };
 103
 104 struct swchnlcmd {
 105         enum swchnlcmd_id cmdid;
 106         u32 para1;
 107         u32 para2;
 108         u32 msdelay;
 109 };
 110
 111 enum hw90_block_e {
 112         HW90_BLOCK_MAC = 0,
 113         HW90_BLOCK_PHY0 = 1,
 114         HW90_BLOCK_PHY1 = 2,
 115         HW90_BLOCK_RF = 3,
 116         HW90_BLOCK_MAXIMUM = 4,
 117 };
 118
 119 enum baseband_config_type {
 120         BASEBAND_CONFIG_PHY_REG = 0,
 121         BASEBAND_CONFIG_AGC_TAB = 1,
 122 };
 123
 124 enum ra_offset_area {
 125         RA_OFFSET_LEGACY_OFDM1,
 126         RA_OFFSET_LEGACY_OFDM2,
 127         RA_OFFSET_HT_OFDM1,
 128         RA_OFFSET_HT_OFDM2,
 129         RA_OFFSET_HT_OFDM3,
 130         RA_OFFSET_HT_OFDM4,
 131         RA_OFFSET_HT_CCK,
 132 };
 133
 134 enum antenna_path {
 135         ANTENNA_NONE,
 136         ANTENNA_D,
 137         ANTENNA_C,
 138         ANTENNA_CD,
 139         ANTENNA_B,
 140         ANTENNA_BD,
 141         ANTENNA_BC,
 142         ANTENNA_BCD,
 143         ANTENNA_A,
 144         ANTENNA_AD,
 145         ANTENNA_AC,
 146         ANTENNA_ACD,
 147         ANTENNA_AB,
 148         ANTENNA_ABD,
 149         ANTENNA_ABC,
 150         ANTENNA_ABCD
 151 };
 152
 153 struct r_antenna_select_ofdm {
 154         u32 r_tx_antenna:4;
 155         u32 r_ant_l:4;
 156         u32 r_ant_non_ht:4;
 157         u32 r_ant_ht1:4;
 158         u32 r_ant_ht2:4;
 159         u32 r_ant_ht_s1:4;
 160         u32 r_ant_non_ht_s1:4;
 161         u32 ofdm_txsc:2;
 162         u32 reserved:2;
 163 };
 164
 165 struct r_antenna_select_cck {
 166         u8 r_cckrx_enable_2:2;
 167         u8 r_cckrx_enable:2;
 168         u8 r_ccktx_enable:4;
 169 };
 170
 171
 172 struct efuse_contents {
 173         u8 mac_addr[ETH_ALEN];
 174         u8 cck_tx_power_idx[6];
 175         u8 ht40_1s_tx_power_idx[6];
 176         u8 ht40_2s_tx_power_idx_diff[3];
 177         u8 ht20_tx_power_idx_diff[3];
 178         u8 ofdm_tx_power_idx_diff[3];
 179         u8 ht40_max_power_offset[3];
 180         u8 ht20_max_power_offset[3];
 181         u8 channel_plan;
 182         u8 thermal_meter;
 183         u8 rf_option[5];
 184         u8 version;
 185         u8 oem_id;
 186         u8 regulatory;
 187 };
 188
 189 struct tx_power_struct {
 190         u8 cck[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 191         u8 ht40_1s[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 192         u8 ht40_2s[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 193         u8 ht20_diff[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 194         u8 legacy_ht_diff[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 195         u8 legacy_ht_txpowerdiff;
 196         u8 groupht20[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 197         u8 groupht40[RTL8821AE_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
 198         u8 pwrgroup_cnt;
 199         u32 mcs_original_offset[4][16];
 200 };
 201 enum _ANT_DIV_TYPE
 202 {
 203         NO_ANTDIV                               = 0xFF,
 204         CG_TRX_HW_ANTDIV                = 0x01,
 205         CGCS_RX_HW_ANTDIV               = 0x02,
 206         FIXED_HW_ANTDIV         = 0x03,
 207         CG_TRX_SMART_ANTDIV             = 0x04,
 208         CGCS_RX_SW_ANTDIV               = 0x05,
 209
 210 };
 211
 212 extern u32 rtl8821ae_phy_query_bb_reg(struct ieee80211_hw *hw,
 213                                    u32 regaddr, u32 bitmask);
 214 extern void rtl8821ae_phy_set_bb_reg(struct ieee80211_hw *hw,
 215                                   u32 regaddr, u32 bitmask, u32 data);
 216 extern u32 rtl8821ae_phy_query_rf_reg(struct ieee80211_hw *hw,
 217                                    enum radio_path rfpath, u32 regaddr,
 218                                    u32 bitmask);
 219 extern void rtl8821ae_phy_set_rf_reg(struct ieee80211_hw *hw,
 220                                   enum radio_path rfpath, u32 regaddr,
 221                                   u32 bitmask, u32 data);
 222 extern bool rtl8821ae_phy_mac_config(struct ieee80211_hw *hw);
 223 extern bool rtl8821ae_phy_bb_config(struct ieee80211_hw *hw);
 224 extern bool rtl8821ae_phy_rf_config(struct ieee80211_hw *hw);
 225 extern void rtl8821ae_phy_switch_wirelessband(struct ieee80211_hw *hw, u8 band);
 226 extern void rtl8821ae_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
 227 extern void rtl8821ae_phy_get_txpower_level(struct ieee80211_hw *hw,
 228                                          long *powerlevel);
 229 extern void rtl8821ae_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
 230 extern void rtl8821ae_phy_scan_operation_backup(struct ieee80211_hw *hw,
 231                                              u8 operation);
 232 extern void rtl8821ae_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
 233 extern void rtl8821ae_phy_set_bw_mode(struct ieee80211_hw *hw,
 234                                    enum nl80211_channel_type ch_type);
 235 extern void rtl8821ae_phy_sw_chnl_callback(struct ieee80211_hw *hw);
 236 extern u8 rtl8821ae_phy_sw_chnl(struct ieee80211_hw *hw);
 237 extern void rtl8821ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
 238 extern void rtl8812ae_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
 239 void rtl8821ae_phy_ap_calibrate(struct ieee80211_hw *hw, char delta);
 240 void rtl8821ae_phy_lc_calibrate(struct ieee80211_hw *hw);
 241 void rtl8821ae_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
 242 bool rtl8812ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 243                                           enum radio_path rfpath);
 244 bool rtl8821ae_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
 245                                           enum radio_path rfpath);
 246 bool rtl8821ae_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
 247 extern bool rtl8821ae_phy_set_rf_power_state(struct ieee80211_hw *hw,
 248                                           enum rf_pwrstate rfpwr_state);
 249 u8 _rtl8812ae_get_right_chnl_place_for_iqk(u8 chnl);
 250 void rtl8821ae_phy_set_txpower_level_by_path(struct ieee80211_hw *hw, u8 channel, u8 path);
 251 void rtl8812ae_do_iqk(struct ieee80211_hw *hw,u8 delta_thermal_index,
 252         u8 thermal_value, u8 threshold);
 253 void rtl8821ae_do_iqk(struct ieee80211_hw *hw,u8 delta_thermal_index,
 254         u8 thermal_value, u8 threshold);
 255 void rtl8821ae_reset_iqk_result(struct ieee80211_hw *hw);
 256
 257
 258 #endif