drivers/staging/rtl8821ae/rtl8821ae/def.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2010  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #ifndef __RTL8821AE_DEF_H__
  31 #define __RTL8821AE_DEF_H__
  32
  33 /*--------------------------Define -------------------------------------------*/
  34 /* BIT 7 HT Rate*/
  35 /*TxHT = 0*/
  36 #define MGN_1M                          0x02
  37 #define MGN_2M                          0x04
  38 #define MGN_5_5M                        0x0b
  39 #define MGN_11M                         0x16
  40
  41 #define MGN_6M                          0x0c
  42 #define MGN_9M                          0x12
  43 #define MGN_12M                         0x18
  44 #define MGN_18M                         0x24
  45 #define MGN_24M                         0x30
  46 #define MGN_36M                         0x48
  47 #define MGN_48M                         0x60
  48 #define MGN_54M                         0x6c
  49
  50 // TxHT = 1
  51 #define MGN_MCS0                        0x80
  52 #define MGN_MCS1                        0x81
  53 #define MGN_MCS2                        0x82
  54 #define MGN_MCS3                        0x83
  55 #define MGN_MCS4                        0x84
  56 #define MGN_MCS5                        0x85
  57 #define MGN_MCS6                        0x86
  58 #define MGN_MCS7                        0x87
  59 #define MGN_MCS8                        0x88
  60 #define MGN_MCS9                        0x89
  61 #define MGN_MCS10                       0x8a
  62 #define MGN_MCS11                       0x8b
  63 #define MGN_MCS12                       0x8c
  64 #define MGN_MCS13                       0x8d
  65 #define MGN_MCS14                       0x8e
  66 #define MGN_MCS15                       0x8f
  67 //VHT rate
  68 #define MGN_VHT1SS_MCS0         0x90
  69 #define MGN_VHT1SS_MCS1         0x91
  70 #define MGN_VHT1SS_MCS2         0x92
  71 #define MGN_VHT1SS_MCS3         0x93
  72 #define MGN_VHT1SS_MCS4         0x94
  73 #define MGN_VHT1SS_MCS5         0x95
  74 #define MGN_VHT1SS_MCS6         0x96
  75 #define MGN_VHT1SS_MCS7         0x97
  76 #define MGN_VHT1SS_MCS8         0x98
  77 #define MGN_VHT1SS_MCS9         0x99
  78 #define MGN_VHT2SS_MCS0         0x9a
  79 #define MGN_VHT2SS_MCS1         0x9b
  80 #define MGN_VHT2SS_MCS2         0x9c
  81 #define MGN_VHT2SS_MCS3         0x9d
  82 #define MGN_VHT2SS_MCS4         0x9e
  83 #define MGN_VHT2SS_MCS5         0x9f
  84 #define MGN_VHT2SS_MCS6         0xa0
  85 #define MGN_VHT2SS_MCS7         0xa1
  86 #define MGN_VHT2SS_MCS8         0xa2
  87 #define MGN_VHT2SS_MCS9         0xa3
  88
  89 #define MGN_VHT3SS_MCS0         0xa4
  90 #define MGN_VHT3SS_MCS1         0xa5
  91 #define MGN_VHT3SS_MCS2         0xa6
  92 #define MGN_VHT3SS_MCS3         0xa7
  93 #define MGN_VHT3SS_MCS4         0xa8
  94 #define MGN_VHT3SS_MCS5         0xa9
  95 #define MGN_VHT3SS_MCS6         0xaa
  96 #define MGN_VHT3SS_MCS7         0xab
  97 #define MGN_VHT3SS_MCS8         0xac
  98 #define MGN_VHT3SS_MCS9         0xad
  99
 100 #define MGN_MCS0_SG                     0xc0
 101 #define MGN_MCS1_SG                     0xc1
 102 #define MGN_MCS2_SG                     0xc2
 103 #define MGN_MCS3_SG                     0xc3
 104 #define MGN_MCS4_SG                     0xc4
 105 #define MGN_MCS5_SG                     0xc5
 106 #define MGN_MCS6_SG                     0xc6
 107 #define MGN_MCS7_SG                     0xc7
 108 #define MGN_MCS8_SG                     0xc8
 109 #define MGN_MCS9_SG                     0xc9
 110 #define MGN_MCS10_SG            0xca
 111 #define MGN_MCS11_SG            0xcb
 112 #define MGN_MCS12_SG            0xcc
 113 #define MGN_MCS13_SG            0xcd
 114 #define MGN_MCS14_SG            0xce
 115 #define MGN_MCS15_SG            0xcf
 116
 117 #define MGN_UNKNOWN                     0xff
 118
 119
 120 /* 30 ms */
 121 #define WIFI_NAV_UPPER_US                               30000
 122 #define HAL_92C_NAV_UPPER_UNIT                  128
 123
 124 #define HAL_RETRY_LIMIT_INFRA                           48
 125 #define HAL_RETRY_LIMIT_AP_ADHOC                        7
 126
 127 #define RESET_DELAY_8185                                        20
 128
 129 #define RT_IBSS_INT_MASKS       (IMR_BCNINT | IMR_TBDOK | IMR_TBDER)
 130 #define RT_AC_INT_MASKS         (IMR_VIDOK | IMR_VODOK | IMR_BEDOK|IMR_BKDOK)
 131
 132 #define NUM_OF_FIRMWARE_QUEUE                           10
 133 #define NUM_OF_PAGES_IN_FW                                      0x100
 134 #define NUM_OF_PAGE_IN_FW_QUEUE_BK                      0x07
 135 #define NUM_OF_PAGE_IN_FW_QUEUE_BE                      0x07
 136 #define NUM_OF_PAGE_IN_FW_QUEUE_VI                      0x07
 137 #define NUM_OF_PAGE_IN_FW_QUEUE_VO                      0x07
 138 #define NUM_OF_PAGE_IN_FW_QUEUE_HCCA            0x0
 139 #define NUM_OF_PAGE_IN_FW_QUEUE_CMD                     0x0
 140 #define NUM_OF_PAGE_IN_FW_QUEUE_MGNT            0x02
 141 #define NUM_OF_PAGE_IN_FW_QUEUE_HIGH            0x02
 142 #define NUM_OF_PAGE_IN_FW_QUEUE_BCN                     0x2
 143 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB                     0xA1
 144
 145 #define NUM_OF_PAGE_IN_FW_QUEUE_BK_DTM          0x026
 146 #define NUM_OF_PAGE_IN_FW_QUEUE_BE_DTM          0x048
 147 #define NUM_OF_PAGE_IN_FW_QUEUE_VI_DTM          0x048
 148 #define NUM_OF_PAGE_IN_FW_QUEUE_VO_DTM          0x026
 149 #define NUM_OF_PAGE_IN_FW_QUEUE_PUB_DTM         0x00
 150
 151 #define MAX_RX_DMA_BUFFER_SIZE                          0x3E80
 152
 153
 154 #define MAX_LINES_HWCONFIG_TXT                          1000
 155 #define MAX_BYTES_LINE_HWCONFIG_TXT                     256
 156
 157 #define SW_THREE_WIRE                                           0
 158 #define HW_THREE_WIRE                                           2
 159
 160 #define BT_DEMO_BOARD                                           0
 161 #define BT_QA_BOARD                                                     1
 162 #define BT_FPGA                                                         2
 163
 164 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 165 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 166 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 167
 168 #define MAX_H2C_QUEUE_NUM                                       10
 169
 170 #define RX_MPDU_QUEUE                                           0
 171 #define RX_CMD_QUEUE                                            1
 172 #define RX_MAX_QUEUE                                            2
 173 #define AC2QUEUEID(_AC)                                         (_AC)
 174
 175 #define C2H_RX_CMD_HDR_LEN                                      8
 176 #define GET_C2H_CMD_CMD_LEN(__prxhdr)           \
 177         LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
 178 #define GET_C2H_CMD_ELEMENT_ID(__prxhdr)        \
 179         LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
 180 #define GET_C2H_CMD_CMD_SEQ(__prxhdr)           \
 181         LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
 182 #define GET_C2H_CMD_CONTINUE(__prxhdr)          \
 183         LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
 184 #define GET_C2H_CMD_CONTENT(__prxhdr)           \
 185         ((u8*)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
 186
 187 #define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)    \
 188         LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
 189 #define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)               \
 190         LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
 191 #define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)   \
 192         LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
 193 #define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)    \
 194         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
 195 #define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)             \
 196         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
 197 #define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
 198         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
 199 #define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)               \
 200         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
 201 #define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)              \
 202         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
 203 #define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)               \
 204         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
 205
 206 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
 207
 208 #define CHIP_8812                               BIT(2)
 209 #define CHIP_8821                               (BIT(0)|BIT(2))
 210
 211 #define CHIP_8821A                                              (BIT(0)|BIT(2))
 212 #define NORMAL_CHIP                                     BIT(3)
 213 #define RF_TYPE_1T1R                                    (~(BIT(4)|BIT(5)|BIT(6)))
 214 #define RF_TYPE_1T2R                                    BIT(4)
 215 #define RF_TYPE_2T2R                                    BIT(5)
 216 #define CHIP_VENDOR_UMC                                 BIT(7)
 217 #define B_CUT_VERSION                                   BIT(12)
 218 #define C_CUT_VERSION                                   BIT(13)
 219 #define D_CUT_VERSION                                   ((BIT(12)|BIT(13)))
 220 #define E_CUT_VERSION                                   BIT(14)
 221 #define RF_RL_ID                                                (BIT(31)|BIT(30)|BIT(29)|BIT(28))
 222
 223
 224
 225 enum version_8821ae {
 226         VERSION_TEST_CHIP_1T1R_8812 = 0x0004,
 227         VERSION_TEST_CHIP_2T2R_8812 = 0x0024,
 228         VERSION_NORMAL_TSMC_CHIP_1T1R_8812 = 0x100c,
 229         VERSION_NORMAL_TSMC_CHIP_2T2R_8812 = 0x102c,
 230         VERSION_NORMAL_TSMC_CHIP_1T1R_8812_C_CUT = 0x200c,
 231         VERSION_NORMAL_TSMC_CHIP_2T2R_8812_C_CUT = 0x202c,
 232         VERSION_TEST_CHIP_8821 = 0x0005,
 233         VERSION_NORMAL_TSMC_CHIP_8821 = 0x000d,
 234         VERSION_NORMAL_TSMC_CHIP_8821_B_CUT = 0x100d,
 235         VERSION_UNKNOWN = 0xFF,
 236 };
 237
 238 enum vht_data_sc{
 239         VHT_DATA_SC_DONOT_CARE = 0,
 240         VHT_DATA_SC_20_UPPER_OF_80MHZ = 1,
 241         VHT_DATA_SC_20_LOWER_OF_80MHZ = 2,
 242         VHT_DATA_SC_20_UPPERST_OF_80MHZ = 3,
 243         VHT_DATA_SC_20_LOWEST_OF_80MHZ = 4,
 244         VHT_DATA_SC_20_RECV1 = 5,
 245         VHT_DATA_SC_20_RECV2 = 6,
 246         VHT_DATA_SC_20_RECV3 = 7,
 247         VHT_DATA_SC_20_RECV4 = 8,
 248         VHT_DATA_SC_40_UPPER_OF_80MHZ = 9,
 249         VHT_DATA_SC_40_LOWER_OF_80MHZ = 10,
 250 };
 251
 252
 253 /* MASK */
 254 #define IC_TYPE_MASK                                    (BIT(0)|BIT(1)|BIT(2))
 255 #define CHIP_TYPE_MASK                                  BIT(3)
 256 #define RF_TYPE_MASK                                    (BIT(4)|BIT(5)|BIT(6))
 257 #define MANUFACTUER_MASK                                BIT(7)
 258 #define ROM_VERSION_MASK                                (BIT(11)|BIT(10)|BIT(9)|BIT(8))
 259 #define CUT_VERSION_MASK                                (BIT(15)|BIT(14)|BIT(13)|BIT(12))
 260
 261 /* Get element */
 262 #define GET_CVID_IC_TYPE(version)                       ((version) & IC_TYPE_MASK)
 263 #define GET_CVID_CHIP_TYPE(version)                     ((version) & CHIP_TYPE_MASK)
 264 #define GET_CVID_RF_TYPE(version)                       ((version) & RF_TYPE_MASK)
 265 #define GET_CVID_MANUFACTUER(version)           ((version) & MANUFACTUER_MASK)
 266 #define GET_CVID_ROM_VERSION(version)           ((version) & ROM_VERSION_MASK)
 267 #define GET_CVID_CUT_VERSION(version)           ((version) & CUT_VERSION_MASK)
 268
 269 #define IS_1T1R(version)                        ((GET_CVID_RF_TYPE(version))? false : true)
 270 #define IS_1T2R(version)                        ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
 271                                                                         ? true : false)
 272 #define IS_2T2R(version)                        ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
 273                                                                         ? true : false)
 274
 275 #define IS_8812_SERIES(version)                 ((GET_CVID_IC_TYPE(version) == CHIP_8812)? \
 276                                                                                 true : false)
 277 #define IS_8821_SERIES(version)                 ((GET_CVID_IC_TYPE(version) == CHIP_8821)? \
 278                                                                                 true : false)
 279
 280 #define IS_VENDOR_8812A_TEST_CHIP(version)      ((IS_8812_SERIES(version)) ? \
 281                                                                                                 ((IS_NORMAL_CHIP(version)) ? \
 282                                                                                                 false : true) : false)
 283 #define IS_VENDOR_8812A_MP_CHIP(version)                ((IS_8812_SERIES(version)) ? \
 284                                                                                                 ((IS_NORMAL_CHIP(version)) ? \
 285                                                                                                 true : false) : false)
 286 #define IS_VENDOR_8812A_C_CUT(version)          ((IS_8812_SERIES(version)) ? \
 287                                                                                         ((GET_CVID_CUT_VERSION(version) == C_CUT_VERSION) ? \
 288                                                                                         true : false) : false)
 289
 290 #define IS_VENDOR_8821A_TEST_CHIP(version)      ((IS_8821_SERIES(version)) ? \
 291                                                                                                 ((IS_NORMAL_CHIP(version)) ? \
 292                                                                                                 false : true) : false)
 293 #define IS_VENDOR_8821A_MP_CHIP(version)                ((IS_8821_SERIES(version)) ? \
 294                                                                                                 ((IS_NORMAL_CHIP(version)) ? \
 295                                                                                                 true : false) : false)
 296 #define IS_VENDOR_8821A_B_CUT(version)          ((IS_8821_SERIES(version)) ? \
 297                                                                                                 ((GET_CVID_CUT_VERSION(version) == B_CUT_VERSION) ? \
 298                                                                                                 true : false) : false)
 299
 300
 301 enum rf_optype {
 302         RF_OP_BY_SW_3WIRE = 0,
 303         RF_OP_BY_FW,
 304         RF_OP_MAX
 305 };
 306
 307 enum rf_power_state {
 308         RF_ON,
 309         RF_OFF,
 310         RF_SLEEP,
 311         RF_SHUT_DOWN,
 312 };
 313
 314 enum power_save_mode {
 315         POWER_SAVE_MODE_ACTIVE,
 316         POWER_SAVE_MODE_SAVE,
 317 };
 318
 319 enum power_polocy_config {
 320         POWERCFG_MAX_POWER_SAVINGS,
 321         POWERCFG_GLOBAL_POWER_SAVINGS,
 322         POWERCFG_LOCAL_POWER_SAVINGS,
 323         POWERCFG_LENOVO,
 324 };
 325
 326 enum interface_select_pci {
 327         INTF_SEL1_MINICARD = 0,
 328         INTF_SEL0_PCIE = 1,
 329         INTF_SEL2_RSV = 2,
 330         INTF_SEL3_RSV = 3,
 331 };
 332
 333 enum hal_fw_c2h_cmd_id {
 334         HAL_FW_C2H_CMD_Read_MACREG = 0,
 335         HAL_FW_C2H_CMD_Read_BBREG = 1,
 336         HAL_FW_C2H_CMD_Read_RFREG = 2,
 337         HAL_FW_C2H_CMD_Read_EEPROM = 3,
 338         HAL_FW_C2H_CMD_Read_EFUSE = 4,
 339         HAL_FW_C2H_CMD_Read_CAM = 5,
 340         HAL_FW_C2H_CMD_Get_BasicRate = 6,
 341         HAL_FW_C2H_CMD_Get_DataRate = 7,
 342         HAL_FW_C2H_CMD_Survey = 8,
 343         HAL_FW_C2H_CMD_SurveyDone = 9,
 344         HAL_FW_C2H_CMD_JoinBss = 10,
 345         HAL_FW_C2H_CMD_AddSTA = 11,
 346         HAL_FW_C2H_CMD_DelSTA = 12,
 347         HAL_FW_C2H_CMD_AtimDone = 13,
 348         HAL_FW_C2H_CMD_TX_Report = 14,
 349         HAL_FW_C2H_CMD_CCX_Report = 15,
 350         HAL_FW_C2H_CMD_DTM_Report = 16,
 351         HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
 352         HAL_FW_C2H_CMD_C2HLBK = 18,
 353         HAL_FW_C2H_CMD_C2HDBG = 19,
 354         HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
 355         HAL_FW_C2H_CMD_MAX
 356 };
 357
 358 enum rtl_desc_qsel {
 359         QSLT_BK = 0x2,
 360         QSLT_BE = 0x0,
 361         QSLT_VI = 0x5,
 362         QSLT_VO = 0x7,
 363         QSLT_BEACON = 0x10,
 364         QSLT_HIGH = 0x11,
 365         QSLT_MGNT = 0x12,
 366         QSLT_CMD = 0x13,
 367 };
 368
 369 enum rtl_desc8821ae_rate {
 370         DESC_RATE1M = 0x00,
 371         DESC_RATE2M = 0x01,
 372         DESC_RATE5_5M = 0x02,
 373         DESC_RATE11M = 0x03,
 374
 375         DESC_RATE6M = 0x04,
 376         DESC_RATE9M = 0x05,
 377         DESC_RATE12M = 0x06,
 378         DESC_RATE18M = 0x07,
 379         DESC_RATE24M = 0x08,
 380         DESC_RATE36M = 0x09,
 381         DESC_RATE48M = 0x0a,
 382         DESC_RATE54M = 0x0b,
 383
 384         DESC_RATEMCS0 = 0x0c,
 385         DESC_RATEMCS1 = 0x0d,
 386         DESC_RATEMCS2 = 0x0e,
 387         DESC_RATEMCS3 = 0x0f,
 388         DESC_RATEMCS4 = 0x10,
 389         DESC_RATEMCS5 = 0x11,
 390         DESC_RATEMCS6 = 0x12,
 391         DESC_RATEMCS7 = 0x13,
 392         DESC_RATEMCS8 = 0x14,
 393         DESC_RATEMCS9 = 0x15,
 394         DESC_RATEMCS10 = 0x16,
 395         DESC_RATEMCS11 = 0x17,
 396         DESC_RATEMCS12 = 0x18,
 397         DESC_RATEMCS13 = 0x19,
 398         DESC_RATEMCS14 = 0x1a,
 399         DESC_RATEMCS15 = 0x1b,
 400         DESC_RATEVHT1SS_MCS0 = 0x1c,
 401         DESC_RATEVHT1SS_MCS1 = 0x1d,
 402         DESC_RATEVHT1SS_MCS2 = 0x1e,
 403         DESC_RATEVHT1SS_MCS3 = 0x1f,
 404         DESC_RATEVHT1SS_MCS4 = 0x20,
 405         DESC_RATEVHT1SS_MCS5 = 0x21,
 406         DESC_RATEVHT1SS_MCS6 = 0x22,
 407         DESC_RATEVHT1SS_MCS7 = 0x23,
 408         DESC_RATEVHT1SS_MCS8 = 0x24,
 409         DESC_RATEVHT1SS_MCS9 = 0x25,
 410         DESC_RATEVHT2SS_MCS0 = 0x26,
 411         DESC_RATEVHT2SS_MCS1 = 0x27,
 412         DESC_RATEVHT2SS_MCS2 = 0x28,
 413         DESC_RATEVHT2SS_MCS3 = 0x29,
 414         DESC_RATEVHT2SS_MCS4 = 0x2a,
 415         DESC_RATEVHT2SS_MCS5 = 0x2b,
 416         DESC_RATEVHT2SS_MCS6 = 0x2c,
 417         DESC_RATEVHT2SS_MCS7 = 0x2d,
 418         DESC_RATEVHT2SS_MCS8 = 0x2e,
 419         DESC_RATEVHT2SS_MCS9 = 0x2f,
 420 };
 421
 422 enum rx_packet_type{
 423         NORMAL_RX,
 424         TX_REPORT1,
 425         TX_REPORT2,
 426         HIS_REPORT,
 427         C2H_PACKET,
 428 };
 429
 430 struct phy_sts_cck_8821ae_t {
 431         u8 adc_pwdb_X[4];
 432         u8 sq_rpt;
 433         u8 cck_agc_rpt;
 434 };
 435
 436 struct h2c_cmd_8821ae {
 437         u8 element_id;
 438         u32 cmd_len;
 439         u8 *p_cmdbuffer;
 440 };
 441
 442 #endif