3 #include "r819xE_phyreg.h"
4 #include "r8190_rtl8256.h"
5 #include "r819xE_phy.h"
8 #include "ieee80211/dot11d.h"
10 static const u32 RF_CHANNEL_TABLE_ZEBRA[] = {
28 u32 Rtl8190PciMACPHY_Array[] = {
29 0x03c,0xffff0000,0x00000f0f,
30 0x340,0xffffffff,0x161a1a1a,
31 0x344,0xffffffff,0x12121416,
32 0x348,0x0000ffff,0x00001818,
33 0x12c,0xffffffff,0x04000802,
34 0x318,0x00000fff,0x00000800,
36 u32 Rtl8190PciMACPHY_Array_PG[] = {
37 0x03c,0xffff0000,0x00000f0f,
38 0x340,0xffffffff,0x0a0c0d0f,
39 0x344,0xffffffff,0x06070809,
40 0x344,0xffffffff,0x06070809,
41 0x348,0x0000ffff,0x00000000,
42 0x12c,0xffffffff,0x04000802,
43 0x318,0x00000fff,0x00000800,
46 u32 Rtl8190PciAGCTAB_Array[AGCTAB_ArrayLength] = {
241 u32 Rtl8190PciPHY_REGArray[PHY_REGArrayLength] = {
383 u32 Rtl8190PciPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
526 u32 Rtl8190PciRadioA_Array[RadioA_ArrayLength] = {
651 u32 Rtl8190PciRadioB_Array[RadioB_ArrayLength] = {
692 u32 Rtl8190PciRadioC_Array[RadioC_ArrayLength] = {
817 u32 Rtl8190PciRadioD_Array[RadioD_ArrayLength] = {
860 static u32 Rtl8192PciEMACPHY_Array[] = {
861 0x03c,0xffff0000,0x00000f0f,
862 0x340,0xffffffff,0x161a1a1a,
863 0x344,0xffffffff,0x12121416,
864 0x348,0x0000ffff,0x00001818,
865 0x12c,0xffffffff,0x04000802,
866 0x318,0x00000fff,0x00000100,
868 static u32 Rtl8192PciEMACPHY_Array_PG[] = {
869 0x03c,0xffff0000,0x00000f0f,
870 0xe00,0xffffffff,0x06090909,
871 0xe04,0xffffffff,0x00030306,
872 0xe08,0x0000ff00,0x00000000,
873 0xe10,0xffffffff,0x0a0c0d0f,
874 0xe14,0xffffffff,0x06070809,
875 0xe18,0xffffffff,0x0a0c0d0f,
876 0xe1c,0xffffffff,0x06070809,
877 0x12c,0xffffffff,0x04000802,
878 0x318,0x00000fff,0x00000800,
880 static u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLength] = {
1074 static u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLength] = {
1076 static u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
1226 static u32 Rtl8192PciERadioA_Array[RadioA_ArrayLength] = {
1351 static u32 Rtl8192PciERadioB_Array[RadioB_ArrayLength] = {
1392 static u32 Rtl8192PciERadioC_Array[RadioC_ArrayLength] = {
1394 static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = {
1398 /*************************Define local function prototype**********************/
1400 static u32 phy_FwRFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset);
1401 static void phy_FwRFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data);
1402 /*************************Define local function prototype**********************/
1403 /******************************************************************************
1404 *function: This function read BB parameters from Header file we gen,
1405 * and do register read/write
1406 * input: u32 dwBitMask //taget bit pos in the addr to be modified
1408 * return: u32 return the shift bit bit position of the mask
1409 * ****************************************************************************/
1410 static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
1413 for (i=0; i<=31; i++)
1415 if (((dwBitMask>>i)&0x1) == 1)
1420 /******************************************************************************
1421 *function: This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
1424 * return: 0(illegal, false), 1(legal,true)
1425 * ***************************************************************************/
1426 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
1429 struct r8192_priv *priv = ieee80211_priv(dev);
1431 if(priv->rf_type == RF_2T4R)
1435 else if (priv->rf_type == RF_1T2R)
1437 if(eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
1439 else if(eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
1444 if (priv->rf_type == RF_2T4R)
1446 else if (priv->rf_type == RF_1T2R)
1448 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
1450 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
1457 /******************************************************************************
1458 *function: This function set specific bits to BB register
1459 * input: net_device dev
1460 * u32 dwRegAddr //target addr to be modified
1461 * u32 dwBitMask //taget bit pos in the addr to be modified
1462 * u32 dwData //value to be write
1466 * ****************************************************************************/
1467 void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
1470 u32 OriginalValue, BitShift, NewValue;
1472 if(dwBitMask!= bMaskDWord)
1473 {//if not "double word" write
1474 OriginalValue = read_nic_dword(dev, dwRegAddr);
1475 BitShift = rtl8192_CalculateBitShift(dwBitMask);
1476 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
1477 write_nic_dword(dev, dwRegAddr, NewValue);
1479 write_nic_dword(dev, dwRegAddr, dwData);
1481 /******************************************************************************
1482 *function: This function reads specific bits from BB register
1483 * input: net_device dev
1484 * u32 dwRegAddr //target addr to be readback
1485 * u32 dwBitMask //taget bit pos in the addr to be readback
1487 * return: u32 Data //the readback register value
1489 * ****************************************************************************/
1490 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
1492 u32 OriginalValue, BitShift;
1494 OriginalValue = read_nic_dword(dev, dwRegAddr);
1495 BitShift = rtl8192_CalculateBitShift(dwBitMask);
1496 return (OriginalValue & dwBitMask) >> BitShift;
1498 /******************************************************************************
1499 *function: This function read register from RF chip
1500 * input: net_device dev
1501 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1502 * u32 Offset //target address to be read
1504 * return: u32 readback value
1505 * notice: There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
1506 * ****************************************************************************/
1507 static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
1509 struct r8192_priv *priv = ieee80211_priv(dev);
1512 BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
1513 //rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
1514 //make sure RF register offset is correct
1517 //switch page for 8256 RF IC
1518 if (priv->rf_chip == RF_8256)
1521 //analog to digital off, for protection
1522 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1525 //analog to digital off, for protection
1526 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1531 priv->RfReg0Value[eRFPath] |= 0x140;
1532 //Switch to Reg_Mode2 for Reg 31-45
1533 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
1535 NewOffset = Offset -30;
1537 else if (Offset >= 16)
1539 priv->RfReg0Value[eRFPath] |= 0x100;
1540 priv->RfReg0Value[eRFPath] &= (~0x40);
1541 //Switch to Reg_Mode 1 for Reg16-30
1542 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
1544 NewOffset = Offset - 15;
1551 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
1554 //put desired read addr to LSSI control Register
1555 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
1556 //Issue a posedge trigger
1558 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x0);
1559 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadEdge, 0x1);
1562 // TODO: we should not delay such a long time. Ask help from SD3
1565 ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
1568 // Switch back to Reg_Mode0;
1569 if(priv->rf_chip == RF_8256)
1571 priv->RfReg0Value[eRFPath] &= 0xebf;
1575 pPhyReg->rf3wireOffset,
1577 (priv->RfReg0Value[eRFPath] << 16));
1580 if(priv->rf_type == RF_2T4R)
1582 //analog to digital on
1583 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1585 else if(priv->rf_type == RF_1T2R)
1587 //analog to digital on
1588 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
1592 //analog to digital on
1593 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1603 /******************************************************************************
1604 *function: This function write data to RF register
1605 * input: net_device dev
1606 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1607 * u32 Offset //target address to be written
1608 * u32 Data //The new register data to be written
1611 * notice: For RF8256 only.
1612 ===========================================================
1613 *Reg Mode RegCTL[1] RegCTL[0] Note
1614 * (Reg00[12]) (Reg00[10])
1615 *===========================================================
1616 *Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
1617 *------------------------------------------------------------------
1618 *Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
1619 *------------------------------------------------------------------
1620 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
1621 *------------------------------------------------------------------
1622 * ****************************************************************************/
1623 static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
1625 struct r8192_priv *priv = ieee80211_priv(dev);
1626 u32 DataAndAddr = 0, NewOffset = 0;
1627 BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
1630 if (priv->rf_chip == RF_8256)
1634 //analog to digital off, for protection
1635 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1638 //analog to digital off, for protection
1639 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1645 priv->RfReg0Value[eRFPath] |= 0x140;
1646 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
1647 NewOffset = Offset - 30;
1649 else if (Offset >= 16)
1651 priv->RfReg0Value[eRFPath] |= 0x100;
1652 priv->RfReg0Value[eRFPath] &= (~0x40);
1653 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
1654 NewOffset = Offset - 15;
1661 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
1665 // Put write addr in [5:0] and write data in [31:16]
1666 DataAndAddr = (Data<<16) | (NewOffset&0x3f);
1669 rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
1673 priv->RfReg0Value[eRFPath] = Data;
1675 // Switch back to Reg_Mode0;
1676 if(priv->rf_chip == RF_8256)
1680 priv->RfReg0Value[eRFPath] &= 0xebf;
1683 pPhyReg->rf3wireOffset,
1685 (priv->RfReg0Value[eRFPath] << 16));
1688 if(priv->rf_type == RF_2T4R)
1690 //analog to digital on
1691 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1693 else if(priv->rf_type == RF_1T2R)
1695 //analog to digital on
1696 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
1700 //analog to digital on
1701 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1707 /******************************************************************************
1708 *function: This function set specific bits to RF register
1709 * input: net_device dev
1710 * RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1711 * u32 RegAddr //target addr to be modified
1712 * u32 BitMask //taget bit pos in the addr to be modified
1713 * u32 Data //value to be write
1717 * ****************************************************************************/
1718 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
1720 struct r8192_priv *priv = ieee80211_priv(dev);
1721 u32 Original_Value, BitShift, New_Value;
1724 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1727 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
1730 //spin_lock_irqsave(&priv->rf_lock, flags);
1731 //down(&priv->rf_sem);
1733 RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
1734 if (priv->Rf_Mode == RF_OP_By_FW)
1736 if (BitMask != bMask12Bits) // RF data is 12 bits only
1738 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
1739 BitShift = rtl8192_CalculateBitShift(BitMask);
1740 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
1742 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
1744 phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
1750 if (BitMask != bMask12Bits) // RF data is 12 bits only
1752 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
1753 BitShift = rtl8192_CalculateBitShift(BitMask);
1754 New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
1756 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
1758 rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
1760 //spin_unlock_irqrestore(&priv->rf_lock, flags);
1761 //up(&priv->rf_sem);
1764 /******************************************************************************
1765 *function: This function reads specific bits from RF register
1766 * input: net_device dev
1767 * u32 RegAddr //target addr to be readback
1768 * u32 BitMask //taget bit pos in the addr to be readback
1770 * return: u32 Data //the readback register value
1772 * ****************************************************************************/
1773 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
1775 u32 Original_Value, Readback_Value, BitShift;
1776 struct r8192_priv *priv = ieee80211_priv(dev);
1777 if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1780 if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
1783 down(&priv->rf_sem);
1784 if (priv->Rf_Mode == RF_OP_By_FW)
1786 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
1791 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
1794 BitShift = rtl8192_CalculateBitShift(BitMask);
1795 Readback_Value = (Original_Value & BitMask) >> BitShift;
1798 return Readback_Value;
1801 /******************************************************************************
1802 *function: We support firmware to execute RF-R/W.
1807 * ***************************************************************************/
1808 static u32 phy_FwRFSerialRead(
1809 struct net_device* dev,
1810 RF90_RADIO_PATH_E eRFPath,
1815 //DbgPrint("FW RF CTRL\n\r");
1816 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
1817 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
1818 much time. This is only for site survey. */
1819 // 1. Read operation need not insert data. bit 0-11
1820 //Data &= bMask12Bits;
1821 // 2. Write RF register address. Bit 12-19
1822 Data |= ((Offset&0xFF)<<12);
1823 // 3. Write RF path. bit 20-21
1824 Data |= ((eRFPath&0x3)<<20);
1825 // 4. Set RF read indicator. bit 22=0
1827 // 5. Trigger Fw to operate the command. bit 31
1829 // 6. We can not execute read operation if bit 31 is 1.
1830 while (read_nic_dword(dev, QPNR)&0x80000000)
1832 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1835 //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
1841 // 7. Execute read operation.
1842 write_nic_dword(dev, QPNR, Data);
1843 // 8. Check if firmawre send back RF content.
1844 while (read_nic_dword(dev, QPNR)&0x80000000)
1846 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1849 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
1855 return read_nic_dword(dev, RF_DATA);
1858 /******************************************************************************
1859 *function: We support firmware to execute RF-R/W.
1864 * ***************************************************************************/
1866 phy_FwRFSerialWrite(
1867 struct net_device* dev,
1868 RF90_RADIO_PATH_E eRFPath,
1874 //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
1875 /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
1876 not execute the scheme in the initial step. Otherwise, RF-R/W will waste
1877 much time. This is only for site survey. */
1879 // 1. Set driver write bit and 12 bit data. bit 0-11
1880 //Data &= bMask12Bits; // Done by uper layer.
1881 // 2. Write RF register address. bit 12-19
1882 Data |= ((Offset&0xFF)<<12);
1883 // 3. Write RF path. bit 20-21
1884 Data |= ((eRFPath&0x3)<<20);
1885 // 4. Set RF write indicator. bit 22=1
1887 // 5. Trigger Fw to operate the command. bit 31=1
1890 // 6. Write operation. We can not write if bit 31 is 1.
1891 while (read_nic_dword(dev, QPNR)&0x80000000)
1893 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1896 //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
1902 // 7. No matter check bit. We always force the write. Because FW will
1903 // not accept the command.
1904 write_nic_dword(dev, QPNR, Data);
1905 /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
1906 to finish RF write operation. */
1907 /* 2008/01/17 MH We support delay in firmware side now. */
1913 /******************************************************************************
1914 *function: This function read BB parameters from Header file we gen,
1915 * and do register read/write
1919 * notice: BB parameters may change all the time, so please make
1920 * sure it has been synced with the newest.
1921 * ***************************************************************************/
1922 void rtl8192_phy_configmac(struct net_device* dev)
1924 u32 dwArrayLen = 0, i = 0;
1925 u32* pdwArray = NULL;
1926 struct r8192_priv *priv = ieee80211_priv(dev);
1928 if(Adapter->bInHctTest)
1930 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_ArrayDTM\n");
1931 dwArrayLen = MACPHY_ArrayLengthDTM;
1932 pdwArray = Rtl819XMACPHY_ArrayDTM;
1934 else if(priv->bTXPowerDataReadFromEEPORM)
1936 if(priv->bTXPowerDataReadFromEEPORM)
1938 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
1939 dwArrayLen = MACPHY_Array_PGLength;
1940 pdwArray = Rtl819XMACPHY_Array_PG;
1945 RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n");
1946 dwArrayLen = MACPHY_ArrayLength;
1947 pdwArray = Rtl819XMACPHY_Array;
1949 for(i = 0; i<dwArrayLen; i=i+3){
1950 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
1951 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1952 if(pdwArray[i] == 0x318)
1954 pdwArray[i+2] = 0x00000800;
1955 //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1956 // ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1958 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1962 /******************************************************************************
1963 *function: This function do dirty work
1967 * notice: BB parameters may change all the time, so please make
1968 * sure it has been synced with the newest.
1969 * ***************************************************************************/
1971 void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
1975 u32* Rtl819XPHY_REGArray_Table = NULL;
1976 u32* Rtl819XAGCTAB_Array_Table = NULL;
1977 u16 AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
1978 struct r8192_priv *priv = ieee80211_priv(dev);
1980 u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
1981 if(Adapter->bInHctTest)
1983 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1984 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1986 if(priv->RF_Type == RF_2T4R)
1988 PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1989 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1991 else if (priv->RF_Type == RF_1T2R)
1993 PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1994 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
2000 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
2001 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
2002 if(priv->rf_type == RF_2T4R)
2004 PHY_REGArrayLen = PHY_REGArrayLength;
2005 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
2007 else if (priv->rf_type == RF_1T2R)
2009 PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
2010 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
2014 if (ConfigType == BaseBand_Config_PHY_REG)
2016 for (i=0; i<PHY_REGArrayLen; i+=2)
2018 rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
2019 RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
2022 else if (ConfigType == BaseBand_Config_AGC_TAB)
2024 for (i=0; i<AGCTAB_ArrayLen; i+=2)
2026 rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
2027 RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
2031 /******************************************************************************
2032 *function: This function initialize Register definition offset for Radio Path
2034 * input: net_device dev
2037 * notice: Initialization value here is constant and it should never be changed
2038 * ***************************************************************************/
2039 static void rtl8192_InitBBRFRegDef(struct net_device* dev)
2041 struct r8192_priv *priv = ieee80211_priv(dev);
2042 // RF Interface Sowrtware Control
2043 priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
2044 priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
2045 priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
2046 priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
2048 // RF Interface Readback Value
2049 priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
2050 priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
2051 priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
2052 priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
2054 // RF Interface Output (and Enable)
2055 priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
2056 priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
2057 priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
2058 priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
2060 // RF Interface (Output and) Enable
2061 priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
2062 priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
2063 priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
2064 priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
2066 //Addr of LSSI. Wirte RF register by driver
2067 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
2068 priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
2069 priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
2070 priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
2073 priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
2074 priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
2075 priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2076 priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2078 // Tx AGC Gain Stage (same for all path. Should we remove this?)
2079 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2080 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2081 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2082 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2084 // Tranceiver A~D HSSI Parameter-1
2085 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
2086 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
2087 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1; //wire control parameter1
2088 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1; //wire control parameter1
2090 // Tranceiver A~D HSSI Parameter-2
2091 priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
2092 priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
2093 priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2; //wire control parameter2
2094 priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2; //wire control parameter1
2096 // RF switch Control
2097 priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
2098 priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
2099 priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2100 priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2103 priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
2104 priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
2105 priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
2106 priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
2109 priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
2110 priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
2111 priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
2112 priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
2115 priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
2116 priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
2117 priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
2118 priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
2121 priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
2122 priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
2123 priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
2124 priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
2127 priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
2128 priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
2129 priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
2130 priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
2133 priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
2134 priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
2135 priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
2136 priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
2138 // Tranceiver LSSI Readback
2139 priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
2140 priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
2141 priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
2142 priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
2145 /******************************************************************************
2146 *function: This function is to write register and then readback to make sure whether BB and RF is OK
2147 * input: net_device dev
2148 * HW90_BLOCK_E CheckBlock
2149 * RF90_RADIO_PATH_E eRFPath //only used when checkblock is HW90_BLOCK_RF
2151 * return: return whether BB and RF is ok(0:OK; 1:Fail)
2152 * notice: This function may be removed in the ASIC
2153 * ***************************************************************************/
2154 RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
2156 //struct r8192_priv *priv = ieee80211_priv(dev);
2157 // BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
2158 RT_STATUS ret = RT_STATUS_SUCCESS;
2159 u32 i, CheckTimes = 4, dwRegRead = 0;
2161 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
2162 // Initialize register address offset to be checked
2163 WriteAddr[HW90_BLOCK_MAC] = 0x100;
2164 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
2165 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
2166 WriteAddr[HW90_BLOCK_RF] = 0x3;
2167 RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
2168 for(i=0 ; i < CheckTimes ; i++)
2172 // Write Data to register and readback
2176 case HW90_BLOCK_MAC:
2177 RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
2180 case HW90_BLOCK_PHY0:
2181 case HW90_BLOCK_PHY1:
2182 write_nic_dword(dev, WriteAddr[CheckBlock], WriteData[i]);
2183 dwRegRead = read_nic_dword(dev, WriteAddr[CheckBlock]);
2187 WriteData[i] &= 0xfff;
2188 rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
2189 // TODO: we should not delay for such a long time. Ask SD3
2191 dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
2196 ret = RT_STATUS_FAILURE;
2202 // Check whether readback data is correct
2204 if(dwRegRead != WriteData[i])
2206 RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
2207 ret = RT_STATUS_FAILURE;
2216 /******************************************************************************
2217 *function: This function initialize BB&RF
2218 * input: net_device dev
2221 * notice: Initialization value may change all the time, so please make
2222 * sure it has been synced with the newest.
2223 * ***************************************************************************/
2224 static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
2226 struct r8192_priv *priv = ieee80211_priv(dev);
2227 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2228 u8 bRegValue = 0, eCheckItem = 0;
2230 /**************************************
2231 //<1>Initialize BaseBand
2232 **************************************/
2234 /*--set BB Global Reset--*/
2235 bRegValue = read_nic_byte(dev, BB_GLOBAL_RESET);
2236 write_nic_byte(dev, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
2238 /*---set BB reset Active---*/
2239 dwRegValue = read_nic_dword(dev, CPU_GEN);
2240 write_nic_dword(dev, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
2242 /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
2243 // TODO: this function should be removed on ASIC , Emily 2007.2.2
2244 for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
2246 rtStatus = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
2247 if(rtStatus != RT_STATUS_SUCCESS)
2249 RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
2253 /*---- Set CCK and OFDM Block "OFF"----*/
2254 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
2255 /*----BB Register Initilazation----*/
2256 //==m==>Set PHY REG From Header<==m==
2257 rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
2259 /*----Set BB reset de-Active----*/
2260 dwRegValue = read_nic_dword(dev, CPU_GEN);
2261 write_nic_dword(dev, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
2263 /*----BB AGC table Initialization----*/
2264 //==m==>Set PHY REG From Header<==m==
2265 rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
2267 if (priv->card_8192_version > VERSION_8190_BD)
2269 if(priv->rf_type == RF_2T4R)
2271 // Antenna gain offset from B/C/D to A
2272 dwRegValue = ( priv->AntennaTxPwDiff[2]<<8 |
2273 priv->AntennaTxPwDiff[1]<<4 |
2274 priv->AntennaTxPwDiff[0]);
2277 dwRegValue = 0x0; //Antenna gain offset doesn't make sense in RF 1T2R.
2278 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
2279 (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
2284 dwRegValue = priv->CrystalCap & 0x3; // bit0~1 of crystal cap
2285 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue);
2286 dwRegValue = ((priv->CrystalCap & 0xc)>>2); // bit2~3 of crystal cap
2287 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, bXtalCap23, dwRegValue);
2290 dwRegValue = priv->CrystalCap;
2291 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
2297 // Check if the CCK HighPower is turned ON.
2298 // This is used to calculate PWDB.
2299 // priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
2302 /******************************************************************************
2303 *function: This function initialize BB&RF
2304 * input: net_device dev
2307 * notice: Initialization value may change all the time, so please make
2308 * sure it has been synced with the newest.
2309 * ***************************************************************************/
2310 RT_STATUS rtl8192_BBConfig(struct net_device* dev)
2312 rtl8192_InitBBRFRegDef(dev);
2313 //config BB&RF. As hardCode based initialization has not been well
2314 //implemented, so use file first.FIXME:should implement it for hardcode?
2315 return rtl8192_BB_Config_ParaFile(dev);
2318 /******************************************************************************
2319 *function: This function obtains the initialization value of Tx power Level offset
2320 * input: net_device dev
2323 * ***************************************************************************/
2324 void rtl8192_phy_getTxPower(struct net_device* dev)
2326 struct r8192_priv *priv = ieee80211_priv(dev);
2328 priv->MCSTxPowerLevelOriginalOffset[0] =
2329 read_nic_dword(dev, MCS_TXAGC);
2330 priv->MCSTxPowerLevelOriginalOffset[1] =
2331 read_nic_dword(dev, (MCS_TXAGC+4));
2332 priv->CCKTxPowerLevelOriginalOffset =
2333 read_nic_dword(dev, CCK_TXAGC);
2336 priv->MCSTxPowerLevelOriginalOffset[0] =
2337 read_nic_dword(dev, rTxAGC_Rate18_06);
2338 priv->MCSTxPowerLevelOriginalOffset[1] =
2339 read_nic_dword(dev, rTxAGC_Rate54_24);
2340 priv->MCSTxPowerLevelOriginalOffset[2] =
2341 read_nic_dword(dev, rTxAGC_Mcs03_Mcs00);
2342 priv->MCSTxPowerLevelOriginalOffset[3] =
2343 read_nic_dword(dev, rTxAGC_Mcs07_Mcs04);
2344 priv->MCSTxPowerLevelOriginalOffset[4] =
2345 read_nic_dword(dev, rTxAGC_Mcs11_Mcs08);
2346 priv->MCSTxPowerLevelOriginalOffset[5] =
2347 read_nic_dword(dev, rTxAGC_Mcs15_Mcs12);
2351 // read rx initial gain
2352 priv->DefaultInitialGain[0] = read_nic_byte(dev, rOFDM0_XAAGCCore1);
2353 priv->DefaultInitialGain[1] = read_nic_byte(dev, rOFDM0_XBAGCCore1);
2354 priv->DefaultInitialGain[2] = read_nic_byte(dev, rOFDM0_XCAGCCore1);
2355 priv->DefaultInitialGain[3] = read_nic_byte(dev, rOFDM0_XDAGCCore1);
2356 RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
2357 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
2358 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
2361 priv->framesync = read_nic_byte(dev, rOFDM0_RxDetector3);
2362 priv->framesyncC34 = read_nic_dword(dev, rOFDM0_RxDetector2);
2363 RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
2364 rOFDM0_RxDetector3, priv->framesync);
2365 // read SIFS (save the value read fome MACPHY_REG.txt)
2366 priv->SifsTime = read_nic_word(dev, SIFS);
2369 /******************************************************************************
2370 *function: This function obtains the initialization value of Tx power Level offset
2371 * input: net_device dev
2374 * ***************************************************************************/
2375 void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
2377 struct r8192_priv *priv = ieee80211_priv(dev);
2378 u8 powerlevel = 0,powerlevelOFDM24G = 0;
2382 if(priv->epromtype == EPROM_93c46)
2384 powerlevel = priv->TxPowerLevelCCK[channel-1];
2385 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
2387 else if(priv->epromtype == EPROM_93c56)
2389 if(priv->rf_type == RF_1T2R)
2391 powerlevel = priv->TxPowerLevelCCK_C[channel-1];
2392 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
2394 else if(priv->rf_type == RF_2T4R)
2396 // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-C Tx
2397 // Power must be calculated by the antenna diff.
2398 // So we have to rewrite Antenna gain offset register here.
2399 powerlevel = priv->TxPowerLevelCCK_A[channel-1];
2400 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
2402 ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
2403 -priv->TxPowerLevelOFDM24G_A[channel-1];
2404 ant_pwr_diff &= 0xf;
2405 //DbgPrint(" ant_pwr_diff = 0x%x", (u8)(ant_pwr_diff));
2406 priv->RF_C_TxPwDiff = ant_pwr_diff;
2408 priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
2409 priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);// RF-C
2410 priv->AntennaTxPwDiff[0] = 0;// RF-B, don't care
2412 // Antenna gain offset from B/C/D to A
2413 u4RegValue = ( priv->AntennaTxPwDiff[2]<<8 |
2414 priv->AntennaTxPwDiff[1]<<4 |
2415 priv->AntennaTxPwDiff[0]);
2417 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
2418 (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2423 // CCX 2 S31, AP control of client transmit power:
2424 // 1. We shall not exceed Cell Power Limit as possible as we can.
2425 // 2. Tolerance is +/- 5dB.
2426 // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2429 // 1. 802.11h power contraint
2431 // 071011, by rcnjko.
2433 if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
2434 pMgntInfo->bWithCcxCellPwr &&
2435 channel == pMgntInfo->dot11CurrentChannelNumber)
2437 u8 CckCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
2438 u8 LegacyOfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);
2439 u8 OfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pMgntInfo->CcxCellPwr);
2441 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2442 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2443 pMgntInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2444 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2445 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2446 channel, powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2449 if(powerlevel > CckCellPwrIdx)
2450 powerlevel = CckCellPwrIdx;
2451 // Legacy OFDM, HT OFDM
2452 if(powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff > OfdmCellPwrIdx)
2454 if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
2456 powerlevelOFDM24G = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
2460 LegacyOfdmCellPwrIdx = 0;
2464 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2465 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2466 powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2469 pHalData->CurrentCckTxPwrIdx = powerlevel;
2470 pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
2472 switch(priv->rf_chip)
2475 // PHY_SetRF8225CckTxPower(Adapter, powerlevel);
2476 // PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
2479 PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
2480 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2485 RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __FUNCTION__);
2490 /******************************************************************************
2491 *function: This function check Rf chip to do RF config
2492 * input: net_device dev
2494 * return: only 8256 is supported
2495 * ***************************************************************************/
2496 RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev)
2498 struct r8192_priv *priv = ieee80211_priv(dev);
2499 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2500 switch(priv->rf_chip)
2503 // rtStatus = PHY_RF8225_Config(Adapter);
2506 rtStatus = PHY_RF8256_Config(dev);
2512 //rtStatus = PHY_RF8225_Config(Adapter);
2516 RT_TRACE(COMP_ERR, "error chip id\n");
2522 /******************************************************************************
2523 *function: This function update Initial gain
2524 * input: net_device dev
2526 * return: As Windows has not implemented this, wait for complement
2527 * ***************************************************************************/
2528 void rtl8192_phy_updateInitGain(struct net_device* dev)
2532 /******************************************************************************
2533 *function: This function read RF parameters from general head file, and do RF 3-wire
2534 * input: net_device dev
2536 * return: return code show if RF configuration is successful(0:pass, 1:fail)
2537 * Note: Delay may be required for RF configuration
2538 * ***************************************************************************/
2539 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
2548 for(i = 0;i<RadioA_ArrayLength; i=i+2){
2550 if(Rtl819XRadioA_Array[i] == 0xfe){
2554 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]);
2560 for(i = 0;i<RadioB_ArrayLength; i=i+2){
2562 if(Rtl819XRadioB_Array[i] == 0xfe){
2566 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]);
2572 for(i = 0;i<RadioC_ArrayLength; i=i+2){
2574 if(Rtl819XRadioC_Array[i] == 0xfe){
2578 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]);
2584 for(i = 0;i<RadioD_ArrayLength; i=i+2){
2586 if(Rtl819XRadioD_Array[i] == 0xfe){
2590 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]);
2602 /******************************************************************************
2603 *function: This function set Tx Power of the channel
2604 * input: struct net_device *dev
2609 * ***************************************************************************/
2610 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
2612 struct r8192_priv *priv = ieee80211_priv(dev);
2613 u8 powerlevel = priv->TxPowerLevelCCK[channel-1];
2614 u8 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
2616 switch(priv->rf_chip)
2620 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
2621 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
2626 PHY_SetRF8256CCKTxPower(dev, powerlevel);
2627 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2633 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
2637 /****************************************************************************************
2638 *function: This function set command table variable(struct SwChnlCmd).
2639 * input: SwChnlCmd* CmdTable //table to be set.
2640 * u32 CmdTableIdx //variable index in table to be set
2641 * u32 CmdTableSz //table size.
2642 * SwChnlCmdID CmdID //command ID to set.
2647 * return: true if finished, false otherwise
2649 * ************************************************************************************/
2650 static u8 rtl8192_phy_SetSwChnlCmdArray(
2651 SwChnlCmd* CmdTable,
2662 if(CmdTable == NULL)
2664 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
2667 if(CmdTableIdx >= CmdTableSz)
2669 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
2670 CmdTableIdx, CmdTableSz);
2674 pCmd = CmdTable + CmdTableIdx;
2675 pCmd->CmdID = CmdID;
2676 pCmd->Para1 = Para1;
2677 pCmd->Para2 = Para2;
2678 pCmd->msDelay = msDelay;
2682 /******************************************************************************
2683 *function: This function set channel step by step
2684 * input: struct net_device *dev
2686 * u8* stage //3 stages
2688 * u32* delay //whether need to delay
2689 * output: store new stage, step and delay for next step(combine with function above)
2690 * return: true if finished, false otherwise
2691 * Note: Wait for simpler function to replace it //wb
2692 * ***************************************************************************/
2693 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay)
2695 struct r8192_priv *priv = ieee80211_priv(dev);
2696 // PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
2697 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
2698 u32 PreCommonCmdCnt;
2699 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
2700 u32 PostCommonCmdCnt;
2701 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
2703 SwChnlCmd *CurrentCmd = NULL;
2704 //RF90_RADIO_PATH_E eRFPath;
2709 RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
2710 // RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
2712 #ifdef ENABLE_DOT11D
2713 if (!IsLegalChannel(priv->ieee80211, channel))
2715 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
2716 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
2720 //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
2721 //for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
2723 //if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
2725 // <1> Fill up pre common command.
2726 PreCommonCmdCnt = 0;
2727 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2728 CmdID_SetTxPowerLevel, 0, 0, 0);
2729 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2730 CmdID_End, 0, 0, 0);
2732 // <2> Fill up post common command.
2733 PostCommonCmdCnt = 0;
2735 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
2736 CmdID_End, 0, 0, 0);
2738 // <3> Fill up RF dependent command.
2740 switch( priv->rf_chip )
2743 if (!(channel >= 1 && channel <= 14))
2745 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
2748 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2749 CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
2750 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2751 CmdID_End, 0, 0, 0);
2755 // TEST!! This is not the table for 8256!!
2756 if (!(channel >= 1 && channel <= 14))
2758 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
2761 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2762 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
2763 rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2764 CmdID_End, 0, 0, 0);
2771 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
2781 CurrentCmd=&PreCommonCmd[*step];
2784 CurrentCmd=&RfDependCmd[*step];
2787 CurrentCmd=&PostCommonCmd[*step];
2791 if(CurrentCmd->CmdID==CmdID_End)
2805 switch(CurrentCmd->CmdID)
2807 case CmdID_SetTxPowerLevel:
2808 if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later!
2809 rtl8192_SetTxPowerLevel(dev,channel);
2811 case CmdID_WritePortUlong:
2812 write_nic_dword(dev, CurrentCmd->Para1, CurrentCmd->Para2);
2814 case CmdID_WritePortUshort:
2815 write_nic_word(dev, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
2817 case CmdID_WritePortUchar:
2818 write_nic_byte(dev, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
2820 case CmdID_RF_WriteReg:
2821 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
2822 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
2830 }/*for(Number of RF paths)*/
2832 (*delay)=CurrentCmd->msDelay;
2837 /******************************************************************************
2838 *function: This function does acturally set channel work
2839 * input: struct net_device *dev
2843 * Note: We should not call this function directly
2844 * ***************************************************************************/
2845 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
2847 struct r8192_priv *priv = ieee80211_priv(dev);
2850 while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
2853 msleep(delay);//or mdelay? need further consideration
2858 /******************************************************************************
2859 *function: Callback routine of the work item for switch channel.
2864 * ***************************************************************************/
2865 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
2868 struct r8192_priv *priv = ieee80211_priv(dev);
2870 RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
2872 RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv);
2874 rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
2876 RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
2879 /******************************************************************************
2880 *function: This function scheduled actural workitem to set channel
2881 * input: net_device dev
2882 * u8 channel //channel to set
2884 * return: return code show if workitem is scheduled(1:pass, 0:fail)
2885 * Note: Delay may be required for RF configuration
2886 * ***************************************************************************/
2887 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
2889 struct r8192_priv *priv = ieee80211_priv(dev);
2890 RT_TRACE(COMP_PHY, "=====>%s()\n", __FUNCTION__);
2893 if(priv->SwChnlInProgress)
2896 // if(pHalData->SetBWModeInProgress)
2899 //--------------------------------------------
2900 switch(priv->ieee80211->mode)
2902 case WIRELESS_MODE_A:
2903 case WIRELESS_MODE_N_5G:
2905 RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
2909 case WIRELESS_MODE_B:
2911 RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
2915 case WIRELESS_MODE_G:
2916 case WIRELESS_MODE_N_24G:
2918 RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
2923 //--------------------------------------------
2925 priv->SwChnlInProgress = true;
2931 priv->SwChnlStage=0;
2933 // schedule_work(&(priv->SwChnlWorkItem));
2934 // rtl8192_SwChnl_WorkItem(dev);
2936 // queue_work(priv->priv_wq,&(priv->SwChnlWorkItem));
2937 rtl8192_SwChnl_WorkItem(dev);
2939 priv->SwChnlInProgress = false;
2943 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev )
2945 struct r8192_priv *priv = ieee80211_priv(dev);
2947 switch(priv->CurrentChannelBW)
2950 case HT_CHANNEL_WIDTH_20:
2951 //added by vivi, cck,tx power track, 20080703
2952 priv->CCKPresentAttentuation =
2953 priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
2955 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
2956 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
2957 if(priv->CCKPresentAttentuation < 0)
2958 priv->CCKPresentAttentuation = 0;
2960 RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
2962 if(priv->ieee80211->current_network.channel== 14 && !priv->bcck_in_ch14)
2964 priv->bcck_in_ch14 = TRUE;
2965 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2967 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
2969 priv->bcck_in_ch14 = FALSE;
2970 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2973 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2977 case HT_CHANNEL_WIDTH_20_40:
2978 //added by vivi, cck,tx power track, 20080703
2979 priv->CCKPresentAttentuation =
2980 priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
2982 RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
2983 if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
2984 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
2985 if(priv->CCKPresentAttentuation < 0)
2986 priv->CCKPresentAttentuation = 0;
2988 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
2990 priv->bcck_in_ch14 = TRUE;
2991 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2993 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
2995 priv->bcck_in_ch14 = FALSE;
2996 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2999 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
3005 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
3007 struct r8192_priv *priv = ieee80211_priv(dev);
3009 if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
3010 priv->bcck_in_ch14 = TRUE;
3011 else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
3012 priv->bcck_in_ch14 = FALSE;
3014 //write to default index and tx power track will be done in dm.
3015 switch(priv->CurrentChannelBW)
3018 case HT_CHANNEL_WIDTH_20:
3019 if(priv->Record_CCK_20Mindex == 0)
3020 priv->Record_CCK_20Mindex = 6; //set default value.
3021 priv->CCK_index = priv->Record_CCK_20Mindex;//6;
3022 RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index);
3026 case HT_CHANNEL_WIDTH_20_40:
3027 priv->CCK_index = priv->Record_CCK_40Mindex;//0;
3028 RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index);
3031 dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
3035 static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
3038 struct r8192_priv *priv = ieee80211_priv(dev);
3042 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
3044 //if(pHalData->bDcut == TRUE)
3045 if(priv->IC_Cut >= IC_VersionCut_D)
3046 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
3048 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
3054 /******************************************************************************
3055 *function: Callback routine of the work item for set bandwidth mode.
3056 * input: struct net_device *dev
3057 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
3058 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
3061 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
3062 * test whether current work in the queue or not.//do I?
3063 * ***************************************************************************/
3064 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
3067 struct r8192_priv *priv = ieee80211_priv(dev);
3070 RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem() Switch to %s bandwidth\n",
3071 priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
3074 if(priv->rf_chip== RF_PSEUDO_11N)
3076 priv->SetBWModeInProgress= false;
3081 priv->SetBWModeInProgress= false;
3084 //<1>Set MAC register
3085 regBwOpMode = read_nic_byte(dev, BW_OPMODE);
3087 switch(priv->CurrentChannelBW)
3089 case HT_CHANNEL_WIDTH_20:
3090 regBwOpMode |= BW_OPMODE_20MHZ;
3091 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3092 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3095 case HT_CHANNEL_WIDTH_20_40:
3096 regBwOpMode &= ~BW_OPMODE_20MHZ;
3097 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3098 write_nic_byte(dev, BW_OPMODE, regBwOpMode);
3102 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3106 //<2>Set PHY related register
3107 switch(priv->CurrentChannelBW)
3109 case HT_CHANNEL_WIDTH_20:
3110 // Add by Vivi 20071119
3111 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3112 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3113 // rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
3115 // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
3116 // write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3117 // write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3118 // write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3119 if(!priv->btxpower_tracking)
3121 write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3122 write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3123 write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3126 CCK_Tx_Power_Track_BW_Switch(dev);
3129 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
3130 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x44); // 0xc30 is for 8190 only, Emily
3133 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
3138 case HT_CHANNEL_WIDTH_20_40:
3139 // Add by Vivi 20071119
3140 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3141 rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3142 //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3143 //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
3144 //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3146 // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3147 //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
3148 //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
3149 //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3150 if(!priv->btxpower_tracking)
3152 write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
3153 write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
3154 write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3157 CCK_Tx_Power_Track_BW_Switch(dev);
3159 // Set Control channel to upper or lower. These settings are required only for 40MHz
3160 rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3161 rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3165 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
3166 rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x42); // 0xc30 is for 8190 only, Emily
3168 // Set whether CCK should be sent in upper or lower channel. Suggest by YN. 20071207
3169 // It is set in Tx descriptor for 8192x series
3170 if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
3172 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x01);
3173 }else if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
3175 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x02);
3180 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
3185 RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
3189 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3192 //<3>Set RF related register
3193 switch( priv->rf_chip )
3197 PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
3202 PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3206 // PHY_SetRF8258Bandwidth();
3214 RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
3218 atomic_dec(&(priv->ieee80211->atm_swbw));
3219 priv->SetBWModeInProgress= false;
3221 RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
3224 /******************************************************************************
3225 *function: This function schedules bandwith switch work.
3226 * input: struct net_device *dev
3227 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
3228 * HT_EXTCHNL_OFFSET Offset //Upper, Lower, or Don't care
3231 * Note: I doubt whether SetBWModeInProgress flag is necessary as we can
3232 * test whether current work in the queue or not.//do I?
3233 * ***************************************************************************/
3234 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
3236 struct r8192_priv *priv = ieee80211_priv(dev);
3239 if(priv->SetBWModeInProgress)
3242 atomic_inc(&(priv->ieee80211->atm_swbw));
3243 priv->SetBWModeInProgress= true;
3245 priv->CurrentChannelBW = Bandwidth;
3247 if(Offset==HT_EXTCHNL_OFFSET_LOWER)
3248 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
3249 else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
3250 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
3252 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
3254 //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
3255 // schedule_work(&(priv->SetBWModeWorkItem));
3256 rtl8192_SetBWModeWorkItem(dev);
3261 void InitialGain819xPci(struct net_device *dev, u8 Operation)
3263 #define SCAN_RX_INITIAL_GAIN 0x17
3264 #define POWER_DETECTION_TH 0x08
3265 struct r8192_priv *priv = ieee80211_priv(dev);
3274 RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
3275 initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];//
3276 BitMask = bMaskByte0;
3277 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3278 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3279 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
3280 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3281 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
3282 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
3283 BitMask = bMaskByte2;
3284 priv->initgain_backup.cca = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
3286 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3287 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3288 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3289 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3290 RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
3292 RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
3293 write_nic_byte(dev, rOFDM0_XAAGCCore1, initial_gain);
3294 write_nic_byte(dev, rOFDM0_XBAGCCore1, initial_gain);
3295 write_nic_byte(dev, rOFDM0_XCAGCCore1, initial_gain);
3296 write_nic_byte(dev, rOFDM0_XDAGCCore1, initial_gain);
3297 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
3298 write_nic_byte(dev, 0xa0a, POWER_DETECTION_TH);
3301 RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
3302 BitMask = 0x7f; //Bit0~ Bit6
3303 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3304 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8); // FW DIG OFF
3306 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
3307 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
3308 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
3309 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
3310 BitMask = bMaskByte2;
3311 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
3313 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3314 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3315 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3316 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3317 RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
3319 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
3322 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3323 rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1); // FW DIG ON
3326 RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");