drivers/staging/rtl8192e/r819xE_phy.c

   1 #include "r8192E.h"
   2 #include "r8192E_hw.h"
   3 #include "r819xE_phyreg.h"
   4 #include "r8190_rtl8256.h"
   5 #include "r819xE_phy.h"
   6 #include "r8192E_dm.h"
   7 #ifdef ENABLE_DOT11D
   8 #include "ieee80211/dot11d.h"
   9 #endif
  10 static const u32 RF_CHANNEL_TABLE_ZEBRA[] = {
  11         0,
  12         0x085c, //2412 1
  13         0x08dc, //2417 2
  14         0x095c, //2422 3
  15         0x09dc, //2427 4
  16         0x0a5c, //2432 5
  17         0x0adc, //2437 6
  18         0x0b5c, //2442 7
  19         0x0bdc, //2447 8
  20         0x0c5c, //2452 9
  21         0x0cdc, //2457 10
  22         0x0d5c, //2462 11
  23         0x0ddc, //2467 12
  24         0x0e5c, //2472 13
  25         0x0f72, //2484
  26 };
  27 #ifdef RTL8190P
  28 u32 Rtl8190PciMACPHY_Array[] = {
  29 0x03c,0xffff0000,0x00000f0f,
  30 0x340,0xffffffff,0x161a1a1a,
  31 0x344,0xffffffff,0x12121416,
  32 0x348,0x0000ffff,0x00001818,
  33 0x12c,0xffffffff,0x04000802,
  34 0x318,0x00000fff,0x00000800,
  35 };
  36 u32 Rtl8190PciMACPHY_Array_PG[] = {
  37 0x03c,0xffff0000,0x00000f0f,
  38 0x340,0xffffffff,0x0a0c0d0f,
  39 0x344,0xffffffff,0x06070809,
  40 0x344,0xffffffff,0x06070809,
  41 0x348,0x0000ffff,0x00000000,
  42 0x12c,0xffffffff,0x04000802,
  43 0x318,0x00000fff,0x00000800,
  44 };
  45
  46 u32 Rtl8190PciAGCTAB_Array[AGCTAB_ArrayLength] = {
  47 0xc78,0x7d000001,
  48 0xc78,0x7d010001,
  49 0xc78,0x7d020001,
  50 0xc78,0x7d030001,
  51 0xc78,0x7c040001,
  52 0xc78,0x7b050001,
  53 0xc78,0x7a060001,
  54 0xc78,0x79070001,
  55 0xc78,0x78080001,
  56 0xc78,0x77090001,
  57 0xc78,0x760a0001,
  58 0xc78,0x750b0001,
  59 0xc78,0x740c0001,
  60 0xc78,0x730d0001,
  61 0xc78,0x720e0001,
  62 0xc78,0x710f0001,
  63 0xc78,0x70100001,
  64 0xc78,0x6f110001,
  65 0xc78,0x6e120001,
  66 0xc78,0x6d130001,
  67 0xc78,0x6c140001,
  68 0xc78,0x6b150001,
  69 0xc78,0x6a160001,
  70 0xc78,0x69170001,
  71 0xc78,0x68180001,
  72 0xc78,0x67190001,
  73 0xc78,0x661a0001,
  74 0xc78,0x651b0001,
  75 0xc78,0x641c0001,
  76 0xc78,0x491d0001,
  77 0xc78,0x481e0001,
  78 0xc78,0x471f0001,
  79 0xc78,0x46200001,
  80 0xc78,0x45210001,
  81 0xc78,0x44220001,
  82 0xc78,0x43230001,
  83 0xc78,0x28240001,
  84 0xc78,0x27250001,
  85 0xc78,0x26260001,
  86 0xc78,0x25270001,
  87 0xc78,0x24280001,
  88 0xc78,0x23290001,
  89 0xc78,0x222a0001,
  90 0xc78,0x212b0001,
  91 0xc78,0x202c0001,
  92 0xc78,0x0a2d0001,
  93 0xc78,0x082e0001,
  94 0xc78,0x062f0001,
  95 0xc78,0x05300001,
  96 0xc78,0x04310001,
  97 0xc78,0x03320001,
  98 0xc78,0x02330001,
  99 0xc78,0x01340001,
 100 0xc78,0x00350001,
 101 0xc78,0x00360001,
 102 0xc78,0x00370001,
 103 0xc78,0x00380001,
 104 0xc78,0x00390001,
 105 0xc78,0x003a0001,
 106 0xc78,0x003b0001,
 107 0xc78,0x003c0001,
 108 0xc78,0x003d0001,
 109 0xc78,0x003e0001,
 110 0xc78,0x003f0001,
 111 0xc78,0x7d400001,
 112 0xc78,0x7d410001,
 113 0xc78,0x7d420001,
 114 0xc78,0x7d430001,
 115 0xc78,0x7c440001,
 116 0xc78,0x7b450001,
 117 0xc78,0x7a460001,
 118 0xc78,0x79470001,
 119 0xc78,0x78480001,
 120 0xc78,0x77490001,
 121 0xc78,0x764a0001,
 122 0xc78,0x754b0001,
 123 0xc78,0x744c0001,
 124 0xc78,0x734d0001,
 125 0xc78,0x724e0001,
 126 0xc78,0x714f0001,
 127 0xc78,0x70500001,
 128 0xc78,0x6f510001,
 129 0xc78,0x6e520001,
 130 0xc78,0x6d530001,
 131 0xc78,0x6c540001,
 132 0xc78,0x6b550001,
 133 0xc78,0x6a560001,
 134 0xc78,0x69570001,
 135 0xc78,0x68580001,
 136 0xc78,0x67590001,
 137 0xc78,0x665a0001,
 138 0xc78,0x655b0001,
 139 0xc78,0x645c0001,
 140 0xc78,0x495d0001,
 141 0xc78,0x485e0001,
 142 0xc78,0x475f0001,
 143 0xc78,0x46600001,
 144 0xc78,0x45610001,
 145 0xc78,0x44620001,
 146 0xc78,0x43630001,
 147 0xc78,0x28640001,
 148 0xc78,0x27650001,
 149 0xc78,0x26660001,
 150 0xc78,0x25670001,
 151 0xc78,0x24680001,
 152 0xc78,0x23690001,
 153 0xc78,0x226a0001,
 154 0xc78,0x216b0001,
 155 0xc78,0x206c0001,
 156 0xc78,0x0a6d0001,
 157 0xc78,0x086e0001,
 158 0xc78,0x066f0001,
 159 0xc78,0x05700001,
 160 0xc78,0x04710001,
 161 0xc78,0x03720001,
 162 0xc78,0x02730001,
 163 0xc78,0x01740001,
 164 0xc78,0x00750001,
 165 0xc78,0x00760001,
 166 0xc78,0x00770001,
 167 0xc78,0x00780001,
 168 0xc78,0x00790001,
 169 0xc78,0x007a0001,
 170 0xc78,0x007b0001,
 171 0xc78,0x007c0001,
 172 0xc78,0x007d0001,
 173 0xc78,0x007e0001,
 174 0xc78,0x007f0001,
 175 0xc78,0x3600001e,
 176 0xc78,0x3601001e,
 177 0xc78,0x3602001e,
 178 0xc78,0x3603001e,
 179 0xc78,0x3604001e,
 180 0xc78,0x3605001e,
 181 0xc78,0x3a06001e,
 182 0xc78,0x3c07001e,
 183 0xc78,0x3e08001e,
 184 0xc78,0x4209001e,
 185 0xc78,0x430a001e,
 186 0xc78,0x450b001e,
 187 0xc78,0x470c001e,
 188 0xc78,0x480d001e,
 189 0xc78,0x490e001e,
 190 0xc78,0x4b0f001e,
 191 0xc78,0x4c10001e,
 192 0xc78,0x4d11001e,
 193 0xc78,0x4d12001e,
 194 0xc78,0x4e13001e,
 195 0xc78,0x4f14001e,
 196 0xc78,0x5015001e,
 197 0xc78,0x5116001e,
 198 0xc78,0x5117001e,
 199 0xc78,0x5218001e,
 200 0xc78,0x5219001e,
 201 0xc78,0x531a001e,
 202 0xc78,0x541b001e,
 203 0xc78,0x541c001e,
 204 0xc78,0x551d001e,
 205 0xc78,0x561e001e,
 206 0xc78,0x561f001e,
 207 0xc78,0x5720001e,
 208 0xc78,0x5821001e,
 209 0xc78,0x5822001e,
 210 0xc78,0x5923001e,
 211 0xc78,0x5924001e,
 212 0xc78,0x5a25001e,
 213 0xc78,0x5b26001e,
 214 0xc78,0x5b27001e,
 215 0xc78,0x5c28001e,
 216 0xc78,0x5c29001e,
 217 0xc78,0x5d2a001e,
 218 0xc78,0x5d2b001e,
 219 0xc78,0x5e2c001e,
 220 0xc78,0x5e2d001e,
 221 0xc78,0x5f2e001e,
 222 0xc78,0x602f001e,
 223 0xc78,0x6030001e,
 224 0xc78,0x6131001e,
 225 0xc78,0x6132001e,
 226 0xc78,0x6233001e,
 227 0xc78,0x6234001e,
 228 0xc78,0x6335001e,
 229 0xc78,0x6336001e,
 230 0xc78,0x6437001e,
 231 0xc78,0x6538001e,
 232 0xc78,0x6639001e,
 233 0xc78,0x663a001e,
 234 0xc78,0x673b001e,
 235 0xc78,0x683c001e,
 236 0xc78,0x693d001e,
 237 0xc78,0x6a3e001e,
 238 0xc78,0x6b3f001e,
 239 };
 240
 241 u32 Rtl8190PciPHY_REGArray[PHY_REGArrayLength] = {
 242 0x800,0x00050060,
 243 0x804,0x00000005,
 244 0x808,0x0000fc00,
 245 0x80c,0x0000001c,
 246 0x810,0x801010aa,
 247 0x814,0x000908c0,
 248 0x818,0x00000000,
 249 0x81c,0x00000000,
 250 0x820,0x00000004,
 251 0x824,0x00690000,
 252 0x828,0x00000004,
 253 0x82c,0x00e90000,
 254 0x830,0x00000004,
 255 0x834,0x00690000,
 256 0x838,0x00000004,
 257 0x83c,0x00e90000,
 258 0x840,0x00000000,
 259 0x844,0x00000000,
 260 0x848,0x00000000,
 261 0x84c,0x00000000,
 262 0x850,0x00000000,
 263 0x854,0x00000000,
 264 0x858,0x65a965a9,
 265 0x85c,0x65a965a9,
 266 0x860,0x001f0010,
 267 0x864,0x007f0010,
 268 0x868,0x001f0010,
 269 0x86c,0x007f0010,
 270 0x870,0x0f100f70,
 271 0x874,0x0f100f70,
 272 0x878,0x00000000,
 273 0x87c,0x00000000,
 274 0x880,0x5c385eb8,
 275 0x884,0x6357060d,
 276 0x888,0x0460c341,
 277 0x88c,0x0000ff00,
 278 0x890,0x00000000,
 279 0x894,0xfffffffe,
 280 0x898,0x4c42382f,
 281 0x89c,0x00656056,
 282 0x8b0,0x00000000,
 283 0x8e0,0x00000000,
 284 0x8e4,0x00000000,
 285 0x900,0x00000000,
 286 0x904,0x00000023,
 287 0x908,0x00000000,
 288 0x90c,0x35541545,
 289 0xa00,0x00d0c7d8,
 290 0xa04,0xab1f0008,
 291 0xa08,0x80cd8300,
 292 0xa0c,0x2e62740f,
 293 0xa10,0x95009b78,
 294 0xa14,0x11145008,
 295 0xa18,0x00881117,
 296 0xa1c,0x89140fa0,
 297 0xa20,0x1a1b0000,
 298 0xa24,0x090e1317,
 299 0xa28,0x00000204,
 300 0xa2c,0x00000000,
 301 0xc00,0x00000040,
 302 0xc04,0x0000500f,
 303 0xc08,0x000000e4,
 304 0xc0c,0x6c6c6c6c,
 305 0xc10,0x08000000,
 306 0xc14,0x40000100,
 307 0xc18,0x08000000,
 308 0xc1c,0x40000100,
 309 0xc20,0x08000000,
 310 0xc24,0x40000100,
 311 0xc28,0x08000000,
 312 0xc2c,0x40000100,
 313 0xc30,0x6de9ac44,
 314 0xc34,0x164052cd,
 315 0xc38,0x00070a14,
 316 0xc3c,0x0a969764,
 317 0xc40,0x1f7c403f,
 318 0xc44,0x000100b7,
 319 0xc48,0xec020000,
 320 0xc4c,0x00000300,
 321 0xc50,0x69543420,
 322 0xc54,0x433c0094,
 323 0xc58,0x69543420,
 324 0xc5c,0x433c0094,
 325 0xc60,0x69543420,
 326 0xc64,0x433c0094,
 327 0xc68,0x69543420,
 328 0xc6c,0x433c0094,
 329 0xc70,0x2c7f000d,
 330 0xc74,0x0186175b,
 331 0xc78,0x0000001f,
 332 0xc7c,0x00b91612,
 333 0xc80,0x40000100,
 334 0xc84,0x00000000,
 335 0xc88,0x40000100,
 336 0xc8c,0x08000000,
 337 0xc90,0x40000100,
 338 0xc94,0x00000000,
 339 0xc98,0x40000100,
 340 0xc9c,0x00000000,
 341 0xca0,0x00492492,
 342 0xca4,0x00000000,
 343 0xca8,0x00000000,
 344 0xcac,0x00000000,
 345 0xcb0,0x00000000,
 346 0xcb4,0x00000000,
 347 0xcb8,0x00000000,
 348 0xcbc,0x00492492,
 349 0xcc0,0x00000000,
 350 0xcc4,0x00000000,
 351 0xcc8,0x00000000,
 352 0xccc,0x00000000,
 353 0xcd0,0x00000000,
 354 0xcd4,0x00000000,
 355 0xcd8,0x64b22427,
 356 0xcdc,0x00766932,
 357 0xce0,0x00222222,
 358 0xd00,0x00000740,
 359 0xd04,0x0000040f,
 360 0xd08,0x0000803f,
 361 0xd0c,0x00000001,
 362 0xd10,0xa0633333,
 363 0xd14,0x33333c63,
 364 0xd18,0x6a8f5b6b,
 365 0xd1c,0x00000000,
 366 0xd20,0x00000000,
 367 0xd24,0x00000000,
 368 0xd28,0x00000000,
 369 0xd2c,0xcc979975,
 370 0xd30,0x00000000,
 371 0xd34,0x00000000,
 372 0xd38,0x00000000,
 373 0xd3c,0x00027293,
 374 0xd40,0x00000000,
 375 0xd44,0x00000000,
 376 0xd48,0x00000000,
 377 0xd4c,0x00000000,
 378 0xd50,0x6437140a,
 379 0xd54,0x024dbd02,
 380 0xd58,0x00000000,
 381 0xd5c,0x14032064,
 382 };
 383 u32 Rtl8190PciPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
 384 0x800,0x00050060,
 385 0x804,0x00000004,
 386 0x808,0x0000fc00,
 387 0x80c,0x0000001c,
 388 0x810,0x801010aa,
 389 0x814,0x000908c0,
 390 0x818,0x00000000,
 391 0x81c,0x00000000,
 392 0x820,0x00000004,
 393 0x824,0x00690000,
 394 0x828,0x00000004,
 395 0x82c,0x00e90000,
 396 0x830,0x00000004,
 397 0x834,0x00690000,
 398 0x838,0x00000004,
 399 0x83c,0x00e90000,
 400 0x840,0x00000000,
 401 0x844,0x00000000,
 402 0x848,0x00000000,
 403 0x84c,0x00000000,
 404 0x850,0x00000000,
 405 0x854,0x00000000,
 406 0x858,0x65a965a9,
 407 0x85c,0x65a965a9,
 408 0x860,0x001f0000,
 409 0x864,0x007f0000,
 410 0x868,0x001f0010,
 411 0x86c,0x007f0010,
 412 0x870,0x0f100f70,
 413 0x874,0x0f100f70,
 414 0x878,0x00000000,
 415 0x87c,0x00000000,
 416 0x880,0x5c385898,
 417 0x884,0x6357060d,
 418 0x888,0x0460c341,
 419 0x88c,0x0000fc00,
 420 0x890,0x00000000,
 421 0x894,0xfffffffe,
 422 0x898,0x4c42382f,
 423 0x89c,0x00656056,
 424 0x8b0,0x00000000,
 425 0x8e0,0x00000000,
 426 0x8e4,0x00000000,
 427 0x900,0x00000000,
 428 0x904,0x00000023,
 429 0x908,0x00000000,
 430 0x90c,0x34441444,
 431 0xa00,0x00d0c7d8,
 432 0xa04,0x2b1f0008,
 433 0xa08,0x80cd8300,
 434 0xa0c,0x2e62740f,
 435 0xa10,0x95009b78,
 436 0xa14,0x11145008,
 437 0xa18,0x00881117,
 438 0xa1c,0x89140fa0,
 439 0xa20,0x1a1b0000,
 440 0xa24,0x090e1317,
 441 0xa28,0x00000204,
 442 0xa2c,0x00000000,
 443 0xc00,0x00000040,
 444 0xc04,0x0000500c,
 445 0xc08,0x000000e4,
 446 0xc0c,0x6c6c6c6c,
 447 0xc10,0x08000000,
 448 0xc14,0x40000100,
 449 0xc18,0x08000000,
 450 0xc1c,0x40000100,
 451 0xc20,0x08000000,
 452 0xc24,0x40000100,
 453 0xc28,0x08000000,
 454 0xc2c,0x40000100,
 455 0xc30,0x6de9ac44,
 456 0xc34,0x164052cd,
 457 0xc38,0x00070a14,
 458 0xc3c,0x0a969764,
 459 0xc40,0x1f7c403f,
 460 0xc44,0x000100b7,
 461 0xc48,0xec020000,
 462 0xc4c,0x00000300,
 463 0xc50,0x69543420,
 464 0xc54,0x433c0094,
 465 0xc58,0x69543420,
 466 0xc5c,0x433c0094,
 467 0xc60,0x69543420,
 468 0xc64,0x433c0094,
 469 0xc68,0x69543420,
 470 0xc6c,0x433c0094,
 471 0xc70,0x2c7f000d,
 472 0xc74,0x0186175b,
 473 0xc78,0x0000001f,
 474 0xc7c,0x00b91612,
 475 0xc80,0x40000100,
 476 0xc84,0x00000000,
 477 0xc88,0x40000100,
 478 0xc8c,0x08000000,
 479 0xc90,0x40000100,
 480 0xc94,0x00000000,
 481 0xc98,0x40000100,
 482 0xc9c,0x00000000,
 483 0xca0,0x00492492,
 484 0xca4,0x00000000,
 485 0xca8,0x00000000,
 486 0xcac,0x00000000,
 487 0xcb0,0x00000000,
 488 0xcb4,0x00000000,
 489 0xcb8,0x00000000,
 490 0xcbc,0x00492492,
 491 0xcc0,0x00000000,
 492 0xcc4,0x00000000,
 493 0xcc8,0x00000000,
 494 0xccc,0x00000000,
 495 0xcd0,0x00000000,
 496 0xcd4,0x00000000,
 497 0xcd8,0x64b22427,
 498 0xcdc,0x00766932,
 499 0xce0,0x00222222,
 500 0xd00,0x00000740,
 501 0xd04,0x0000040c,
 502 0xd08,0x0000803f,
 503 0xd0c,0x00000001,
 504 0xd10,0xa0633333,
 505 0xd14,0x33333c63,
 506 0xd18,0x6a8f5b6b,
 507 0xd1c,0x00000000,
 508 0xd20,0x00000000,
 509 0xd24,0x00000000,
 510 0xd28,0x00000000,
 511 0xd2c,0xcc979975,
 512 0xd30,0x00000000,
 513 0xd34,0x00000000,
 514 0xd38,0x00000000,
 515 0xd3c,0x00027293,
 516 0xd40,0x00000000,
 517 0xd44,0x00000000,
 518 0xd48,0x00000000,
 519 0xd4c,0x00000000,
 520 0xd50,0x6437140a,
 521 0xd54,0x024dbd02,
 522 0xd58,0x00000000,
 523 0xd5c,0x14032064,
 524 };
 525
 526 u32 Rtl8190PciRadioA_Array[RadioA_ArrayLength] = {
 527 0x019,0x00000003,
 528 0x000,0x000000bf,
 529 0x001,0x00000ee0,
 530 0x002,0x0000004c,
 531 0x003,0x000007f1,
 532 0x004,0x00000975,
 533 0x005,0x00000c58,
 534 0x006,0x00000ae6,
 535 0x007,0x000000ca,
 536 0x008,0x00000e1c,
 537 0x009,0x000007f0,
 538 0x00a,0x000009d0,
 539 0x00b,0x000001ba,
 540 0x00c,0x00000240,
 541 0x00e,0x00000020,
 542 0x00f,0x00000990,
 543 0x012,0x00000806,
 544 0x014,0x000005ab,
 545 0x015,0x00000f80,
 546 0x016,0x00000020,
 547 0x017,0x00000597,
 548 0x018,0x0000050a,
 549 0x01a,0x00000f80,
 550 0x01b,0x00000f5e,
 551 0x01c,0x00000008,
 552 0x01d,0x00000607,
 553 0x01e,0x000006cc,
 554 0x01f,0x00000000,
 555 0x020,0x000001a5,
 556 0x01f,0x00000001,
 557 0x020,0x00000165,
 558 0x01f,0x00000002,
 559 0x020,0x000000c6,
 560 0x01f,0x00000003,
 561 0x020,0x00000086,
 562 0x01f,0x00000004,
 563 0x020,0x00000046,
 564 0x01f,0x00000005,
 565 0x020,0x000001e6,
 566 0x01f,0x00000006,
 567 0x020,0x000001a6,
 568 0x01f,0x00000007,
 569 0x020,0x00000166,
 570 0x01f,0x00000008,
 571 0x020,0x000000c7,
 572 0x01f,0x00000009,
 573 0x020,0x00000087,
 574 0x01f,0x0000000a,
 575 0x020,0x000000f7,
 576 0x01f,0x0000000b,
 577 0x020,0x000000d7,
 578 0x01f,0x0000000c,
 579 0x020,0x000000b7,
 580 0x01f,0x0000000d,
 581 0x020,0x00000097,
 582 0x01f,0x0000000e,
 583 0x020,0x00000077,
 584 0x01f,0x0000000f,
 585 0x020,0x00000057,
 586 0x01f,0x00000010,
 587 0x020,0x00000037,
 588 0x01f,0x00000011,
 589 0x020,0x000000fb,
 590 0x01f,0x00000012,
 591 0x020,0x000000db,
 592 0x01f,0x00000013,
 593 0x020,0x000000bb,
 594 0x01f,0x00000014,
 595 0x020,0x000000ff,
 596 0x01f,0x00000015,
 597 0x020,0x000000e3,
 598 0x01f,0x00000016,
 599 0x020,0x000000c3,
 600 0x01f,0x00000017,
 601 0x020,0x000000a3,
 602 0x01f,0x00000018,
 603 0x020,0x00000083,
 604 0x01f,0x00000019,
 605 0x020,0x00000063,
 606 0x01f,0x0000001a,
 607 0x020,0x00000043,
 608 0x01f,0x0000001b,
 609 0x020,0x00000023,
 610 0x01f,0x0000001c,
 611 0x020,0x00000003,
 612 0x01f,0x0000001d,
 613 0x020,0x000001e3,
 614 0x01f,0x0000001e,
 615 0x020,0x000001c3,
 616 0x01f,0x0000001f,
 617 0x020,0x000001a3,
 618 0x01f,0x00000020,
 619 0x020,0x00000183,
 620 0x01f,0x00000021,
 621 0x020,0x00000163,
 622 0x01f,0x00000022,
 623 0x020,0x00000143,
 624 0x01f,0x00000023,
 625 0x020,0x00000123,
 626 0x01f,0x00000024,
 627 0x020,0x00000103,
 628 0x023,0x00000203,
 629 0x024,0x00000200,
 630 0x00b,0x000001ba,
 631 0x02c,0x000003d7,
 632 0x02d,0x00000ff0,
 633 0x000,0x00000037,
 634 0x004,0x00000160,
 635 0x007,0x00000080,
 636 0x002,0x0000088d,
 637 0x0fe,0x00000000,
 638 0x0fe,0x00000000,
 639 0x016,0x00000200,
 640 0x016,0x00000380,
 641 0x016,0x00000020,
 642 0x016,0x000001a0,
 643 0x000,0x000000bf,
 644 0x00d,0x0000001f,
 645 0x00d,0x00000c9f,
 646 0x002,0x0000004d,
 647 0x000,0x00000cbf,
 648 0x004,0x00000975,
 649 0x007,0x00000700,
 650 };
 651 u32 Rtl8190PciRadioB_Array[RadioB_ArrayLength] = {
 652 0x019,0x00000003,
 653 0x000,0x000000bf,
 654 0x001,0x000006e0,
 655 0x002,0x0000004c,
 656 0x003,0x000007f1,
 657 0x004,0x00000975,
 658 0x005,0x00000c58,
 659 0x006,0x00000ae6,
 660 0x007,0x000000ca,
 661 0x008,0x00000e1c,
 662 0x000,0x000000b7,
 663 0x00a,0x00000850,
 664 0x000,0x000000bf,
 665 0x00b,0x000001ba,
 666 0x00c,0x00000240,
 667 0x00e,0x00000020,
 668 0x015,0x00000f80,
 669 0x016,0x00000020,
 670 0x017,0x00000597,
 671 0x018,0x0000050a,
 672 0x01a,0x00000e00,
 673 0x01b,0x00000f5e,
 674 0x01d,0x00000607,
 675 0x01e,0x000006cc,
 676 0x00b,0x000001ba,
 677 0x023,0x00000203,
 678 0x024,0x00000200,
 679 0x000,0x00000037,
 680 0x004,0x00000160,
 681 0x016,0x00000200,
 682 0x016,0x00000380,
 683 0x016,0x00000020,
 684 0x016,0x000001a0,
 685 0x00d,0x00000ccc,
 686 0x000,0x000000bf,
 687 0x002,0x0000004d,
 688 0x000,0x00000cbf,
 689 0x004,0x00000975,
 690 0x007,0x00000700,
 691 };
 692 u32 Rtl8190PciRadioC_Array[RadioC_ArrayLength] = {
 693 0x019,0x00000003,
 694 0x000,0x000000bf,
 695 0x001,0x00000ee0,
 696 0x002,0x0000004c,
 697 0x003,0x000007f1,
 698 0x004,0x00000975,
 699 0x005,0x00000c58,
 700 0x006,0x00000ae6,
 701 0x007,0x000000ca,
 702 0x008,0x00000e1c,
 703 0x009,0x000007f0,
 704 0x00a,0x000009d0,
 705 0x00b,0x000001ba,
 706 0x00c,0x00000240,
 707 0x00e,0x00000020,
 708 0x00f,0x00000990,
 709 0x012,0x00000806,
 710 0x014,0x000005ab,
 711 0x015,0x00000f80,
 712 0x016,0x00000020,
 713 0x017,0x00000597,
 714 0x018,0x0000050a,
 715 0x01a,0x00000f80,
 716 0x01b,0x00000f5e,
 717 0x01c,0x00000008,
 718 0x01d,0x00000607,
 719 0x01e,0x000006cc,
 720 0x01f,0x00000000,
 721 0x020,0x000001a5,
 722 0x01f,0x00000001,
 723 0x020,0x00000165,
 724 0x01f,0x00000002,
 725 0x020,0x000000c6,
 726 0x01f,0x00000003,
 727 0x020,0x00000086,
 728 0x01f,0x00000004,
 729 0x020,0x00000046,
 730 0x01f,0x00000005,
 731 0x020,0x000001e6,
 732 0x01f,0x00000006,
 733 0x020,0x000001a6,
 734 0x01f,0x00000007,
 735 0x020,0x00000166,
 736 0x01f,0x00000008,
 737 0x020,0x000000c7,
 738 0x01f,0x00000009,
 739 0x020,0x00000087,
 740 0x01f,0x0000000a,
 741 0x020,0x000000f7,
 742 0x01f,0x0000000b,
 743 0x020,0x000000d7,
 744 0x01f,0x0000000c,
 745 0x020,0x000000b7,
 746 0x01f,0x0000000d,
 747 0x020,0x00000097,
 748 0x01f,0x0000000e,
 749 0x020,0x00000077,
 750 0x01f,0x0000000f,
 751 0x020,0x00000057,
 752 0x01f,0x00000010,
 753 0x020,0x00000037,
 754 0x01f,0x00000011,
 755 0x020,0x000000fb,
 756 0x01f,0x00000012,
 757 0x020,0x000000db,
 758 0x01f,0x00000013,
 759 0x020,0x000000bb,
 760 0x01f,0x00000014,
 761 0x020,0x000000ff,
 762 0x01f,0x00000015,
 763 0x020,0x000000e3,
 764 0x01f,0x00000016,
 765 0x020,0x000000c3,
 766 0x01f,0x00000017,
 767 0x020,0x000000a3,
 768 0x01f,0x00000018,
 769 0x020,0x00000083,
 770 0x01f,0x00000019,
 771 0x020,0x00000063,
 772 0x01f,0x0000001a,
 773 0x020,0x00000043,
 774 0x01f,0x0000001b,
 775 0x020,0x00000023,
 776 0x01f,0x0000001c,
 777 0x020,0x00000003,
 778 0x01f,0x0000001d,
 779 0x020,0x000001e3,
 780 0x01f,0x0000001e,
 781 0x020,0x000001c3,
 782 0x01f,0x0000001f,
 783 0x020,0x000001a3,
 784 0x01f,0x00000020,
 785 0x020,0x00000183,
 786 0x01f,0x00000021,
 787 0x020,0x00000163,
 788 0x01f,0x00000022,
 789 0x020,0x00000143,
 790 0x01f,0x00000023,
 791 0x020,0x00000123,
 792 0x01f,0x00000024,
 793 0x020,0x00000103,
 794 0x023,0x00000203,
 795 0x024,0x00000200,
 796 0x00b,0x000001ba,
 797 0x02c,0x000003d7,
 798 0x02d,0x00000ff0,
 799 0x000,0x00000037,
 800 0x004,0x00000160,
 801 0x007,0x00000080,
 802 0x002,0x0000088d,
 803 0x0fe,0x00000000,
 804 0x0fe,0x00000000,
 805 0x016,0x00000200,
 806 0x016,0x00000380,
 807 0x016,0x00000020,
 808 0x016,0x000001a0,
 809 0x000,0x000000bf,
 810 0x00d,0x0000001f,
 811 0x00d,0x00000c9f,
 812 0x002,0x0000004d,
 813 0x000,0x00000cbf,
 814 0x004,0x00000975,
 815 0x007,0x00000700,
 816 };
 817 u32 Rtl8190PciRadioD_Array[RadioD_ArrayLength] = {
 818 0x019,0x00000003,
 819 0x000,0x000000bf,
 820 0x001,0x000006e0,
 821 0x002,0x0000004c,
 822 0x003,0x000007f1,
 823 0x004,0x00000975,
 824 0x005,0x00000c58,
 825 0x006,0x00000ae6,
 826 0x007,0x000000ca,
 827 0x008,0x00000e1c,
 828 0x000,0x000000b7,
 829 0x00a,0x00000850,
 830 0x000,0x000000bf,
 831 0x00b,0x000001ba,
 832 0x00c,0x00000240,
 833 0x00e,0x00000020,
 834 0x015,0x00000f80,
 835 0x016,0x00000020,
 836 0x017,0x00000597,
 837 0x018,0x0000050a,
 838 0x01a,0x00000e00,
 839 0x01b,0x00000f5e,
 840 0x01d,0x00000607,
 841 0x01e,0x000006cc,
 842 0x00b,0x000001ba,
 843 0x023,0x00000203,
 844 0x024,0x00000200,
 845 0x000,0x00000037,
 846 0x004,0x00000160,
 847 0x016,0x00000200,
 848 0x016,0x00000380,
 849 0x016,0x00000020,
 850 0x016,0x000001a0,
 851 0x00d,0x00000ccc,
 852 0x000,0x000000bf,
 853 0x002,0x0000004d,
 854 0x000,0x00000cbf,
 855 0x004,0x00000975,
 856 0x007,0x00000700,
 857 };
 858 #endif
 859 #ifdef RTL8192E
 860 static u32 Rtl8192PciEMACPHY_Array[] = {
 861 0x03c,0xffff0000,0x00000f0f,
 862 0x340,0xffffffff,0x161a1a1a,
 863 0x344,0xffffffff,0x12121416,
 864 0x348,0x0000ffff,0x00001818,
 865 0x12c,0xffffffff,0x04000802,
 866 0x318,0x00000fff,0x00000100,
 867 };
 868 static u32 Rtl8192PciEMACPHY_Array_PG[] = {
 869 0x03c,0xffff0000,0x00000f0f,
 870 0xe00,0xffffffff,0x06090909,
 871 0xe04,0xffffffff,0x00030306,
 872 0xe08,0x0000ff00,0x00000000,
 873 0xe10,0xffffffff,0x0a0c0d0f,
 874 0xe14,0xffffffff,0x06070809,
 875 0xe18,0xffffffff,0x0a0c0d0f,
 876 0xe1c,0xffffffff,0x06070809,
 877 0x12c,0xffffffff,0x04000802,
 878 0x318,0x00000fff,0x00000800,
 879 };
 880 static u32 Rtl8192PciEAGCTAB_Array[AGCTAB_ArrayLength] = {
 881 0xc78,0x7d000001,
 882 0xc78,0x7d010001,
 883 0xc78,0x7d020001,
 884 0xc78,0x7d030001,
 885 0xc78,0x7d040001,
 886 0xc78,0x7d050001,
 887 0xc78,0x7c060001,
 888 0xc78,0x7b070001,
 889 0xc78,0x7a080001,
 890 0xc78,0x79090001,
 891 0xc78,0x780a0001,
 892 0xc78,0x770b0001,
 893 0xc78,0x760c0001,
 894 0xc78,0x750d0001,
 895 0xc78,0x740e0001,
 896 0xc78,0x730f0001,
 897 0xc78,0x72100001,
 898 0xc78,0x71110001,
 899 0xc78,0x70120001,
 900 0xc78,0x6f130001,
 901 0xc78,0x6e140001,
 902 0xc78,0x6d150001,
 903 0xc78,0x6c160001,
 904 0xc78,0x6b170001,
 905 0xc78,0x6a180001,
 906 0xc78,0x69190001,
 907 0xc78,0x681a0001,
 908 0xc78,0x671b0001,
 909 0xc78,0x661c0001,
 910 0xc78,0x651d0001,
 911 0xc78,0x641e0001,
 912 0xc78,0x491f0001,
 913 0xc78,0x48200001,
 914 0xc78,0x47210001,
 915 0xc78,0x46220001,
 916 0xc78,0x45230001,
 917 0xc78,0x44240001,
 918 0xc78,0x43250001,
 919 0xc78,0x28260001,
 920 0xc78,0x27270001,
 921 0xc78,0x26280001,
 922 0xc78,0x25290001,
 923 0xc78,0x242a0001,
 924 0xc78,0x232b0001,
 925 0xc78,0x222c0001,
 926 0xc78,0x212d0001,
 927 0xc78,0x202e0001,
 928 0xc78,0x0a2f0001,
 929 0xc78,0x08300001,
 930 0xc78,0x06310001,
 931 0xc78,0x05320001,
 932 0xc78,0x04330001,
 933 0xc78,0x03340001,
 934 0xc78,0x02350001,
 935 0xc78,0x01360001,
 936 0xc78,0x00370001,
 937 0xc78,0x00380001,
 938 0xc78,0x00390001,
 939 0xc78,0x003a0001,
 940 0xc78,0x003b0001,
 941 0xc78,0x003c0001,
 942 0xc78,0x003d0001,
 943 0xc78,0x003e0001,
 944 0xc78,0x003f0001,
 945 0xc78,0x7d400001,
 946 0xc78,0x7d410001,
 947 0xc78,0x7d420001,
 948 0xc78,0x7d430001,
 949 0xc78,0x7d440001,
 950 0xc78,0x7d450001,
 951 0xc78,0x7c460001,
 952 0xc78,0x7b470001,
 953 0xc78,0x7a480001,
 954 0xc78,0x79490001,
 955 0xc78,0x784a0001,
 956 0xc78,0x774b0001,
 957 0xc78,0x764c0001,
 958 0xc78,0x754d0001,
 959 0xc78,0x744e0001,
 960 0xc78,0x734f0001,
 961 0xc78,0x72500001,
 962 0xc78,0x71510001,
 963 0xc78,0x70520001,
 964 0xc78,0x6f530001,
 965 0xc78,0x6e540001,
 966 0xc78,0x6d550001,
 967 0xc78,0x6c560001,
 968 0xc78,0x6b570001,
 969 0xc78,0x6a580001,
 970 0xc78,0x69590001,
 971 0xc78,0x685a0001,
 972 0xc78,0x675b0001,
 973 0xc78,0x665c0001,
 974 0xc78,0x655d0001,
 975 0xc78,0x645e0001,
 976 0xc78,0x495f0001,
 977 0xc78,0x48600001,
 978 0xc78,0x47610001,
 979 0xc78,0x46620001,
 980 0xc78,0x45630001,
 981 0xc78,0x44640001,
 982 0xc78,0x43650001,
 983 0xc78,0x28660001,
 984 0xc78,0x27670001,
 985 0xc78,0x26680001,
 986 0xc78,0x25690001,
 987 0xc78,0x246a0001,
 988 0xc78,0x236b0001,
 989 0xc78,0x226c0001,
 990 0xc78,0x216d0001,
 991 0xc78,0x206e0001,
 992 0xc78,0x0a6f0001,
 993 0xc78,0x08700001,
 994 0xc78,0x06710001,
 995 0xc78,0x05720001,
 996 0xc78,0x04730001,
 997 0xc78,0x03740001,
 998 0xc78,0x02750001,
 999 0xc78,0x01760001,
1000 0xc78,0x00770001,
1001 0xc78,0x00780001,
1002 0xc78,0x00790001,
1003 0xc78,0x007a0001,
1004 0xc78,0x007b0001,
1005 0xc78,0x007c0001,
1006 0xc78,0x007d0001,
1007 0xc78,0x007e0001,
1008 0xc78,0x007f0001,
1009 0xc78,0x2e00001e,
1010 0xc78,0x2e01001e,
1011 0xc78,0x2e02001e,
1012 0xc78,0x2e03001e,
1013 0xc78,0x2e04001e,
1014 0xc78,0x2e05001e,
1015 0xc78,0x3006001e,
1016 0xc78,0x3407001e,
1017 0xc78,0x3908001e,
1018 0xc78,0x3c09001e,
1019 0xc78,0x3f0a001e,
1020 0xc78,0x420b001e,
1021 0xc78,0x440c001e,
1022 0xc78,0x450d001e,
1023 0xc78,0x460e001e,
1024 0xc78,0x460f001e,
1025 0xc78,0x4710001e,
1026 0xc78,0x4811001e,
1027 0xc78,0x4912001e,
1028 0xc78,0x4a13001e,
1029 0xc78,0x4b14001e,
1030 0xc78,0x4b15001e,
1031 0xc78,0x4c16001e,
1032 0xc78,0x4d17001e,
1033 0xc78,0x4e18001e,
1034 0xc78,0x4f19001e,
1035 0xc78,0x4f1a001e,
1036 0xc78,0x501b001e,
1037 0xc78,0x511c001e,
1038 0xc78,0x521d001e,
1039 0xc78,0x521e001e,
1040 0xc78,0x531f001e,
1041 0xc78,0x5320001e,
1042 0xc78,0x5421001e,
1043 0xc78,0x5522001e,
1044 0xc78,0x5523001e,
1045 0xc78,0x5624001e,
1046 0xc78,0x5725001e,
1047 0xc78,0x5726001e,
1048 0xc78,0x5827001e,
1049 0xc78,0x5828001e,
1050 0xc78,0x5929001e,
1051 0xc78,0x592a001e,
1052 0xc78,0x5a2b001e,
1053 0xc78,0x5b2c001e,
1054 0xc78,0x5c2d001e,
1055 0xc78,0x5c2e001e,
1056 0xc78,0x5d2f001e,
1057 0xc78,0x5e30001e,
1058 0xc78,0x5f31001e,
1059 0xc78,0x6032001e,
1060 0xc78,0x6033001e,
1061 0xc78,0x6134001e,
1062 0xc78,0x6235001e,
1063 0xc78,0x6336001e,
1064 0xc78,0x6437001e,
1065 0xc78,0x6438001e,
1066 0xc78,0x6539001e,
1067 0xc78,0x663a001e,
1068 0xc78,0x673b001e,
1069 0xc78,0x673c001e,
1070 0xc78,0x683d001e,
1071 0xc78,0x693e001e,
1072 0xc78,0x6a3f001e,
1073 };
1074 static u32 Rtl8192PciEPHY_REGArray[PHY_REGArrayLength] = {
1075 0x0, };
1076 static u32 Rtl8192PciEPHY_REG_1T2RArray[PHY_REG_1T2RArrayLength] = {
1077 0x800,0x00000000,
1078 0x804,0x00000001,
1079 0x808,0x0000fc00,
1080 0x80c,0x0000001c,
1081 0x810,0x801010aa,
1082 0x814,0x008514d0,
1083 0x818,0x00000040,
1084 0x81c,0x00000000,
1085 0x820,0x00000004,
1086 0x824,0x00690000,
1087 0x828,0x00000004,
1088 0x82c,0x00e90000,
1089 0x830,0x00000004,
1090 0x834,0x00690000,
1091 0x838,0x00000004,
1092 0x83c,0x00e90000,
1093 0x840,0x00000000,
1094 0x844,0x00000000,
1095 0x848,0x00000000,
1096 0x84c,0x00000000,
1097 0x850,0x00000000,
1098 0x854,0x00000000,
1099 0x858,0x65a965a9,
1100 0x85c,0x65a965a9,
1101 0x860,0x001f0010,
1102 0x864,0x007f0010,
1103 0x868,0x001f0010,
1104 0x86c,0x007f0010,
1105 0x870,0x0f100f70,
1106 0x874,0x0f100f70,
1107 0x878,0x00000000,
1108 0x87c,0x00000000,
1109 0x880,0x6870e36c,
1110 0x884,0xe3573600,
1111 0x888,0x4260c340,
1112 0x88c,0x0000ff00,
1113 0x890,0x00000000,
1114 0x894,0xfffffffe,
1115 0x898,0x4c42382f,
1116 0x89c,0x00656056,
1117 0x8b0,0x00000000,
1118 0x8e0,0x00000000,
1119 0x8e4,0x00000000,
1120 0x900,0x00000000,
1121 0x904,0x00000023,
1122 0x908,0x00000000,
1123 0x90c,0x31121311,
1124 0xa00,0x00d0c7d8,
1125 0xa04,0x811f0008,
1126 0xa08,0x80cd8300,
1127 0xa0c,0x2e62740f,
1128 0xa10,0x95009b78,
1129 0xa14,0x11145008,
1130 0xa18,0x00881117,
1131 0xa1c,0x89140fa0,
1132 0xa20,0x1a1b0000,
1133 0xa24,0x090e1317,
1134 0xa28,0x00000204,
1135 0xa2c,0x00000000,
1136 0xc00,0x00000040,
1137 0xc04,0x00005433,
1138 0xc08,0x000000e4,
1139 0xc0c,0x6c6c6c6c,
1140 0xc10,0x08800000,
1141 0xc14,0x40000100,
1142 0xc18,0x08000000,
1143 0xc1c,0x40000100,
1144 0xc20,0x08000000,
1145 0xc24,0x40000100,
1146 0xc28,0x08000000,
1147 0xc2c,0x40000100,
1148 0xc30,0x6de9ac44,
1149 0xc34,0x465c52cd,
1150 0xc38,0x497f5994,
1151 0xc3c,0x0a969764,
1152 0xc40,0x1f7c403f,
1153 0xc44,0x000100b7,
1154 0xc48,0xec020000,
1155 0xc4c,0x00000300,
1156 0xc50,0x69543420,
1157 0xc54,0x433c0094,
1158 0xc58,0x69543420,
1159 0xc5c,0x433c0094,
1160 0xc60,0x69543420,
1161 0xc64,0x433c0094,
1162 0xc68,0x69543420,
1163 0xc6c,0x433c0094,
1164 0xc70,0x2c7f000d,
1165 0xc74,0x0186175b,
1166 0xc78,0x0000001f,
1167 0xc7c,0x00b91612,
1168 0xc80,0x40000100,
1169 0xc84,0x20000000,
1170 0xc88,0x40000100,
1171 0xc8c,0x20200000,
1172 0xc90,0x40000100,
1173 0xc94,0x00000000,
1174 0xc98,0x40000100,
1175 0xc9c,0x00000000,
1176 0xca0,0x00492492,
1177 0xca4,0x00000000,
1178 0xca8,0x00000000,
1179 0xcac,0x00000000,
1180 0xcb0,0x00000000,
1181 0xcb4,0x00000000,
1182 0xcb8,0x00000000,
1183 0xcbc,0x00492492,
1184 0xcc0,0x00000000,
1185 0xcc4,0x00000000,
1186 0xcc8,0x00000000,
1187 0xccc,0x00000000,
1188 0xcd0,0x00000000,
1189 0xcd4,0x00000000,
1190 0xcd8,0x64b22427,
1191 0xcdc,0x00766932,
1192 0xce0,0x00222222,
1193 0xd00,0x00000750,
1194 0xd04,0x00000403,
1195 0xd08,0x0000907f,
1196 0xd0c,0x00000001,
1197 0xd10,0xa0633333,
1198 0xd14,0x33333c63,
1199 0xd18,0x6a8f5b6b,
1200 0xd1c,0x00000000,
1201 0xd20,0x00000000,
1202 0xd24,0x00000000,
1203 0xd28,0x00000000,
1204 0xd2c,0xcc979975,
1205 0xd30,0x00000000,
1206 0xd34,0x00000000,
1207 0xd38,0x00000000,
1208 0xd3c,0x00027293,
1209 0xd40,0x00000000,
1210 0xd44,0x00000000,
1211 0xd48,0x00000000,
1212 0xd4c,0x00000000,
1213 0xd50,0x6437140a,
1214 0xd54,0x024dbd02,
1215 0xd58,0x00000000,
1216 0xd5c,0x04032064,
1217 0xe00,0x161a1a1a,
1218 0xe04,0x12121416,
1219 0xe08,0x00001800,
1220 0xe0c,0x00000000,
1221 0xe10,0x161a1a1a,
1222 0xe14,0x12121416,
1223 0xe18,0x161a1a1a,
1224 0xe1c,0x12121416,
1225 };
1226 static u32 Rtl8192PciERadioA_Array[RadioA_ArrayLength] = {
1227 0x019,0x00000003,
1228 0x000,0x000000bf,
1229 0x001,0x00000ee0,
1230 0x002,0x0000004c,
1231 0x003,0x000007f1,
1232 0x004,0x00000975,
1233 0x005,0x00000c58,
1234 0x006,0x00000ae6,
1235 0x007,0x000000ca,
1236 0x008,0x00000e1c,
1237 0x009,0x000007f0,
1238 0x00a,0x000009d0,
1239 0x00b,0x000001ba,
1240 0x00c,0x00000240,
1241 0x00e,0x00000020,
1242 0x00f,0x00000990,
1243 0x012,0x00000806,
1244 0x014,0x000005ab,
1245 0x015,0x00000f80,
1246 0x016,0x00000020,
1247 0x017,0x00000597,
1248 0x018,0x0000050a,
1249 0x01a,0x00000f80,
1250 0x01b,0x00000f5e,
1251 0x01c,0x00000008,
1252 0x01d,0x00000607,
1253 0x01e,0x000006cc,
1254 0x01f,0x00000000,
1255 0x020,0x000001a5,
1256 0x01f,0x00000001,
1257 0x020,0x00000165,
1258 0x01f,0x00000002,
1259 0x020,0x000000c6,
1260 0x01f,0x00000003,
1261 0x020,0x00000086,
1262 0x01f,0x00000004,
1263 0x020,0x00000046,
1264 0x01f,0x00000005,
1265 0x020,0x000001e6,
1266 0x01f,0x00000006,
1267 0x020,0x000001a6,
1268 0x01f,0x00000007,
1269 0x020,0x00000166,
1270 0x01f,0x00000008,
1271 0x020,0x000000c7,
1272 0x01f,0x00000009,
1273 0x020,0x00000087,
1274 0x01f,0x0000000a,
1275 0x020,0x000000f7,
1276 0x01f,0x0000000b,
1277 0x020,0x000000d7,
1278 0x01f,0x0000000c,
1279 0x020,0x000000b7,
1280 0x01f,0x0000000d,
1281 0x020,0x00000097,
1282 0x01f,0x0000000e,
1283 0x020,0x00000077,
1284 0x01f,0x0000000f,
1285 0x020,0x00000057,
1286 0x01f,0x00000010,
1287 0x020,0x00000037,
1288 0x01f,0x00000011,
1289 0x020,0x000000fb,
1290 0x01f,0x00000012,
1291 0x020,0x000000db,
1292 0x01f,0x00000013,
1293 0x020,0x000000bb,
1294 0x01f,0x00000014,
1295 0x020,0x000000ff,
1296 0x01f,0x00000015,
1297 0x020,0x000000e3,
1298 0x01f,0x00000016,
1299 0x020,0x000000c3,
1300 0x01f,0x00000017,
1301 0x020,0x000000a3,
1302 0x01f,0x00000018,
1303 0x020,0x00000083,
1304 0x01f,0x00000019,
1305 0x020,0x00000063,
1306 0x01f,0x0000001a,
1307 0x020,0x00000043,
1308 0x01f,0x0000001b,
1309 0x020,0x00000023,
1310 0x01f,0x0000001c,
1311 0x020,0x00000003,
1312 0x01f,0x0000001d,
1313 0x020,0x000001e3,
1314 0x01f,0x0000001e,
1315 0x020,0x000001c3,
1316 0x01f,0x0000001f,
1317 0x020,0x000001a3,
1318 0x01f,0x00000020,
1319 0x020,0x00000183,
1320 0x01f,0x00000021,
1321 0x020,0x00000163,
1322 0x01f,0x00000022,
1323 0x020,0x00000143,
1324 0x01f,0x00000023,
1325 0x020,0x00000123,
1326 0x01f,0x00000024,
1327 0x020,0x00000103,
1328 0x023,0x00000203,
1329 0x024,0x00000100,
1330 0x00b,0x000001ba,
1331 0x02c,0x000003d7,
1332 0x02d,0x00000ff0,
1333 0x000,0x00000037,
1334 0x004,0x00000160,
1335 0x007,0x00000080,
1336 0x002,0x0000088d,
1337 0x0fe,0x00000000,
1338 0x0fe,0x00000000,
1339 0x016,0x00000200,
1340 0x016,0x00000380,
1341 0x016,0x00000020,
1342 0x016,0x000001a0,
1343 0x000,0x000000bf,
1344 0x00d,0x0000001f,
1345 0x00d,0x00000c9f,
1346 0x002,0x0000004d,
1347 0x000,0x00000cbf,
1348 0x004,0x00000975,
1349 0x007,0x00000700,
1350 };
1351 static u32 Rtl8192PciERadioB_Array[RadioB_ArrayLength] = {
1352 0x019,0x00000003,
1353 0x000,0x000000bf,
1354 0x001,0x000006e0,
1355 0x002,0x0000004c,
1356 0x003,0x000007f1,
1357 0x004,0x00000975,
1358 0x005,0x00000c58,
1359 0x006,0x00000ae6,
1360 0x007,0x000000ca,
1361 0x008,0x00000e1c,
1362 0x000,0x000000b7,
1363 0x00a,0x00000850,
1364 0x000,0x000000bf,
1365 0x00b,0x000001ba,
1366 0x00c,0x00000240,
1367 0x00e,0x00000020,
1368 0x015,0x00000f80,
1369 0x016,0x00000020,
1370 0x017,0x00000597,
1371 0x018,0x0000050a,
1372 0x01a,0x00000e00,
1373 0x01b,0x00000f5e,
1374 0x01d,0x00000607,
1375 0x01e,0x000006cc,
1376 0x00b,0x000001ba,
1377 0x023,0x00000203,
1378 0x024,0x00000100,
1379 0x000,0x00000037,
1380 0x004,0x00000160,
1381 0x016,0x00000200,
1382 0x016,0x00000380,
1383 0x016,0x00000020,
1384 0x016,0x000001a0,
1385 0x00d,0x00000ccc,
1386 0x000,0x000000bf,
1387 0x002,0x0000004d,
1388 0x000,0x00000cbf,
1389 0x004,0x00000975,
1390 0x007,0x00000700,
1391 };
1392 static u32 Rtl8192PciERadioC_Array[RadioC_ArrayLength] = {
1393 0x0,  };
1394 static u32 Rtl8192PciERadioD_Array[RadioD_ArrayLength] = {
1395 0x0, };
1396 #endif
1397
1398 /*************************Define local function prototype**********************/
1399
1400 static u32 phy_FwRFSerialRead(struct net_device* dev,RF90_RADIO_PATH_E  eRFPath,u32 Offset);
1401 static void phy_FwRFSerialWrite(struct net_device* dev,RF90_RADIO_PATH_E eRFPath,u32 Offset,u32 Data);
1402 /*************************Define local function prototype**********************/
1403 /******************************************************************************
1404  *function:  This function read BB parameters from Header file we gen,
1405  *           and do register read/write
1406  *   input:  u32        dwBitMask  //taget bit pos in the addr to be modified
1407  *  output:  none
1408  *  return:  u32        return the shift bit bit position of the mask
1409  * ****************************************************************************/
1410 static u32 rtl8192_CalculateBitShift(u32 dwBitMask)
1411 {
1412         u32 i;
1413         for (i=0; i<=31; i++)
1414         {
1415                 if (((dwBitMask>>i)&0x1) == 1)
1416                         break;
1417         }
1418         return i;
1419 }
1420 /******************************************************************************
1421  *function:  This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
1422  *   input:  none
1423  *  output:  none
1424  *  return:  0(illegal, false), 1(legal,true)
1425  * ***************************************************************************/
1426 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev, u32 eRFPath)
1427 {
1428         u8 ret = 1;
1429         struct r8192_priv *priv = ieee80211_priv(dev);
1430 #ifdef RTL8190P
1431         if(priv->rf_type == RF_2T4R)
1432         {
1433                 ret= 1;
1434         }
1435         else if (priv->rf_type == RF_1T2R)
1436         {
1437                 if(eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
1438                         ret = 0;
1439                 else if(eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
1440                         ret =  1;
1441         }
1442 #else
1443         #ifdef RTL8192E
1444         if (priv->rf_type == RF_2T4R)
1445                 ret = 0;
1446         else if (priv->rf_type == RF_1T2R)
1447         {
1448                 if (eRFPath == RF90_PATH_A || eRFPath == RF90_PATH_B)
1449                         ret = 1;
1450                 else if (eRFPath == RF90_PATH_C || eRFPath == RF90_PATH_D)
1451                         ret = 0;
1452         }
1453         #endif
1454 #endif
1455         return ret;
1456 }
1457 /******************************************************************************
1458  *function:  This function set specific bits to BB register
1459  *   input:  net_device dev
1460  *           u32        dwRegAddr  //target addr to be modified
1461  *           u32        dwBitMask  //taget bit pos in the addr to be modified
1462  *           u32        dwData     //value to be write
1463  *  output:  none
1464  *  return:  none
1465  *  notice:
1466  * ****************************************************************************/
1467 void rtl8192_setBBreg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask, u32 dwData)
1468 {
1469         struct r8192_priv *priv = ieee80211_priv(dev);
1470         u32 OriginalValue, BitShift, NewValue;
1471
1472         if(dwBitMask!= bMaskDWord)
1473         {//if not "double word" write
1474                 OriginalValue = read_nic_dword(priv, dwRegAddr);
1475                 BitShift = rtl8192_CalculateBitShift(dwBitMask);
1476                 NewValue = (((OriginalValue) & (~dwBitMask)) | (dwData << BitShift));
1477                 write_nic_dword(priv, dwRegAddr, NewValue);
1478         }else
1479                 write_nic_dword(priv, dwRegAddr, dwData);
1480 }
1481 /******************************************************************************
1482  *function:  This function reads specific bits from BB register
1483  *   input:  net_device dev
1484  *           u32        dwRegAddr  //target addr to be readback
1485  *           u32        dwBitMask  //taget bit pos in the addr to be readback
1486  *  output:  none
1487  *  return:  u32        Data    //the readback register value
1488  *  notice:
1489  * ****************************************************************************/
1490 u32 rtl8192_QueryBBReg(struct net_device* dev, u32 dwRegAddr, u32 dwBitMask)
1491 {
1492         struct r8192_priv *priv = ieee80211_priv(dev);
1493         u32 OriginalValue, BitShift;
1494
1495         OriginalValue = read_nic_dword(priv, dwRegAddr);
1496         BitShift = rtl8192_CalculateBitShift(dwBitMask);
1497         return (OriginalValue & dwBitMask) >> BitShift;
1498 }
1499 /******************************************************************************
1500  *function:  This function read register from RF chip
1501  *   input:  net_device dev
1502  *           RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1503  *           u32        Offset     //target address to be read
1504  *  output:  none
1505  *  return:  u32        readback value
1506  *  notice:  There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
1507  * ****************************************************************************/
1508 static u32 rtl8192_phy_RFSerialRead(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset)
1509 {
1510         struct r8192_priv *priv = ieee80211_priv(dev);
1511         u32 ret = 0;
1512         u32 NewOffset = 0;
1513         BB_REGISTER_DEFINITION_T* pPhyReg = &priv->PHYRegDef[eRFPath];
1514         //rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
1515         //make sure RF register offset is correct
1516         Offset &= 0x3f;
1517
1518         //switch page for 8256 RF IC
1519         if (priv->rf_chip == RF_8256)
1520         {
1521 #ifdef RTL8190P
1522                 //analog to digital off, for protection
1523                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1524 #else
1525         #ifdef RTL8192E
1526                 //analog to digital off, for protection
1527                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1528         #endif
1529 #endif
1530                 if (Offset >= 31)
1531                 {
1532                         priv->RfReg0Value[eRFPath] |= 0x140;
1533                         //Switch to Reg_Mode2 for Reg 31-45
1534                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
1535                         //modify offset
1536                         NewOffset = Offset -30;
1537                 }
1538                 else if (Offset >= 16)
1539                 {
1540                         priv->RfReg0Value[eRFPath] |= 0x100;
1541                         priv->RfReg0Value[eRFPath] &= (~0x40);
1542                         //Switch to Reg_Mode 1 for Reg16-30
1543                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16) );
1544
1545                         NewOffset = Offset - 15;
1546                 }
1547                 else
1548                         NewOffset = Offset;
1549         }
1550         else
1551         {
1552                 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
1553                 NewOffset = Offset;
1554         }
1555         //put desired read addr to LSSI control Register
1556         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, NewOffset);
1557         //Issue a posedge trigger
1558         //
1559         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
1560         rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
1561
1562
1563         // TODO: we should not delay such a  long time. Ask help from SD3
1564         msleep(1);
1565
1566         ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
1567
1568
1569         // Switch back to Reg_Mode0;
1570         if(priv->rf_chip == RF_8256)
1571         {
1572                 priv->RfReg0Value[eRFPath] &= 0xebf;
1573
1574                 rtl8192_setBBreg(
1575                         dev,
1576                         pPhyReg->rf3wireOffset,
1577                         bMaskDWord,
1578                         (priv->RfReg0Value[eRFPath] << 16));
1579
1580 #ifdef RTL8190P
1581                 if(priv->rf_type == RF_2T4R)
1582                 {
1583                         //analog to digital on
1584                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1585                 }
1586                 else if(priv->rf_type == RF_1T2R)
1587                 {
1588                         //analog to digital on
1589                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
1590                 }
1591 #else
1592         #ifdef RTL8192E
1593                 //analog to digital on
1594                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1595         #endif
1596 #endif
1597         }
1598
1599
1600         return ret;
1601
1602 }
1603
1604 /******************************************************************************
1605  *function:  This function write data to RF register
1606  *   input:  net_device dev
1607  *           RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1608  *           u32        Offset     //target address to be written
1609  *           u32        Data    //The new register data to be written
1610  *  output:  none
1611  *  return:  none
1612  *  notice:  For RF8256 only.
1613   ===========================================================
1614  *Reg Mode      RegCTL[1]       RegCTL[0]               Note
1615  *              (Reg00[12])     (Reg00[10])
1616  *===========================================================
1617  *Reg_Mode0     0               x                       Reg 0 ~15(0x0 ~ 0xf)
1618  *------------------------------------------------------------------
1619  *Reg_Mode1     1               0                       Reg 16 ~30(0x1 ~ 0xf)
1620  *------------------------------------------------------------------
1621  * Reg_Mode2    1               1                       Reg 31 ~ 45(0x1 ~ 0xf)
1622  *------------------------------------------------------------------
1623  * ****************************************************************************/
1624 static void rtl8192_phy_RFSerialWrite(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 Offset, u32 Data)
1625 {
1626         struct r8192_priv *priv = ieee80211_priv(dev);
1627         u32 DataAndAddr = 0, NewOffset = 0;
1628         BB_REGISTER_DEFINITION_T        *pPhyReg = &priv->PHYRegDef[eRFPath];
1629
1630         Offset &= 0x3f;
1631         if (priv->rf_chip == RF_8256)
1632         {
1633
1634 #ifdef RTL8190P
1635                 //analog to digital off, for protection
1636                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1637 #else
1638         #ifdef RTL8192E
1639                 //analog to digital off, for protection
1640                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
1641         #endif
1642 #endif
1643
1644                 if (Offset >= 31)
1645                 {
1646                         priv->RfReg0Value[eRFPath] |= 0x140;
1647                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath] << 16));
1648                         NewOffset = Offset - 30;
1649                 }
1650                 else if (Offset >= 16)
1651                 {
1652                         priv->RfReg0Value[eRFPath] |= 0x100;
1653                         priv->RfReg0Value[eRFPath] &= (~0x40);
1654                         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
1655                         NewOffset = Offset - 15;
1656                 }
1657                 else
1658                         NewOffset = Offset;
1659         }
1660         else
1661         {
1662                 RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
1663                 NewOffset = Offset;
1664         }
1665
1666         // Put write addr in [5:0]  and write data in [31:16]
1667         DataAndAddr = (Data<<16) | (NewOffset&0x3f);
1668
1669         // Write Operation
1670         rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
1671
1672
1673         if(Offset==0x0)
1674                 priv->RfReg0Value[eRFPath] = Data;
1675
1676         // Switch back to Reg_Mode0;
1677         if(priv->rf_chip == RF_8256)
1678         {
1679                 if(Offset != 0)
1680                 {
1681                         priv->RfReg0Value[eRFPath] &= 0xebf;
1682                         rtl8192_setBBreg(
1683                                 dev,
1684                                 pPhyReg->rf3wireOffset,
1685                                 bMaskDWord,
1686                                 (priv->RfReg0Value[eRFPath] << 16));
1687                 }
1688 #ifdef RTL8190P
1689                 if(priv->rf_type == RF_2T4R)
1690                 {
1691                         //analog to digital on
1692                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0xf);// 0x88c[11:8]
1693                 }
1694                 else if(priv->rf_type == RF_1T2R)
1695                 {
1696                         //analog to digital on
1697                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xc00, 0x3);// 0x88c[11:10]
1698                 }
1699 #else
1700         #ifdef RTL8192E
1701                 //analog to digital on
1702                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
1703         #endif
1704 #endif
1705         }
1706 }
1707
1708 /******************************************************************************
1709  *function:  This function set specific bits to RF register
1710  *   input:  net_device dev
1711  *           RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
1712  *           u32        RegAddr  //target addr to be modified
1713  *           u32        BitMask  //taget bit pos in the addr to be modified
1714  *           u32        Data     //value to be write
1715  *  output:  none
1716  *  return:  none
1717  *  notice:
1718  * ****************************************************************************/
1719 void rtl8192_phy_SetRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask, u32 Data)
1720 {
1721         struct r8192_priv *priv = ieee80211_priv(dev);
1722         u32 Original_Value, BitShift, New_Value;
1723 //      u8      time = 0;
1724
1725         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1726                 return;
1727 #ifdef RTL8192E
1728         if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
1729                 return;
1730 #endif
1731         //down(&priv->rf_sem);
1732
1733         RT_TRACE(COMP_PHY, "FW RF CTRL is not ready now\n");
1734         if (priv->Rf_Mode == RF_OP_By_FW)
1735         {
1736                 if (BitMask != bMask12Bits) // RF data is 12 bits only
1737                 {
1738                         Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
1739                         BitShift =  rtl8192_CalculateBitShift(BitMask);
1740                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
1741
1742                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, New_Value);
1743                 }else
1744                         phy_FwRFSerialWrite(dev, eRFPath, RegAddr, Data);
1745                 udelay(200);
1746
1747         }
1748         else
1749         {
1750                 if (BitMask != bMask12Bits) // RF data is 12 bits only
1751                 {
1752                         Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
1753                         BitShift =  rtl8192_CalculateBitShift(BitMask);
1754                         New_Value = (((Original_Value) & (~BitMask)) | (Data<< BitShift));
1755
1756                         rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, New_Value);
1757                 }else
1758                         rtl8192_phy_RFSerialWrite(dev, eRFPath, RegAddr, Data);
1759         }
1760         //up(&priv->rf_sem);
1761 }
1762
1763 /******************************************************************************
1764  *function:  This function reads specific bits from RF register
1765  *   input:  net_device dev
1766  *           u32        RegAddr  //target addr to be readback
1767  *           u32        BitMask  //taget bit pos in the addr to be readback
1768  *  output:  none
1769  *  return:  u32        Data    //the readback register value
1770  *  notice:
1771  * ****************************************************************************/
1772 u32 rtl8192_phy_QueryRFReg(struct net_device* dev, RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask)
1773 {
1774         u32 Original_Value, Readback_Value, BitShift;
1775         struct r8192_priv *priv = ieee80211_priv(dev);
1776         if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
1777                 return 0;
1778 #ifdef RTL8192E
1779         if(priv->ieee80211->eRFPowerState != eRfOn && !priv->being_init_adapter)
1780                 return  0;
1781 #endif
1782         down(&priv->rf_sem);
1783         if (priv->Rf_Mode == RF_OP_By_FW)
1784         {
1785                 Original_Value = phy_FwRFSerialRead(dev, eRFPath, RegAddr);
1786                 udelay(200);
1787         }
1788         else
1789         {
1790                 Original_Value = rtl8192_phy_RFSerialRead(dev, eRFPath, RegAddr);
1791
1792         }
1793         BitShift =  rtl8192_CalculateBitShift(BitMask);
1794         Readback_Value = (Original_Value & BitMask) >> BitShift;
1795         up(&priv->rf_sem);
1796 //      udelay(200);
1797         return Readback_Value;
1798 }
1799
1800 /******************************************************************************
1801  *function:  We support firmware to execute RF-R/W.
1802  *   input:  dev
1803  *  output:  none
1804  *  return:  none
1805  *  notice:
1806  * ***************************************************************************/
1807 static u32 phy_FwRFSerialRead(
1808         struct net_device* dev,
1809         RF90_RADIO_PATH_E       eRFPath,
1810         u32                             Offset  )
1811 {
1812         struct r8192_priv *priv = ieee80211_priv(dev);
1813         u32             Data = 0;
1814         u8              time = 0;
1815         //DbgPrint("FW RF CTRL\n\r");
1816         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
1817            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
1818            much time. This is only for site survey. */
1819         // 1. Read operation need not insert data. bit 0-11
1820         //Data &= bMask12Bits;
1821         // 2. Write RF register address. Bit 12-19
1822         Data |= ((Offset&0xFF)<<12);
1823         // 3. Write RF path.  bit 20-21
1824         Data |= ((eRFPath&0x3)<<20);
1825         // 4. Set RF read indicator. bit 22=0
1826         //Data |= 0x00000;
1827         // 5. Trigger Fw to operate the command. bit 31
1828         Data |= 0x80000000;
1829         // 6. We can not execute read operation if bit 31 is 1.
1830         while (read_nic_dword(priv, QPNR)&0x80000000)
1831         {
1832                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1833                 if (time++ < 100)
1834                 {
1835                         //DbgPrint("FW not finish RF-R Time=%d\n\r", time);
1836                         udelay(10);
1837                 }
1838                 else
1839                         break;
1840         }
1841         // 7. Execute read operation.
1842         write_nic_dword(priv, QPNR, Data);
1843         // 8. Check if firmawre send back RF content.
1844         while (read_nic_dword(priv, QPNR)&0x80000000)
1845         {
1846                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1847                 if (time++ < 100)
1848                 {
1849                         //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
1850                         udelay(10);
1851                 }
1852                 else
1853                         return 0;
1854         }
1855         return read_nic_dword(priv, RF_DATA);
1856 }
1857
1858 /******************************************************************************
1859  *function:  We support firmware to execute RF-R/W.
1860  *   input:  dev
1861  *  output:  none
1862  *  return:  none
1863  *  notice:
1864  * ***************************************************************************/
1865 static void
1866 phy_FwRFSerialWrite(
1867                 struct net_device* dev,
1868                 RF90_RADIO_PATH_E       eRFPath,
1869                 u32                             Offset,
1870                 u32                             Data    )
1871 {
1872         struct r8192_priv *priv = ieee80211_priv(dev);
1873         u8      time = 0;
1874
1875         //DbgPrint("N FW RF CTRL RF-%d OF%02x DATA=%03x\n\r", eRFPath, Offset, Data);
1876         /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
1877            not execute the scheme in the initial step. Otherwise, RF-R/W will waste
1878            much time. This is only for site survey. */
1879
1880         // 1. Set driver write bit and 12 bit data. bit 0-11
1881         //Data &= bMask12Bits;  // Done by uper layer.
1882         // 2. Write RF register address. bit 12-19
1883         Data |= ((Offset&0xFF)<<12);
1884         // 3. Write RF path.  bit 20-21
1885         Data |= ((eRFPath&0x3)<<20);
1886         // 4. Set RF write indicator. bit 22=1
1887         Data |= 0x400000;
1888         // 5. Trigger Fw to operate the command. bit 31=1
1889         Data |= 0x80000000;
1890
1891         // 6. Write operation. We can not write if bit 31 is 1.
1892         while (read_nic_dword(priv, QPNR)&0x80000000)
1893         {
1894                 // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
1895                 if (time++ < 100)
1896                 {
1897                         //DbgPrint("FW not finish RF-W Time=%d\n\r", time);
1898                         udelay(10);
1899                 }
1900                 else
1901                         break;
1902         }
1903         // 7. No matter check bit. We always force the write. Because FW will
1904         //    not accept the command.
1905         write_nic_dword(priv, QPNR, Data);
1906         /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
1907            to finish RF write operation. */
1908         /* 2008/01/17 MH We support delay in firmware side now. */
1909         //delay_us(20);
1910
1911 }
1912
1913
1914 /******************************************************************************
1915  *function:  This function read BB parameters from Header file we gen,
1916  *           and do register read/write
1917  *   input:  dev
1918  *  output:  none
1919  *  return:  none
1920  *  notice:  BB parameters may change all the time, so please make
1921  *           sure it has been synced with the newest.
1922  * ***************************************************************************/
1923 void rtl8192_phy_configmac(struct net_device* dev)
1924 {
1925         u32 dwArrayLen = 0, i = 0;
1926         u32* pdwArray = NULL;
1927         struct r8192_priv *priv = ieee80211_priv(dev);
1928 #ifdef TO_DO_LIST
1929 if(Adapter->bInHctTest)
1930         {
1931                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_ArrayDTM\n");
1932                 dwArrayLen = MACPHY_ArrayLengthDTM;
1933                 pdwArray = Rtl819XMACPHY_ArrayDTM;
1934         }
1935         else if(priv->bTXPowerDataReadFromEEPORM)
1936 #endif
1937          if(priv->bTXPowerDataReadFromEEPORM)
1938         {
1939                 RT_TRACE(COMP_PHY, "Rtl819XMACPHY_Array_PG\n");
1940                 dwArrayLen = MACPHY_Array_PGLength;
1941                 pdwArray = Rtl819XMACPHY_Array_PG;
1942
1943         }
1944         else
1945         {
1946                 RT_TRACE(COMP_PHY,"Read rtl819XMACPHY_Array\n");
1947                 dwArrayLen = MACPHY_ArrayLength;
1948                 pdwArray = Rtl819XMACPHY_Array;
1949         }
1950         for(i = 0; i<dwArrayLen; i=i+3){
1951                 RT_TRACE(COMP_DBG, "The Rtl8190MACPHY_Array[0] is %x Rtl8190MACPHY_Array[1] is %x Rtl8190MACPHY_Array[2] is %x\n",
1952                                 pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1953                 if(pdwArray[i] == 0x318)
1954                 {
1955                         pdwArray[i+2] = 0x00000800;
1956                         //DbgPrint("ptrArray[i], ptrArray[i+1], ptrArray[i+2] = %x, %x, %x\n",
1957                         //      ptrArray[i], ptrArray[i+1], ptrArray[i+2]);
1958                 }
1959                 rtl8192_setBBreg(dev, pdwArray[i], pdwArray[i+1], pdwArray[i+2]);
1960         }
1961 }
1962
1963 /******************************************************************************
1964  *function:  This function do dirty work
1965  *   input:  dev
1966  *  output:  none
1967  *  return:  none
1968  *  notice:  BB parameters may change all the time, so please make
1969  *           sure it has been synced with the newest.
1970  * ***************************************************************************/
1971
1972 void rtl8192_phyConfigBB(struct net_device* dev, u8 ConfigType)
1973 {
1974         int i;
1975         //u8 ArrayLength;
1976         u32*    Rtl819XPHY_REGArray_Table = NULL;
1977         u32*    Rtl819XAGCTAB_Array_Table = NULL;
1978         u16     AGCTAB_ArrayLen, PHY_REGArrayLen = 0;
1979         struct r8192_priv *priv = ieee80211_priv(dev);
1980 #ifdef TO_DO_LIST
1981         u32 *rtl8192PhyRegArrayTable = NULL, *rtl8192AgcTabArrayTable = NULL;
1982         if(Adapter->bInHctTest)
1983         {
1984                 AGCTAB_ArrayLen = AGCTAB_ArrayLengthDTM;
1985                 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_ArrayDTM;
1986
1987                 if(priv->RF_Type == RF_2T4R)
1988                 {
1989                         PHY_REGArrayLen = PHY_REGArrayLengthDTM;
1990                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArrayDTM;
1991                 }
1992                 else if (priv->RF_Type == RF_1T2R)
1993                 {
1994                         PHY_REGArrayLen = PHY_REG_1T2RArrayLengthDTM;
1995                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArrayDTM;
1996                 }
1997         }
1998         else
1999 #endif
2000         {
2001                 AGCTAB_ArrayLen = AGCTAB_ArrayLength;
2002                 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_Array;
2003                 if(priv->rf_type == RF_2T4R)
2004                 {
2005                         PHY_REGArrayLen = PHY_REGArrayLength;
2006                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REGArray;
2007                 }
2008                 else if (priv->rf_type == RF_1T2R)
2009                 {
2010                         PHY_REGArrayLen = PHY_REG_1T2RArrayLength;
2011                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T2RArray;
2012                 }
2013         }
2014
2015         if (ConfigType == BaseBand_Config_PHY_REG)
2016         {
2017                 for (i=0; i<PHY_REGArrayLen; i+=2)
2018                 {
2019                         rtl8192_setBBreg(dev, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
2020                         RT_TRACE(COMP_DBG, "i: %x, The Rtl819xUsbPHY_REGArray[0] is %x Rtl819xUsbPHY_REGArray[1] is %x \n",i, Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]);
2021                 }
2022         }
2023         else if (ConfigType == BaseBand_Config_AGC_TAB)
2024         {
2025                 for (i=0; i<AGCTAB_ArrayLen; i+=2)
2026                 {
2027                         rtl8192_setBBreg(dev, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
2028                         RT_TRACE(COMP_DBG, "i:%x, The rtl819XAGCTAB_Array[0] is %x rtl819XAGCTAB_Array[1] is %x \n",i, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
2029                 }
2030         }
2031 }
2032 /******************************************************************************
2033  *function:  This function initialize Register definition offset for Radio Path
2034  *           A/B/C/D
2035  *   input:  net_device dev
2036  *  output:  none
2037  *  return:  none
2038  *  notice:  Initialization value here is constant and it should never be changed
2039  * ***************************************************************************/
2040 static void rtl8192_InitBBRFRegDef(struct net_device* dev)
2041 {
2042         struct r8192_priv *priv = ieee80211_priv(dev);
2043 // RF Interface Sowrtware Control
2044         priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
2045         priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
2046         priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
2047         priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
2048
2049         // RF Interface Readback Value
2050         priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
2051         priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
2052         priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
2053         priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
2054
2055         // RF Interface Output (and Enable)
2056         priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
2057         priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
2058         priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
2059         priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
2060
2061         // RF Interface (Output and)  Enable
2062         priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
2063         priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
2064         priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
2065         priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
2066
2067         //Addr of LSSI. Wirte RF register by driver
2068         priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
2069         priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
2070         priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
2071         priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
2072
2073         // RF parameter
2074         priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  //BB Band Select
2075         priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
2076         priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2077         priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
2078
2079         // Tx AGC Gain Stage (same for all path. Should we remove this?)
2080         priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2081         priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2082         priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2083         priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
2084
2085         // Tranceiver A~D HSSI Parameter-1
2086         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  //wire control parameter1
2087         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  //wire control parameter1
2088         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;  //wire control parameter1
2089         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;  //wire control parameter1
2090
2091         // Tranceiver A~D HSSI Parameter-2
2092         priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2
2093         priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2
2094         priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;  //wire control parameter2
2095         priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;  //wire control parameter1
2096
2097         // RF switch Control
2098         priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
2099         priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
2100         priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2101         priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
2102
2103         // AGC control 1
2104         priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
2105         priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
2106         priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
2107         priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
2108
2109         // AGC control 2
2110         priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
2111         priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
2112         priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
2113         priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
2114
2115         // RX AFE control 1
2116         priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
2117         priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
2118         priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
2119         priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
2120
2121         // RX AFE control 1
2122         priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
2123         priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
2124         priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
2125         priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
2126
2127         // Tx AFE control 1
2128         priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
2129         priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
2130         priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
2131         priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
2132
2133         // Tx AFE control 2
2134         priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
2135         priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
2136         priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
2137         priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
2138
2139         // Tranceiver LSSI Readback
2140         priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
2141         priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
2142         priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
2143         priv->PHYRegDef[RF90_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
2144
2145 }
2146 /******************************************************************************
2147  *function:  This function is to write register and then readback to make sure whether BB and RF is OK
2148  *   input:  net_device dev
2149  *           HW90_BLOCK_E CheckBlock
2150  *           RF90_RADIO_PATH_E eRFPath  //only used when checkblock is HW90_BLOCK_RF
2151  *  output:  none
2152  *  return:  return whether BB and RF is ok(0:OK; 1:Fail)
2153  *  notice:  This function may be removed in the ASIC
2154  * ***************************************************************************/
2155 RT_STATUS rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath)
2156 {
2157         struct r8192_priv *priv = ieee80211_priv(dev);
2158 //      BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
2159         RT_STATUS ret = RT_STATUS_SUCCESS;
2160         u32 i, CheckTimes = 4, dwRegRead = 0;
2161         u32 WriteAddr[4];
2162         u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
2163         // Initialize register address offset to be checked
2164         WriteAddr[HW90_BLOCK_MAC] = 0x100;
2165         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
2166         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
2167         WriteAddr[HW90_BLOCK_RF] = 0x3;
2168         RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
2169         for(i=0 ; i < CheckTimes ; i++)
2170         {
2171
2172                 //
2173                 // Write Data to register and readback
2174                 //
2175                 switch(CheckBlock)
2176                 {
2177                 case HW90_BLOCK_MAC:
2178                         RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
2179                         break;
2180
2181                 case HW90_BLOCK_PHY0:
2182                 case HW90_BLOCK_PHY1:
2183                         write_nic_dword(priv, WriteAddr[CheckBlock], WriteData[i]);
2184                         dwRegRead = read_nic_dword(priv, WriteAddr[CheckBlock]);
2185                         break;
2186
2187                 case HW90_BLOCK_RF:
2188                         WriteData[i] &= 0xfff;
2189                         rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
2190                         // TODO: we should not delay for such a long time. Ask SD3
2191                         mdelay(10);
2192                         dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
2193                         mdelay(10);
2194                         break;
2195
2196                 default:
2197                         ret = RT_STATUS_FAILURE;
2198                         break;
2199                 }
2200
2201
2202                 //
2203                 // Check whether readback data is correct
2204                 //
2205                 if(dwRegRead != WriteData[i])
2206                 {
2207                         RT_TRACE(COMP_ERR, "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
2208                         ret = RT_STATUS_FAILURE;
2209                         break;
2210                 }
2211         }
2212
2213         return ret;
2214 }
2215
2216
2217 /******************************************************************************
2218  *function:  This function initialize BB&RF
2219  *   input:  net_device dev
2220  *  output:  none
2221  *  return:  none
2222  *  notice:  Initialization value may change all the time, so please make
2223  *           sure it has been synced with the newest.
2224  * ***************************************************************************/
2225 static RT_STATUS rtl8192_BB_Config_ParaFile(struct net_device* dev)
2226 {
2227         struct r8192_priv *priv = ieee80211_priv(dev);
2228         RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2229         u8 bRegValue = 0, eCheckItem = 0;
2230         u32 dwRegValue = 0;
2231         /**************************************
2232         //<1>Initialize BaseBand
2233         **************************************/
2234
2235         /*--set BB Global Reset--*/
2236         bRegValue = read_nic_byte(priv, BB_GLOBAL_RESET);
2237         write_nic_byte(priv, BB_GLOBAL_RESET,(bRegValue|BB_GLOBAL_RESET_BIT));
2238
2239         /*---set BB reset Active---*/
2240         dwRegValue = read_nic_dword(priv, CPU_GEN);
2241         write_nic_dword(priv, CPU_GEN, (dwRegValue&(~CPU_GEN_BB_RST)));
2242
2243         /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
2244         // TODO: this function should be removed on ASIC , Emily 2007.2.2
2245         for(eCheckItem=(HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem<=HW90_BLOCK_PHY1; eCheckItem++)
2246         {
2247                 rtStatus  = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
2248                 if(rtStatus != RT_STATUS_SUCCESS)
2249                 {
2250                         RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
2251                         return rtStatus;
2252                 }
2253         }
2254         /*---- Set CCK and OFDM Block "OFF"----*/
2255         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
2256         /*----BB Register Initilazation----*/
2257         //==m==>Set PHY REG From Header<==m==
2258         rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
2259
2260         /*----Set BB reset de-Active----*/
2261         dwRegValue = read_nic_dword(priv, CPU_GEN);
2262         write_nic_dword(priv, CPU_GEN, (dwRegValue|CPU_GEN_BB_RST));
2263
2264         /*----BB AGC table Initialization----*/
2265         //==m==>Set PHY REG From Header<==m==
2266         rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
2267
2268         if (priv->card_8192_version  > VERSION_8190_BD)
2269         {
2270                 if(priv->rf_type == RF_2T4R)
2271                 {
2272                 // Antenna gain offset from B/C/D to A
2273                 dwRegValue = (  priv->AntennaTxPwDiff[2]<<8 |
2274                                                 priv->AntennaTxPwDiff[1]<<4 |
2275                                                 priv->AntennaTxPwDiff[0]);
2276                 }
2277                 else
2278                         dwRegValue = 0x0;       //Antenna gain offset doesn't make sense in RF 1T2R.
2279                 rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
2280                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), dwRegValue);
2281
2282
2283                 //XSTALLCap
2284 #ifdef RTL8190P
2285         dwRegValue = priv->CrystalCap & 0x3;    // bit0~1 of crystal cap
2286         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap01, dwRegValue);
2287         dwRegValue = ((priv->CrystalCap & 0xc)>>2);     // bit2~3 of crystal cap
2288         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, bXtalCap23, dwRegValue);
2289 #else
2290         #ifdef RTL8192E
2291                 dwRegValue = priv->CrystalCap;
2292                 rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap92x, dwRegValue);
2293         #endif
2294 #endif
2295
2296         }
2297
2298         // Check if the CCK HighPower is turned ON.
2299         // This is used to calculate PWDB.
2300 //      priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
2301         return rtStatus;
2302 }
2303 /******************************************************************************
2304  *function:  This function initialize BB&RF
2305  *   input:  net_device dev
2306  *  output:  none
2307  *  return:  none
2308  *  notice:  Initialization value may change all the time, so please make
2309  *           sure it has been synced with the newest.
2310  * ***************************************************************************/
2311 RT_STATUS rtl8192_BBConfig(struct net_device* dev)
2312 {
2313         rtl8192_InitBBRFRegDef(dev);
2314         //config BB&RF. As hardCode based initialization has not been well
2315         //implemented, so use file first.FIXME:should implement it for hardcode?
2316         return rtl8192_BB_Config_ParaFile(dev);
2317 }
2318
2319 /******************************************************************************
2320  *function:  This function obtains the initialization value of Tx power Level offset
2321  *   input:  net_device dev
2322  *  output:  none
2323  *  return:  none
2324  * ***************************************************************************/
2325 void rtl8192_phy_getTxPower(struct net_device* dev)
2326 {
2327         struct r8192_priv *priv = ieee80211_priv(dev);
2328 #ifdef RTL8190P
2329         priv->MCSTxPowerLevelOriginalOffset[0] =
2330                 read_nic_dword(priv, MCS_TXAGC);
2331         priv->MCSTxPowerLevelOriginalOffset[1] =
2332                 read_nic_dword(priv, (MCS_TXAGC+4));
2333         priv->CCKTxPowerLevelOriginalOffset =
2334                 read_nic_dword(priv, CCK_TXAGC);
2335 #else
2336         #ifdef RTL8192E
2337         priv->MCSTxPowerLevelOriginalOffset[0] =
2338                 read_nic_dword(priv, rTxAGC_Rate18_06);
2339         priv->MCSTxPowerLevelOriginalOffset[1] =
2340                 read_nic_dword(priv, rTxAGC_Rate54_24);
2341         priv->MCSTxPowerLevelOriginalOffset[2] =
2342                 read_nic_dword(priv, rTxAGC_Mcs03_Mcs00);
2343         priv->MCSTxPowerLevelOriginalOffset[3] =
2344                 read_nic_dword(priv, rTxAGC_Mcs07_Mcs04);
2345         priv->MCSTxPowerLevelOriginalOffset[4] =
2346                 read_nic_dword(priv, rTxAGC_Mcs11_Mcs08);
2347         priv->MCSTxPowerLevelOriginalOffset[5] =
2348                 read_nic_dword(priv, rTxAGC_Mcs15_Mcs12);
2349         #endif
2350 #endif
2351
2352         // read rx initial gain
2353         priv->DefaultInitialGain[0] = read_nic_byte(priv, rOFDM0_XAAGCCore1);
2354         priv->DefaultInitialGain[1] = read_nic_byte(priv, rOFDM0_XBAGCCore1);
2355         priv->DefaultInitialGain[2] = read_nic_byte(priv, rOFDM0_XCAGCCore1);
2356         priv->DefaultInitialGain[3] = read_nic_byte(priv, rOFDM0_XDAGCCore1);
2357         RT_TRACE(COMP_INIT, "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
2358                 priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
2359                 priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
2360
2361         // read framesync
2362         priv->framesync = read_nic_byte(priv, rOFDM0_RxDetector3);
2363         priv->framesyncC34 = read_nic_dword(priv, rOFDM0_RxDetector2);
2364         RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
2365                 rOFDM0_RxDetector3, priv->framesync);
2366         // read SIFS (save the value read fome MACPHY_REG.txt)
2367         priv->SifsTime = read_nic_word(priv, SIFS);
2368 }
2369
2370 /******************************************************************************
2371  *function:  This function obtains the initialization value of Tx power Level offset
2372  *   input:  net_device dev
2373  *  output:  none
2374  *  return:  none
2375  * ***************************************************************************/
2376 void rtl8192_phy_setTxPower(struct net_device* dev, u8 channel)
2377 {
2378         struct r8192_priv *priv = ieee80211_priv(dev);
2379         u8      powerlevel = 0,powerlevelOFDM24G = 0;
2380         char ant_pwr_diff;
2381         u32     u4RegValue;
2382
2383         if(priv->epromtype == EPROM_93c46)
2384         {
2385                 powerlevel = priv->TxPowerLevelCCK[channel-1];
2386                 powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
2387         }
2388         else if(priv->epromtype == EPROM_93c56)
2389         {
2390                 if(priv->rf_type == RF_1T2R)
2391                 {
2392                         powerlevel = priv->TxPowerLevelCCK_C[channel-1];
2393                         powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_C[channel-1];
2394                 }
2395                 else if(priv->rf_type == RF_2T4R)
2396                 {
2397                         // Mainly we use RF-A Tx Power to write the Tx Power registers, but the RF-C Tx
2398                         // Power must be calculated by the antenna diff.
2399                         // So we have to rewrite Antenna gain offset register here.
2400                         powerlevel = priv->TxPowerLevelCCK_A[channel-1];
2401                         powerlevelOFDM24G = priv->TxPowerLevelOFDM24G_A[channel-1];
2402
2403                         ant_pwr_diff = priv->TxPowerLevelOFDM24G_C[channel-1]
2404                                                 -priv->TxPowerLevelOFDM24G_A[channel-1];
2405                         ant_pwr_diff &= 0xf;
2406                         //DbgPrint(" ant_pwr_diff = 0x%x", (u8)(ant_pwr_diff));
2407                         priv->RF_C_TxPwDiff = ant_pwr_diff;
2408
2409                         priv->AntennaTxPwDiff[2] = 0;// RF-D, don't care
2410                         priv->AntennaTxPwDiff[1] = (u8)(ant_pwr_diff);// RF-C
2411                         priv->AntennaTxPwDiff[0] = 0;// RF-B, don't care
2412
2413                         // Antenna gain offset from B/C/D to A
2414                         u4RegValue = (  priv->AntennaTxPwDiff[2]<<8 |
2415                                                 priv->AntennaTxPwDiff[1]<<4 |
2416                                                 priv->AntennaTxPwDiff[0]);
2417
2418                         rtl8192_setBBreg(dev, rFPGA0_TxGainStage,
2419                         (bXBTxAGC|bXCTxAGC|bXDTxAGC), u4RegValue);
2420                 }
2421         }
2422 #ifdef TODO
2423         //
2424         // CCX 2 S31, AP control of client transmit power:
2425         // 1. We shall not exceed Cell Power Limit as possible as we can.
2426         // 2. Tolerance is +/- 5dB.
2427         // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2428         //
2429         // TODO:
2430         // 1. 802.11h power contraint
2431         //
2432         // 071011, by rcnjko.
2433         //
2434         if(     pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
2435                 pMgntInfo->bWithCcxCellPwr &&
2436                 channel == pMgntInfo->dot11CurrentChannelNumber)
2437         {
2438                 u8      CckCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pMgntInfo->CcxCellPwr);
2439                 u8      LegacyOfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pMgntInfo->CcxCellPwr);
2440                 u8      OfdmCellPwrIdx = DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pMgntInfo->CcxCellPwr);
2441
2442                 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2443                         ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2444                         pMgntInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2445                 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2446                         ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2447                         channel, powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2448
2449                 // CCK
2450                 if(powerlevel > CckCellPwrIdx)
2451                         powerlevel = CckCellPwrIdx;
2452                 // Legacy OFDM, HT OFDM
2453                 if(powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff > OfdmCellPwrIdx)
2454                 {
2455                         if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
2456                         {
2457                                 powerlevelOFDM24G = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
2458                         }
2459                         else
2460                         {
2461                                 LegacyOfdmCellPwrIdx = 0;
2462                         }
2463                 }
2464
2465                 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2466                         ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2467                         powerlevel, powerlevelOFDM24G + pHalData->LegacyHTTxPowerDiff, powerlevelOFDM24G));
2468         }
2469
2470         pHalData->CurrentCckTxPwrIdx = powerlevel;
2471         pHalData->CurrentOfdm24GTxPwrIdx = powerlevelOFDM24G;
2472 #endif
2473         switch(priv->rf_chip)
2474         {
2475         case RF_8225:
2476         //      PHY_SetRF8225CckTxPower(Adapter, powerlevel);
2477         //      PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
2478                 break;
2479         case RF_8256:
2480                 PHY_SetRF8256CCKTxPower(dev, powerlevel); //need further implement
2481                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2482                 break;
2483         case RF_8258:
2484                 break;
2485         default:
2486                 RT_TRACE(COMP_ERR, "unknown rf chip in funtion %s()\n", __FUNCTION__);
2487                 break;
2488         }
2489 }
2490
2491 /******************************************************************************
2492  *function:  This function check Rf chip to do RF config
2493  *   input:  net_device dev
2494  *  output:  none
2495  *  return:  only 8256 is supported
2496  * ***************************************************************************/
2497 RT_STATUS rtl8192_phy_RFConfig(struct net_device* dev)
2498 {
2499         struct r8192_priv *priv = ieee80211_priv(dev);
2500         RT_STATUS rtStatus = RT_STATUS_SUCCESS;
2501         switch(priv->rf_chip)
2502         {
2503                 case RF_8225:
2504 //                      rtStatus = PHY_RF8225_Config(Adapter);
2505                         break;
2506                 case RF_8256:
2507                         rtStatus = PHY_RF8256_Config(dev);
2508                         break;
2509
2510                 case RF_8258:
2511                         break;
2512                 case RF_PSEUDO_11N:
2513                 //rtStatus = PHY_RF8225_Config(Adapter);
2514                 break;
2515
2516                 default:
2517                         RT_TRACE(COMP_ERR, "error chip id\n");
2518                         break;
2519         }
2520         return rtStatus;
2521 }
2522
2523 /******************************************************************************
2524  *function:  This function update Initial gain
2525  *   input:  net_device dev
2526  *  output:  none
2527  *  return:  As Windows has not implemented this, wait for complement
2528  * ***************************************************************************/
2529 void rtl8192_phy_updateInitGain(struct net_device* dev)
2530 {
2531 }
2532
2533 /******************************************************************************
2534  *function:  This function read RF parameters from general head file, and do RF 3-wire
2535  *   input:  net_device dev
2536  *  output:  none
2537  *  return:  return code show if RF configuration is successful(0:pass, 1:fail)
2538  *    Note:  Delay may be required for RF configuration
2539  * ***************************************************************************/
2540 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev, RF90_RADIO_PATH_E eRFPath)
2541 {
2542
2543         int i;
2544         //u32* pRFArray;
2545         u8 ret = 0;
2546
2547         switch(eRFPath){
2548                 case RF90_PATH_A:
2549                         for(i = 0;i<RadioA_ArrayLength; i=i+2){
2550
2551                                 if(Rtl819XRadioA_Array[i] == 0xfe){
2552                                                 msleep(100);
2553                                                 continue;
2554                                 }
2555                                 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioA_Array[i], bMask12Bits, Rtl819XRadioA_Array[i+1]);
2556                                 //msleep(1);
2557
2558                         }
2559                         break;
2560                 case RF90_PATH_B:
2561                         for(i = 0;i<RadioB_ArrayLength; i=i+2){
2562
2563                                 if(Rtl819XRadioB_Array[i] == 0xfe){
2564                                                 msleep(100);
2565                                                 continue;
2566                                 }
2567                                 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioB_Array[i], bMask12Bits, Rtl819XRadioB_Array[i+1]);
2568                                 //msleep(1);
2569
2570                         }
2571                         break;
2572                 case RF90_PATH_C:
2573                         for(i = 0;i<RadioC_ArrayLength; i=i+2){
2574
2575                                 if(Rtl819XRadioC_Array[i] == 0xfe){
2576                                                 msleep(100);
2577                                                 continue;
2578                                 }
2579                                 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioC_Array[i], bMask12Bits, Rtl819XRadioC_Array[i+1]);
2580                                 //msleep(1);
2581
2582                         }
2583                         break;
2584                 case RF90_PATH_D:
2585                         for(i = 0;i<RadioD_ArrayLength; i=i+2){
2586
2587                                 if(Rtl819XRadioD_Array[i] == 0xfe){
2588                                                 msleep(100);
2589                                                 continue;
2590                                 }
2591                                 rtl8192_phy_SetRFReg(dev, eRFPath, Rtl819XRadioD_Array[i], bMask12Bits, Rtl819XRadioD_Array[i+1]);
2592                                 //msleep(1);
2593
2594                         }
2595                         break;
2596                 default:
2597                         break;
2598         }
2599
2600         return ret;
2601
2602 }
2603 /******************************************************************************
2604  *function:  This function set Tx Power of the channel
2605  *   input:  struct net_device *dev
2606  *           u8                 channel
2607  *  output:  none
2608  *  return:  none
2609  *    Note:
2610  * ***************************************************************************/
2611 static void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
2612 {
2613         struct r8192_priv *priv = ieee80211_priv(dev);
2614         u8      powerlevel = priv->TxPowerLevelCCK[channel-1];
2615         u8      powerlevelOFDM24G = priv->TxPowerLevelOFDM24G[channel-1];
2616
2617         switch(priv->rf_chip)
2618         {
2619         case RF_8225:
2620 #ifdef TO_DO_LIST
2621                 PHY_SetRF8225CckTxPower(Adapter, powerlevel);
2622                 PHY_SetRF8225OfdmTxPower(Adapter, powerlevelOFDM24G);
2623 #endif
2624                 break;
2625
2626         case RF_8256:
2627                 PHY_SetRF8256CCKTxPower(dev, powerlevel);
2628                 PHY_SetRF8256OFDMTxPower(dev, powerlevelOFDM24G);
2629                 break;
2630
2631         case RF_8258:
2632                 break;
2633         default:
2634                 RT_TRACE(COMP_ERR, "unknown rf chip ID in rtl8192_SetTxPowerLevel()\n");
2635                 break;
2636         }
2637 }
2638 /****************************************************************************************
2639  *function:  This function set command table variable(struct SwChnlCmd).
2640  *   input:  SwChnlCmd*         CmdTable        //table to be set.
2641  *           u32                CmdTableIdx     //variable index in table to be set
2642  *           u32                CmdTableSz      //table size.
2643  *           SwChnlCmdID        CmdID           //command ID to set.
2644  *           u32                Para1
2645  *           u32                Para2
2646  *           u32                msDelay
2647  *  output:
2648  *  return:  true if finished, false otherwise
2649  *    Note:
2650  * ************************************************************************************/
2651 static u8 rtl8192_phy_SetSwChnlCmdArray(
2652         SwChnlCmd*              CmdTable,
2653         u32                     CmdTableIdx,
2654         u32                     CmdTableSz,
2655         SwChnlCmdID             CmdID,
2656         u32                     Para1,
2657         u32                     Para2,
2658         u32                     msDelay
2659         )
2660 {
2661         SwChnlCmd* pCmd;
2662
2663         if(CmdTable == NULL)
2664         {
2665                 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n");
2666                 return false;
2667         }
2668         if(CmdTableIdx >= CmdTableSz)
2669         {
2670                 RT_TRACE(COMP_ERR, "phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%d, CmdTableSz:%d\n",
2671                                 CmdTableIdx, CmdTableSz);
2672                 return false;
2673         }
2674
2675         pCmd = CmdTable + CmdTableIdx;
2676         pCmd->CmdID = CmdID;
2677         pCmd->Para1 = Para1;
2678         pCmd->Para2 = Para2;
2679         pCmd->msDelay = msDelay;
2680
2681         return true;
2682 }
2683 /******************************************************************************
2684  *function:  This function set channel step by step
2685  *   input:  struct net_device *dev
2686  *           u8                 channel
2687  *           u8*                stage //3 stages
2688  *           u8*                step  //
2689  *           u32*               delay //whether need to delay
2690  *  output:  store new stage, step and delay for next step(combine with function above)
2691  *  return:  true if finished, false otherwise
2692  *    Note:  Wait for simpler function to replace it //wb
2693  * ***************************************************************************/
2694 static u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8* stage, u8* step, u32* delay)
2695 {
2696         struct r8192_priv *priv = ieee80211_priv(dev);
2697 //      PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
2698         SwChnlCmd                               PreCommonCmd[MAX_PRECMD_CNT];
2699         u32                                     PreCommonCmdCnt;
2700         SwChnlCmd                               PostCommonCmd[MAX_POSTCMD_CNT];
2701         u32                                     PostCommonCmdCnt;
2702         SwChnlCmd                               RfDependCmd[MAX_RFDEPENDCMD_CNT];
2703         u32                                     RfDependCmdCnt;
2704         SwChnlCmd                               *CurrentCmd = NULL;
2705         //RF90_RADIO_PATH_E             eRFPath;
2706         u8              eRFPath;
2707 //      u32             RfRetVal;
2708 //      u8              RetryCnt;
2709
2710         RT_TRACE(COMP_TRACE, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
2711 //      RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
2712
2713 #ifdef ENABLE_DOT11D
2714         if (!IsLegalChannel(priv->ieee80211, channel))
2715         {
2716                 RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
2717                 return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
2718         }
2719 #endif
2720
2721         //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
2722         //for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
2723         {
2724                 //if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
2725                 //      return false;
2726                 // <1> Fill up pre common command.
2727                 PreCommonCmdCnt = 0;
2728                 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2729                                         CmdID_SetTxPowerLevel, 0, 0, 0);
2730                 rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
2731                                         CmdID_End, 0, 0, 0);
2732
2733                 // <2> Fill up post common command.
2734                 PostCommonCmdCnt = 0;
2735
2736                 rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
2737                                         CmdID_End, 0, 0, 0);
2738
2739                 // <3> Fill up RF dependent command.
2740                 RfDependCmdCnt = 0;
2741                 switch( priv->rf_chip )
2742                 {
2743                 case RF_8225:
2744                         if (!(channel >= 1 && channel <= 14))
2745                         {
2746                                 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8225: %d\n", channel);
2747                                 return false;
2748                         }
2749                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2750                                 CmdID_RF_WriteReg, rZebra1_Channel, RF_CHANNEL_TABLE_ZEBRA[channel], 10);
2751                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2752                                 CmdID_End, 0, 0, 0);
2753                         break;
2754
2755                 case RF_8256:
2756                         // TEST!! This is not the table for 8256!!
2757                         if (!(channel >= 1 && channel <= 14))
2758                         {
2759                                 RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
2760                                 return false;
2761                         }
2762                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2763                                 CmdID_RF_WriteReg, rZebra1_Channel, channel, 10);
2764                         rtl8192_phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
2765                         CmdID_End, 0, 0, 0);
2766                         break;
2767
2768                 case RF_8258:
2769                         break;
2770
2771                 default:
2772                         RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
2773                         return false;
2774                         break;
2775                 }
2776
2777
2778                 do{
2779                         switch(*stage)
2780                         {
2781                         case 0:
2782                                 CurrentCmd=&PreCommonCmd[*step];
2783                                 break;
2784                         case 1:
2785                                 CurrentCmd=&RfDependCmd[*step];
2786                                 break;
2787                         case 2:
2788                                 CurrentCmd=&PostCommonCmd[*step];
2789                                 break;
2790                         }
2791
2792                         if(CurrentCmd->CmdID==CmdID_End)
2793                         {
2794                                 if((*stage)==2)
2795                                 {
2796                                         return true;
2797                                 }
2798                                 else
2799                                 {
2800                                         (*stage)++;
2801                                         (*step)=0;
2802                                         continue;
2803                                 }
2804                         }
2805
2806                         switch(CurrentCmd->CmdID)
2807                         {
2808                         case CmdID_SetTxPowerLevel:
2809                                 if(priv->card_8192_version > (u8)VERSION_8190_BD) //xiong: consider it later!
2810                                         rtl8192_SetTxPowerLevel(dev,channel);
2811                                 break;
2812                         case CmdID_WritePortUlong:
2813                                 write_nic_dword(priv, CurrentCmd->Para1, CurrentCmd->Para2);
2814                                 break;
2815                         case CmdID_WritePortUshort:
2816                                 write_nic_word(priv, CurrentCmd->Para1, (u16)CurrentCmd->Para2);
2817                                 break;
2818                         case CmdID_WritePortUchar:
2819                                 write_nic_byte(priv, CurrentCmd->Para1, (u8)CurrentCmd->Para2);
2820                                 break;
2821                         case CmdID_RF_WriteReg:
2822                                 for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
2823                                         rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bMask12Bits, CurrentCmd->Para2<<7);
2824                                 break;
2825                         default:
2826                                 break;
2827                         }
2828
2829                         break;
2830                 }while(true);
2831         }/*for(Number of RF paths)*/
2832
2833         (*delay)=CurrentCmd->msDelay;
2834         (*step)++;
2835         return false;
2836 }
2837
2838 /******************************************************************************
2839  *function:  This function does acturally set channel work
2840  *   input:  struct net_device *dev
2841  *           u8                 channel
2842  *  output:  none
2843  *  return:  noin
2844  *    Note:  We should not call this function directly
2845  * ***************************************************************************/
2846 static void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
2847 {
2848         struct r8192_priv *priv = ieee80211_priv(dev);
2849         u32     delay = 0;
2850
2851         while(!rtl8192_phy_SwChnlStepByStep(dev,channel,&priv->SwChnlStage,&priv->SwChnlStep,&delay))
2852         {
2853                 if(delay>0)
2854                         msleep(delay);//or mdelay? need further consideration
2855                 if(!priv->up)
2856                         break;
2857         }
2858 }
2859 /******************************************************************************
2860  *function:  Callback routine of the work item for switch channel.
2861  *   input:
2862  *
2863  *  output:  none
2864  *  return:  noin
2865  * ***************************************************************************/
2866 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
2867 {
2868
2869         struct r8192_priv *priv = ieee80211_priv(dev);
2870
2871         RT_TRACE(COMP_TRACE, "==> SwChnlCallback819xUsbWorkItem()\n");
2872
2873         RT_TRACE(COMP_TRACE, "=====>--%s(), set chan:%d, priv:%p\n", __FUNCTION__, priv->chan, priv);
2874
2875         rtl8192_phy_FinishSwChnlNow(dev , priv->chan);
2876
2877         RT_TRACE(COMP_TRACE, "<== SwChnlCallback819xUsbWorkItem()\n");
2878 }
2879
2880 /******************************************************************************
2881  *function:  This function scheduled actural workitem to set channel
2882  *   input:  net_device dev
2883  *           u8         channel //channel to set
2884  *  output:  none
2885  *  return:  return code show if workitem is scheduled(1:pass, 0:fail)
2886  *    Note:  Delay may be required for RF configuration
2887  * ***************************************************************************/
2888 u8 rtl8192_phy_SwChnl(struct net_device* dev, u8 channel)
2889 {
2890         struct r8192_priv *priv = ieee80211_priv(dev);
2891         RT_TRACE(COMP_PHY, "=====>%s()\n", __FUNCTION__);
2892         if(!priv->up)
2893                 return false;
2894         if(priv->SwChnlInProgress)
2895                 return false;
2896
2897 //      if(pHalData->SetBWModeInProgress)
2898 //              return;
2899
2900         //--------------------------------------------
2901         switch(priv->ieee80211->mode)
2902         {
2903         case WIRELESS_MODE_A:
2904         case WIRELESS_MODE_N_5G:
2905                 if (channel<=14){
2906                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_A but channel<=14");
2907                         return false;
2908                 }
2909                 break;
2910         case WIRELESS_MODE_B:
2911                 if (channel>14){
2912                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_B but channel>14");
2913                         return false;
2914                 }
2915                 break;
2916         case WIRELESS_MODE_G:
2917         case WIRELESS_MODE_N_24G:
2918                 if (channel>14){
2919                         RT_TRACE(COMP_ERR, "WIRELESS_MODE_G but channel>14");
2920                         return false;
2921                 }
2922                 break;
2923         }
2924         //--------------------------------------------
2925
2926         priv->SwChnlInProgress = true;
2927         if(channel == 0)
2928                 channel = 1;
2929
2930         priv->chan=channel;
2931
2932         priv->SwChnlStage=0;
2933         priv->SwChnlStep=0;
2934 //      schedule_work(&(priv->SwChnlWorkItem));
2935 //      rtl8192_SwChnl_WorkItem(dev);
2936         if(priv->up) {
2937 //              queue_work(priv->priv_wq,&(priv->SwChnlWorkItem));
2938         rtl8192_SwChnl_WorkItem(dev);
2939         }
2940         priv->SwChnlInProgress = false;
2941         return true;
2942 }
2943
2944 static void CCK_Tx_Power_Track_BW_Switch_TSSI(struct net_device *dev    )
2945 {
2946         struct r8192_priv *priv = ieee80211_priv(dev);
2947
2948         switch(priv->CurrentChannelBW)
2949         {
2950                 /* 20 MHz channel*/
2951                 case HT_CHANNEL_WIDTH_20:
2952         //added by vivi, cck,tx power track, 20080703
2953                         priv->CCKPresentAttentuation =
2954                                 priv->CCKPresentAttentuation_20Mdefault + priv->CCKPresentAttentuation_difference;
2955
2956                         if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
2957                                 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
2958                         if(priv->CCKPresentAttentuation < 0)
2959                                 priv->CCKPresentAttentuation = 0;
2960
2961                         RT_TRACE(COMP_POWER_TRACKING, "20M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
2962
2963                         if(priv->ieee80211->current_network.channel== 14 && !priv->bcck_in_ch14)
2964                         {
2965                                 priv->bcck_in_ch14 = TRUE;
2966                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2967                         }
2968                         else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
2969                         {
2970                                 priv->bcck_in_ch14 = FALSE;
2971                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2972                         }
2973                         else
2974                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2975                 break;
2976
2977                 /* 40 MHz channel*/
2978                 case HT_CHANNEL_WIDTH_20_40:
2979                         //added by vivi, cck,tx power track, 20080703
2980                         priv->CCKPresentAttentuation =
2981                                 priv->CCKPresentAttentuation_40Mdefault + priv->CCKPresentAttentuation_difference;
2982
2983                         RT_TRACE(COMP_POWER_TRACKING, "40M, priv->CCKPresentAttentuation = %d\n", priv->CCKPresentAttentuation);
2984                         if(priv->CCKPresentAttentuation > (CCKTxBBGainTableLength-1))
2985                                 priv->CCKPresentAttentuation = CCKTxBBGainTableLength-1;
2986                         if(priv->CCKPresentAttentuation < 0)
2987                                 priv->CCKPresentAttentuation = 0;
2988
2989                         if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
2990                         {
2991                                 priv->bcck_in_ch14 = TRUE;
2992                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2993                         }
2994                         else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
2995                         {
2996                                 priv->bcck_in_ch14 = FALSE;
2997                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
2998                         }
2999                         else
3000                                 dm_cck_txpower_adjust(dev,priv->bcck_in_ch14);
3001                 break;
3002         }
3003 }
3004
3005 #ifndef RTL8190P
3006 static void CCK_Tx_Power_Track_BW_Switch_ThermalMeter(struct net_device *dev)
3007 {
3008         struct r8192_priv *priv = ieee80211_priv(dev);
3009
3010         if(priv->ieee80211->current_network.channel == 14 && !priv->bcck_in_ch14)
3011                 priv->bcck_in_ch14 = TRUE;
3012         else if(priv->ieee80211->current_network.channel != 14 && priv->bcck_in_ch14)
3013                 priv->bcck_in_ch14 = FALSE;
3014
3015         //write to default index and tx power track will be done in dm.
3016         switch(priv->CurrentChannelBW)
3017         {
3018                 /* 20 MHz channel*/
3019                 case HT_CHANNEL_WIDTH_20:
3020                         if(priv->Record_CCK_20Mindex == 0)
3021                                 priv->Record_CCK_20Mindex = 6;  //set default value.
3022                         priv->CCK_index = priv->Record_CCK_20Mindex;//6;
3023                         RT_TRACE(COMP_POWER_TRACKING, "20MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(),CCK_index = %d\n", priv->CCK_index);
3024                 break;
3025
3026                 /* 40 MHz channel*/
3027                 case HT_CHANNEL_WIDTH_20_40:
3028                         priv->CCK_index = priv->Record_CCK_40Mindex;//0;
3029                         RT_TRACE(COMP_POWER_TRACKING, "40MHz, CCK_Tx_Power_Track_BW_Switch_ThermalMeter(), CCK_index = %d\n", priv->CCK_index);
3030                 break;
3031         }
3032         dm_cck_txpower_adjust(dev, priv->bcck_in_ch14);
3033 }
3034 #endif
3035
3036 static void CCK_Tx_Power_Track_BW_Switch(struct net_device *dev)
3037 {
3038 #ifdef RTL8192E
3039         struct r8192_priv *priv = ieee80211_priv(dev);
3040 #endif
3041
3042 #ifdef RTL8190P
3043         CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
3044 #else
3045         //if(pHalData->bDcut == TRUE)
3046         if(priv->IC_Cut >= IC_VersionCut_D)
3047                 CCK_Tx_Power_Track_BW_Switch_TSSI(dev);
3048         else
3049                 CCK_Tx_Power_Track_BW_Switch_ThermalMeter(dev);
3050 #endif
3051 }
3052
3053
3054 //
3055 /******************************************************************************
3056  *function:  Callback routine of the work item for set bandwidth mode.
3057  *   input:  struct net_device *dev
3058  *           HT_CHANNEL_WIDTH   Bandwidth  //20M or 40M
3059  *           HT_EXTCHNL_OFFSET Offset      //Upper, Lower, or Don't care
3060  *  output:  none
3061  *  return:  none
3062  *    Note:  I doubt whether SetBWModeInProgress flag is necessary as we can
3063  *           test whether current work in the queue or not.//do I?
3064  * ***************************************************************************/
3065 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
3066 {
3067
3068         struct r8192_priv *priv = ieee80211_priv(dev);
3069         u8 regBwOpMode;
3070
3071         RT_TRACE(COMP_SWBW, "==>rtl8192_SetBWModeWorkItem()  Switch to %s bandwidth\n",
3072                                         priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz")
3073
3074
3075         if(priv->rf_chip== RF_PSEUDO_11N)
3076         {
3077                 priv->SetBWModeInProgress= false;
3078                 return;
3079         }
3080         if(!priv->up)
3081         {
3082                 priv->SetBWModeInProgress= false;
3083                 return;
3084         }
3085         //<1>Set MAC register
3086         regBwOpMode = read_nic_byte(priv, BW_OPMODE);
3087
3088         switch(priv->CurrentChannelBW)
3089         {
3090                 case HT_CHANNEL_WIDTH_20:
3091                         regBwOpMode |= BW_OPMODE_20MHZ;
3092                        // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3093                         write_nic_byte(priv, BW_OPMODE, regBwOpMode);
3094                         break;
3095
3096                 case HT_CHANNEL_WIDTH_20_40:
3097                         regBwOpMode &= ~BW_OPMODE_20MHZ;
3098                         // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
3099                         write_nic_byte(priv, BW_OPMODE, regBwOpMode);
3100                         break;
3101
3102                 default:
3103                         RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n",priv->CurrentChannelBW);
3104                         break;
3105         }
3106
3107         //<2>Set PHY related register
3108         switch(priv->CurrentChannelBW)
3109         {
3110                 case HT_CHANNEL_WIDTH_20:
3111                         // Add by Vivi 20071119
3112                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
3113                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
3114 //                      rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
3115
3116                         // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
3117 //                      write_nic_dword(dev, rCCK0_TxFilter1, 0x1a1b0000);
3118 //                      write_nic_dword(dev, rCCK0_TxFilter2, 0x090e1317);
3119 //                      write_nic_dword(dev, rCCK0_DebugPort, 0x00000204);
3120                         if(!priv->btxpower_tracking)
3121                         {
3122                                 write_nic_dword(priv, rCCK0_TxFilter1, 0x1a1b0000);
3123                                 write_nic_dword(priv, rCCK0_TxFilter2, 0x090e1317);
3124                                 write_nic_dword(priv, rCCK0_DebugPort, 0x00000204);
3125                         }
3126                         else
3127                                 CCK_Tx_Power_Track_BW_Switch(dev);
3128
3129 #ifdef RTL8190P
3130                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 1);
3131                         rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x44);    // 0xc30 is for 8190 only, Emily
3132 #else
3133         #ifdef RTL8192E
3134                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
3135         #endif
3136 #endif
3137
3138                         break;
3139                 case HT_CHANNEL_WIDTH_20_40:
3140                         // Add by Vivi 20071119
3141                         rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
3142                         rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
3143                         //rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3144                     //rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
3145                         //rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3146
3147                         // Correct the tx power for CCK rate in 40M. Suggest by YN, 20071207
3148                         //write_nic_dword(dev, rCCK0_TxFilter1, 0x35360000);
3149                         //write_nic_dword(dev, rCCK0_TxFilter2, 0x121c252e);
3150                         //write_nic_dword(dev, rCCK0_DebugPort, 0x00000409);
3151                         if(!priv->btxpower_tracking)
3152                         {
3153                                 write_nic_dword(priv, rCCK0_TxFilter1, 0x35360000);
3154                                 write_nic_dword(priv, rCCK0_TxFilter2, 0x121c252e);
3155                                 write_nic_dword(priv, rCCK0_DebugPort, 0x00000409);
3156                         }
3157                         else
3158                                 CCK_Tx_Power_Track_BW_Switch(dev);
3159
3160                         // Set Control channel to upper or lower. These settings are required only for 40MHz
3161                         rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
3162                         rtl8192_setBBreg(dev, rOFDM1_LSTF, 0xC00, priv->nCur40MhzPrimeSC);
3163
3164
3165 #ifdef RTL8190P
3166                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bADClkPhase, 0);
3167                         rtl8192_setBBreg(dev, rOFDM0_RxDetector1, bMaskByte0, 0x42);    // 0xc30 is for 8190 only, Emily
3168
3169                         // Set whether CCK should be sent in upper or lower channel. Suggest by YN. 20071207
3170                         // It is set in Tx descriptor for 8192x series
3171                         if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
3172                         {
3173                                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x01);
3174                         }else if(priv->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
3175                         {
3176                                 rtl8192_setBBreg(dev, rFPGA0_RFMOD, (BIT6|BIT5), 0x02);
3177                         }
3178
3179 #else
3180         #ifdef RTL8192E
3181                         rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 0);
3182         #endif
3183 #endif
3184                         break;
3185                 default:
3186                         RT_TRACE(COMP_ERR, "SetChannelBandwidth819xUsb(): unknown Bandwidth: %#X\n" ,priv->CurrentChannelBW);
3187                         break;
3188
3189         }
3190         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
3191
3192 #if 1
3193         //<3>Set RF related register
3194         switch( priv->rf_chip )
3195         {
3196                 case RF_8225:
3197 #ifdef TO_DO_LIST
3198                         PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
3199 #endif
3200                         break;
3201
3202                 case RF_8256:
3203                         PHY_SetRF8256Bandwidth(dev, priv->CurrentChannelBW);
3204                         break;
3205
3206                 case RF_8258:
3207                         // PHY_SetRF8258Bandwidth();
3208                         break;
3209
3210                 case RF_PSEUDO_11N:
3211                         // Do Nothing
3212                         break;
3213
3214                 default:
3215                         RT_TRACE(COMP_ERR, "Unknown RFChipID: %d\n", priv->rf_chip);
3216                         break;
3217         }
3218 #endif
3219         atomic_dec(&(priv->ieee80211->atm_swbw));
3220         priv->SetBWModeInProgress= false;
3221
3222         RT_TRACE(COMP_SWBW, "<==SetBWMode819xUsb()");
3223 }
3224
3225 /******************************************************************************
3226  *function:  This function schedules bandwith switch work.
3227  *   input:  struct net_device *dev
3228  *           HT_CHANNEL_WIDTH   Bandwidth  //20M or 40M
3229  *           HT_EXTCHNL_OFFSET Offset      //Upper, Lower, or Don't care
3230  *  output:  none
3231  *  return:  none
3232  *    Note:  I doubt whether SetBWModeInProgress flag is necessary as we can
3233  *           test whether current work in the queue or not.//do I?
3234  * ***************************************************************************/
3235 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH Bandwidth, HT_EXTCHNL_OFFSET Offset)
3236 {
3237         struct r8192_priv *priv = ieee80211_priv(dev);
3238
3239
3240         if(priv->SetBWModeInProgress)
3241                 return;
3242
3243          atomic_inc(&(priv->ieee80211->atm_swbw));
3244         priv->SetBWModeInProgress= true;
3245
3246         priv->CurrentChannelBW = Bandwidth;
3247
3248         if(Offset==HT_EXTCHNL_OFFSET_LOWER)
3249                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
3250         else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
3251                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
3252         else
3253                 priv->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
3254
3255         //queue_work(priv->priv_wq, &(priv->SetBWModeWorkItem));
3256         //      schedule_work(&(priv->SetBWModeWorkItem));
3257         rtl8192_SetBWModeWorkItem(dev);
3258
3259 }
3260
3261
3262 void InitialGain819xPci(struct net_device *dev, u8 Operation)
3263 {
3264 #define SCAN_RX_INITIAL_GAIN    0x17
3265 #define POWER_DETECTION_TH      0x08
3266         struct r8192_priv *priv = ieee80211_priv(dev);
3267         u32                                     BitMask;
3268         u8                                      initial_gain;
3269
3270         if(priv->up)
3271         {
3272                 switch(Operation)
3273                 {
3274                         case IG_Backup:
3275                         RT_TRACE(COMP_SCAN, "IG_Backup, backup the initial gain.\n");
3276                                 initial_gain = SCAN_RX_INITIAL_GAIN;//pHalData->DefaultInitialGain[0];//
3277                                 BitMask = bMaskByte0;
3278                                 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3279                                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
3280                                 priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, BitMask);
3281                                 priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, BitMask);
3282                                 priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, BitMask);
3283                                 priv->initgain_backup.xdagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XDAGCCore1, BitMask);
3284                                 BitMask  = bMaskByte2;
3285                                 priv->initgain_backup.cca               = (u8)rtl8192_QueryBBReg(dev, rCCK0_CCA, BitMask);
3286
3287                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3288                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3289                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3290                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3291                         RT_TRACE(COMP_SCAN, "Scan InitialGainBackup 0xa0a is %x\n",priv->initgain_backup.cca);
3292
3293                         RT_TRACE(COMP_SCAN, "Write scan initial gain = 0x%x \n", initial_gain);
3294                                 write_nic_byte(priv, rOFDM0_XAAGCCore1, initial_gain);
3295                                 write_nic_byte(priv, rOFDM0_XBAGCCore1, initial_gain);
3296                                 write_nic_byte(priv, rOFDM0_XCAGCCore1, initial_gain);
3297                                 write_nic_byte(priv, rOFDM0_XDAGCCore1, initial_gain);
3298                                 RT_TRACE(COMP_SCAN, "Write scan 0xa0a = 0x%x \n", POWER_DETECTION_TH);
3299                                 write_nic_byte(priv, 0xa0a, POWER_DETECTION_TH);
3300                                 break;
3301                         case IG_Restore:
3302                         RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
3303                                 BitMask = 0x7f; //Bit0~ Bit6
3304                                 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3305                                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
3306
3307                                 rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, BitMask, (u32)priv->initgain_backup.xaagccore1);
3308                                 rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, BitMask, (u32)priv->initgain_backup.xbagccore1);
3309                                 rtl8192_setBBreg(dev, rOFDM0_XCAGCCore1, BitMask, (u32)priv->initgain_backup.xcagccore1);
3310                                 rtl8192_setBBreg(dev, rOFDM0_XDAGCCore1, BitMask, (u32)priv->initgain_backup.xdagccore1);
3311                                 BitMask  = bMaskByte2;
3312                                 rtl8192_setBBreg(dev, rCCK0_CCA, BitMask, (u32)priv->initgain_backup.cca);
3313
3314                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc50 is %x\n",priv->initgain_backup.xaagccore1);
3315                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc58 is %x\n",priv->initgain_backup.xbagccore1);
3316                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc60 is %x\n",priv->initgain_backup.xcagccore1);
3317                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xc68 is %x\n",priv->initgain_backup.xdagccore1);
3318                         RT_TRACE(COMP_SCAN, "Scan BBInitialGainRestore 0xa0a is %x\n",priv->initgain_backup.cca);
3319
3320                                 rtl8192_phy_setTxPower(dev,priv->ieee80211->current_network.channel);
3321
3322
3323                                 if(dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
3324                                         rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   // FW DIG ON
3325                                 break;
3326                         default:
3327                         RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");
3328                                 break;
3329                 }
3330         }
3331 }
3332