drivers/staging/rtl8188eu/include/hal8188e_phy_cfg.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7 #ifndef __INC_HAL8188EPHYCFG_H__
   8 #define __INC_HAL8188EPHYCFG_H__
   9
  10
  11 /*--------------------------Define Parameters-------------------------------*/
  12 #define LOOP_LIMIT                      5
  13 #define MAX_STALL_TIME                  50              /* us */
  14 #define AntennaDiversityValue           0x80
  15 #define MAX_TXPWR_IDX_NMODE_92S         63
  16 #define Reset_Cnt_Limit                 3
  17
  18 #define MAX_AGGR_NUM                    0x07
  19
  20
  21 /*--------------------------Define Parameters-------------------------------*/
  22
  23
  24 /*------------------------------Define structure----------------------------*/
  25 enum sw_chnl_cmd_id {
  26         CmdID_End,
  27         CmdID_SetTxPowerLevel,
  28         CmdID_BBRegWrite10,
  29         CmdID_WritePortUlong,
  30         CmdID_WritePortUshort,
  31         CmdID_WritePortUchar,
  32         CmdID_RF_WriteReg,
  33 };
  34
  35 /* 1. Switch channel related */
  36 struct sw_chnl_cmd {
  37         enum sw_chnl_cmd_id CmdID;
  38         u32 Para1;
  39         u32 Para2;
  40         u32 msDelay;
  41 };
  42
  43 enum hw90_block {
  44         HW90_BLOCK_MAC = 0,
  45         HW90_BLOCK_PHY0 = 1,
  46         HW90_BLOCK_PHY1 = 2,
  47         HW90_BLOCK_RF = 3,
  48         HW90_BLOCK_MAXIMUM = 4, /*  Never use this */
  49 };
  50
  51 enum rf_radio_path {
  52         RF_PATH_A = 0,                  /* Radio Path A */
  53         RF_PATH_B = 1,                  /* Radio Path B */
  54 };
  55
  56 #define MAX_PG_GROUP 13
  57
  58 #define RF_PATH_MAX                     2
  59 #define         MAX_RF_PATH             RF_PATH_MAX
  60 #define         MAX_TX_COUNT            4 /* path numbers */
  61
  62 #define CHANNEL_MAX_NUMBER              14      /*  14 is the max chnl number */
  63 #define MAX_CHNL_GROUP_24G              6       /*  ch1~2, ch3~5, ch6~8,
  64                                                  *ch9~11, ch12~13, CH 14
  65                                                  * total three groups
  66                                                  */
  67 #define CHANNEL_GROUP_MAX_88E           6
  68
  69 enum wireless_mode {
  70         WIRELESS_MODE_UNKNOWN = 0x00,
  71         WIRELESS_MODE_A                 = BIT(2),
  72         WIRELESS_MODE_B                 = BIT(0),
  73         WIRELESS_MODE_G                 = BIT(1),
  74         WIRELESS_MODE_AUTO              = BIT(5),
  75         WIRELESS_MODE_N_24G             = BIT(3),
  76         WIRELESS_MODE_N_5G              = BIT(4),
  77         WIRELESS_MODE_AC                = BIT(6)
  78 };
  79
  80 enum phy_rate_tx_offset_area {
  81         RA_OFFSET_LEGACY_OFDM1,
  82         RA_OFFSET_LEGACY_OFDM2,
  83         RA_OFFSET_HT_OFDM1,
  84         RA_OFFSET_HT_OFDM2,
  85         RA_OFFSET_HT_OFDM3,
  86         RA_OFFSET_HT_OFDM4,
  87         RA_OFFSET_HT_CCK,
  88 };
  89
  90 struct bb_reg_def {
  91         u32 rfintfs;            /*  set software control: */
  92                                 /*      0x870~0x877[8 bytes] */
  93         u32 rfintfi;            /*  readback data: */
  94                                 /*      0x8e0~0x8e7[8 bytes] */
  95         u32 rfintfo;            /*  output data: */
  96                                 /*      0x860~0x86f [16 bytes] */
  97         u32 rfintfe;            /*  output enable: */
  98                                 /*      0x860~0x86f [16 bytes] */
  99         u32 rf3wireOffset;      /*  LSSI data: */
 100                                 /*      0x840~0x84f [16 bytes] */
 101         u32 rfLSSI_Select;      /*  BB Band Select: */
 102                                 /*      0x878~0x87f [8 bytes] */
 103         u32 rfTxGainStage;      /*  Tx gain stage: */
 104                                 /*      0x80c~0x80f [4 bytes] */
 105         u32 rfHSSIPara1;        /*  wire parameter control1 : */
 106                                 /*      0x820~0x823,0x828~0x82b,
 107                                  *      0x830~0x833, 0x838~0x83b [16 bytes]
 108                                  */
 109         u32 rfHSSIPara2;        /*  wire parameter control2 : */
 110                                 /*      0x824~0x827,0x82c~0x82f, 0x834~0x837,
 111                                  *      0x83c~0x83f [16 bytes]
 112                                  */
 113         u32 rfSwitchControl;    /* Tx Rx antenna control : */
 114                                 /*      0x858~0x85f [16 bytes] */
 115         u32 rfAGCControl1;      /* AGC parameter control1 : */
 116                                 /*      0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63,
 117                                  * 0xc68~0xc6b [16 bytes]
 118                                  */
 119         u32 rfAGCControl2;      /* AGC parameter control2 : */
 120                                 /*      0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67,
 121                                  *      0xc6c~0xc6f [16 bytes]
 122                                  */
 123         u32 rfRxIQImbalance;    /* OFDM Rx IQ imbalance matrix : */
 124                                 /*      0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27,
 125                                  *      0xc2c~0xc2f [16 bytes]
 126                                  */
 127         u32 rfRxAFE;            /* Rx IQ DC ofset and Rx digital filter,
 128                                  * Rx DC notch filter :
 129                                  */
 130                                 /*      0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23,
 131                                  *      0xc28~0xc2b [16 bytes]
 132                                  */
 133         u32 rfTxIQImbalance;    /* OFDM Tx IQ imbalance matrix */
 134                                 /*      0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93,
 135                                  *       0xc98~0xc9b [16 bytes]
 136                                  */
 137         u32 rfTxAFE;            /* Tx IQ DC Offset and Tx DFIR type */
 138                                 /*      0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97,
 139                                  *      0xc9c~0xc9f [16 bytes]
 140                                  */
 141         u32 rfLSSIReadBack;     /* LSSI RF readback data SI mode */
 142                                 /*      0x8a0~0x8af [16 bytes] */
 143         u32 rfLSSIReadBackPi;   /* LSSI RF readback data PI mode 0x8b8-8bc for
 144                                  * Path A and B
 145                                  */
 146 };
 147
 148 /*------------------------------Define structure----------------------------*/
 149
 150
 151 /*------------------------Export global variable----------------------------*/
 152 /*------------------------Export global variable----------------------------*/
 153
 154
 155 /*------------------------Export Marco Definition---------------------------*/
 156 /*------------------------Export Marco Definition---------------------------*/
 157
 158
 159 /*--------------------------Exported Function prototype---------------------*/
 160 /*  */
 161 /*  BB and RF register read/write */
 162 /*  */
 163
 164 /* Read initi reg value for tx power setting. */
 165 void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter);
 166
 167 /*  BB TX Power R/W */
 168 void PHY_GetTxPowerLevel8188E(struct adapter *adapter, u32 *powerlevel);
 169
 170 void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation);
 171
 172 /*  Call after initialization */
 173 void ChkFwCmdIoDone(struct adapter *adapter);
 174
 175 /*  BB/MAC/RF other monitor API */
 176 void PHY_SetRFPathSwitch_8188E(struct adapter *adapter, bool main);
 177
 178 void PHY_SwitchEphyParameter(struct adapter *adapter);
 179
 180 void PHY_EnableHostClkReq(struct adapter *adapter);
 181
 182 bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant);
 183
 184 /*--------------------------Exported Function prototype---------------------*/
 185
 186 #define PHY_SetMacReg   PHY_SetBBReg
 187
 188 #define SIC_HW_SUPPORT                  0
 189
 190 #define SIC_MAX_POLL_CNT                5
 191
 192 #define SIC_CMD_READY                   0
 193 #define SIC_CMD_WRITE                   1
 194 #define SIC_CMD_READ                    2
 195
 196 #define SIC_CMD_REG                     0x1EB           /*  1byte */
 197 #define SIC_ADDR_REG                    0x1E8           /*  1b9~1ba, 2 bytes */
 198 #define SIC_DATA_REG                    0x1EC           /*  1bc~1bf */
 199
 200 #endif  /*  __INC_HAL8192CPHYCFG_H */