drivers/staging/rtl8187se/r8185b_init.c

   1 /*
   2  * Copyright (c) Realtek Semiconductor Corp. All rights reserved.
   3  *
   4  * Module Name:
   5  *      r8185b_init.c
   6  *
   7  * Abstract:
   8  *      Hardware Initialization and Hardware IO for RTL8185B
   9  *
  10  * Major Change History:
  11  *      When            Who                             What
  12  *      ----------      ---------------         -------------------------------
  13  *      2006-11-15      Xiong                   Created
  14  *
  15  * Notes:
  16  *      This file is ported from RTL8185B Windows driver.
  17  *
  18  *
  19  */
  20
  21 /*--------------------------Include File------------------------------------*/
  22 #include <linux/spinlock.h>
  23 #include "r8180_hw.h"
  24 #include "r8180.h"
  25 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
  26 #include "r8180_93cx6.h"   /* Card EEPROM */
  27 #include "r8180_wx.h"
  28 #include "ieee80211/dot11d.h"
  29 /* #define CONFIG_RTL8180_IO_MAP */
  30 #define TC_3W_POLL_MAX_TRY_CNT 5
  31
  32 static u8 MAC_REG_TABLE[][2] =  {
  33         /*PAGA 0:       */
  34         /* 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185() */
  35         /* 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185(). */
  36         /* 0x1F0~0x1F8  set in MacConfig_85BASIC() */
  37         {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
  38         {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
  39         {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
  40         {0x94, 0x0F}, {0x95, 0x32},
  41         {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
  42         {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
  43         {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
  44         {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
  45         {0xff, 0x00},
  46
  47         /*PAGE 1: */
  48         /* For Flextronics system Logo PCIHCT failure: */
  49         /* 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1 */
  50         {0x5e, 0x01},
  51         {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
  52         {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
  53         {0x82, 0xFF}, {0x83, 0x03},
  54         {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, /* lzm add 080826 */
  55         {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22}, /* lzm add 080826 */
  56         {0xe2, 0x00},
  57
  58
  59         /* PAGE 2: */
  60         {0x5e, 0x02},
  61         {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
  62         {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
  63         {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
  64         {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
  65         {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
  66         {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
  67         {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
  68
  69         /* PAGA 0: */
  70         {0x5e, 0x00}, {0x9f, 0x03}
  71         };
  72
  73
  74 static u8  ZEBRA_AGC[] = {
  75         0,
  76         0x7E, 0x7E, 0x7E, 0x7E, 0x7D, 0x7C, 0x7B, 0x7A, 0x79, 0x78, 0x77, 0x76, 0x75, 0x74, 0x73, 0x72,
  77         0x71, 0x70, 0x6F, 0x6E, 0x6D, 0x6C, 0x6B, 0x6A, 0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62,
  78         0x48, 0x47, 0x46, 0x45, 0x44, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x08, 0x07,
  79         0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  80         0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x15, 0x16,
  81         0x17, 0x17, 0x18, 0x18, 0x19, 0x1a, 0x1a, 0x1b, 0x1b, 0x1c, 0x1c, 0x1d, 0x1d, 0x1d, 0x1e, 0x1e,
  82         0x1f, 0x1f, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x21, 0x22, 0x22, 0x22, 0x23, 0x23, 0x24,
  83         0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F
  84         };
  85
  86 static u32 ZEBRA_RF_RX_GAIN_TABLE[] = {
  87         0x0096, 0x0076, 0x0056, 0x0036, 0x0016, 0x01f6, 0x01d6, 0x01b6,
  88         0x0196, 0x0176, 0x00F7, 0x00D7, 0x00B7, 0x0097, 0x0077, 0x0057,
  89         0x0037, 0x00FB, 0x00DB, 0x00BB, 0x00FF, 0x00E3, 0x00C3, 0x00A3,
  90         0x0083, 0x0063, 0x0043, 0x0023, 0x0003, 0x01E3, 0x01C3, 0x01A3,
  91         0x0183, 0x0163, 0x0143, 0x0123, 0x0103
  92         };
  93
  94 static u8 OFDM_CONFIG[] = {
  95         /* OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX */
  96         /* OFDM reg0x3C[4]=1'b1: Enable RX power saving mode */
  97         /* ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test */
  98         /* 0x00 */
  99         0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
 100         0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
 101         /* 0x10 */
 102         0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
 103         0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
 104         /* 0x20 */
 105         0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
 106         0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
 107         /* 0x30 */
 108         0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
 109         0xD8, 0x3C, 0x7B, 0x10, 0x10
 110         };
 111
 112         /*---------------------------------------------------------------
 113          *      Hardware IO
 114          *      the code is ported from Windows source code
 115          *---------------------------------------------------------------
 116          */
 117
 118 void PlatformIOWrite1Byte(struct net_device *dev, u32 offset, u8 data)
 119 {
 120         write_nic_byte(dev, offset, data);
 121         read_nic_byte(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
 122 }
 123
 124 void PlatformIOWrite2Byte(struct net_device *dev, u32 offset, u16 data)
 125 {
 126         write_nic_word(dev, offset, data);
 127         read_nic_word(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
 128 }
 129
 130 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
 131
 132 void PlatformIOWrite4Byte(struct net_device *dev, u32 offset, u32 data)
 133 {
 134         if (offset == PhyAddr) {
 135         /* For Base Band configuration. */
 136                 unsigned char   cmdByte;
 137                 unsigned long   dataBytes;
 138                 unsigned char   idx;
 139                 u8              u1bTmp;
 140
 141                 cmdByte = (u8)(data & 0x000000ff);
 142                 dataBytes = data>>8;
 143
 144                 /*
 145                  *      071010, rcnjko:
 146                  *      The critical section is only BB read/write race condition.
 147                  *      Assumption:
 148                  *      1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
 149                  *      acquiring the spinlock in such context.
 150                  *      2. PlatformIOWrite4Byte() MUST NOT be recursive.
 151                  */
 152                 /* NdisAcquireSpinLock( &(pDevice->IoSpinLock) ); */
 153
 154                 for (idx = 0; idx < 30; idx++) {
 155                 /* Make sure command bit is clear before access it. */
 156                         u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
 157                         if ((u1bTmp & BIT7) == 0)
 158                                 break;
 159                         else
 160                                 mdelay(10);
 161                 }
 162
 163                 for (idx = 0; idx < 3; idx++)
 164                         PlatformIOWrite1Byte(dev, offset+1+idx, ((u8 *)&dataBytes)[idx]);
 165
 166                 write_nic_byte(dev, offset, cmdByte);
 167
 168                 /* NdisReleaseSpinLock( &(pDevice->IoSpinLock) ); */
 169         } else {
 170                 write_nic_dword(dev, offset, data);
 171                 read_nic_dword(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
 172         }
 173 }
 174
 175 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset)
 176 {
 177         u8      data = 0;
 178
 179         data = read_nic_byte(dev, offset);
 180
 181
 182         return data;
 183 }
 184
 185 u16 PlatformIORead2Byte(struct net_device *dev, u32 offset)
 186 {
 187         u16     data = 0;
 188
 189         data = read_nic_word(dev, offset);
 190
 191
 192         return data;
 193 }
 194
 195 u32 PlatformIORead4Byte(struct net_device *dev, u32 offset)
 196 {
 197         u32     data = 0;
 198
 199         data = read_nic_dword(dev, offset);
 200
 201
 202         return data;
 203 }
 204
 205 void SetOutputEnableOfRfPins(struct net_device *dev)
 206 {
 207         write_nic_word(dev, RFPinsEnable, 0x1bff);
 208 }
 209
 210 static bool HwHSSIThreeWire(struct net_device *dev,
 211                             u8 *pDataBuf,
 212                             bool write)
 213 {
 214         u8      TryCnt;
 215         u8      u1bTmp;
 216
 217         /* Check if WE and RE are cleared. */
 218         for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) {
 219                 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 220                 if ((u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0)
 221                         break;
 222
 223                 udelay(10);
 224         }
 225         if (TryCnt == TC_3W_POLL_MAX_TRY_CNT) {
 226                 netdev_err(dev,
 227                            "HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n",
 228                            u1bTmp);
 229         return false;
 230         }
 231
 232         /* RTL8187S HSSI Read/Write Function */
 233         u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 234         u1bTmp |= RF_SW_CFG_SI; /* reg08[1]=1 Serial Interface(SI) */
 235         write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 236
 237         /* jong: HW SI read must set reg84[3]=0. */
 238         u1bTmp = read_nic_byte(dev, RFPinsSelect);
 239         u1bTmp &= ~BIT3;
 240         write_nic_byte(dev, RFPinsSelect, u1bTmp);
 241         /*  Fill up data buffer for write operation. */
 242
 243         /* SI - reg274[3:0] : RF register's Address */
 244         if (write)
 245                 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 246         else
 247                 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 248
 249         /* Set up command: WE or RE. */
 250         if (write)
 251                 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 252         else
 253                 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 254
 255
 256         /* Check if DONE is set. */
 257         for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) {
 258                 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 259                 if (u1bTmp & SW_3W_CMD1_DONE)
 260                         break;
 261
 262                 udelay(10);
 263         }
 264
 265         write_nic_byte(dev, SW_3W_CMD1, 0);
 266
 267         /* Read back data for read operation. */
 268         if (!write) {
 269                 /* Serial Interface : reg363_362[11:0] */
 270                 *((u16 *)pDataBuf) = read_nic_word(dev, SI_DATA_READ);
 271                 *((u16 *)pDataBuf) &= 0x0FFF;
 272         }
 273
 274         return true;
 275 }
 276
 277 void RF_WriteReg(struct net_device *dev, u8 offset, u16 data)
 278 {
 279         u16 reg = (data << 4) | (offset & 0x0f);
 280         HwHSSIThreeWire(dev, (u8 *)&reg, true);
 281 }
 282
 283 u16 RF_ReadReg(struct net_device *dev, u8 offset)
 284 {
 285         u16 reg = offset & 0x0f;
 286         HwHSSIThreeWire(dev, (u8 *)&reg, false);
 287         return reg;
 288 }
 289
 290
 291 /* by Owen on 04/07/14 for writing BB register successfully */
 292 void WriteBBPortUchar(struct net_device *dev, u32 Data)
 293 {
 294         /* u8   TimeoutCounter; */
 295         u8      RegisterContent;
 296         u8      UCharData;
 297
 298         UCharData = (u8)((Data & 0x0000ff00) >> 8);
 299         PlatformIOWrite4Byte(dev, PhyAddr, Data);
 300         /* for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--) */
 301         {
 302                 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
 303                 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 304                 /*if(UCharData == RegisterContent)      */
 305                 /*      break;  */
 306         }
 307 }
 308
 309 u8 ReadBBPortUchar(struct net_device *dev, u32 addr)
 310 {
 311         /*u8    TimeoutCounter; */
 312         u8      RegisterContent;
 313
 314         PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
 315         RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 316
 317         return RegisterContent;
 318 }
 319 /*
 320  *      Description:
 321  *      Perform Antenna settings with antenna diversity on 87SE.
 322  *              Created by Roger, 2008.01.25.
 323  */
 324 bool SetAntennaConfig87SE(struct net_device *dev,
 325                           u8   DefaultAnt, /* 0: Main, 1: Aux. */
 326                           bool bAntDiversity) /* 1:Enable, 0: Disable. */
 327 {
 328         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 329         bool   bAntennaSwitched = true;
 330
 331         /* printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity); */
 332
 333         /* Threshold for antenna diversity. */
 334         write_phy_cck(dev, 0x0c, 0x09); /* Reg0c : 09 */
 335
 336         if (bAntDiversity) {    /*      Enable Antenna Diversity. */
 337                 if (DefaultAnt == 1) {  /* aux antenna */
 338
 339                         /* Mac register, aux antenna */
 340                         write_nic_byte(dev, ANTSEL, 0x00);
 341
 342                         /* Config CCK RX antenna. */
 343                         write_phy_cck(dev, 0x11, 0xbb); /* Reg11 : bb */
 344                         write_phy_cck(dev, 0x01, 0xc7); /* Reg01 : c7 */
 345
 346                         /* Config OFDM RX antenna. */
 347                         write_phy_ofdm(dev, 0x0D, 0x54);        /* Reg0d : 54 */
 348                         write_phy_ofdm(dev, 0x18, 0xb2);        /* Reg18 : b2 */
 349                 } else { /*  use main antenna */
 350                         /* Mac register, main antenna */
 351                         write_nic_byte(dev, ANTSEL, 0x03);
 352                         /* base band */
 353                         /*  Config CCK RX antenna. */
 354                         write_phy_cck(dev, 0x11, 0x9b); /* Reg11 : 9b */
 355                         write_phy_cck(dev, 0x01, 0xc7); /* Reg01 : c7 */
 356
 357                         /* Config OFDM RX antenna. */
 358                         write_phy_ofdm(dev, 0x0d, 0x5c);  /* Reg0d : 5c */
 359                         write_phy_ofdm(dev, 0x18, 0xb2);  /* Reg18 : b2 */
 360                 }
 361         } else {
 362                 /* Disable Antenna Diversity. */
 363                 if (DefaultAnt == 1) { /* aux Antenna */
 364                         /* Mac register, aux antenna */
 365                         write_nic_byte(dev, ANTSEL, 0x00);
 366
 367                         /* Config CCK RX antenna. */
 368                         write_phy_cck(dev, 0x11, 0xbb); /* Reg11 : bb */
 369                         write_phy_cck(dev, 0x01, 0x47); /* Reg01 : 47 */
 370
 371                         /* Config OFDM RX antenna. */
 372                         write_phy_ofdm(dev, 0x0D, 0x54);        /* Reg0d : 54 */
 373                         write_phy_ofdm(dev, 0x18, 0x32);        /* Reg18 : 32 */
 374                 } else { /* main Antenna */
 375                         /* Mac register, main antenna */
 376                         write_nic_byte(dev, ANTSEL, 0x03);
 377
 378                         /* Config CCK RX antenna.       */
 379                         write_phy_cck(dev, 0x11, 0x9b); /* Reg11 : 9b */
 380                         write_phy_cck(dev, 0x01, 0x47); /* Reg01 : 47 */
 381
 382                         /* Config OFDM RX antenna. */
 383                         write_phy_ofdm(dev, 0x0D, 0x5c); /* Reg0d : 5c */
 384                         write_phy_ofdm(dev, 0x18, 0x32); /*Reg18 : 32 */
 385                 }
 386         }
 387         priv->CurrAntennaIndex = DefaultAnt; /* Update default settings. */
 388         return  bAntennaSwitched;
 389 }
 390 /*
 391  *--------------------------------------------------------------
 392  *              Hardware Initialization.
 393  *              the code is ported from Windows source code
 394  *--------------------------------------------------------------
 395  */
 396
 397 void ZEBRA_Config_85BASIC_HardCode(struct net_device *dev)
 398 {
 399
 400         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 401         u32                     i;
 402         u32     addr, data;
 403         u32 u4bRegOffset, u4bRegValue;
 404         u16 u4bRF23, u4bRF24;
 405         u8                      u1b24E;
 406         int d_cut = 0;
 407
 408
 409 /*
 410  *===========================================================================
 411  *      87S_PCIE :: RADIOCFG.TXT
 412  *===========================================================================
 413  */
 414
 415
 416         /* Page1 : reg16-reg30 */
 417         RF_WriteReg(dev, 0x00, 0x013f);         mdelay(1); /* switch to page1 */
 418         u4bRF23 = RF_ReadReg(dev, 0x08);        mdelay(1);
 419         u4bRF24 = RF_ReadReg(dev, 0x09);        mdelay(1);
 420
 421         if (u4bRF23 == 0x818 && u4bRF24 == 0x70C) {
 422                 d_cut = 1;
 423                 netdev_info(dev, "card type changed from C- to D-cut\n");
 424         }
 425
 426         /* Page0 : reg0-reg15 */
 427
 428         RF_WriteReg(dev, 0x00, 0x009f);         mdelay(1);/* 1  */
 429         RF_WriteReg(dev, 0x01, 0x06e0);         mdelay(1);
 430         RF_WriteReg(dev, 0x02, 0x004d);         mdelay(1);/* 2  */
 431         RF_WriteReg(dev, 0x03, 0x07f1);         mdelay(1);/* 3  */
 432         RF_WriteReg(dev, 0x04, 0x0975);         mdelay(1);
 433         RF_WriteReg(dev, 0x05, 0x0c72);         mdelay(1);
 434         RF_WriteReg(dev, 0x06, 0x0ae6);         mdelay(1);
 435         RF_WriteReg(dev, 0x07, 0x00ca);         mdelay(1);
 436         RF_WriteReg(dev, 0x08, 0x0e1c);         mdelay(1);
 437         RF_WriteReg(dev, 0x09, 0x02f0);         mdelay(1);
 438         RF_WriteReg(dev, 0x0a, 0x09d0);         mdelay(1);
 439         RF_WriteReg(dev, 0x0b, 0x01ba);         mdelay(1);
 440         RF_WriteReg(dev, 0x0c, 0x0640);         mdelay(1);
 441         RF_WriteReg(dev, 0x0d, 0x08df);         mdelay(1);
 442         RF_WriteReg(dev, 0x0e, 0x0020);         mdelay(1);
 443         RF_WriteReg(dev, 0x0f, 0x0990);         mdelay(1);
 444
 445         /*  Page1 : reg16-reg30 */
 446         RF_WriteReg(dev, 0x00, 0x013f);         mdelay(1);
 447         RF_WriteReg(dev, 0x03, 0x0806);         mdelay(1);
 448         RF_WriteReg(dev, 0x04, 0x03a7);         mdelay(1);
 449         RF_WriteReg(dev, 0x05, 0x059b);         mdelay(1);
 450         RF_WriteReg(dev, 0x06, 0x0081);         mdelay(1);
 451         RF_WriteReg(dev, 0x07, 0x01A0);         mdelay(1);
 452 /* Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl. */
 453         RF_WriteReg(dev, 0x0a, 0x0001);         mdelay(1);
 454         RF_WriteReg(dev, 0x0b, 0x0418);         mdelay(1);
 455
 456         if (d_cut) {
 457                 RF_WriteReg(dev, 0x0c, 0x0fbe);         mdelay(1);
 458                 RF_WriteReg(dev, 0x0d, 0x0008);         mdelay(1);
 459                 RF_WriteReg(dev, 0x0e, 0x0807);         mdelay(1); /* RX LO buffer */
 460         } else {
 461                 RF_WriteReg(dev, 0x0c, 0x0fbe);         mdelay(1);
 462                 RF_WriteReg(dev, 0x0d, 0x0008);         mdelay(1);
 463                 RF_WriteReg(dev, 0x0e, 0x0806);         mdelay(1); /* RX LO buffer */
 464         }
 465
 466         RF_WriteReg(dev, 0x0f, 0x0acc);         mdelay(1);
 467         RF_WriteReg(dev, 0x00, 0x01d7);         mdelay(1); /* 6 */
 468         RF_WriteReg(dev, 0x03, 0x0e00);         mdelay(1);
 469         RF_WriteReg(dev, 0x04, 0x0e50);         mdelay(1);
 470
 471         for (i = 0; i <= 36; i++) {
 472                 RF_WriteReg(dev, 0x01, i);              mdelay(1);
 473                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
 474         }
 475
 476         RF_WriteReg(dev, 0x05, 0x0203);         mdelay(1); /* 203, 343 */
 477         RF_WriteReg(dev, 0x06, 0x0200);         mdelay(1); /* 400 */
 478         RF_WriteReg(dev, 0x00, 0x0137);         mdelay(1); /* switch to reg16-reg30, and HSSI disable 137 */
 479         mdelay(10); /* Deay 10 ms. */           /* 0xfd */
 480
 481         RF_WriteReg(dev, 0x0d, 0x0008);         mdelay(1); /* Z4 synthesizer loop filter setting, 392 */
 482         mdelay(10); /* Deay 10 ms. */           /* 0xfd */
 483
 484         RF_WriteReg(dev, 0x00, 0x0037);         mdelay(1); /* switch to reg0-reg15, and HSSI disable */
 485         mdelay(10); /* Deay 10 ms. */           /* 0xfd */
 486
 487         RF_WriteReg(dev, 0x04, 0x0160);         mdelay(1); /* CBC on, Tx Rx disable, High gain */
 488         mdelay(10); /* Deay 10 ms. */           /* 0xfd */
 489
 490         RF_WriteReg(dev, 0x07, 0x0080);         mdelay(1); /* Z4 setted channel 1 */
 491         mdelay(10); /* Deay 10 ms. */           /* 0xfd */
 492
 493         RF_WriteReg(dev, 0x02, 0x088D);         mdelay(1); /* LC calibration */
 494         mdelay(200); /* Deay 200 ms. */         /* 0xfd */
 495         mdelay(10);  /* Deay 10 ms. */          /* 0xfd */
 496         mdelay(10);  /* Deay 10 ms. */          /* 0xfd */
 497
 498         RF_WriteReg(dev, 0x00, 0x0137);         mdelay(1); /* switch to reg16-reg30 137, and HSSI disable 137 */
 499         mdelay(10); /* Deay 10 ms. */           /* 0xfd */
 500
 501         RF_WriteReg(dev, 0x07, 0x0000);         mdelay(1);
 502         RF_WriteReg(dev, 0x07, 0x0180);         mdelay(1);
 503         RF_WriteReg(dev, 0x07, 0x0220);         mdelay(1);
 504         RF_WriteReg(dev, 0x07, 0x03E0);         mdelay(1);
 505
 506         /* DAC calibration off 20070702 */
 507         RF_WriteReg(dev, 0x06, 0x00c1);         mdelay(1);
 508         RF_WriteReg(dev, 0x0a, 0x0001);         mdelay(1);
 509         /* For crystal calibration, added by Roger, 2007.12.11. */
 510         if (priv->bXtalCalibration) { /* reg 30.        */
 511          /*
 512           *  enable crystal calibration.
 513           *             RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
 514           *             (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
 515           *             (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
 516           *             So we should minus 4 BITs offset.
 517           */
 518                 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11 | BIT9); mdelay(1);
 519                 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
 520                       (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11 | BIT9);
 521         } else {
 522                 /* using default value. Xin=6, Xout=6.  */
 523                 RF_WriteReg(dev, 0x0f, 0x0acc);         mdelay(1);
 524         }
 525
 526         RF_WriteReg(dev, 0x00, 0x00bf);         mdelay(1); /* switch to reg0-reg15, and HSSI enable */
 527         RF_WriteReg(dev, 0x0d, 0x08df);         mdelay(1); /* Rx BB start calibration, 00c//+edward */
 528         RF_WriteReg(dev, 0x02, 0x004d);         mdelay(1); /* temperature meter off */
 529         RF_WriteReg(dev, 0x04, 0x0975);         mdelay(1); /* Rx mode */
 530         mdelay(10);     /* Deay 10 ms.*/        /* 0xfe */
 531         mdelay(10);     /* Deay 10 ms.*/        /* 0xfe */
 532         mdelay(10);     /* Deay 10 ms.*/        /* 0xfe */
 533         RF_WriteReg(dev, 0x00, 0x0197);         mdelay(1); /* Rx mode*/ /*+edward */
 534         RF_WriteReg(dev, 0x05, 0x05ab);         mdelay(1); /* Rx mode*/ /*+edward */
 535         RF_WriteReg(dev, 0x00, 0x009f);         mdelay(1); /* Rx mode*/ /*+edward */
 536         RF_WriteReg(dev, 0x01, 0x0000);         mdelay(1); /* Rx mode*/ /*+edward */
 537         RF_WriteReg(dev, 0x02, 0x0000);         mdelay(1); /* Rx mode*/ /*+edward */
 538         /* power save parameters. */
 539         u1b24E = read_nic_byte(dev, 0x24E);
 540         write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
 541
 542         /*=============================================================================
 543          *
 544          *===========================================================================
 545          * CCKCONF.TXT
 546          *===========================================================================
 547          *
 548          *      [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
 549          *      CCK reg0x00[7]=1'b1 :power saving for TX (default)
 550          *      CCK reg0x00[6]=1'b1: power saving for RX (default)
 551          *      CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
 552          *      CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
 553          *      CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
 554          */
 555
 556         write_phy_cck(dev, 0x00, 0xc8);
 557         write_phy_cck(dev, 0x06, 0x1c);
 558         write_phy_cck(dev, 0x10, 0x78);
 559         write_phy_cck(dev, 0x2e, 0xd0);
 560         write_phy_cck(dev, 0x2f, 0x06);
 561         write_phy_cck(dev, 0x01, 0x46);
 562
 563         /* power control */
 564         write_nic_byte(dev, CCK_TXAGC, 0x10);
 565         write_nic_byte(dev, OFDM_TXAGC, 0x1B);
 566         write_nic_byte(dev, ANTSEL, 0x03);
 567
 568
 569
 570         /*
 571          *===========================================================================
 572          *      AGC.txt
 573          *===========================================================================
 574          */
 575
 576         write_phy_ofdm(dev, 0x00, 0x12);
 577
 578         for (i = 0; i < 128; i++) {
 579
 580                 data = ZEBRA_AGC[i+1];
 581                 data = data << 8;
 582                 data = data | 0x0000008F;
 583
 584                 addr = i + 0x80; /* enable writing AGC table */
 585                 addr = addr << 8;
 586                 addr = addr | 0x0000008E;
 587
 588                 WriteBBPortUchar(dev, data);
 589                 WriteBBPortUchar(dev, addr);
 590                 WriteBBPortUchar(dev, 0x0000008E);
 591         }
 592
 593         PlatformIOWrite4Byte(dev, PhyAddr, 0x00001080); /* Annie, 2006-05-05 */
 594
 595         /*
 596          *===========================================================================
 597          *
 598          *===========================================================================
 599          * OFDMCONF.TXT
 600          *===========================================================================
 601          */
 602
 603         for (i = 0; i < 60; i++) {
 604                 u4bRegOffset = i;
 605                 u4bRegValue = OFDM_CONFIG[i];
 606
 607                 WriteBBPortUchar(dev,
 608                                 (0x00000080 |
 609                                 (u4bRegOffset & 0x7f) |
 610                                 ((u4bRegValue & 0xff) << 8)));
 611         }
 612
 613         /*
 614          *===========================================================================
 615          * by amy for antenna
 616          *===========================================================================
 617          */
 618         /* Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.   */
 619         SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
 620 }
 621
 622
 623 void UpdateInitialGain(struct net_device *dev)
 624 {
 625         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 626
 627         /* lzm add 080826 */
 628         if (priv->eRFPowerState != eRfOn) {
 629                 /*      Don't access BB/RF under disable PLL situation.
 630                  *      RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
 631                  *      Back to the original state
 632                  */
 633                 priv->InitialGain = priv->InitialGainBackUp;
 634                 return;
 635         }
 636
 637         switch (priv->InitialGain) {
 638         case 1: /* m861dBm */
 639                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
 640                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 641                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
 642                 break;
 643
 644         case 2: /* m862dBm */
 645                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
 646                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 647                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
 648                 break;
 649
 650         case 3: /* m863dBm */
 651                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
 652                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 653                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
 654                 break;
 655
 656         case 4: /* m864dBm */
 657                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
 658                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 659                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
 660                 break;
 661
 662         case 5: /* m82dBm */
 663                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
 664                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
 665                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
 666                 break;
 667
 668         case 6: /* m78dBm */
 669                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
 670                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
 671                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
 672                 break;
 673
 674         case 7: /* m74dBm */
 675                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
 676                 write_phy_ofdm(dev, 0x24, 0xa6);        mdelay(1);
 677                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
 678                 break;
 679
 680         case 8:
 681                 write_phy_ofdm(dev, 0x17, 0x66);        mdelay(1);
 682                 write_phy_ofdm(dev, 0x24, 0xb6);        mdelay(1);
 683                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
 684                 break;
 685
 686         default: /* MP */
 687                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
 688                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 689                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
 690                 break;
 691         }
 692 }
 693 /*
 694  *      Description:
 695  *              Tx Power tracking mechanism routine on 87SE.
 696  *      Created by Roger, 2007.12.11.
 697  */
 698 void InitTxPwrTracking87SE(struct net_device *dev)
 699 {
 700         u32     u4bRfReg;
 701
 702         u4bRfReg = RF_ReadReg(dev, 0x02);
 703
 704         /* Enable Thermal meter indication.     */
 705         RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN);                  mdelay(1);
 706 }
 707
 708 void PhyConfig8185(struct net_device *dev)
 709 {
 710         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 711                 write_nic_dword(dev, RCR, priv->ReceiveConfig);
 712            priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
 713         /*  RF config */
 714         ZEBRA_Config_85BASIC_HardCode(dev);
 715         /* Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06. */
 716         if (priv->bDigMechanism) {
 717                 if (priv->InitialGain == 0)
 718                         priv->InitialGain = 4;
 719         }
 720
 721         /*
 722          *      Enable thermal meter indication to implement TxPower tracking on 87SE.
 723          *      We initialize thermal meter here to avoid unsuccessful configuration.
 724          *      Added by Roger, 2007.12.11.
 725          */
 726         if (priv->bTxPowerTrack)
 727                 InitTxPwrTracking87SE(dev);
 728
 729         priv->InitialGainBackUp = priv->InitialGain;
 730         UpdateInitialGain(dev);
 731
 732         return;
 733 }
 734
 735 void HwConfigureRTL8185(struct net_device *dev)
 736 {
 737         /* RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control. */
 738         u8 bUNIVERSAL_CONTROL_RL = 0;
 739         u8 bUNIVERSAL_CONTROL_AGC = 1;
 740         u8 bUNIVERSAL_CONTROL_ANT = 1;
 741         u8 bAUTO_RATE_FALLBACK_CTL = 1;
 742         u8 val8;
 743         write_nic_word(dev, BRSR, 0x0fff);
 744         /* Retry limit */
 745         val8 = read_nic_byte(dev, CW_CONF);
 746
 747         if (bUNIVERSAL_CONTROL_RL)
 748                 val8 = val8 & 0xfd;
 749         else
 750                 val8 = val8 | 0x02;
 751
 752         write_nic_byte(dev, CW_CONF, val8);
 753
 754         /* Tx AGC */
 755         val8 = read_nic_byte(dev, TXAGC_CTL);
 756         if (bUNIVERSAL_CONTROL_AGC) {
 757                 write_nic_byte(dev, CCK_TXAGC, 128);
 758                 write_nic_byte(dev, OFDM_TXAGC, 128);
 759                 val8 = val8 & 0xfe;
 760         } else {
 761                 val8 = val8 | 0x01 ;
 762         }
 763
 764
 765         write_nic_byte(dev, TXAGC_CTL, val8);
 766
 767         /* Tx Antenna including Feedback control */
 768         val8 = read_nic_byte(dev, TXAGC_CTL);
 769
 770         if (bUNIVERSAL_CONTROL_ANT) {
 771                 write_nic_byte(dev, ANTSEL, 0x00);
 772                 val8 = val8 & 0xfd;
 773         } else {
 774                 val8 = val8 & (val8|0x02); /* xiong-2006-11-15 */
 775         }
 776
 777         write_nic_byte(dev, TXAGC_CTL, val8);
 778
 779         /* Auto Rate fallback control   */
 780         val8 = read_nic_byte(dev, RATE_FALLBACK);
 781         val8 &= 0x7c;
 782         if (bAUTO_RATE_FALLBACK_CTL) {
 783                 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
 784
 785                 /* <RJ_TODO_8185B> We shall set up the ARFR according to user's setting. */
 786                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); /* set 1M ~ 54Mbps. */
 787         }
 788         write_nic_byte(dev, RATE_FALLBACK, val8);
 789 }
 790
 791 static void MacConfig_85BASIC_HardCode(struct net_device *dev)
 792 {
 793         /*
 794          *==========================================================================
 795          * MACREG.TXT
 796          *==========================================================================
 797          */
 798         int nLinesRead = 0;
 799         u32 u4bRegOffset, u4bRegValue, u4bPageIndex = 0;
 800         int i;
 801
 802         nLinesRead = sizeof(MAC_REG_TABLE)/2;
 803
 804         for (i = 0; i < nLinesRead; i++) { /* nLinesRead=101 */
 805                 u4bRegOffset = MAC_REG_TABLE[i][0];
 806                 u4bRegValue = MAC_REG_TABLE[i][1];
 807
 808                                 if (u4bRegOffset == 0x5e)
 809                                         u4bPageIndex = u4bRegValue;
 810                                 else
 811                                         u4bRegOffset |= (u4bPageIndex << 8);
 812
 813                 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
 814         }
 815         /* ============================================================================ */
 816 }
 817
 818 static void MacConfig_85BASIC(struct net_device *dev)
 819 {
 820
 821         u8                      u1DA;
 822         MacConfig_85BASIC_HardCode(dev);
 823
 824         /* ============================================================================ */
 825
 826         /* Follow TID_AC_MAP of WMac. */
 827         write_nic_word(dev, TID_AC_MAP, 0xfa50);
 828
 829         /* Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko. */
 830         write_nic_word(dev, IntMig, 0x0000);
 831
 832         /* Prevent TPC to cause CRC error. Added by Annie, 2006-06-10. */
 833         PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
 834         PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
 835         PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
 836
 837         /* Asked for by SD3 CM Lin, 2006.06.27, by rcnjko. */
 838         /* power save parameter based on "87SE power save parameters 20071127.doc", as follow. */
 839
 840         /* Enable DA10 TX power saving */
 841         u1DA = read_nic_byte(dev, PHYPR);
 842         write_nic_byte(dev, PHYPR, (u1DA | BIT2));
 843
 844         /* POWER: */
 845         write_nic_word(dev, 0x360, 0x1000);
 846         write_nic_word(dev, 0x362, 0x1000);
 847
 848         /* AFE. */
 849         write_nic_word(dev, 0x370, 0x0560);
 850         write_nic_word(dev, 0x372, 0x0560);
 851         write_nic_word(dev, 0x374, 0x0DA4);
 852         write_nic_word(dev, 0x376, 0x0DA4);
 853         write_nic_word(dev, 0x378, 0x0560);
 854         write_nic_word(dev, 0x37A, 0x0560);
 855         write_nic_word(dev, 0x37C, 0x00EC);
 856         write_nic_word(dev, 0x37E, 0x00EC); /* +edward */
 857         write_nic_byte(dev, 0x24E, 0x01);
 858 }
 859
 860 u8 GetSupportedWirelessMode8185(struct net_device *dev)
 861 {
 862         return WIRELESS_MODE_B | WIRELESS_MODE_G;
 863 }
 864
 865 void ActUpdateChannelAccessSetting(struct net_device *dev,
 866                                    WIRELESS_MODE WirelessMode,
 867                                    PCHANNEL_ACCESS_SETTING ChnlAccessSetting)
 868 {
 869         struct          r8180_priv *priv = ieee80211_priv(dev);
 870         struct          ieee80211_device *ieee = priv->ieee80211;
 871         AC_CODING       eACI;
 872         AC_PARAM        AcParam;
 873         u8              bFollowLegacySetting = 0;
 874         u8              u1bAIFS;
 875
 876         /*
 877          *      <RJ_TODO_8185B>
 878          *      TODO: We still don't know how to set up these registers, just follow WMAC to
 879          *      verify 8185B FPAG.
 880          *
 881          *      <RJ_TODO_8185B>
 882          *      Jong said CWmin/CWmax register are not functional in 8185B,
 883          *      so we shall fill channel access realted register into AC parameter registers,
 884          *      even in nQBss.
 885          */
 886         ChnlAccessSetting->SIFS_Timer = 0x22; /* Suggested by Jong, 2005.12.08. */
 887         ChnlAccessSetting->DIFS_Timer = 0x1C; /* 2006.06.02, by rcnjko. */
 888         ChnlAccessSetting->SlotTimeTimer = 9; /* 2006.06.02, by rcnjko. */
 889         ChnlAccessSetting->EIFS_Timer = 0x5B; /* Suggested by wcchu, it is the default value of EIFS register, 2005.12.08. */
 890         ChnlAccessSetting->CWminIndex = 3; /* 2006.06.02, by rcnjko. */
 891         ChnlAccessSetting->CWmaxIndex = 7; /* 2006.06.02, by rcnjko. */
 892
 893         write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
 894         write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer); /* Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29. */
 895
 896         u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer);
 897
 898         write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
 899
 900         write_nic_byte(dev, AckTimeOutReg, 0x5B); /* <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08. */
 901
 902         { /* Legacy 802.11. */
 903                 bFollowLegacySetting = 1;
 904
 905         }
 906
 907         /* this setting is copied from rtl8187B.  xiong-2006-11-13 */
 908         if (bFollowLegacySetting) {
 909
 910                 /*
 911                  *      Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
 912                  *      2005.12.01, by rcnjko.
 913                  */
 914                 AcParam.longData = 0;
 915                 AcParam.f.AciAifsn.f.AIFSN = 2; /* Follow 802.11 DIFS.  */
 916                 AcParam.f.AciAifsn.f.ACM = 0;
 917                 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; /* Follow 802.11 CWmin. */
 918                 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; /* Follow 802.11 CWmax. */
 919                 AcParam.f.TXOPLimit = 0;
 920
 921                 /* lzm reserved 080826 */
 922                 /* For turbo mode setting. port from 87B by Isaiah 2008-08-01 */
 923                 if (ieee->current_network.Turbo_Enable == 1)
 924                         AcParam.f.TXOPLimit = 0x01FF;
 925                 /* For 87SE with Intel 4965  Ad-Hoc mode have poor throughput (19MB) */
 926                 if (ieee->iw_mode == IW_MODE_ADHOC)
 927                         AcParam.f.TXOPLimit = 0x0020;
 928
 929                 for (eACI = 0; eACI < AC_MAX; eACI++) {
 930                         AcParam.f.AciAifsn.f.ACI = (u8)eACI;
 931                         {
 932                                 PAC_PARAM       pAcParam = (PAC_PARAM)(&AcParam);
 933                                 AC_CODING       eACI;
 934                                 u8              u1bAIFS;
 935                                 u32             u4bAcParam;
 936
 937                                 /*  Retrieve parameters to update. */
 938                                 eACI = pAcParam->f.AciAifsn.f.ACI;
 939                                 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
 940                                 u4bAcParam = ((((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET)    |
 941                                                 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET)  |
 942                                                 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET)  |
 943                                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
 944
 945                                 switch (eACI) {
 946                                 case AC1_BK:
 947                                         /* write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); */
 948                                         break;
 949
 950                                 case AC0_BE:
 951                                         /* write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); */
 952                                         break;
 953
 954                                 case AC2_VI:
 955                                         /* write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); */
 956                                         break;
 957
 958                                 case AC3_VO:
 959                                         /* write_nic_dword(dev, AC_BK_PARAM, u4bAcParam); */
 960                                         break;
 961
 962                                 default:
 963                                         DMESGW("SetHwReg8185(): invalid ACI: %d !\n", eACI);
 964                                         break;
 965                                 }
 966
 967                                 /* Cehck ACM bit. */
 968                                 /* If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13. */
 969                                 {
 970                                         PACI_AIFSN      pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
 971                                         AC_CODING       eACI = pAciAifsn->f.ACI;
 972
 973                                         /*for 8187B AsynIORead issue */
 974                                         u8      AcmCtrl = 0;
 975                                         if (pAciAifsn->f.ACM) {
 976                                                 /* ACM bit is 1. */
 977                                                 switch (eACI) {
 978                                                 case AC0_BE:
 979                                                         AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN); /* or 0x21 */
 980                                                         break;
 981
 982                                                 case AC2_VI:
 983                                                         AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN); /* or 0x42 */
 984                                                         break;
 985
 986                                                 case AC3_VO:
 987                                                         AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN); /* or 0x84 */
 988                                                         break;
 989
 990                                                 default:
 991                                                         DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI);
 992                                                         break;
 993                                                 }
 994                                         } else {
 995                                                 /* ACM bit is 0. */
 996                                                 switch (eACI) {
 997                                                 case AC0_BE:
 998                                                         AcmCtrl &= ((~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN)); /* and 0xDE */
 999                                                         break;
1000
1001                                                 case AC2_VI:
1002                                                         AcmCtrl &= ((~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN)); /* and 0xBD */
1003                                                         break;
1004
1005                                                 case AC3_VO:
1006                                                         AcmCtrl &= ((~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN)); /* and 0x7B */
1007                                                         break;
1008
1009                                                 default:
1010                                                         break;
1011                                                 }
1012                                         }
1013                                         write_nic_byte(dev, ACM_CONTROL, 0);
1014                                 }
1015                         }
1016                 }
1017         }
1018 }
1019
1020 void ActSetWirelessMode8185(struct net_device *dev, u8 btWirelessMode)
1021 {
1022         struct  r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1023         struct  ieee80211_device *ieee = priv->ieee80211;
1024         u8      btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1025
1026         if ((btWirelessMode & btSupportedWirelessMode) == 0)    {
1027                 /* Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko. */
1028                 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
1029                         btWirelessMode, btSupportedWirelessMode);
1030                 return;
1031         }
1032
1033         /* 1. Assign wireless mode to switch if necessary. */
1034         if (btWirelessMode == WIRELESS_MODE_AUTO) {
1035                 if ((btSupportedWirelessMode & WIRELESS_MODE_A)) {
1036                         btWirelessMode = WIRELESS_MODE_A;
1037                 } else if (btSupportedWirelessMode & WIRELESS_MODE_G) {
1038                                 btWirelessMode = WIRELESS_MODE_G;
1039
1040                 } else if ((btSupportedWirelessMode & WIRELESS_MODE_B)) {
1041                                 btWirelessMode = WIRELESS_MODE_B;
1042                 } else {
1043                         DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
1044                                btSupportedWirelessMode);
1045                         btWirelessMode = WIRELESS_MODE_B;
1046                 }
1047         }
1048
1049         /*
1050          * 2. Swtich band: RF or BB specific actions,
1051          * for example, refresh tables in omc8255, or change initial gain if necessary.
1052          * Nothing to do for Zebra to switch band.
1053          * Update current wireless mode if we switch to specified band successfully.
1054          */
1055
1056         ieee->mode = (WIRELESS_MODE)btWirelessMode;
1057
1058         /* 3. Change related setting. */
1059         if (ieee->mode == WIRELESS_MODE_A)
1060                 DMESG("WIRELESS_MODE_A\n");
1061         else if (ieee->mode == WIRELESS_MODE_B)
1062                 DMESG("WIRELESS_MODE_B\n");
1063         else if (ieee->mode == WIRELESS_MODE_G)
1064                 DMESG("WIRELESS_MODE_G\n");
1065
1066         ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
1067 }
1068
1069 void rtl8185b_irq_enable(struct net_device *dev)
1070 {
1071         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1072
1073         priv->irq_enabled = 1;
1074         write_nic_dword(dev, IMR, priv->IntrMask);
1075 }
1076
1077 void MgntDisconnectIBSS(struct net_device *dev)
1078 {
1079         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1080         u8 i;
1081
1082         for (i = 0; i < 6 ; i++)
1083                 priv->ieee80211->current_network.bssid[i] = 0x55;
1084
1085
1086
1087         priv->ieee80211->state = IEEE80211_NOLINK;
1088         /*
1089          *      Stop Beacon.
1090          *
1091          *      Vista add a Adhoc profile, HW radio off until OID_DOT11_RESET_REQUEST
1092          *      Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
1093          *      Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
1094          *
1095          *      Disable Beacon Queue Own bit, suggested by jong
1096          */
1097         ieee80211_stop_send_beacons(priv->ieee80211);
1098
1099         priv->ieee80211->link_change(dev);
1100         notify_wx_assoc_event(priv->ieee80211);
1101 }
1102
1103 void MlmeDisassociateRequest(struct net_device *dev, u8 *asSta, u8 asRsn)
1104 {
1105         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1106         u8 i;
1107
1108         SendDisassociation(priv->ieee80211, asSta, asRsn);
1109
1110         if (memcmp(priv->ieee80211->current_network.bssid, asSta, 6) == 0) {
1111                 /* ShuChen TODO: change media status. */
1112
1113                 for (i = 0; i < 6; i++)
1114                         priv->ieee80211->current_network.bssid[i] = 0x22;
1115
1116                 ieee80211_disassociate(priv->ieee80211);
1117         }
1118 }
1119
1120 void MgntDisconnectAP(struct net_device *dev, u8 asRsn)
1121 {
1122         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1123
1124         /*
1125          * Commented out by rcnjko, 2005.01.27:
1126          * I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
1127          *
1128          *      2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
1129          *
1130          *      In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
1131          *      2004.10.11, by rcnjko.
1132          */
1133         MlmeDisassociateRequest(dev, priv->ieee80211->current_network.bssid, asRsn);
1134
1135         priv->ieee80211->state = IEEE80211_NOLINK;
1136 }
1137
1138 bool MgntDisconnect(struct net_device *dev, u8 asRsn)
1139 {
1140         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1141         /*
1142          *      Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
1143          */
1144
1145         if (IS_DOT11D_ENABLE(priv->ieee80211))
1146                 Dot11d_Reset(priv->ieee80211);
1147         /* In adhoc mode, update beacon frame. */
1148         if (priv->ieee80211->state == IEEE80211_LINKED) {
1149                 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
1150                         MgntDisconnectIBSS(dev);
1151
1152                 if (priv->ieee80211->iw_mode == IW_MODE_INFRA) {
1153                         /*
1154                          *      We clear key here instead of MgntDisconnectAP() because that
1155                          *      MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
1156                          *      e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
1157                          *      used to handle disassociation related things to AP, e.g. send Disassoc
1158                          *      frame to AP.  2005.01.27, by rcnjko.
1159                          */
1160                         MgntDisconnectAP(dev, asRsn);
1161                 }
1162                 /* Indicate Disconnect, 2005.02.23, by rcnjko.  */
1163         }
1164         return true;
1165 }
1166 /*
1167  *      Description:
1168  *              Chang RF Power State.
1169  *              Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
1170  *
1171  *      Assumption:
1172  *              PASSIVE LEVEL.
1173  */
1174 bool SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState)
1175 {
1176         struct  r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1177         bool    bResult = false;
1178
1179         if (eRFPowerState == priv->eRFPowerState)
1180                 return bResult;
1181
1182         bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
1183
1184         return bResult;
1185 }
1186
1187 bool MgntActSet_RF_State(struct net_device *dev, RT_RF_POWER_STATE StateToSet, u32 ChangeSource)
1188 {
1189         struct  r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1190         bool    bActionAllowed = false;
1191         bool    bConnectBySSID = false;
1192         RT_RF_POWER_STATE rtState;
1193         u16     RFWaitCounter = 0;
1194         unsigned long flag;
1195         /*
1196          *      Prevent the race condition of RF state change. By Bruce, 2007-11-28.
1197          *      Only one thread can change the RF state at one time, and others should wait to be executed.
1198          */
1199         while (true) {
1200                 spin_lock_irqsave(&priv->rf_ps_lock, flag);
1201                 if (priv->RFChangeInProgress) {
1202                         spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1203                         /*  Set RF after the previous action is done.   */
1204                         while (priv->RFChangeInProgress) {
1205                                 RFWaitCounter++;
1206                                 udelay(1000); /* 1 ms   */
1207
1208                                 /* Wait too long, return FALSE to avoid to be stuck here. */
1209                                 if (RFWaitCounter > 1000) { /* 1sec */
1210                                         printk("MgntActSet_RF_State(): Wait too long to set RF\n");
1211                                         /* TODO: Reset RF state? */
1212                                         return false;
1213                                 }
1214                         }
1215                 } else {
1216                         priv->RFChangeInProgress = true;
1217                         spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1218                         break;
1219                 }
1220         }
1221         rtState = priv->eRFPowerState;
1222
1223         switch (StateToSet) {
1224         case eRfOn:
1225                 /*
1226                  *      Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
1227                  *      the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
1228                  */
1229                 priv->RfOffReason &= (~ChangeSource);
1230
1231                 if (!priv->RfOffReason) {
1232                         priv->RfOffReason = 0;
1233                         bActionAllowed = true;
1234
1235                         if (rtState == eRfOff && ChangeSource >= RF_CHANGE_BY_HW)
1236                                 bConnectBySSID = true;
1237                 }
1238                 break;
1239
1240         case eRfOff:
1241                  /* 070125, rcnjko: we always keep connected in AP mode. */
1242
1243                 if (priv->RfOffReason > RF_CHANGE_BY_IPS) {
1244                         /*
1245                          *      060808, Annie:
1246                          *      Disconnect to current BSS when radio off. Asked by QuanTa.
1247                          *
1248                          *      Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
1249                          *      because we do NOT need to set ssid to dummy ones.
1250                          */
1251                         MgntDisconnect(dev, disas_lv_ss);
1252                         /* Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI. */
1253                 }
1254
1255                 priv->RfOffReason |= ChangeSource;
1256                 bActionAllowed = true;
1257                 break;
1258         case eRfSleep:
1259                 priv->RfOffReason |= ChangeSource;
1260                 bActionAllowed = true;
1261                 break;
1262         default:
1263                 break;
1264         }
1265
1266         if (bActionAllowed) {
1267                 /* Config HW to the specified mode. */
1268                 SetRFPowerState(dev, StateToSet);
1269         }
1270
1271         /* Release RF spinlock  */
1272         spin_lock_irqsave(&priv->rf_ps_lock, flag);
1273         priv->RFChangeInProgress = false;
1274         spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1275         return bActionAllowed;
1276 }
1277
1278 void InactivePowerSave(struct net_device *dev)
1279 {
1280         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1281         /*
1282          *      This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
1283          *      is really scheduled.
1284          *      The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
1285          *      previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
1286          *      blocks the IPS procedure of switching RF.
1287          */
1288         priv->bSwRfProcessing = true;
1289
1290         MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
1291
1292         /*
1293          *      To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
1294          */
1295
1296         priv->bSwRfProcessing = false;
1297 }
1298
1299 /*
1300  *      Description:
1301  *              Enter the inactive power save mode. RF will be off
1302  */
1303 void IPSEnter(struct net_device *dev)
1304 {
1305         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1306         RT_RF_POWER_STATE rtState;
1307         if (priv->bInactivePs) {
1308                 rtState = priv->eRFPowerState;
1309
1310                 /*
1311                  *      Do not enter IPS in the following conditions:
1312                  *      (1) RF is already OFF or Sleep
1313                  *      (2) bSwRfProcessing (indicates the IPS is still under going)
1314                  *      (3) Connected (only disconnected can trigger IPS)
1315                  *      (4) IBSS (send Beacon)
1316                  *      (5) AP mode (send Beacon)
1317                  */
1318                 if (rtState == eRfOn && !priv->bSwRfProcessing
1319                         && (priv->ieee80211->state != IEEE80211_LINKED)) {
1320                         priv->eInactivePowerState = eRfOff;
1321                         InactivePowerSave(dev);
1322                 }
1323         }
1324 }
1325 void IPSLeave(struct net_device *dev)
1326 {
1327         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1328         RT_RF_POWER_STATE rtState;
1329         if (priv->bInactivePs) {
1330                 rtState = priv->eRFPowerState;
1331                 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS) {
1332                         priv->eInactivePowerState = eRfOn;
1333                         InactivePowerSave(dev);
1334                 }
1335         }
1336 }
1337
1338 void rtl8185b_adapter_start(struct net_device *dev)
1339 {
1340         struct r8180_priv *priv = ieee80211_priv(dev);
1341         struct ieee80211_device *ieee = priv->ieee80211;
1342
1343         u8 SupportedWirelessMode;
1344         u8 InitWirelessMode;
1345         u8 bInvalidWirelessMode = 0;
1346         u8 tmpu8;
1347         u8 btCR9346;
1348         u8 TmpU1b;
1349         u8 btPSR;
1350
1351         write_nic_byte(dev, 0x24e, (BIT5|BIT6|BIT0));
1352         rtl8180_reset(dev);
1353
1354         priv->dma_poll_mask = 0;
1355         priv->dma_poll_stop_mask = 0;
1356
1357         HwConfigureRTL8185(dev);
1358         write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
1359         write_nic_word(dev, MAC4, ((u32 *)dev->dev_addr)[1] & 0xffff);
1360         write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3); /* default network type to 'No Link' */
1361         write_nic_word(dev, BcnItv, 100);
1362         write_nic_word(dev, AtimWnd, 2);
1363         PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
1364         write_nic_byte(dev, WPA_CONFIG, 0);
1365         MacConfig_85BASIC(dev);
1366         /* Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko. */
1367         /* BT_DEMO_BOARD type */
1368         PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
1369
1370         /*
1371          *---------------------------------------------------------------------------
1372          *      Set up PHY related.
1373          *---------------------------------------------------------------------------
1374          */
1375         /* Enable Config3.PARAM_En to revise AnaaParm. */
1376         write_nic_byte(dev, CR9346, 0xc0); /* enable config register write */
1377         tmpu8 = read_nic_byte(dev, CONFIG3);
1378         write_nic_byte(dev, CONFIG3, (tmpu8 | CONFIG3_PARM_En));
1379         /* Turn on Analog power. */
1380         /* Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko. */
1381         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
1382         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
1383         write_nic_word(dev, ANAPARAM3, 0x0010);
1384
1385         write_nic_byte(dev, CONFIG3, tmpu8);
1386         write_nic_byte(dev, CR9346, 0x00);
1387         /* enable EEM0 and EEM1 in 9346CR */
1388         btCR9346 = read_nic_byte(dev, CR9346);
1389         write_nic_byte(dev, CR9346, (btCR9346 | 0xC0));
1390
1391         /* B cut use LED1 to control HW RF on/off */
1392         TmpU1b = read_nic_byte(dev, CONFIG5);
1393         TmpU1b = TmpU1b & ~BIT3;
1394         write_nic_byte(dev, CONFIG5, TmpU1b);
1395
1396         /* disable EEM0 and EEM1 in 9346CR */
1397         btCR9346 &= ~(0xC0);
1398         write_nic_byte(dev, CR9346, btCR9346);
1399
1400         /* Enable Led (suggested by Jong) */
1401         /* B-cut RF Radio on/off  5e[3]=0 */
1402         btPSR = read_nic_byte(dev, PSR);
1403         write_nic_byte(dev, PSR, (btPSR | BIT3));
1404         /* setup initial timing for RFE. */
1405         write_nic_word(dev, RFPinsOutput, 0x0480);
1406         SetOutputEnableOfRfPins(dev);
1407         write_nic_word(dev, RFPinsSelect, 0x2488);
1408
1409         /* PHY config. */
1410         PhyConfig8185(dev);
1411
1412         /*
1413          *      We assume RegWirelessMode has already been initialized before,
1414          *      however, we has to validate the wireless mode here and provide a
1415          *      reasonable initialized value if necessary. 2005.01.13, by rcnjko.
1416          */
1417         SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1418         if ((ieee->mode != WIRELESS_MODE_B) &&
1419                 (ieee->mode != WIRELESS_MODE_G) &&
1420                 (ieee->mode != WIRELESS_MODE_A) &&
1421                 (ieee->mode != WIRELESS_MODE_AUTO)) {
1422                 /* It should be one of B, G, A, or AUTO. */
1423                 bInvalidWirelessMode = 1;
1424         } else {
1425         /* One of B, G, A, or AUTO. */
1426                 /* Check if the wireless mode is supported by RF. */
1427                 if      ((ieee->mode != WIRELESS_MODE_AUTO) &&
1428                         (ieee->mode & SupportedWirelessMode) == 0) {
1429                         bInvalidWirelessMode = 1;
1430                 }
1431         }
1432
1433         if (bInvalidWirelessMode || ieee->mode == WIRELESS_MODE_AUTO) {
1434                 /* Auto or other invalid value. */
1435                 /* Assigne a wireless mode to initialize. */
1436                 if ((SupportedWirelessMode & WIRELESS_MODE_A)) {
1437                         InitWirelessMode = WIRELESS_MODE_A;
1438                 } else if ((SupportedWirelessMode & WIRELESS_MODE_G)) {
1439                         InitWirelessMode = WIRELESS_MODE_G;
1440                 } else if ((SupportedWirelessMode & WIRELESS_MODE_B)) {
1441                         InitWirelessMode = WIRELESS_MODE_B;
1442                 } else {
1443                         DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
1444                                  SupportedWirelessMode);
1445                         InitWirelessMode = WIRELESS_MODE_B;
1446                 }
1447
1448                 /* Initialize RegWirelessMode if it is not a valid one. */
1449                 if (bInvalidWirelessMode)
1450                         ieee->mode = (WIRELESS_MODE)InitWirelessMode;
1451
1452         } else {
1453         /* One of B, G, A. */
1454                 InitWirelessMode = ieee->mode;
1455         }
1456         priv->eRFPowerState = eRfOff;
1457         priv->RfOffReason = 0;
1458         {
1459                 MgntActSet_RF_State(dev, eRfOn, 0);
1460         }
1461                 /*
1462                  *      If inactive power mode is enabled, disable rf while in disconnected state.
1463                  */
1464         if (priv->bInactivePs)
1465                 MgntActSet_RF_State(dev , eRfOff, RF_CHANGE_BY_IPS);
1466
1467         ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
1468
1469         /* ----------------------------------------------------------------------------- */
1470
1471         rtl8185b_irq_enable(dev);
1472
1473         netif_start_queue(dev);
1474 }
1475
1476 void rtl8185b_rx_enable(struct net_device *dev)
1477 {
1478         u8 cmd;
1479         /* for now we accept data, management & ctl frame*/
1480         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1481
1482
1483         if (dev->flags & IFF_PROMISC)
1484                 DMESG("NIC in promisc mode");
1485
1486         if (priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
1487            dev->flags & IFF_PROMISC) {
1488                 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
1489                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
1490         }
1491
1492         if (priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1493                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
1494
1495
1496         if (priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1497                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
1498
1499         write_nic_dword(dev, RCR, priv->ReceiveConfig);
1500
1501         fix_rx_fifo(dev);
1502
1503         cmd = read_nic_byte(dev, CMD);
1504         write_nic_byte(dev, CMD, cmd | (1<<CMD_RX_ENABLE_SHIFT));
1505
1506 }
1507
1508 void rtl8185b_tx_enable(struct net_device *dev)
1509 {
1510         u8 cmd;
1511         u8 byte;
1512         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1513
1514         write_nic_dword(dev, TCR, priv->TransmitConfig);
1515         byte = read_nic_byte(dev, MSR);
1516         byte |= MSR_LINK_ENEDCA;
1517         write_nic_byte(dev, MSR, byte);
1518
1519         fix_tx_fifo(dev);
1520
1521         cmd = read_nic_byte(dev, CMD);
1522         write_nic_byte(dev, CMD, cmd | (1<<CMD_TX_ENABLE_SHIFT));
1523 }
1524