drivers/staging/rtl8187se/r8185b_init.c

   1 /*
   2  * Copyright (c) Realtek Semiconductor Corp. All rights reserved.
   3  *
   4  * Module Name:
   5  *      r8185b_init.c
   6  *
   7  * Abstract:
   8  *      Hardware Initialization and Hardware IO for RTL8185B
   9  *
  10  * Major Change History:
  11  *      When            Who                             What
  12  *      ----------      ---------------         -------------------------------
  13  *      2006-11-15      Xiong                   Created
  14  *
  15  * Notes:
  16  *      This file is ported from RTL8185B Windows driver.
  17  *
  18  *
  19  */
  20
  21 /*--------------------------Include File------------------------------------*/
  22 #include <linux/spinlock.h>
  23 #include "r8180_hw.h"
  24 #include "r8180.h"
  25 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
  26 #include "r8180_93cx6.h"   /* Card EEPROM */
  27 #include "r8180_wx.h"
  28 #include "ieee80211/dot11d.h"
  29 /* #define CONFIG_RTL8180_IO_MAP */
  30 #define TC_3W_POLL_MAX_TRY_CNT 5
  31
  32 static u8 MAC_REG_TABLE[][2] =  {
  33         /*PAGA 0:       */
  34         /* 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185() */
  35         /* 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185(). */
  36         /* 0x1F0~0x1F8  set in MacConfig_85BASIC() */
  37         {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
  38         {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
  39         {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
  40         {0x94, 0x0F}, {0x95, 0x32},
  41         {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
  42         {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
  43         {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
  44         {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
  45         {0xff, 0x00},
  46
  47         /*PAGE 1: */
  48         /* For Flextronics system Logo PCIHCT failure: */
  49         /* 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1 */
  50         {0x5e, 0x01},
  51         {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
  52         {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
  53         {0x82, 0xFF}, {0x83, 0x03},
  54         {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, /* lzm add 080826 */
  55         {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22}, /* lzm add 080826 */
  56         {0xe2, 0x00},
  57
  58
  59         /* PAGE 2: */
  60         {0x5e, 0x02},
  61         {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
  62         {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
  63         {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
  64         {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
  65         {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
  66         {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
  67         {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
  68
  69         /* PAGA 0: */
  70         {0x5e, 0x00}, {0x9f, 0x03}
  71         };
  72
  73
  74 static u8  ZEBRA_AGC[] = {
  75         0,
  76         0x7E, 0x7E, 0x7E, 0x7E, 0x7D, 0x7C, 0x7B, 0x7A, 0x79, 0x78, 0x77, 0x76, 0x75, 0x74, 0x73, 0x72,
  77         0x71, 0x70, 0x6F, 0x6E, 0x6D, 0x6C, 0x6B, 0x6A, 0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62,
  78         0x48, 0x47, 0x46, 0x45, 0x44, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x08, 0x07,
  79         0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
  80         0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x15, 0x16,
  81         0x17, 0x17, 0x18, 0x18, 0x19, 0x1a, 0x1a, 0x1b, 0x1b, 0x1c, 0x1c, 0x1d, 0x1d, 0x1d, 0x1e, 0x1e,
  82         0x1f, 0x1f, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x21, 0x22, 0x22, 0x22, 0x23, 0x23, 0x24,
  83         0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F
  84         };
  85
  86 static u32 ZEBRA_RF_RX_GAIN_TABLE[] = {
  87         0x0096, 0x0076, 0x0056, 0x0036, 0x0016, 0x01f6, 0x01d6, 0x01b6,
  88         0x0196, 0x0176, 0x00F7, 0x00D7, 0x00B7, 0x0097, 0x0077, 0x0057,
  89         0x0037, 0x00FB, 0x00DB, 0x00BB, 0x00FF, 0x00E3, 0x00C3, 0x00A3,
  90         0x0083, 0x0063, 0x0043, 0x0023, 0x0003, 0x01E3, 0x01C3, 0x01A3,
  91         0x0183, 0x0163, 0x0143, 0x0123, 0x0103
  92         };
  93
  94 static u8 OFDM_CONFIG[] = {
  95         /* OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX */
  96         /* OFDM reg0x3C[4]=1'b1: Enable RX power saving mode */
  97         /* ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test */
  98         /* 0x00 */
  99         0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
 100         0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
 101         /* 0x10 */
 102         0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
 103         0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
 104         /* 0x20 */
 105         0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
 106         0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
 107         /* 0x30 */
 108         0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
 109         0xD8, 0x3C, 0x7B, 0x10, 0x10
 110         };
 111
 112         /*---------------------------------------------------------------
 113          *      Hardware IO
 114          *      the code is ported from Windows source code
 115          *---------------------------------------------------------------
 116          */
 117
 118 static u8 PlatformIORead1Byte(struct net_device *dev, u32 offset)
 119 {
 120         return read_nic_byte(dev, offset);
 121 }
 122
 123 void PlatformIOWrite1Byte(struct net_device *dev, u32 offset, u8 data)
 124 {
 125         write_nic_byte(dev, offset, data);
 126         read_nic_byte(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
 127 }
 128
 129 void PlatformIOWrite2Byte(struct net_device *dev, u32 offset, u16 data)
 130 {
 131         write_nic_word(dev, offset, data);
 132         read_nic_word(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
 133 }
 134
 135 void PlatformIOWrite4Byte(struct net_device *dev, u32 offset, u32 data)
 136 {
 137         if (offset == PhyAddr) {
 138         /* For Base Band configuration. */
 139                 unsigned char   cmdByte;
 140                 unsigned long   dataBytes;
 141                 unsigned char   idx;
 142                 u8              u1bTmp;
 143
 144                 cmdByte = (u8)(data & 0x000000ff);
 145                 dataBytes = data>>8;
 146
 147                 /*
 148                  *      071010, rcnjko:
 149                  *      The critical section is only BB read/write race condition.
 150                  *      Assumption:
 151                  *      1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
 152                  *      acquiring the spinlock in such context.
 153                  *      2. PlatformIOWrite4Byte() MUST NOT be recursive.
 154                  */
 155                 /* NdisAcquireSpinLock( &(pDevice->IoSpinLock) ); */
 156
 157                 for (idx = 0; idx < 30; idx++) {
 158                 /* Make sure command bit is clear before access it. */
 159                         u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
 160                         if ((u1bTmp & BIT7) == 0)
 161                                 break;
 162                         else
 163                                 mdelay(10);
 164                 }
 165
 166                 for (idx = 0; idx < 3; idx++)
 167                         PlatformIOWrite1Byte(dev, offset+1+idx, ((u8 *)&dataBytes)[idx]);
 168
 169                 write_nic_byte(dev, offset, cmdByte);
 170
 171                 /* NdisReleaseSpinLock( &(pDevice->IoSpinLock) ); */
 172         } else {
 173                 write_nic_dword(dev, offset, data);
 174                 read_nic_dword(dev, offset); /* To make sure write operation is completed, 2005.11.09, by rcnjko. */
 175         }
 176 }
 177
 178 void SetOutputEnableOfRfPins(struct net_device *dev)
 179 {
 180         write_nic_word(dev, RFPinsEnable, 0x1bff);
 181 }
 182
 183 static bool HwHSSIThreeWire(struct net_device *dev,
 184                             u8 *pDataBuf,
 185                             bool write)
 186 {
 187         u8      TryCnt;
 188         u8      u1bTmp;
 189
 190         /* Check if WE and RE are cleared. */
 191         for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) {
 192                 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 193                 if ((u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0)
 194                         break;
 195
 196                 udelay(10);
 197         }
 198         if (TryCnt == TC_3W_POLL_MAX_TRY_CNT) {
 199                 netdev_err(dev,
 200                            "HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n",
 201                            u1bTmp);
 202         return false;
 203         }
 204
 205         /* RTL8187S HSSI Read/Write Function */
 206         u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 207         u1bTmp |= RF_SW_CFG_SI; /* reg08[1]=1 Serial Interface(SI) */
 208         write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 209
 210         /* jong: HW SI read must set reg84[3]=0. */
 211         u1bTmp = read_nic_byte(dev, RFPinsSelect);
 212         u1bTmp &= ~BIT3;
 213         write_nic_byte(dev, RFPinsSelect, u1bTmp);
 214         /*  Fill up data buffer for write operation. */
 215
 216         /* SI - reg274[3:0] : RF register's Address */
 217         if (write)
 218                 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 219         else
 220                 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 221
 222         /* Set up command: WE or RE. */
 223         if (write)
 224                 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 225         else
 226                 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 227
 228
 229         /* Check if DONE is set. */
 230         for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) {
 231                 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 232                 if (u1bTmp & SW_3W_CMD1_DONE)
 233                         break;
 234
 235                 udelay(10);
 236         }
 237
 238         write_nic_byte(dev, SW_3W_CMD1, 0);
 239
 240         /* Read back data for read operation. */
 241         if (!write) {
 242                 /* Serial Interface : reg363_362[11:0] */
 243                 *((u16 *)pDataBuf) = read_nic_word(dev, SI_DATA_READ);
 244                 *((u16 *)pDataBuf) &= 0x0FFF;
 245         }
 246
 247         return true;
 248 }
 249
 250 void RF_WriteReg(struct net_device *dev, u8 offset, u16 data)
 251 {
 252         u16 reg = (data << 4) | (offset & 0x0f);
 253         HwHSSIThreeWire(dev, (u8 *)&reg, true);
 254 }
 255
 256 u16 RF_ReadReg(struct net_device *dev, u8 offset)
 257 {
 258         u16 reg = offset & 0x0f;
 259         HwHSSIThreeWire(dev, (u8 *)&reg, false);
 260         return reg;
 261 }
 262
 263 static u8 ReadBBPortUchar(struct net_device *dev, u32 addr)
 264 {
 265         PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
 266         return PlatformIORead1Byte(dev, PhyDataR);
 267 }
 268
 269 /* by Owen on 04/07/14 for writing BB register successfully */
 270 static void WriteBBPortUchar(struct net_device *dev, u32 Data)
 271 {
 272         PlatformIOWrite4Byte(dev, PhyAddr, Data);
 273         ReadBBPortUchar(dev, Data);
 274 }
 275
 276 /*
 277  *      Description:
 278  *      Perform Antenna settings with antenna diversity on 87SE.
 279  *              Created by Roger, 2008.01.25.
 280  */
 281 bool SetAntennaConfig87SE(struct net_device *dev,
 282                           u8   DefaultAnt, /* 0: Main, 1: Aux. */
 283                           bool bAntDiversity) /* 1:Enable, 0: Disable. */
 284 {
 285         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 286         bool   bAntennaSwitched = true;
 287
 288         /* printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity); */
 289
 290         /* Threshold for antenna diversity. */
 291         write_phy_cck(dev, 0x0c, 0x09); /* Reg0c : 09 */
 292
 293         if (bAntDiversity) {    /*      Enable Antenna Diversity. */
 294                 if (DefaultAnt == 1) {  /* aux antenna */
 295
 296                         /* Mac register, aux antenna */
 297                         write_nic_byte(dev, ANTSEL, 0x00);
 298
 299                         /* Config CCK RX antenna. */
 300                         write_phy_cck(dev, 0x11, 0xbb); /* Reg11 : bb */
 301                         write_phy_cck(dev, 0x01, 0xc7); /* Reg01 : c7 */
 302
 303                         /* Config OFDM RX antenna. */
 304                         write_phy_ofdm(dev, 0x0D, 0x54);        /* Reg0d : 54 */
 305                         write_phy_ofdm(dev, 0x18, 0xb2);        /* Reg18 : b2 */
 306                 } else { /*  use main antenna */
 307                         /* Mac register, main antenna */
 308                         write_nic_byte(dev, ANTSEL, 0x03);
 309                         /* base band */
 310                         /*  Config CCK RX antenna. */
 311                         write_phy_cck(dev, 0x11, 0x9b); /* Reg11 : 9b */
 312                         write_phy_cck(dev, 0x01, 0xc7); /* Reg01 : c7 */
 313
 314                         /* Config OFDM RX antenna. */
 315                         write_phy_ofdm(dev, 0x0d, 0x5c);  /* Reg0d : 5c */
 316                         write_phy_ofdm(dev, 0x18, 0xb2);  /* Reg18 : b2 */
 317                 }
 318         } else {
 319                 /* Disable Antenna Diversity. */
 320                 if (DefaultAnt == 1) { /* aux Antenna */
 321                         /* Mac register, aux antenna */
 322                         write_nic_byte(dev, ANTSEL, 0x00);
 323
 324                         /* Config CCK RX antenna. */
 325                         write_phy_cck(dev, 0x11, 0xbb); /* Reg11 : bb */
 326                         write_phy_cck(dev, 0x01, 0x47); /* Reg01 : 47 */
 327
 328                         /* Config OFDM RX antenna. */
 329                         write_phy_ofdm(dev, 0x0D, 0x54);        /* Reg0d : 54 */
 330                         write_phy_ofdm(dev, 0x18, 0x32);        /* Reg18 : 32 */
 331                 } else { /* main Antenna */
 332                         /* Mac register, main antenna */
 333                         write_nic_byte(dev, ANTSEL, 0x03);
 334
 335                         /* Config CCK RX antenna.       */
 336                         write_phy_cck(dev, 0x11, 0x9b); /* Reg11 : 9b */
 337                         write_phy_cck(dev, 0x01, 0x47); /* Reg01 : 47 */
 338
 339                         /* Config OFDM RX antenna. */
 340                         write_phy_ofdm(dev, 0x0D, 0x5c); /* Reg0d : 5c */
 341                         write_phy_ofdm(dev, 0x18, 0x32); /*Reg18 : 32 */
 342                 }
 343         }
 344         priv->CurrAntennaIndex = DefaultAnt; /* Update default settings. */
 345         return  bAntennaSwitched;
 346 }
 347 /*
 348  *--------------------------------------------------------------
 349  *              Hardware Initialization.
 350  *              the code is ported from Windows source code
 351  *--------------------------------------------------------------
 352  */
 353
 354 void ZEBRA_Config_85BASIC_HardCode(struct net_device *dev)
 355 {
 356
 357         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 358         u32                     i;
 359         u32     addr, data;
 360         u32 u4bRegOffset, u4bRegValue;
 361         u16 u4bRF23, u4bRF24;
 362         u8                      u1b24E;
 363         int d_cut = 0;
 364
 365
 366 /*
 367  *===========================================================================
 368  *      87S_PCIE :: RADIOCFG.TXT
 369  *===========================================================================
 370  */
 371
 372
 373         /* Page1 : reg16-reg30 */
 374         RF_WriteReg(dev, 0x00, 0x013f);         mdelay(1); /* switch to page1 */
 375         u4bRF23 = RF_ReadReg(dev, 0x08);        mdelay(1);
 376         u4bRF24 = RF_ReadReg(dev, 0x09);        mdelay(1);
 377
 378         if (u4bRF23 == 0x818 && u4bRF24 == 0x70C) {
 379                 d_cut = 1;
 380                 netdev_info(dev, "card type changed from C- to D-cut\n");
 381         }
 382
 383         /* Page0 : reg0-reg15 */
 384
 385         RF_WriteReg(dev, 0x00, 0x009f);         mdelay(1);/* 1  */
 386         RF_WriteReg(dev, 0x01, 0x06e0);         mdelay(1);
 387         RF_WriteReg(dev, 0x02, 0x004d);         mdelay(1);/* 2  */
 388         RF_WriteReg(dev, 0x03, 0x07f1);         mdelay(1);/* 3  */
 389         RF_WriteReg(dev, 0x04, 0x0975);         mdelay(1);
 390         RF_WriteReg(dev, 0x05, 0x0c72);         mdelay(1);
 391         RF_WriteReg(dev, 0x06, 0x0ae6);         mdelay(1);
 392         RF_WriteReg(dev, 0x07, 0x00ca);         mdelay(1);
 393         RF_WriteReg(dev, 0x08, 0x0e1c);         mdelay(1);
 394         RF_WriteReg(dev, 0x09, 0x02f0);         mdelay(1);
 395         RF_WriteReg(dev, 0x0a, 0x09d0);         mdelay(1);
 396         RF_WriteReg(dev, 0x0b, 0x01ba);         mdelay(1);
 397         RF_WriteReg(dev, 0x0c, 0x0640);         mdelay(1);
 398         RF_WriteReg(dev, 0x0d, 0x08df);         mdelay(1);
 399         RF_WriteReg(dev, 0x0e, 0x0020);         mdelay(1);
 400         RF_WriteReg(dev, 0x0f, 0x0990);         mdelay(1);
 401
 402         /*  Page1 : reg16-reg30 */
 403         RF_WriteReg(dev, 0x00, 0x013f);         mdelay(1);
 404         RF_WriteReg(dev, 0x03, 0x0806);         mdelay(1);
 405         RF_WriteReg(dev, 0x04, 0x03a7);         mdelay(1);
 406         RF_WriteReg(dev, 0x05, 0x059b);         mdelay(1);
 407         RF_WriteReg(dev, 0x06, 0x0081);         mdelay(1);
 408         RF_WriteReg(dev, 0x07, 0x01A0);         mdelay(1);
 409 /* Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl. */
 410         RF_WriteReg(dev, 0x0a, 0x0001);         mdelay(1);
 411         RF_WriteReg(dev, 0x0b, 0x0418);         mdelay(1);
 412
 413         if (d_cut) {
 414                 RF_WriteReg(dev, 0x0c, 0x0fbe);         mdelay(1);
 415                 RF_WriteReg(dev, 0x0d, 0x0008);         mdelay(1);
 416                 RF_WriteReg(dev, 0x0e, 0x0807);         mdelay(1); /* RX LO buffer */
 417         } else {
 418                 RF_WriteReg(dev, 0x0c, 0x0fbe);         mdelay(1);
 419                 RF_WriteReg(dev, 0x0d, 0x0008);         mdelay(1);
 420                 RF_WriteReg(dev, 0x0e, 0x0806);         mdelay(1); /* RX LO buffer */
 421         }
 422
 423         RF_WriteReg(dev, 0x0f, 0x0acc);         mdelay(1);
 424         RF_WriteReg(dev, 0x00, 0x01d7);         mdelay(1); /* 6 */
 425         RF_WriteReg(dev, 0x03, 0x0e00);         mdelay(1);
 426         RF_WriteReg(dev, 0x04, 0x0e50);         mdelay(1);
 427
 428         for (i = 0; i <= 36; i++) {
 429                 RF_WriteReg(dev, 0x01, i);              mdelay(1);
 430                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
 431         }
 432
 433         RF_WriteReg(dev, 0x05, 0x0203);         mdelay(1); /* 203, 343 */
 434         RF_WriteReg(dev, 0x06, 0x0200);         mdelay(1); /* 400 */
 435         RF_WriteReg(dev, 0x00, 0x0137);         mdelay(1); /* switch to reg16-reg30, and HSSI disable 137 */
 436         mdelay(10); /* Deay 10 ms. */           /* 0xfd */
 437
 438         RF_WriteReg(dev, 0x0d, 0x0008);         mdelay(1); /* Z4 synthesizer loop filter setting, 392 */
 439         mdelay(10); /* Deay 10 ms. */           /* 0xfd */
 440
 441         RF_WriteReg(dev, 0x00, 0x0037);         mdelay(1); /* switch to reg0-reg15, and HSSI disable */
 442         mdelay(10); /* Deay 10 ms. */           /* 0xfd */
 443
 444         RF_WriteReg(dev, 0x04, 0x0160);         mdelay(1); /* CBC on, Tx Rx disable, High gain */
 445         mdelay(10); /* Deay 10 ms. */           /* 0xfd */
 446
 447         RF_WriteReg(dev, 0x07, 0x0080);         mdelay(1); /* Z4 setted channel 1 */
 448         mdelay(10); /* Deay 10 ms. */           /* 0xfd */
 449
 450         RF_WriteReg(dev, 0x02, 0x088D);         mdelay(1); /* LC calibration */
 451         mdelay(200); /* Deay 200 ms. */         /* 0xfd */
 452         mdelay(10);  /* Deay 10 ms. */          /* 0xfd */
 453         mdelay(10);  /* Deay 10 ms. */          /* 0xfd */
 454
 455         RF_WriteReg(dev, 0x00, 0x0137);         mdelay(1); /* switch to reg16-reg30 137, and HSSI disable 137 */
 456         mdelay(10); /* Deay 10 ms. */           /* 0xfd */
 457
 458         RF_WriteReg(dev, 0x07, 0x0000);         mdelay(1);
 459         RF_WriteReg(dev, 0x07, 0x0180);         mdelay(1);
 460         RF_WriteReg(dev, 0x07, 0x0220);         mdelay(1);
 461         RF_WriteReg(dev, 0x07, 0x03E0);         mdelay(1);
 462
 463         /* DAC calibration off 20070702 */
 464         RF_WriteReg(dev, 0x06, 0x00c1);         mdelay(1);
 465         RF_WriteReg(dev, 0x0a, 0x0001);         mdelay(1);
 466         /* For crystal calibration, added by Roger, 2007.12.11. */
 467         if (priv->bXtalCalibration) { /* reg 30.        */
 468          /*
 469           *  enable crystal calibration.
 470           *             RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
 471           *             (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
 472           *             (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
 473           *             So we should minus 4 BITs offset.
 474           */
 475                 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11 | BIT9); mdelay(1);
 476                 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
 477                       (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11 | BIT9);
 478         } else {
 479                 /* using default value. Xin=6, Xout=6.  */
 480                 RF_WriteReg(dev, 0x0f, 0x0acc);         mdelay(1);
 481         }
 482
 483         RF_WriteReg(dev, 0x00, 0x00bf);         mdelay(1); /* switch to reg0-reg15, and HSSI enable */
 484         RF_WriteReg(dev, 0x0d, 0x08df);         mdelay(1); /* Rx BB start calibration, 00c//+edward */
 485         RF_WriteReg(dev, 0x02, 0x004d);         mdelay(1); /* temperature meter off */
 486         RF_WriteReg(dev, 0x04, 0x0975);         mdelay(1); /* Rx mode */
 487         mdelay(10);     /* Deay 10 ms.*/        /* 0xfe */
 488         mdelay(10);     /* Deay 10 ms.*/        /* 0xfe */
 489         mdelay(10);     /* Deay 10 ms.*/        /* 0xfe */
 490         RF_WriteReg(dev, 0x00, 0x0197);         mdelay(1); /* Rx mode*/ /*+edward */
 491         RF_WriteReg(dev, 0x05, 0x05ab);         mdelay(1); /* Rx mode*/ /*+edward */
 492         RF_WriteReg(dev, 0x00, 0x009f);         mdelay(1); /* Rx mode*/ /*+edward */
 493         RF_WriteReg(dev, 0x01, 0x0000);         mdelay(1); /* Rx mode*/ /*+edward */
 494         RF_WriteReg(dev, 0x02, 0x0000);         mdelay(1); /* Rx mode*/ /*+edward */
 495         /* power save parameters. */
 496         u1b24E = read_nic_byte(dev, 0x24E);
 497         write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
 498
 499         /*=============================================================================
 500          *
 501          *===========================================================================
 502          * CCKCONF.TXT
 503          *===========================================================================
 504          *
 505          *      [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
 506          *      CCK reg0x00[7]=1'b1 :power saving for TX (default)
 507          *      CCK reg0x00[6]=1'b1: power saving for RX (default)
 508          *      CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
 509          *      CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
 510          *      CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
 511          */
 512
 513         write_phy_cck(dev, 0x00, 0xc8);
 514         write_phy_cck(dev, 0x06, 0x1c);
 515         write_phy_cck(dev, 0x10, 0x78);
 516         write_phy_cck(dev, 0x2e, 0xd0);
 517         write_phy_cck(dev, 0x2f, 0x06);
 518         write_phy_cck(dev, 0x01, 0x46);
 519
 520         /* power control */
 521         write_nic_byte(dev, CCK_TXAGC, 0x10);
 522         write_nic_byte(dev, OFDM_TXAGC, 0x1B);
 523         write_nic_byte(dev, ANTSEL, 0x03);
 524
 525
 526
 527         /*
 528          *===========================================================================
 529          *      AGC.txt
 530          *===========================================================================
 531          */
 532
 533         write_phy_ofdm(dev, 0x00, 0x12);
 534
 535         for (i = 0; i < 128; i++) {
 536
 537                 data = ZEBRA_AGC[i+1];
 538                 data = data << 8;
 539                 data = data | 0x0000008F;
 540
 541                 addr = i + 0x80; /* enable writing AGC table */
 542                 addr = addr << 8;
 543                 addr = addr | 0x0000008E;
 544
 545                 WriteBBPortUchar(dev, data);
 546                 WriteBBPortUchar(dev, addr);
 547                 WriteBBPortUchar(dev, 0x0000008E);
 548         }
 549
 550         PlatformIOWrite4Byte(dev, PhyAddr, 0x00001080); /* Annie, 2006-05-05 */
 551
 552         /*
 553          *===========================================================================
 554          *
 555          *===========================================================================
 556          * OFDMCONF.TXT
 557          *===========================================================================
 558          */
 559
 560         for (i = 0; i < 60; i++) {
 561                 u4bRegOffset = i;
 562                 u4bRegValue = OFDM_CONFIG[i];
 563
 564                 WriteBBPortUchar(dev,
 565                                 (0x00000080 |
 566                                 (u4bRegOffset & 0x7f) |
 567                                 ((u4bRegValue & 0xff) << 8)));
 568         }
 569
 570         /*
 571          *===========================================================================
 572          * by amy for antenna
 573          *===========================================================================
 574          */
 575         /* Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.   */
 576         SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
 577 }
 578
 579
 580 void UpdateInitialGain(struct net_device *dev)
 581 {
 582         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 583
 584         /* lzm add 080826 */
 585         if (priv->eRFPowerState != eRfOn) {
 586                 /*      Don't access BB/RF under disable PLL situation.
 587                  *      RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
 588                  *      Back to the original state
 589                  */
 590                 priv->InitialGain = priv->InitialGainBackUp;
 591                 return;
 592         }
 593
 594         switch (priv->InitialGain) {
 595         case 1: /* m861dBm */
 596                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
 597                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 598                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
 599                 break;
 600
 601         case 2: /* m862dBm */
 602                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
 603                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 604                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
 605                 break;
 606
 607         case 3: /* m863dBm */
 608                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
 609                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 610                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
 611                 break;
 612
 613         case 4: /* m864dBm */
 614                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
 615                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 616                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
 617                 break;
 618
 619         case 5: /* m82dBm */
 620                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
 621                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
 622                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
 623                 break;
 624
 625         case 6: /* m78dBm */
 626                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
 627                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
 628                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
 629                 break;
 630
 631         case 7: /* m74dBm */
 632                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
 633                 write_phy_ofdm(dev, 0x24, 0xa6);        mdelay(1);
 634                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
 635                 break;
 636
 637         case 8:
 638                 write_phy_ofdm(dev, 0x17, 0x66);        mdelay(1);
 639                 write_phy_ofdm(dev, 0x24, 0xb6);        mdelay(1);
 640                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
 641                 break;
 642
 643         default: /* MP */
 644                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
 645                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
 646                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
 647                 break;
 648         }
 649 }
 650 /*
 651  *      Description:
 652  *              Tx Power tracking mechanism routine on 87SE.
 653  *      Created by Roger, 2007.12.11.
 654  */
 655 void InitTxPwrTracking87SE(struct net_device *dev)
 656 {
 657         u32     u4bRfReg;
 658
 659         u4bRfReg = RF_ReadReg(dev, 0x02);
 660
 661         /* Enable Thermal meter indication.     */
 662         RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN);                  mdelay(1);
 663 }
 664
 665 void PhyConfig8185(struct net_device *dev)
 666 {
 667         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 668                 write_nic_dword(dev, RCR, priv->ReceiveConfig);
 669            priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
 670         /*  RF config */
 671         ZEBRA_Config_85BASIC_HardCode(dev);
 672         /* Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06. */
 673         if (priv->bDigMechanism) {
 674                 if (priv->InitialGain == 0)
 675                         priv->InitialGain = 4;
 676         }
 677
 678         /*
 679          *      Enable thermal meter indication to implement TxPower tracking on 87SE.
 680          *      We initialize thermal meter here to avoid unsuccessful configuration.
 681          *      Added by Roger, 2007.12.11.
 682          */
 683         if (priv->bTxPowerTrack)
 684                 InitTxPwrTracking87SE(dev);
 685
 686         priv->InitialGainBackUp = priv->InitialGain;
 687         UpdateInitialGain(dev);
 688
 689         return;
 690 }
 691
 692 void HwConfigureRTL8185(struct net_device *dev)
 693 {
 694         /* RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control. */
 695         u8 bUNIVERSAL_CONTROL_RL = 0;
 696         u8 bUNIVERSAL_CONTROL_AGC = 1;
 697         u8 bUNIVERSAL_CONTROL_ANT = 1;
 698         u8 bAUTO_RATE_FALLBACK_CTL = 1;
 699         u8 val8;
 700         write_nic_word(dev, BRSR, 0x0fff);
 701         /* Retry limit */
 702         val8 = read_nic_byte(dev, CW_CONF);
 703
 704         if (bUNIVERSAL_CONTROL_RL)
 705                 val8 = val8 & 0xfd;
 706         else
 707                 val8 = val8 | 0x02;
 708
 709         write_nic_byte(dev, CW_CONF, val8);
 710
 711         /* Tx AGC */
 712         val8 = read_nic_byte(dev, TXAGC_CTL);
 713         if (bUNIVERSAL_CONTROL_AGC) {
 714                 write_nic_byte(dev, CCK_TXAGC, 128);
 715                 write_nic_byte(dev, OFDM_TXAGC, 128);
 716                 val8 = val8 & 0xfe;
 717         } else {
 718                 val8 = val8 | 0x01 ;
 719         }
 720
 721
 722         write_nic_byte(dev, TXAGC_CTL, val8);
 723
 724         /* Tx Antenna including Feedback control */
 725         val8 = read_nic_byte(dev, TXAGC_CTL);
 726
 727         if (bUNIVERSAL_CONTROL_ANT) {
 728                 write_nic_byte(dev, ANTSEL, 0x00);
 729                 val8 = val8 & 0xfd;
 730         } else {
 731                 val8 = val8 & (val8|0x02); /* xiong-2006-11-15 */
 732         }
 733
 734         write_nic_byte(dev, TXAGC_CTL, val8);
 735
 736         /* Auto Rate fallback control   */
 737         val8 = read_nic_byte(dev, RATE_FALLBACK);
 738         val8 &= 0x7c;
 739         if (bAUTO_RATE_FALLBACK_CTL) {
 740                 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
 741
 742                 /* <RJ_TODO_8185B> We shall set up the ARFR according to user's setting. */
 743                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); /* set 1M ~ 54Mbps. */
 744         }
 745         write_nic_byte(dev, RATE_FALLBACK, val8);
 746 }
 747
 748 static void MacConfig_85BASIC_HardCode(struct net_device *dev)
 749 {
 750         /*
 751          *==========================================================================
 752          * MACREG.TXT
 753          *==========================================================================
 754          */
 755         int nLinesRead = 0;
 756         u32 u4bRegOffset, u4bRegValue, u4bPageIndex = 0;
 757         int i;
 758
 759         nLinesRead = sizeof(MAC_REG_TABLE)/2;
 760
 761         for (i = 0; i < nLinesRead; i++) { /* nLinesRead=101 */
 762                 u4bRegOffset = MAC_REG_TABLE[i][0];
 763                 u4bRegValue = MAC_REG_TABLE[i][1];
 764
 765                                 if (u4bRegOffset == 0x5e)
 766                                         u4bPageIndex = u4bRegValue;
 767                                 else
 768                                         u4bRegOffset |= (u4bPageIndex << 8);
 769
 770                 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
 771         }
 772         /* ============================================================================ */
 773 }
 774
 775 static void MacConfig_85BASIC(struct net_device *dev)
 776 {
 777
 778         u8                      u1DA;
 779         MacConfig_85BASIC_HardCode(dev);
 780
 781         /* ============================================================================ */
 782
 783         /* Follow TID_AC_MAP of WMac. */
 784         write_nic_word(dev, TID_AC_MAP, 0xfa50);
 785
 786         /* Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko. */
 787         write_nic_word(dev, IntMig, 0x0000);
 788
 789         /* Prevent TPC to cause CRC error. Added by Annie, 2006-06-10. */
 790         PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
 791         PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
 792         PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
 793
 794         /* Asked for by SD3 CM Lin, 2006.06.27, by rcnjko. */
 795         /* power save parameter based on "87SE power save parameters 20071127.doc", as follow. */
 796
 797         /* Enable DA10 TX power saving */
 798         u1DA = read_nic_byte(dev, PHYPR);
 799         write_nic_byte(dev, PHYPR, (u1DA | BIT2));
 800
 801         /* POWER: */
 802         write_nic_word(dev, 0x360, 0x1000);
 803         write_nic_word(dev, 0x362, 0x1000);
 804
 805         /* AFE. */
 806         write_nic_word(dev, 0x370, 0x0560);
 807         write_nic_word(dev, 0x372, 0x0560);
 808         write_nic_word(dev, 0x374, 0x0DA4);
 809         write_nic_word(dev, 0x376, 0x0DA4);
 810         write_nic_word(dev, 0x378, 0x0560);
 811         write_nic_word(dev, 0x37A, 0x0560);
 812         write_nic_word(dev, 0x37C, 0x00EC);
 813         write_nic_word(dev, 0x37E, 0x00EC); /* +edward */
 814         write_nic_byte(dev, 0x24E, 0x01);
 815 }
 816
 817 u8 GetSupportedWirelessMode8185(struct net_device *dev)
 818 {
 819         return WIRELESS_MODE_B | WIRELESS_MODE_G;
 820 }
 821
 822 void ActUpdateChannelAccessSetting(struct net_device *dev,
 823                                    WIRELESS_MODE WirelessMode,
 824                                    PCHANNEL_ACCESS_SETTING ChnlAccessSetting)
 825 {
 826         AC_CODING       eACI;
 827
 828         /*
 829          *      <RJ_TODO_8185B>
 830          *      TODO: We still don't know how to set up these registers, just follow WMAC to
 831          *      verify 8185B FPAG.
 832          *
 833          *      <RJ_TODO_8185B>
 834          *      Jong said CWmin/CWmax register are not functional in 8185B,
 835          *      so we shall fill channel access realted register into AC parameter registers,
 836          *      even in nQBss.
 837          */
 838         ChnlAccessSetting->SIFS_Timer = 0x22; /* Suggested by Jong, 2005.12.08. */
 839         ChnlAccessSetting->DIFS_Timer = 0x1C; /* 2006.06.02, by rcnjko. */
 840         ChnlAccessSetting->SlotTimeTimer = 9; /* 2006.06.02, by rcnjko. */
 841         ChnlAccessSetting->EIFS_Timer = 0x5B; /* Suggested by wcchu, it is the default value of EIFS register, 2005.12.08. */
 842         ChnlAccessSetting->CWminIndex = 3; /* 2006.06.02, by rcnjko. */
 843         ChnlAccessSetting->CWmaxIndex = 7; /* 2006.06.02, by rcnjko. */
 844
 845         write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
 846         write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer); /* Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29. */
 847
 848         write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
 849
 850         write_nic_byte(dev, AckTimeOutReg, 0x5B); /* <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08. */
 851
 852         for (eACI = 0; eACI < AC_MAX; eACI++) {
 853                 write_nic_byte(dev, ACM_CONTROL, 0);
 854         }
 855 }
 856
 857 void ActSetWirelessMode8185(struct net_device *dev, u8 btWirelessMode)
 858 {
 859         struct  r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 860         struct  ieee80211_device *ieee = priv->ieee80211;
 861         u8      btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
 862
 863         if ((btWirelessMode & btSupportedWirelessMode) == 0)    {
 864                 /* Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko. */
 865                 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
 866                         btWirelessMode, btSupportedWirelessMode);
 867                 return;
 868         }
 869
 870         /* 1. Assign wireless mode to switch if necessary. */
 871         if (btWirelessMode == WIRELESS_MODE_AUTO) {
 872                 if ((btSupportedWirelessMode & WIRELESS_MODE_A)) {
 873                         btWirelessMode = WIRELESS_MODE_A;
 874                 } else if (btSupportedWirelessMode & WIRELESS_MODE_G) {
 875                                 btWirelessMode = WIRELESS_MODE_G;
 876
 877                 } else if ((btSupportedWirelessMode & WIRELESS_MODE_B)) {
 878                                 btWirelessMode = WIRELESS_MODE_B;
 879                 } else {
 880                         DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
 881                                btSupportedWirelessMode);
 882                         btWirelessMode = WIRELESS_MODE_B;
 883                 }
 884         }
 885
 886         /*
 887          * 2. Swtich band: RF or BB specific actions,
 888          * for example, refresh tables in omc8255, or change initial gain if necessary.
 889          * Nothing to do for Zebra to switch band.
 890          * Update current wireless mode if we switch to specified band successfully.
 891          */
 892
 893         ieee->mode = (WIRELESS_MODE)btWirelessMode;
 894
 895         /* 3. Change related setting. */
 896         if (ieee->mode == WIRELESS_MODE_A)
 897                 DMESG("WIRELESS_MODE_A\n");
 898         else if (ieee->mode == WIRELESS_MODE_B)
 899                 DMESG("WIRELESS_MODE_B\n");
 900         else if (ieee->mode == WIRELESS_MODE_G)
 901                 DMESG("WIRELESS_MODE_G\n");
 902
 903         ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
 904 }
 905
 906 void rtl8185b_irq_enable(struct net_device *dev)
 907 {
 908         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 909
 910         priv->irq_enabled = 1;
 911         write_nic_dword(dev, IMR, priv->IntrMask);
 912 }
 913
 914 void MgntDisconnectIBSS(struct net_device *dev)
 915 {
 916         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 917         u8 i;
 918
 919         for (i = 0; i < 6 ; i++)
 920                 priv->ieee80211->current_network.bssid[i] = 0x55;
 921
 922
 923
 924         priv->ieee80211->state = IEEE80211_NOLINK;
 925         /*
 926          *      Stop Beacon.
 927          *
 928          *      Vista add a Adhoc profile, HW radio off until OID_DOT11_RESET_REQUEST
 929          *      Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
 930          *      Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
 931          *
 932          *      Disable Beacon Queue Own bit, suggested by jong
 933          */
 934         ieee80211_stop_send_beacons(priv->ieee80211);
 935
 936         priv->ieee80211->link_change(dev);
 937         notify_wx_assoc_event(priv->ieee80211);
 938 }
 939
 940 void MlmeDisassociateRequest(struct net_device *dev, u8 *asSta, u8 asRsn)
 941 {
 942         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 943         u8 i;
 944
 945         SendDisassociation(priv->ieee80211, asSta, asRsn);
 946
 947         if (memcmp(priv->ieee80211->current_network.bssid, asSta, 6) == 0) {
 948                 /* ShuChen TODO: change media status. */
 949
 950                 for (i = 0; i < 6; i++)
 951                         priv->ieee80211->current_network.bssid[i] = 0x22;
 952
 953                 ieee80211_disassociate(priv->ieee80211);
 954         }
 955 }
 956
 957 void MgntDisconnectAP(struct net_device *dev, u8 asRsn)
 958 {
 959         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 960
 961         /*
 962          * Commented out by rcnjko, 2005.01.27:
 963          * I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
 964          *
 965          *      2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
 966          *
 967          *      In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
 968          *      2004.10.11, by rcnjko.
 969          */
 970         MlmeDisassociateRequest(dev, priv->ieee80211->current_network.bssid, asRsn);
 971
 972         priv->ieee80211->state = IEEE80211_NOLINK;
 973 }
 974
 975 bool MgntDisconnect(struct net_device *dev, u8 asRsn)
 976 {
 977         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 978         /*
 979          *      Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
 980          */
 981
 982         if (IS_DOT11D_ENABLE(priv->ieee80211))
 983                 Dot11d_Reset(priv->ieee80211);
 984         /* In adhoc mode, update beacon frame. */
 985         if (priv->ieee80211->state == IEEE80211_LINKED) {
 986                 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
 987                         MgntDisconnectIBSS(dev);
 988
 989                 if (priv->ieee80211->iw_mode == IW_MODE_INFRA) {
 990                         /*
 991                          *      We clear key here instead of MgntDisconnectAP() because that
 992                          *      MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
 993                          *      e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
 994                          *      used to handle disassociation related things to AP, e.g. send Disassoc
 995                          *      frame to AP.  2005.01.27, by rcnjko.
 996                          */
 997                         MgntDisconnectAP(dev, asRsn);
 998                 }
 999                 /* Indicate Disconnect, 2005.02.23, by rcnjko.  */
1000         }
1001         return true;
1002 }
1003 /*
1004  *      Description:
1005  *              Chang RF Power State.
1006  *              Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
1007  *
1008  *      Assumption:
1009  *              PASSIVE LEVEL.
1010  */
1011 bool SetRFPowerState(struct net_device *dev, RT_RF_POWER_STATE eRFPowerState)
1012 {
1013         struct  r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1014         bool    bResult = false;
1015
1016         if (eRFPowerState == priv->eRFPowerState)
1017                 return bResult;
1018
1019         bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
1020
1021         return bResult;
1022 }
1023
1024 bool MgntActSet_RF_State(struct net_device *dev, RT_RF_POWER_STATE StateToSet, u32 ChangeSource)
1025 {
1026         struct  r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1027         bool    bActionAllowed = false;
1028         bool    bConnectBySSID = false;
1029         RT_RF_POWER_STATE rtState;
1030         u16     RFWaitCounter = 0;
1031         unsigned long flag;
1032         /*
1033          *      Prevent the race condition of RF state change. By Bruce, 2007-11-28.
1034          *      Only one thread can change the RF state at one time, and others should wait to be executed.
1035          */
1036         while (true) {
1037                 spin_lock_irqsave(&priv->rf_ps_lock, flag);
1038                 if (priv->RFChangeInProgress) {
1039                         spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1040                         /*  Set RF after the previous action is done.   */
1041                         while (priv->RFChangeInProgress) {
1042                                 RFWaitCounter++;
1043                                 udelay(1000); /* 1 ms   */
1044
1045                                 /* Wait too long, return FALSE to avoid to be stuck here. */
1046                                 if (RFWaitCounter > 1000) { /* 1sec */
1047                                         printk("MgntActSet_RF_State(): Wait too long to set RF\n");
1048                                         /* TODO: Reset RF state? */
1049                                         return false;
1050                                 }
1051                         }
1052                 } else {
1053                         priv->RFChangeInProgress = true;
1054                         spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1055                         break;
1056                 }
1057         }
1058         rtState = priv->eRFPowerState;
1059
1060         switch (StateToSet) {
1061         case eRfOn:
1062                 /*
1063                  *      Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
1064                  *      the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
1065                  */
1066                 priv->RfOffReason &= (~ChangeSource);
1067
1068                 if (!priv->RfOffReason) {
1069                         priv->RfOffReason = 0;
1070                         bActionAllowed = true;
1071
1072                         if (rtState == eRfOff && ChangeSource >= RF_CHANGE_BY_HW)
1073                                 bConnectBySSID = true;
1074                 }
1075                 break;
1076
1077         case eRfOff:
1078                  /* 070125, rcnjko: we always keep connected in AP mode. */
1079
1080                 if (priv->RfOffReason > RF_CHANGE_BY_IPS) {
1081                         /*
1082                          *      060808, Annie:
1083                          *      Disconnect to current BSS when radio off. Asked by QuanTa.
1084                          *
1085                          *      Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
1086                          *      because we do NOT need to set ssid to dummy ones.
1087                          */
1088                         MgntDisconnect(dev, disas_lv_ss);
1089                         /* Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI. */
1090                 }
1091
1092                 priv->RfOffReason |= ChangeSource;
1093                 bActionAllowed = true;
1094                 break;
1095         case eRfSleep:
1096                 priv->RfOffReason |= ChangeSource;
1097                 bActionAllowed = true;
1098                 break;
1099         default:
1100                 break;
1101         }
1102
1103         if (bActionAllowed) {
1104                 /* Config HW to the specified mode. */
1105                 SetRFPowerState(dev, StateToSet);
1106         }
1107
1108         /* Release RF spinlock  */
1109         spin_lock_irqsave(&priv->rf_ps_lock, flag);
1110         priv->RFChangeInProgress = false;
1111         spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1112         return bActionAllowed;
1113 }
1114
1115 void InactivePowerSave(struct net_device *dev)
1116 {
1117         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1118         /*
1119          *      This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
1120          *      is really scheduled.
1121          *      The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
1122          *      previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
1123          *      blocks the IPS procedure of switching RF.
1124          */
1125         priv->bSwRfProcessing = true;
1126
1127         MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
1128
1129         /*
1130          *      To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
1131          */
1132
1133         priv->bSwRfProcessing = false;
1134 }
1135
1136 /*
1137  *      Description:
1138  *              Enter the inactive power save mode. RF will be off
1139  */
1140 void IPSEnter(struct net_device *dev)
1141 {
1142         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1143         RT_RF_POWER_STATE rtState;
1144         if (priv->bInactivePs) {
1145                 rtState = priv->eRFPowerState;
1146
1147                 /*
1148                  *      Do not enter IPS in the following conditions:
1149                  *      (1) RF is already OFF or Sleep
1150                  *      (2) bSwRfProcessing (indicates the IPS is still under going)
1151                  *      (3) Connected (only disconnected can trigger IPS)
1152                  *      (4) IBSS (send Beacon)
1153                  *      (5) AP mode (send Beacon)
1154                  */
1155                 if (rtState == eRfOn && !priv->bSwRfProcessing
1156                         && (priv->ieee80211->state != IEEE80211_LINKED)) {
1157                         priv->eInactivePowerState = eRfOff;
1158                         InactivePowerSave(dev);
1159                 }
1160         }
1161 }
1162 void IPSLeave(struct net_device *dev)
1163 {
1164         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1165         RT_RF_POWER_STATE rtState;
1166         if (priv->bInactivePs) {
1167                 rtState = priv->eRFPowerState;
1168                 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS) {
1169                         priv->eInactivePowerState = eRfOn;
1170                         InactivePowerSave(dev);
1171                 }
1172         }
1173 }
1174
1175 void rtl8185b_adapter_start(struct net_device *dev)
1176 {
1177         struct r8180_priv *priv = ieee80211_priv(dev);
1178         struct ieee80211_device *ieee = priv->ieee80211;
1179
1180         u8 SupportedWirelessMode;
1181         u8 InitWirelessMode;
1182         u8 bInvalidWirelessMode = 0;
1183         u8 tmpu8;
1184         u8 btCR9346;
1185         u8 TmpU1b;
1186         u8 btPSR;
1187
1188         write_nic_byte(dev, 0x24e, (BIT5|BIT6|BIT0));
1189         rtl8180_reset(dev);
1190
1191         priv->dma_poll_mask = 0;
1192         priv->dma_poll_stop_mask = 0;
1193
1194         HwConfigureRTL8185(dev);
1195         write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
1196         write_nic_word(dev, MAC4, ((u32 *)dev->dev_addr)[1] & 0xffff);
1197         write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3); /* default network type to 'No Link' */
1198         write_nic_word(dev, BcnItv, 100);
1199         write_nic_word(dev, AtimWnd, 2);
1200         PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
1201         write_nic_byte(dev, WPA_CONFIG, 0);
1202         MacConfig_85BASIC(dev);
1203         /* Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko. */
1204         /* BT_DEMO_BOARD type */
1205         PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
1206
1207         /*
1208          *---------------------------------------------------------------------------
1209          *      Set up PHY related.
1210          *---------------------------------------------------------------------------
1211          */
1212         /* Enable Config3.PARAM_En to revise AnaaParm. */
1213         write_nic_byte(dev, CR9346, 0xc0); /* enable config register write */
1214         tmpu8 = read_nic_byte(dev, CONFIG3);
1215         write_nic_byte(dev, CONFIG3, (tmpu8 | CONFIG3_PARM_En));
1216         /* Turn on Analog power. */
1217         /* Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko. */
1218         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
1219         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
1220         write_nic_word(dev, ANAPARAM3, 0x0010);
1221
1222         write_nic_byte(dev, CONFIG3, tmpu8);
1223         write_nic_byte(dev, CR9346, 0x00);
1224         /* enable EEM0 and EEM1 in 9346CR */
1225         btCR9346 = read_nic_byte(dev, CR9346);
1226         write_nic_byte(dev, CR9346, (btCR9346 | 0xC0));
1227
1228         /* B cut use LED1 to control HW RF on/off */
1229         TmpU1b = read_nic_byte(dev, CONFIG5);
1230         TmpU1b = TmpU1b & ~BIT3;
1231         write_nic_byte(dev, CONFIG5, TmpU1b);
1232
1233         /* disable EEM0 and EEM1 in 9346CR */
1234         btCR9346 &= ~(0xC0);
1235         write_nic_byte(dev, CR9346, btCR9346);
1236
1237         /* Enable Led (suggested by Jong) */
1238         /* B-cut RF Radio on/off  5e[3]=0 */
1239         btPSR = read_nic_byte(dev, PSR);
1240         write_nic_byte(dev, PSR, (btPSR | BIT3));
1241         /* setup initial timing for RFE. */
1242         write_nic_word(dev, RFPinsOutput, 0x0480);
1243         SetOutputEnableOfRfPins(dev);
1244         write_nic_word(dev, RFPinsSelect, 0x2488);
1245
1246         /* PHY config. */
1247         PhyConfig8185(dev);
1248
1249         /*
1250          *      We assume RegWirelessMode has already been initialized before,
1251          *      however, we has to validate the wireless mode here and provide a
1252          *      reasonable initialized value if necessary. 2005.01.13, by rcnjko.
1253          */
1254         SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1255         if ((ieee->mode != WIRELESS_MODE_B) &&
1256                 (ieee->mode != WIRELESS_MODE_G) &&
1257                 (ieee->mode != WIRELESS_MODE_A) &&
1258                 (ieee->mode != WIRELESS_MODE_AUTO)) {
1259                 /* It should be one of B, G, A, or AUTO. */
1260                 bInvalidWirelessMode = 1;
1261         } else {
1262         /* One of B, G, A, or AUTO. */
1263                 /* Check if the wireless mode is supported by RF. */
1264                 if      ((ieee->mode != WIRELESS_MODE_AUTO) &&
1265                         (ieee->mode & SupportedWirelessMode) == 0) {
1266                         bInvalidWirelessMode = 1;
1267                 }
1268         }
1269
1270         if (bInvalidWirelessMode || ieee->mode == WIRELESS_MODE_AUTO) {
1271                 /* Auto or other invalid value. */
1272                 /* Assigne a wireless mode to initialize. */
1273                 if ((SupportedWirelessMode & WIRELESS_MODE_A)) {
1274                         InitWirelessMode = WIRELESS_MODE_A;
1275                 } else if ((SupportedWirelessMode & WIRELESS_MODE_G)) {
1276                         InitWirelessMode = WIRELESS_MODE_G;
1277                 } else if ((SupportedWirelessMode & WIRELESS_MODE_B)) {
1278                         InitWirelessMode = WIRELESS_MODE_B;
1279                 } else {
1280                         DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
1281                                  SupportedWirelessMode);
1282                         InitWirelessMode = WIRELESS_MODE_B;
1283                 }
1284
1285                 /* Initialize RegWirelessMode if it is not a valid one. */
1286                 if (bInvalidWirelessMode)
1287                         ieee->mode = (WIRELESS_MODE)InitWirelessMode;
1288
1289         } else {
1290         /* One of B, G, A. */
1291                 InitWirelessMode = ieee->mode;
1292         }
1293         priv->eRFPowerState = eRfOff;
1294         priv->RfOffReason = 0;
1295         {
1296                 MgntActSet_RF_State(dev, eRfOn, 0);
1297         }
1298                 /*
1299                  *      If inactive power mode is enabled, disable rf while in disconnected state.
1300                  */
1301         if (priv->bInactivePs)
1302                 MgntActSet_RF_State(dev , eRfOff, RF_CHANGE_BY_IPS);
1303
1304         ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
1305
1306         /* ----------------------------------------------------------------------------- */
1307
1308         rtl8185b_irq_enable(dev);
1309
1310         netif_start_queue(dev);
1311 }
1312
1313 void rtl8185b_rx_enable(struct net_device *dev)
1314 {
1315         u8 cmd;
1316         /* for now we accept data, management & ctl frame*/
1317         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1318
1319
1320         if (dev->flags & IFF_PROMISC)
1321                 DMESG("NIC in promisc mode");
1322
1323         if (priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
1324            dev->flags & IFF_PROMISC) {
1325                 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
1326                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
1327         }
1328
1329         if (priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1330                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
1331
1332
1333         if (priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1334                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
1335
1336         write_nic_dword(dev, RCR, priv->ReceiveConfig);
1337
1338         fix_rx_fifo(dev);
1339
1340         cmd = read_nic_byte(dev, CMD);
1341         write_nic_byte(dev, CMD, cmd | (1<<CMD_RX_ENABLE_SHIFT));
1342
1343 }
1344
1345 void rtl8185b_tx_enable(struct net_device *dev)
1346 {
1347         u8 cmd;
1348         u8 byte;
1349         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1350
1351         write_nic_dword(dev, TCR, priv->TransmitConfig);
1352         byte = read_nic_byte(dev, MSR);
1353         byte |= MSR_LINK_ENEDCA;
1354         write_nic_byte(dev, MSR, byte);
1355
1356         fix_tx_fifo(dev);
1357
1358         cmd = read_nic_byte(dev, CMD);
1359         write_nic_byte(dev, CMD, cmd | (1<<CMD_TX_ENABLE_SHIFT));
1360 }
1361