1 MediaTek MT7621 PCIe controller
4 - compatible: "mediatek,mt7621-pci"
5 - device_type: Must be "pci"
6 - reg: Base addresses and lengths of the PCIe subsys and root ports.
7 - bus-range: Range of bus numbers associated with this controller.
8 - #address-cells: Address representation for root ports (must be 3)
9 - perst-gpio: PCIe reset signal line.
10 - pinctrl-names : The pin control state names.
11 - pinctrl-0: The "default" pinctrl state.
12 - #size-cells: Size representation for root ports (must be 2)
13 - ranges: Ranges for the PCI memory and I/O regions.
14 - #interrupt-cells: Must be 1
15 - interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties.
16 Please refer to the standard PCI bus binding document for a more detailed
18 - status: either "disabled" or "okay".
19 - resets: Must contain an entry for each entry in reset-names.
20 See ../reset/reset.txt for details.
21 - reset-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
23 - clocks: Must contain an entry for each entry in clock-names.
24 See ../clocks/clock-bindings.txt for details.
25 - clock-names: Must be "pcie0", "pcie1", "pcieN"... based on the number of
28 In addition, the device tree node must have sub-nodes describing each PCIe port
29 interface, having the following mandatory properties:
32 - reg: Only the first four bytes are used to refer to the correct bus number
34 - #address-cells: Must be 3
35 - #size-cells: Must be 2
36 - ranges: Sub-ranges distributed from the PCIe controller node. An empty
37 property is sufficient.
38 - bus-range: Range of bus numbers associated with this port.
43 compatible = "mediatek,mt7621-pci";
44 reg = <0x1e140000 0x100 /* host-pci bridge registers */
45 0x1e142000 0x100 /* pcie port 0 RC control registers */
46 0x1e143000 0x100 /* pcie port 1 RC control registers */
47 0x1e144000 0x100>; /* pcie port 2 RC control registers */
52 perst-gpio = <&gpio 19 GPIO_ACTIVE_HIGH>;
53 pinctrl-names = "default";
54 pinctrl-0 = <&pcie_pins>;
60 0x02000000 0 0x00000000 0x60000000 0 0x10000000 /* pci memory */
61 0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
64 #interrupt-cells = <1>;
65 interrupt-map-mask = <0xF0000 0 0 1>;
66 interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
67 <0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
68 <0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
72 resets = <&rstctrl 24 &rstctrl 25 &rstctrl 26>;
73 reset-names = "pcie0", "pcie1", "pcie2";
74 clocks = <&clkctrl 24 &clkctrl 25 &clkctrl 26>;
75 clock-names = "pcie0", "pcie1", "pcie2";
78 reg = <0x0000 0 0 0 0>;
82 bus-range = <0x00 0xff>;
86 reg = <0x0800 0 0 0 0>;
90 bus-range = <0x00 0xff>;
94 reg = <0x1000 0 0 0 0>;
98 bus-range = <0x00 0xff>;